LLVM API Documentation
00001 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by Chris Lattner and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file defines the interfaces that PPC uses to lower LLVM code into a 00011 // selection DAG. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 00016 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 00017 00018 #include "llvm/Target/TargetLowering.h" 00019 #include "llvm/CodeGen/SelectionDAG.h" 00020 #include "PPC.h" 00021 00022 namespace llvm { 00023 namespace PPCISD { 00024 enum NodeType { 00025 // Start the numbering where the builting ops and target ops leave off. 00026 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END, 00027 00028 /// FSEL - Traditional three-operand fsel node. 00029 /// 00030 FSEL, 00031 00032 /// FCFID - The FCFID instruction, taking an f64 operand and producing 00033 /// and f64 value containing the FP representation of the integer that 00034 /// was temporarily in the f64 operand. 00035 FCFID, 00036 00037 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 00038 /// operand, producing an f64 value containing the integer representation 00039 /// of that FP value. 00040 FCTIDZ, FCTIWZ, 00041 00042 /// STFIWX - The STFIWX instruction. The first operand is an input token 00043 /// chain, then an f64 value to store, then an address to store it to, 00044 /// then a SRCVALUE for the address. 00045 STFIWX, 00046 00047 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 00048 // three v4f32 operands and producing a v4f32 result. 00049 VMADDFP, VNMSUBFP, 00050 00051 /// VPERM - The PPC VPERM Instruction. 00052 /// 00053 VPERM, 00054 00055 /// Hi/Lo - These represent the high and low 16-bit parts of a global 00056 /// address respectively. These nodes have two operands, the first of 00057 /// which must be a TargetGlobalAddress, and the second of which must be a 00058 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 00059 /// though these are usually folded into other nodes. 00060 Hi, Lo, 00061 00062 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 00063 /// at function entry, used for PIC code. 00064 GlobalBaseReg, 00065 00066 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 00067 /// shift amounts. These nodes are generated by the multi-precision shift 00068 /// code. 00069 SRL, SRA, SHL, 00070 00071 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 00072 /// registers. 00073 EXTSW_32, 00074 00075 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 00076 STD_32, 00077 00078 /// CALL - A direct function call. 00079 CALL, 00080 00081 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 00082 /// MTCTR instruction. 00083 MTCTR, 00084 00085 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 00086 /// BCTRL instruction. 00087 BCTRL, 00088 00089 /// Return with a flag operand, matched by 'blr' 00090 RET_FLAG, 00091 00092 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 00093 /// This copies the bits corresponding to the specified CRREG into the 00094 /// resultant GPR. Bits corresponding to other CR regs are undefined. 00095 MFCR, 00096 00097 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 00098 /// instructions. For lack of better number, we use the opcode number 00099 /// encoding for the OPC field to identify the compare. For example, 838 00100 /// is VCMPGTSH. 00101 VCMP, 00102 00103 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 00104 /// altivec VCMP*o instructions. For lack of better number, we use the 00105 /// opcode number encoding for the OPC field to identify the compare. For 00106 /// example, 838 is VCMPGTSH. 00107 VCMPo, 00108 00109 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 00110 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 00111 /// condition register to branch on, OPC is the branch opcode to use (e.g. 00112 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 00113 /// an optional input flag argument. 00114 COND_BRANCH, 00115 00116 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a 00117 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 00118 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 00119 /// i32. 00120 STBRX, 00121 00122 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a 00123 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 00124 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 00125 /// or i32. 00126 LBRX 00127 }; 00128 } 00129 00130 /// Define some predicates that are used for node matching. 00131 namespace PPC { 00132 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 00133 /// VPKUHUM instruction. 00134 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); 00135 00136 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 00137 /// VPKUWUM instruction. 00138 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); 00139 00140 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 00141 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 00142 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 00143 00144 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 00145 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 00146 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 00147 00148 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 00149 /// amount, otherwise return -1. 00150 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 00151 00152 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 00153 /// specifies a splat of a single element that is suitable for input to 00154 /// VSPLTB/VSPLTH/VSPLTW. 00155 bool isSplatShuffleMask(SDNode *N, unsigned EltSize); 00156 00157 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 00158 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 00159 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 00160 00161 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 00162 /// formed by using a vspltis[bhw] instruction of the specified element 00163 /// size, return the constant being splatted. The ByteSize field indicates 00164 /// the number of bytes of each element [124] -> [bhw]. 00165 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 00166 } 00167 00168 class PPCTargetLowering : public TargetLowering { 00169 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 00170 int ReturnAddrIndex; // FrameIndex for return slot. 00171 public: 00172 PPCTargetLowering(TargetMachine &TM); 00173 00174 /// getTargetNodeName() - This method returns the name of a target specific 00175 /// DAG node. 00176 virtual const char *getTargetNodeName(unsigned Opcode) const; 00177 00178 /// LowerOperation - Provide custom lowering hooks for some operations. 00179 /// 00180 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 00181 00182 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 00183 00184 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 00185 uint64_t Mask, 00186 uint64_t &KnownZero, 00187 uint64_t &KnownOne, 00188 unsigned Depth = 0) const; 00189 00190 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 00191 MachineBasicBlock *MBB); 00192 00193 ConstraintType getConstraintType(char ConstraintLetter) const; 00194 std::vector<unsigned> 00195 getRegClassForInlineAsmConstraint(const std::string &Constraint, 00196 MVT::ValueType VT) const; 00197 bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 00198 00199 /// isLegalAddressImmediate - Return true if the integer value can be used 00200 /// as the offset of the target addressing mode. 00201 virtual bool isLegalAddressImmediate(int64_t V) const; 00202 }; 00203 } 00204 00205 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H