LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned ImplicitList1[] = { PPC::CR0, 0 }; 00012 static const unsigned ImplicitList2[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; 00013 static const unsigned ImplicitList3[] = { PPC::LR, 0 }; 00014 static const unsigned ImplicitList4[] = { PPC::CR6, 0 }; 00015 00016 static const TargetOperandInfo OperandInfo2[] = { { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00017 static const TargetOperandInfo OperandInfo3[] = { { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, }; 00018 static const TargetOperandInfo OperandInfo4[] = { { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { 0, 0 }, }; 00019 static const TargetOperandInfo OperandInfo5[] = { { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { 0, 0 }, }; 00020 static const TargetOperandInfo OperandInfo6[] = { { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00021 static const TargetOperandInfo OperandInfo7[] = { { 0, 0 }, }; 00022 static const TargetOperandInfo OperandInfo8[] = { { PPC::CRRCRegClassID, 0 }, { 0, 0 }, }; 00023 static const TargetOperandInfo OperandInfo9[] = { { PPC::CRRCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, }; 00024 static const TargetOperandInfo OperandInfo10[] = { { PPC::CRRCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { 0, 0 }, }; 00025 static const TargetOperandInfo OperandInfo11[] = { { PPC::CRRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00026 static const TargetOperandInfo OperandInfo12[] = { { PPC::CRRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { 0, 0 }, }; 00027 static const TargetOperandInfo OperandInfo13[] = { { PPC::CRRCRegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00028 static const TargetOperandInfo OperandInfo14[] = { { 0, 1 }, { 0, 1 }, }; 00029 static const TargetOperandInfo OperandInfo15[] = { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, }; 00030 static const TargetOperandInfo OperandInfo16[] = { { 0, 0 }, { 0, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00031 static const TargetOperandInfo OperandInfo17[] = { { 0, 0 }, { 0, 0 }, { 0, 0 }, }; 00032 static const TargetOperandInfo OperandInfo18[] = { { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, }; 00033 static const TargetOperandInfo OperandInfo19[] = { { PPC::G8RCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00034 static const TargetOperandInfo OperandInfo20[] = { { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, }; 00035 static const TargetOperandInfo OperandInfo21[] = { { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, }; 00036 static const TargetOperandInfo OperandInfo22[] = { { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, }; 00037 static const TargetOperandInfo OperandInfo23[] = { { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, }; 00038 static const TargetOperandInfo OperandInfo24[] = { { PPC::CRRCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, }; 00039 static const TargetOperandInfo OperandInfo25[] = { { PPC::CRRCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, }; 00040 static const TargetOperandInfo OperandInfo26[] = { { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, }; 00041 static const TargetOperandInfo OperandInfo27[] = { { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, }; 00042 static const TargetOperandInfo OperandInfo28[] = { { PPC::F8RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, }; 00043 static const TargetOperandInfo OperandInfo29[] = { { PPC::F4RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, }; 00044 static const TargetOperandInfo OperandInfo30[] = { { PPC::F4RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, }; 00045 static const TargetOperandInfo OperandInfo31[] = { { PPC::F4RCRegClassID, 0 }, }; 00046 static const TargetOperandInfo OperandInfo32[] = { { PPC::F8RCRegClassID, 0 }, }; 00047 static const TargetOperandInfo OperandInfo33[] = { { PPC::G8RCRegClassID, 0 }, }; 00048 static const TargetOperandInfo OperandInfo34[] = { { PPC::GPRCRegClassID, 0 }, }; 00049 static const TargetOperandInfo OperandInfo35[] = { { PPC::VRRCRegClassID, 0 }, }; 00050 static const TargetOperandInfo OperandInfo36[] = { { PPC::GPRCRegClassID, 0 }, { 0, 0 }, { 0, 1 }, }; 00051 static const TargetOperandInfo OperandInfo37[] = { { PPC::G8RCRegClassID, 0 }, { 0, 0 }, { 0, 1 }, }; 00052 static const TargetOperandInfo OperandInfo38[] = { { PPC::GPRCRegClassID, 0 }, { 0, 1 }, { 0, 1 }, }; 00053 static const TargetOperandInfo OperandInfo39[] = { { PPC::G8RCRegClassID, 0 }, { 0, 1 }, { 0, 1 }, }; 00054 static const TargetOperandInfo OperandInfo40[] = { { PPC::F8RCRegClassID, 0 }, { 0, 0 }, { 0, 1 }, }; 00055 static const TargetOperandInfo OperandInfo41[] = { { PPC::F8RCRegClassID, 0 }, { 0, 1 }, { 0, 1 }, }; 00056 static const TargetOperandInfo OperandInfo42[] = { { PPC::F4RCRegClassID, 0 }, { 0, 0 }, { 0, 1 }, }; 00057 static const TargetOperandInfo OperandInfo43[] = { { PPC::F4RCRegClassID, 0 }, { 0, 1 }, { 0, 1 }, }; 00058 static const TargetOperandInfo OperandInfo44[] = { { PPC::GPRCRegClassID, 0 }, { 0, 0 }, }; 00059 static const TargetOperandInfo OperandInfo45[] = { { PPC::G8RCRegClassID, 0 }, { 0, 0 }, }; 00060 static const TargetOperandInfo OperandInfo46[] = { { PPC::VRRCRegClassID, 0 }, { 0, 1 }, { 0, 1 }, }; 00061 static const TargetOperandInfo OperandInfo47[] = { { PPC::GPRCRegClassID, 0 }, { 0, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00062 static const TargetOperandInfo OperandInfo48[] = { { PPC::CRRCRegClassID, 0 }, { PPC::CRRCRegClassID, 0 }, }; 00063 static const TargetOperandInfo OperandInfo49[] = { { 0, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00064 static const TargetOperandInfo OperandInfo50[] = { { PPC::G8RCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, }; 00065 static const TargetOperandInfo OperandInfo51[] = { { PPC::GPRCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, }; 00066 static const TargetOperandInfo OperandInfo52[] = { { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00067 static const TargetOperandInfo OperandInfo53[] = { { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00068 static const TargetOperandInfo OperandInfo54[] = { { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, }; 00069 static const TargetOperandInfo OperandInfo55[] = { { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, }; 00070 static const TargetOperandInfo OperandInfo56[] = { { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00071 static const TargetOperandInfo OperandInfo57[] = { { PPC::F4RCRegClassID, 0 }, { PPC::CRRCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { PPC::F4RCRegClassID, 0 }, { 0, 0 }, }; 00072 static const TargetOperandInfo OperandInfo58[] = { { PPC::F8RCRegClassID, 0 }, { PPC::CRRCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { PPC::F8RCRegClassID, 0 }, { 0, 0 }, }; 00073 static const TargetOperandInfo OperandInfo59[] = { { PPC::GPRCRegClassID, 0 }, { PPC::CRRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { PPC::GPRCRegClassID, 0 }, { 0, 0 }, }; 00074 static const TargetOperandInfo OperandInfo60[] = { { PPC::G8RCRegClassID, 0 }, { PPC::CRRCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { PPC::G8RCRegClassID, 0 }, { 0, 0 }, }; 00075 static const TargetOperandInfo OperandInfo61[] = { { PPC::VRRCRegClassID, 0 }, { PPC::CRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { 0, 0 }, }; 00076 static const TargetOperandInfo OperandInfo62[] = { { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, }; 00077 static const TargetOperandInfo OperandInfo63[] = { { PPC::VRRCRegClassID, 0 }, { 0, 0 }, { PPC::VRRCRegClassID, 0 }, }; 00078 static const TargetOperandInfo OperandInfo64[] = { { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, }; 00079 static const TargetOperandInfo OperandInfo65[] = { { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, }; 00080 static const TargetOperandInfo OperandInfo66[] = { { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { PPC::VRRCRegClassID, 0 }, { 0, 0 }, }; 00081 static const TargetOperandInfo OperandInfo67[] = { { PPC::VRRCRegClassID, 0 }, { 0, 0 }, }; 00082 00083 static const TargetInstrDescriptor PPCInsts[] = { 00084 { "PHI", 0, 52, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #0 = PHI 00085 { "INLINEASM", 0, 52, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #1 = INLINEASM 00086 { "ADD4", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #2 = ADD4 00087 { "ADD8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #3 = ADD8 00088 { "ADDC", 3, 14, 0, 0|(1<<2)|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #4 = ADDC 00089 { "ADDE", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #5 = ADDE 00090 { "ADDI", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #6 = ADDI 00091 { "ADDI8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #7 = ADDI8 00092 { "ADDIC", 3, 14, 0, 0|(1<<2)|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #8 = ADDIC 00093 { "ADDICo", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #9 = ADDICo 00094 { "ADDIS", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #10 = ADDIS 00095 { "ADDIS8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #11 = ADDIS8 00096 { "ADDME", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #12 = ADDME 00097 { "ADDZE", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #13 = ADDZE 00098 { "ADJCALLSTACKDOWN", 1, 52, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #14 = ADJCALLSTACKDOWN 00099 { "ADJCALLSTACKUP", 1, 52, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #15 = ADJCALLSTACKUP 00100 { "AND", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #16 = AND 00101 { "AND8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #17 = AND8 00102 { "ANDC", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #18 = ANDC 00103 { "ANDC8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #19 = ANDC8 00104 { "ANDISo", 3, 14, 0, 0|(1<<3), NULL, ImplicitList1, OperandInfo4 }, // Inst #20 = ANDISo 00105 { "ANDISo8", 3, 14, 0, 0|(1<<3), NULL, ImplicitList1, OperandInfo5 }, // Inst #21 = ANDISo8 00106 { "ANDIo", 3, 14, 0, 0|(1<<3), NULL, ImplicitList1, OperandInfo4 }, // Inst #22 = ANDIo 00107 { "ANDIo8", 3, 14, 0, 0|(1<<3), NULL, ImplicitList1, OperandInfo5 }, // Inst #23 = ANDIo8 00108 { "B", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo7 }, // Inst #24 = B 00109 { "BCTR", 0, 0, 0|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, 0 }, // Inst #25 = BCTR 00110 { "BCTRL", 0, 0, 0|M_CALL_FLAG|M_VARIABLE_OPS, 0|(7<<3), NULL, ImplicitList2, 0 }, // Inst #26 = BCTRL 00111 { "BEQ", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #27 = BEQ 00112 { "BGE", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #28 = BGE 00113 { "BGT", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #29 = BGT 00114 { "BL", 1, 0, 0|M_CALL_FLAG|M_VARIABLE_OPS, 0|(7<<3), NULL, ImplicitList2, OperandInfo7 }, // Inst #30 = BL 00115 { "BLA", 1, 0, 0|M_CALL_FLAG|M_VARIABLE_OPS, 0|(7<<3), NULL, ImplicitList2, OperandInfo7 }, // Inst #31 = BLA 00116 { "BLE", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #32 = BLE 00117 { "BLR", 0, 0, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, 0 }, // Inst #33 = BLR 00118 { "BLT", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #34 = BLT 00119 { "BNE", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #35 = BNE 00120 { "BNU", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #36 = BNU 00121 { "BUN", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo8 }, // Inst #37 = BUN 00122 { "CMPD", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo9 }, // Inst #38 = CMPD 00123 { "CMPDI", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo10 }, // Inst #39 = CMPDI 00124 { "CMPLD", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo9 }, // Inst #40 = CMPLD 00125 { "CMPLDI", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo10 }, // Inst #41 = CMPLDI 00126 { "CMPLW", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo11 }, // Inst #42 = CMPLW 00127 { "CMPLWI", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo12 }, // Inst #43 = CMPLWI 00128 { "CMPW", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo11 }, // Inst #44 = CMPW 00129 { "CMPWI", 3, 11, 0, 0|(1<<3), NULL, NULL, OperandInfo12 }, // Inst #45 = CMPWI 00130 { "CNTLZW", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #46 = CNTLZW 00131 { "COND_BRANCH", 3, 52, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), NULL, NULL, OperandInfo13 }, // Inst #47 = COND_BRANCH 00132 { "DCBZ", 2, 30, 0, 0|(1<<1), NULL, NULL, OperandInfo14 }, // Inst #48 = DCBZ 00133 { "DCBZL", 2, 30, 0, 0|(1<<1), NULL, NULL, OperandInfo14 }, // Inst #49 = DCBZL 00134 { "DIVD", 3, 12, 0, 0|1|(1<<2)|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #50 = DIVD 00135 { "DIVDU", 3, 12, 0, 0|1|(1<<2)|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #51 = DIVDU 00136 { "DIVW", 3, 13, 0, 0|1|(1<<2)|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #52 = DIVW 00137 { "DIVWU", 3, 13, 0, 0|1|(1<<2)|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #53 = DIVWU 00138 { "DSS", 4, 33, 0, 0, NULL, NULL, OperandInfo15 }, // Inst #54 = DSS 00139 { "DST", 4, 33, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #55 = DST 00140 { "DSTST", 4, 33, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #56 = DSTST 00141 { "DWARF_LABEL", 1, 52, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #57 = DWARF_LABEL 00142 { "DWARF_LOC", 3, 52, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #58 = DWARF_LOC 00143 { "EQV", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #59 = EQV 00144 { "EQV8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #60 = EQV8 00145 { "EXTSB", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #61 = EXTSB 00146 { "EXTSH", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #62 = EXTSH 00147 { "EXTSW", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo18 }, // Inst #63 = EXTSW 00148 { "EXTSW_32", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #64 = EXTSW_32 00149 { "EXTSW_32_64", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo19 }, // Inst #65 = EXTSW_32_64 00150 { "FABSD", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #66 = FABSD 00151 { "FABSS", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo21 }, // Inst #67 = FABSS 00152 { "FADD", 3, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo22 }, // Inst #68 = FADD 00153 { "FADDS", 3, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo23 }, // Inst #69 = FADDS 00154 { "FCFID", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #70 = FCFID 00155 { "FCMPUD", 3, 4, 0, 0|(3<<3), NULL, NULL, OperandInfo24 }, // Inst #71 = FCMPUD 00156 { "FCMPUS", 3, 4, 0, 0|(3<<3), NULL, NULL, OperandInfo25 }, // Inst #72 = FCMPUS 00157 { "FCTIDZ", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #73 = FCTIDZ 00158 { "FCTIWZ", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #74 = FCTIWZ 00159 { "FDIV", 3, 5, 0, 0|(3<<3), NULL, NULL, OperandInfo22 }, // Inst #75 = FDIV 00160 { "FDIVS", 3, 6, 0, 0|(3<<3), NULL, NULL, OperandInfo23 }, // Inst #76 = FDIVS 00161 { "FMADD", 4, 7, 0, 0|(3<<3), NULL, NULL, OperandInfo26 }, // Inst #77 = FMADD 00162 { "FMADDS", 4, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo27 }, // Inst #78 = FMADDS 00163 { "FMRD", 2, 8, 0, 0, NULL, NULL, OperandInfo20 }, // Inst #79 = FMRD 00164 { "FMRS", 2, 8, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #80 = FMRS 00165 { "FMRSD", 2, 8, 0, 0, NULL, NULL, OperandInfo28 }, // Inst #81 = FMRSD 00166 { "FMSUB", 4, 7, 0, 0|(3<<3), NULL, NULL, OperandInfo26 }, // Inst #82 = FMSUB 00167 { "FMSUBS", 4, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo27 }, // Inst #83 = FMSUBS 00168 { "FMUL", 3, 7, 0, 0|(3<<3), NULL, NULL, OperandInfo22 }, // Inst #84 = FMUL 00169 { "FMULS", 3, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo23 }, // Inst #85 = FMULS 00170 { "FNABSD", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #86 = FNABSD 00171 { "FNABSS", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo21 }, // Inst #87 = FNABSS 00172 { "FNEGD", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #88 = FNEGD 00173 { "FNEGS", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo21 }, // Inst #89 = FNEGS 00174 { "FNMADD", 4, 7, 0, 0|(3<<3), NULL, NULL, OperandInfo26 }, // Inst #90 = FNMADD 00175 { "FNMADDS", 4, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo27 }, // Inst #91 = FNMADDS 00176 { "FNMSUB", 4, 7, 0, 0|(3<<3), NULL, NULL, OperandInfo26 }, // Inst #92 = FNMSUB 00177 { "FNMSUBS", 4, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo27 }, // Inst #93 = FNMSUBS 00178 { "FRSP", 2, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo29 }, // Inst #94 = FRSP 00179 { "FSELD", 4, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo26 }, // Inst #95 = FSELD 00180 { "FSELS", 4, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo30 }, // Inst #96 = FSELS 00181 { "FSQRT", 2, 10, 0, 0|(3<<3), NULL, NULL, OperandInfo20 }, // Inst #97 = FSQRT 00182 { "FSQRTS", 2, 10, 0, 0|(3<<3), NULL, NULL, OperandInfo21 }, // Inst #98 = FSQRTS 00183 { "FSUB", 3, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo22 }, // Inst #99 = FSUB 00184 { "FSUBS", 3, 8, 0, 0|(3<<3), NULL, NULL, OperandInfo23 }, // Inst #100 = FSUBS 00185 { "IMPLICIT_DEF_F4", 1, 52, 0, 0, NULL, NULL, OperandInfo31 }, // Inst #101 = IMPLICIT_DEF_F4 00186 { "IMPLICIT_DEF_F8", 1, 52, 0, 0, NULL, NULL, OperandInfo32 }, // Inst #102 = IMPLICIT_DEF_F8 00187 { "IMPLICIT_DEF_G8RC", 1, 52, 0, 0, NULL, NULL, OperandInfo33 }, // Inst #103 = IMPLICIT_DEF_G8RC 00188 { "IMPLICIT_DEF_GPRC", 1, 52, 0, 0, NULL, NULL, OperandInfo34 }, // Inst #104 = IMPLICIT_DEF_GPRC 00189 { "IMPLICIT_DEF_VRRC", 1, 52, 0, 0, NULL, NULL, OperandInfo35 }, // Inst #105 = IMPLICIT_DEF_VRRC 00190 { "LA", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #106 = LA 00191 { "LBZ", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #107 = LBZ 00192 { "LBZ8", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #108 = LBZ8 00193 { "LBZX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #109 = LBZX 00194 { "LBZX8", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #110 = LBZX8 00195 { "LD", 3, 35, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #111 = LD 00196 { "LDX", 3, 35, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #112 = LDX 00197 { "LFD", 3, 37, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo40 }, // Inst #113 = LFD 00198 { "LFDX", 3, 38, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo41 }, // Inst #114 = LFDX 00199 { "LFS", 3, 38, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo42 }, // Inst #115 = LFS 00200 { "LFSX", 3, 38, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo43 }, // Inst #116 = LFSX 00201 { "LHA", 3, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #117 = LHA 00202 { "LHA8", 3, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #118 = LHA8 00203 { "LHAX", 3, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #119 = LHAX 00204 { "LHAX8", 3, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #120 = LHAX8 00205 { "LHBRX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #121 = LHBRX 00206 { "LHZ", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #122 = LHZ 00207 { "LHZ8", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #123 = LHZ8 00208 { "LHZX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #124 = LHZX 00209 { "LHZX8", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #125 = LHZX8 00210 { "LI", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo44 }, // Inst #126 = LI 00211 { "LI8", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo45 }, // Inst #127 = LI8 00212 { "LIS", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo44 }, // Inst #128 = LIS 00213 { "LIS8", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo45 }, // Inst #129 = LIS8 00214 { "LVEBX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #130 = LVEBX 00215 { "LVEHX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #131 = LVEHX 00216 { "LVEWX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #132 = LVEWX 00217 { "LVSL", 3, 33, 0, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #133 = LVSL 00218 { "LVSR", 3, 33, 0, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #134 = LVSR 00219 { "LVX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #135 = LVX 00220 { "LVXL", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #136 = LVXL 00221 { "LWA", 3, 42, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #137 = LWA 00222 { "LWAX", 3, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #138 = LWAX 00223 { "LWBRX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #139 = LWBRX 00224 { "LWZ", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #140 = LWZ 00225 { "LWZ8", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #141 = LWZ8 00226 { "LWZU", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo47 }, // Inst #142 = LWZU 00227 { "LWZX", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #143 = LWZX 00228 { "LWZX8", 3, 33, 0|M_LOAD_FLAG, 0|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #144 = LWZX8 00229 { "MCRF", 2, 2, 0, 0|1|(4<<3), NULL, NULL, OperandInfo48 }, // Inst #145 = MCRF 00230 { "MFCR", 1, 54, 0, 0|(4<<3), NULL, NULL, OperandInfo34 }, // Inst #146 = MFCR 00231 { "MFCTR", 1, 56, 0, 0|1|(1<<3), NULL, NULL, OperandInfo34 }, // Inst #147 = MFCTR 00232 { "MFLR", 1, 56, 0, 0|1|(1<<3), NULL, NULL, OperandInfo34 }, // Inst #148 = MFLR 00233 { "MFOCRF", 2, 54, 0, 0|1|(4<<3), NULL, NULL, OperandInfo44 }, // Inst #149 = MFOCRF 00234 { "MFVRSAVE", 1, 14, 0, 0|1|(1<<3), NULL, NULL, OperandInfo34 }, // Inst #150 = MFVRSAVE 00235 { "MFVSCR", 1, 33, 0, 0, NULL, NULL, OperandInfo35 }, // Inst #151 = MFVSCR 00236 { "MTCRF", 2, 3, 0, 0|(4<<3), NULL, NULL, OperandInfo49 }, // Inst #152 = MTCRF 00237 { "MTCTR", 1, 60, 0, 0|1|(1<<3), NULL, NULL, OperandInfo34 }, // Inst #153 = MTCTR 00238 { "MTCTR8", 1, 60, 0, 0|1|(1<<3), NULL, NULL, OperandInfo33 }, // Inst #154 = MTCTR8 00239 { "MTLR", 1, 60, 0, 0|1|(1<<3), NULL, NULL, OperandInfo34 }, // Inst #155 = MTLR 00240 { "MTVRSAVE", 1, 14, 0, 0|(1<<1)|(1<<3), NULL, NULL, OperandInfo34 }, // Inst #156 = MTVRSAVE 00241 { "MTVSCR", 1, 33, 0, 0, NULL, NULL, OperandInfo35 }, // Inst #157 = MTVSCR 00242 { "MULHD", 3, 20, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #158 = MULHD 00243 { "MULHDU", 3, 21, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #159 = MULHDU 00244 { "MULHW", 3, 20, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #160 = MULHW 00245 { "MULHWU", 3, 21, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #161 = MULHWU 00246 { "MULLD", 3, 19, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #162 = MULLD 00247 { "MULLI", 3, 22, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #163 = MULLI 00248 { "MULLW", 3, 20, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #164 = MULLW 00249 { "MovePCtoLR", 1, 52, 0, 0|(7<<3), NULL, ImplicitList3, OperandInfo7 }, // Inst #165 = MovePCtoLR 00250 { "NAND", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #166 = NAND 00251 { "NAND8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #167 = NAND8 00252 { "NEG", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #168 = NEG 00253 { "NOP", 0, 14, 0, 0|(1<<3), NULL, NULL, 0 }, // Inst #169 = NOP 00254 { "NOR", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #170 = NOR 00255 { "NOR8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #171 = NOR8 00256 { "OR", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #172 = OR 00257 { "OR4To8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo50 }, // Inst #173 = OR4To8 00258 { "OR8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #174 = OR8 00259 { "OR8To4", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo51 }, // Inst #175 = OR8To4 00260 { "ORC", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #176 = ORC 00261 { "ORC8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #177 = ORC8 00262 { "ORI", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #178 = ORI 00263 { "ORI8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #179 = ORI8 00264 { "ORIS", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #180 = ORIS 00265 { "ORIS8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #181 = ORIS8 00266 { "RLDICL", 4, 25, 0, 0|(1<<3), NULL, NULL, OperandInfo52 }, // Inst #182 = RLDICL 00267 { "RLDICR", 4, 25, 0, 0|(1<<3), NULL, NULL, OperandInfo52 }, // Inst #183 = RLDICR 00268 { "RLDIMI", 5, 25, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|(1<<3), NULL, NULL, OperandInfo53 }, // Inst #184 = RLDIMI 00269 { "RLWIMI", 6, 24, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|(1<<2)|(1<<3), NULL, NULL, OperandInfo54 }, // Inst #185 = RLWIMI 00270 { "RLWINM", 5, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo55 }, // Inst #186 = RLWINM 00271 { "RLWINMo", 5, 14, 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, OperandInfo55 }, // Inst #187 = RLWINMo 00272 { "RLWNM", 5, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo56 }, // Inst #188 = RLWNM 00273 { "SELECT_CC_F4", 5, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), NULL, NULL, OperandInfo57 }, // Inst #189 = SELECT_CC_F4 00274 { "SELECT_CC_F8", 5, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), NULL, NULL, OperandInfo58 }, // Inst #190 = SELECT_CC_F8 00275 { "SELECT_CC_I4", 5, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), NULL, NULL, OperandInfo59 }, // Inst #191 = SELECT_CC_I4 00276 { "SELECT_CC_I8", 5, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), NULL, NULL, OperandInfo60 }, // Inst #192 = SELECT_CC_I8 00277 { "SELECT_CC_VRRC", 5, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), NULL, NULL, OperandInfo61 }, // Inst #193 = SELECT_CC_VRRC 00278 { "SLD", 3, 25, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #194 = SLD 00279 { "SLW", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #195 = SLW 00280 { "SRAD", 3, 25, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #196 = SRAD 00281 { "SRADI", 3, 25, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #197 = SRADI 00282 { "SRAW", 3, 26, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #198 = SRAW 00283 { "SRAWI", 3, 26, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #199 = SRAWI 00284 { "SRD", 3, 25, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #200 = SRD 00285 { "SRW", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #201 = SRW 00286 { "STB", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #202 = STB 00287 { "STB8", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #203 = STB8 00288 { "STBX", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #204 = STBX 00289 { "STBX8", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #205 = STBX8 00290 { "STD", 3, 46, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #206 = STD 00291 { "STDUX", 3, 46, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #207 = STDUX 00292 { "STDX", 3, 46, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #208 = STDX 00293 { "STDX_32", 3, 46, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #209 = STDX_32 00294 { "STD_32", 3, 46, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #210 = STD_32 00295 { "STFD", 3, 51, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo40 }, // Inst #211 = STFD 00296 { "STFDX", 3, 51, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo41 }, // Inst #212 = STFDX 00297 { "STFIWX", 3, 51, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo41 }, // Inst #213 = STFIWX 00298 { "STFS", 3, 51, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo42 }, // Inst #214 = STFS 00299 { "STFSX", 3, 51, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo43 }, // Inst #215 = STFSX 00300 { "STH", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #216 = STH 00301 { "STH8", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #217 = STH8 00302 { "STHBRX", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #218 = STHBRX 00303 { "STHX", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #219 = STHX 00304 { "STHX8", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #220 = STHX8 00305 { "STVEBX", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #221 = STVEBX 00306 { "STVEHX", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #222 = STVEHX 00307 { "STVEWX", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #223 = STVEWX 00308 { "STVX", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #224 = STVX 00309 { "STVXL", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo46 }, // Inst #225 = STVXL 00310 { "STW", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo36 }, // Inst #226 = STW 00311 { "STW8", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo37 }, // Inst #227 = STW8 00312 { "STWBRX", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #228 = STWBRX 00313 { "STWU", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo47 }, // Inst #229 = STWU 00314 { "STWUX", 3, 33, 0|M_STORE_FLAG, 0|(2<<3), NULL, NULL, OperandInfo2 }, // Inst #230 = STWUX 00315 { "STWX", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo38 }, // Inst #231 = STWX 00316 { "STWX8", 3, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), NULL, NULL, OperandInfo39 }, // Inst #232 = STWX8 00317 { "SUBF", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #233 = SUBF 00318 { "SUBF8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #234 = SUBF8 00319 { "SUBFC", 3, 14, 0, 0|(1<<2)|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #235 = SUBFC 00320 { "SUBFE", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #236 = SUBFE 00321 { "SUBFIC", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #237 = SUBFIC 00322 { "SUBFIC8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #238 = SUBFIC8 00323 { "SUBFME", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #239 = SUBFME 00324 { "SUBFZE", 2, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo6 }, // Inst #240 = SUBFZE 00325 { "UPDATE_VRSAVE", 2, 52, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #241 = UPDATE_VRSAVE 00326 { "VADDCUW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #242 = VADDCUW 00327 { "VADDFP", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #243 = VADDFP 00328 { "VADDSBS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #244 = VADDSBS 00329 { "VADDSHS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #245 = VADDSHS 00330 { "VADDSWS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #246 = VADDSWS 00331 { "VADDUBM", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #247 = VADDUBM 00332 { "VADDUBS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #248 = VADDUBS 00333 { "VADDUHM", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #249 = VADDUHM 00334 { "VADDUHS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #250 = VADDUHS 00335 { "VADDUWM", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #251 = VADDUWM 00336 { "VADDUWS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #252 = VADDUWS 00337 { "VAND", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #253 = VAND 00338 { "VANDC", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #254 = VANDC 00339 { "VAVGSB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #255 = VAVGSB 00340 { "VAVGSH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #256 = VAVGSH 00341 { "VAVGSW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #257 = VAVGSW 00342 { "VAVGUB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #258 = VAVGUB 00343 { "VAVGUH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #259 = VAVGUH 00344 { "VAVGUW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #260 = VAVGUW 00345 { "VCFSX", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #261 = VCFSX 00346 { "VCFUX", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #262 = VCFUX 00347 { "VCMPBFP", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #263 = VCMPBFP 00348 { "VCMPBFPo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #264 = VCMPBFPo 00349 { "VCMPEQFP", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #265 = VCMPEQFP 00350 { "VCMPEQFPo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #266 = VCMPEQFPo 00351 { "VCMPEQUB", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #267 = VCMPEQUB 00352 { "VCMPEQUBo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #268 = VCMPEQUBo 00353 { "VCMPEQUH", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #269 = VCMPEQUH 00354 { "VCMPEQUHo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #270 = VCMPEQUHo 00355 { "VCMPEQUW", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #271 = VCMPEQUW 00356 { "VCMPEQUWo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #272 = VCMPEQUWo 00357 { "VCMPGEFP", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #273 = VCMPGEFP 00358 { "VCMPGEFPo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #274 = VCMPGEFPo 00359 { "VCMPGTFP", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #275 = VCMPGTFP 00360 { "VCMPGTFPo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #276 = VCMPGTFPo 00361 { "VCMPGTSB", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #277 = VCMPGTSB 00362 { "VCMPGTSBo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #278 = VCMPGTSBo 00363 { "VCMPGTSH", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #279 = VCMPGTSH 00364 { "VCMPGTSHo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #280 = VCMPGTSHo 00365 { "VCMPGTSW", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #281 = VCMPGTSW 00366 { "VCMPGTSWo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #282 = VCMPGTSWo 00367 { "VCMPGTUB", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #283 = VCMPGTUB 00368 { "VCMPGTUBo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #284 = VCMPGTUBo 00369 { "VCMPGTUH", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #285 = VCMPGTUH 00370 { "VCMPGTUHo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #286 = VCMPGTUHo 00371 { "VCMPGTUW", 3, 68, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #287 = VCMPGTUW 00372 { "VCMPGTUWo", 3, 68, 0, 0|(5<<3), NULL, ImplicitList4, OperandInfo62 }, // Inst #288 = VCMPGTUWo 00373 { "VCTSXS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #289 = VCTSXS 00374 { "VCTUXS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #290 = VCTUXS 00375 { "VEXPTEFP", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #291 = VEXPTEFP 00376 { "VLOGEFP", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #292 = VLOGEFP 00377 { "VMADDFP", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #293 = VMADDFP 00378 { "VMAXFP", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #294 = VMAXFP 00379 { "VMAXSB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #295 = VMAXSB 00380 { "VMAXSH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #296 = VMAXSH 00381 { "VMAXSW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #297 = VMAXSW 00382 { "VMAXUB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #298 = VMAXUB 00383 { "VMAXUH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #299 = VMAXUH 00384 { "VMAXUW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #300 = VMAXUW 00385 { "VMHADDSHS", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #301 = VMHADDSHS 00386 { "VMHRADDSHS", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #302 = VMHRADDSHS 00387 { "VMINFP", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #303 = VMINFP 00388 { "VMINSB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #304 = VMINSB 00389 { "VMINSH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #305 = VMINSH 00390 { "VMINSW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #306 = VMINSW 00391 { "VMINUB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #307 = VMINUB 00392 { "VMINUH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #308 = VMINUH 00393 { "VMINUW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #309 = VMINUW 00394 { "VMLADDUHM", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #310 = VMLADDUHM 00395 { "VMRGHB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #311 = VMRGHB 00396 { "VMRGHH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #312 = VMRGHH 00397 { "VMRGHW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #313 = VMRGHW 00398 { "VMRGLB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #314 = VMRGLB 00399 { "VMRGLH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #315 = VMRGLH 00400 { "VMRGLW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #316 = VMRGLW 00401 { "VMSUMMBM", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #317 = VMSUMMBM 00402 { "VMSUMSHM", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #318 = VMSUMSHM 00403 { "VMSUMSHS", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #319 = VMSUMSHS 00404 { "VMSUMUBM", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #320 = VMSUMUBM 00405 { "VMSUMUHM", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #321 = VMSUMUHM 00406 { "VMSUMUHS", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #322 = VMSUMUHS 00407 { "VMULESB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #323 = VMULESB 00408 { "VMULESH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #324 = VMULESH 00409 { "VMULEUB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #325 = VMULEUB 00410 { "VMULEUH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #326 = VMULEUH 00411 { "VMULOSB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #327 = VMULOSB 00412 { "VMULOSH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #328 = VMULOSH 00413 { "VMULOUB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #329 = VMULOUB 00414 { "VMULOUH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #330 = VMULOUH 00415 { "VNMSUBFP", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #331 = VNMSUBFP 00416 { "VNOR", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #332 = VNOR 00417 { "VOR", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #333 = VOR 00418 { "VPERM", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #334 = VPERM 00419 { "VPKPX", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #335 = VPKPX 00420 { "VPKSHSS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #336 = VPKSHSS 00421 { "VPKSHUS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #337 = VPKSHUS 00422 { "VPKSWSS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #338 = VPKSWSS 00423 { "VPKSWUS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #339 = VPKSWUS 00424 { "VPKUHUM", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #340 = VPKUHUM 00425 { "VPKUHUS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #341 = VPKUHUS 00426 { "VPKUWUM", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #342 = VPKUWUM 00427 { "VPKUWUS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #343 = VPKUWUS 00428 { "VREFP", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #344 = VREFP 00429 { "VRFIM", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #345 = VRFIM 00430 { "VRFIN", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #346 = VRFIN 00431 { "VRFIP", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #347 = VRFIP 00432 { "VRFIZ", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #348 = VRFIZ 00433 { "VRLB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #349 = VRLB 00434 { "VRLH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #350 = VRLH 00435 { "VRLW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #351 = VRLW 00436 { "VRSQRTEFP", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #352 = VRSQRTEFP 00437 { "VSEL", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo65 }, // Inst #353 = VSEL 00438 { "VSL", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #354 = VSL 00439 { "VSLB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #355 = VSLB 00440 { "VSLDOI", 4, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo66 }, // Inst #356 = VSLDOI 00441 { "VSLH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #357 = VSLH 00442 { "VSLO", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #358 = VSLO 00443 { "VSLW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #359 = VSLW 00444 { "VSPLTB", 3, 71, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #360 = VSPLTB 00445 { "VSPLTH", 3, 71, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #361 = VSPLTH 00446 { "VSPLTISB", 2, 71, 0, 0|(5<<3), NULL, NULL, OperandInfo67 }, // Inst #362 = VSPLTISB 00447 { "VSPLTISH", 2, 71, 0, 0|(5<<3), NULL, NULL, OperandInfo67 }, // Inst #363 = VSPLTISH 00448 { "VSPLTISW", 2, 71, 0, 0|(5<<3), NULL, NULL, OperandInfo67 }, // Inst #364 = VSPLTISW 00449 { "VSPLTW", 3, 71, 0, 0|(5<<3), NULL, NULL, OperandInfo63 }, // Inst #365 = VSPLTW 00450 { "VSR", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #366 = VSR 00451 { "VSRAB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #367 = VSRAB 00452 { "VSRAH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #368 = VSRAH 00453 { "VSRAW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #369 = VSRAW 00454 { "VSRB", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #370 = VSRB 00455 { "VSRH", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #371 = VSRH 00456 { "VSRO", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #372 = VSRO 00457 { "VSRW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #373 = VSRW 00458 { "VSUBCUW", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #374 = VSUBCUW 00459 { "VSUBFP", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #375 = VSUBFP 00460 { "VSUBSBS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #376 = VSUBSBS 00461 { "VSUBSHS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #377 = VSUBSHS 00462 { "VSUBSWS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #378 = VSUBSWS 00463 { "VSUBUBM", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #379 = VSUBUBM 00464 { "VSUBUBS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #380 = VSUBUBS 00465 { "VSUBUHM", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #381 = VSUBUHM 00466 { "VSUBUHS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #382 = VSUBUHS 00467 { "VSUBUWM", 3, 70, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #383 = VSUBUWM 00468 { "VSUBUWS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #384 = VSUBUWS 00469 { "VSUM2SWS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #385 = VSUM2SWS 00470 { "VSUM4SBS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #386 = VSUM4SBS 00471 { "VSUM4SHS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #387 = VSUM4SHS 00472 { "VSUM4UBS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #388 = VSUM4UBS 00473 { "VSUMSWS", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #389 = VSUMSWS 00474 { "VUPKHPX", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #390 = VUPKHPX 00475 { "VUPKHSB", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #391 = VUPKHSB 00476 { "VUPKHSH", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #392 = VUPKHSH 00477 { "VUPKLPX", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #393 = VUPKLPX 00478 { "VUPKLSB", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #394 = VUPKLSB 00479 { "VUPKLSH", 2, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo64 }, // Inst #395 = VUPKLSH 00480 { "VXOR", 3, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo62 }, // Inst #396 = VXOR 00481 { "V_SET0", 1, 67, 0, 0|(5<<3), NULL, NULL, OperandInfo35 }, // Inst #397 = V_SET0 00482 { "XOR", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo2 }, // Inst #398 = XOR 00483 { "XOR8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo3 }, // Inst #399 = XOR8 00484 { "XORI", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #400 = XORI 00485 { "XORI8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #401 = XORI8 00486 { "XORIS", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo4 }, // Inst #402 = XORIS 00487 { "XORIS8", 3, 14, 0, 0|(1<<3), NULL, NULL, OperandInfo5 }, // Inst #403 = XORIS8 00488 }; 00489 } // End llvm namespace