LLVM API Documentation

llvm::TargetInstrInfo Class Reference

#include <TargetInstrInfo.h>

Inheritance diagram for llvm::TargetInstrInfo:

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List of all members.

Public Types

enum  { PHI = 0, INLINEASM = 1 }

Public Member Functions

 TargetInstrInfo (const TargetInstrDescriptor *desc, unsigned NumOpcodes)
virtual ~TargetInstrInfo ()
unsigned getNumOpcodes () const
const TargetInstrDescriptorget (MachineOpCode Opcode) const
const char * getName (MachineOpCode Opcode) const
int getNumOperands (MachineOpCode Opcode) const
InstrSchedClass getSchedClass (MachineOpCode Opcode) const
const unsigned * getImplicitUses (MachineOpCode Opcode) const
const unsigned * getImplicitDefs (MachineOpCode Opcode) const
bool isReturn (MachineOpCode Opcode) const
bool isTwoAddrInstr (MachineOpCode Opcode) const
bool isCommutableInstr (MachineOpCode Opcode) const
bool isTerminatorInstr (unsigned Opcode) const
bool isBranch (MachineOpCode Opcode) const
bool isBarrier (MachineOpCode Opcode) const
bool isCall (MachineOpCode Opcode) const
bool isLoad (MachineOpCode Opcode) const
bool isStore (MachineOpCode Opcode) const
bool usesCustomDAGSchedInsertionHook (unsigned Opcode) const
bool hasVariableOperands (MachineOpCode Opcode) const
virtual bool isMoveInstr (const MachineInstr &MI, unsigned &sourceReg, unsigned &destReg) const
virtual unsigned isLoadFromStackSlot (MachineInstr *MI, int &FrameIndex) const
virtual unsigned isStoreToStackSlot (MachineInstr *MI, int &FrameIndex) const
virtual MachineInstrconvertToThreeAddress (MachineInstr *TA) const
virtual MachineInstrcommuteInstruction (MachineInstr *MI) const
virtual void insertGoto (MachineBasicBlock &MBB, MachineBasicBlock &TMBB) const
virtual MachineBasicBlock::iterator reverseBranchCondition (MachineBasicBlock::iterator MI) const
virtual void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
virtual const TargetRegisterClassgetPointerRegClass () const
bool hasDelaySlot (unsigned Opcode) const

Detailed Description

TargetInstrInfo - Interface to description of machine instructions

Definition at line 118 of file TargetInstrInfo.h.


Member Enumeration Documentation

anonymous enum

Enumerator:
PHI 
INLINEASM 

Definition at line 130 of file TargetInstrInfo.h.


Constructor & Destructor Documentation

TargetInstrInfo::TargetInstrInfo ( const TargetInstrDescriptor desc,
unsigned  NumOpcodes 
)

Definition at line 28 of file TargetInstrInfo.cpp.

References llvm::TargetInstrDescriptors.

TargetInstrInfo::~TargetInstrInfo (  )  [virtual]

Definition at line 37 of file TargetInstrInfo.cpp.

References llvm::TargetInstrDescriptors.


Member Function Documentation

unsigned llvm::TargetInstrInfo::getNumOpcodes (  )  const [inline]

Definition at line 135 of file TargetInstrInfo.h.

const TargetInstrDescriptor& llvm::TargetInstrInfo::get ( MachineOpCode  Opcode  )  const [inline]

get - Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Definition at line 140 of file TargetInstrInfo.h.

Referenced by llvm::ScheduleDAG::EmitNode(), llvm::X86InstrInfo::getBaseOpcodeFor(), getImplicitDefs(), getImplicitUses(), getName(), getNumOperands(), getRegClass(), getSchedClass(), hasDelaySlot(), hasVariableOperands(), isBarrier(), isBranch(), isCall(), isCommutableInstr(), isLoad(), isReturn(), isStore(), isTerminatorInstr(), isTwoAddrInstr(), llvm::LiveVariables::runOnMachineFunction(), and usesCustomDAGSchedInsertionHook().

const char* llvm::TargetInstrInfo::getName ( MachineOpCode  Opcode  )  const [inline]

Definition at line 145 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::Name.

Referenced by llvm::CloneBasicBlock(), llvm::SDNode::getOperationName(), llvm::MachineInstr::print(), and llvm::SimplifyCFG().

int llvm::TargetInstrInfo::getNumOperands ( MachineOpCode  Opcode  )  const [inline]

Definition at line 149 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::numOperands.

InstrSchedClass llvm::TargetInstrInfo::getSchedClass ( MachineOpCode  Opcode  )  const [inline]

Definition at line 153 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::schedClass.

Referenced by llvm::ScheduleDAG::BuildSchedUnits().

const unsigned* llvm::TargetInstrInfo::getImplicitUses ( MachineOpCode  Opcode  )  const [inline]

Definition at line 157 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::ImplicitUses.

const unsigned* llvm::TargetInstrInfo::getImplicitDefs ( MachineOpCode  Opcode  )  const [inline]

Definition at line 161 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::ImplicitDefs.

bool llvm::TargetInstrInfo::isReturn ( MachineOpCode  Opcode  )  const [inline]

Definition at line 170 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_RET_FLAG.

Referenced by RemoveVRSaveCode(), and llvm::LiveVariables::runOnMachineFunction().

bool llvm::TargetInstrInfo::isTwoAddrInstr ( MachineOpCode  Opcode  )  const [inline]

Definition at line 174 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_2_ADDR_FLAG.

Referenced by llvm::ScheduleDAG::BuildSchedUnits().

bool llvm::TargetInstrInfo::isCommutableInstr ( MachineOpCode  Opcode  )  const [inline]

Definition at line 177 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_COMMUTABLE.

Referenced by llvm::ScheduleDAG::BuildSchedUnits().

bool llvm::TargetInstrInfo::isTerminatorInstr ( unsigned  Opcode  )  const [inline]

Definition at line 180 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_TERMINATOR_FLAG.

Referenced by llvm::MachineBasicBlock::getFirstTerminator(), and ReplaceUsesOfBlockWith().

bool llvm::TargetInstrInfo::isBranch ( MachineOpCode  Opcode  )  const [inline]

Definition at line 184 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_BRANCH_FLAG.

Referenced by llvm::X86InstrInfo::reverseBranchCondition().

bool llvm::TargetInstrInfo::isBarrier ( MachineOpCode  Opcode  )  const [inline]

isBarrier - Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.

Definition at line 191 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_BARRIER_FLAG.

bool llvm::TargetInstrInfo::isCall ( MachineOpCode  Opcode  )  const [inline]

Definition at line 195 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_CALL_FLAG.

bool llvm::TargetInstrInfo::isLoad ( MachineOpCode  Opcode  )  const [inline]

Definition at line 198 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_LOAD_FLAG.

bool llvm::TargetInstrInfo::isStore ( MachineOpCode  Opcode  )  const [inline]

Definition at line 201 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_STORE_FLAG.

bool llvm::TargetInstrInfo::usesCustomDAGSchedInsertionHook ( unsigned  Opcode  )  const [inline]

usesCustomDAGSchedInsertionHook - Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.

Definition at line 208 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_USES_CUSTOM_DAG_SCHED_INSERTION.

bool llvm::TargetInstrInfo::hasVariableOperands ( MachineOpCode  Opcode  )  const [inline]

Definition at line 212 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_VARIABLE_OPS.

virtual bool llvm::TargetInstrInfo::isMoveInstr ( const MachineInstr MI,
unsigned &  sourceReg,
unsigned &  destReg 
) const [inline, virtual]

Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.

Reimplemented in llvm::AlphaInstrInfo, llvm::ARMInstrInfo, llvm::IA64InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.

Definition at line 218 of file TargetInstrInfo.h.

Referenced by llvm::LiveIntervals::runOnMachineFunction().

virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlot ( MachineInstr MI,
int &  FrameIndex 
) const [inline, virtual]

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Reimplemented in llvm::AlphaInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.

Definition at line 229 of file TargetInstrInfo.h.

virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlot ( MachineInstr MI,
int &  FrameIndex 
) const [inline, virtual]

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Reimplemented in llvm::AlphaInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.

Definition at line 238 of file TargetInstrInfo.h.

virtual MachineInstr* llvm::TargetInstrInfo::convertToThreeAddress ( MachineInstr TA  )  const [inline, virtual]

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

Reimplemented in llvm::X86InstrInfo.

Definition at line 252 of file TargetInstrInfo.h.

MachineInstr * TargetInstrInfo::commuteInstruction ( MachineInstr MI  )  const [virtual]

commuteInstruction - If a target has any instructions that are commutable, but require converting to a different instruction or making non-trivial changes to commute them, this method can overloaded to do this. The default implementation of this method simply swaps the first two operands of MI and returns it.

If a target wants to make more aggressive changes, they can construct and return a new machine instruction. If an instruction cannot commute, it can also return null.

Reimplemented in llvm::PPCInstrInfo, and llvm::X86InstrInfo.

Definition at line 44 of file TargetInstrInfo.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isRegister(), MI, and llvm::MachineOperand::setReg().

Referenced by llvm::X86InstrInfo::commuteInstruction(), llvm::PPCInstrInfo::commuteInstruction(), and llvm::ScheduleDAG::EmitNode().

virtual void llvm::TargetInstrInfo::insertGoto ( MachineBasicBlock MBB,
MachineBasicBlock TMBB 
) const [inline, virtual]

Insert a goto (unconditional branch) sequence to TMBB, at the end of MBB

Reimplemented in llvm::X86InstrInfo.

Definition at line 270 of file TargetInstrInfo.h.

Referenced by ReplaceUsesOfBlockWith().

virtual MachineBasicBlock::iterator llvm::TargetInstrInfo::reverseBranchCondition ( MachineBasicBlock::iterator  MI  )  const [inline, virtual]

Reverses the branch condition of the MachineInstr pointed by MI. The instruction is replaced and the new MI is returned.

Reimplemented in llvm::X86InstrInfo.

Definition at line 278 of file TargetInstrInfo.h.

virtual void llvm::TargetInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const [inline, virtual]

insertNoop - Insert a noop into the instruction stream at the specified point.

Reimplemented in llvm::PPCInstrInfo.

Definition at line 286 of file TargetInstrInfo.h.

Referenced by llvm::ScheduleDAG::EmitNoop().

virtual const TargetRegisterClass* llvm::TargetInstrInfo::getPointerRegClass (  )  const [inline, virtual]

getPointerRegClass - Returns a TargetRegisterClass used for pointer values.

Reimplemented in llvm::PPCInstrInfo.

Definition at line 294 of file TargetInstrInfo.h.

Referenced by getInstrOperandRegClass().

bool llvm::TargetInstrInfo::hasDelaySlot ( unsigned  Opcode  )  const [inline]

hasDelaySlot - Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 301 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_DELAY_SLOT_FLAG.


The documentation for this class was generated from the following files: