LLVM API Documentation
00001 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the Alpha implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "Alpha.h" 00015 #include "AlphaInstrInfo.h" 00016 #include "AlphaGenInstrInfo.inc" 00017 #include "llvm/CodeGen/MachineInstrBuilder.h" 00018 #include <iostream> 00019 using namespace llvm; 00020 00021 AlphaInstrInfo::AlphaInstrInfo() 00022 : TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { } 00023 00024 00025 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, 00026 unsigned& sourceReg, 00027 unsigned& destReg) const { 00028 MachineOpCode oc = MI.getOpcode(); 00029 if (oc == Alpha::BIS || 00030 oc == Alpha::CPYSS || 00031 oc == Alpha::CPYST || 00032 oc == Alpha::CPYSSt || 00033 oc == Alpha::CPYSTs) { 00034 // or r1, r2, r2 00035 // cpys(s|t) r1 r2 r2 00036 assert(MI.getNumOperands() == 3 && 00037 MI.getOperand(0).isRegister() && 00038 MI.getOperand(1).isRegister() && 00039 MI.getOperand(2).isRegister() && 00040 "invalid Alpha BIS instruction!"); 00041 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 00042 sourceReg = MI.getOperand(1).getReg(); 00043 destReg = MI.getOperand(0).getReg(); 00044 return true; 00045 } 00046 } 00047 return false; 00048 } 00049 00050 unsigned 00051 AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { 00052 switch (MI->getOpcode()) { 00053 case Alpha::LDL: 00054 case Alpha::LDQ: 00055 case Alpha::LDBU: 00056 case Alpha::LDWU: 00057 case Alpha::LDS: 00058 case Alpha::LDT: 00059 if (MI->getOperand(1).isFrameIndex()) { 00060 FrameIndex = MI->getOperand(1).getFrameIndex(); 00061 return MI->getOperand(0).getReg(); 00062 } 00063 break; 00064 } 00065 return 0; 00066 } 00067 00068 unsigned 00069 AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 00070 switch (MI->getOpcode()) { 00071 case Alpha::STL: 00072 case Alpha::STQ: 00073 case Alpha::STB: 00074 case Alpha::STW: 00075 case Alpha::STS: 00076 case Alpha::STT: 00077 if (MI->getOperand(1).isFrameIndex()) { 00078 FrameIndex = MI->getOperand(1).getFrameIndex(); 00079 return MI->getOperand(0).getReg(); 00080 } 00081 break; 00082 } 00083 return 0; 00084 } 00085