addLegalAddressScale(unsigned Scale) | llvm::TargetLowering | [inline, protected] |
addLegalFPImmediate(double Imm) | llvm::TargetLowering | [inline, protected] |
AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, MVT::ValueType DestVT) | llvm::TargetLowering | [inline, protected] |
addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) | llvm::TargetLowering | [inline, protected] |
allowsUnalignedMemoryAccesses() const | llvm::TargetLowering | [inline] |
allowUnalignedMemoryAccesses | llvm::TargetLowering | [protected] |
ArgListTy typedef | llvm::TargetLowering | |
BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector< SDNode * > *Created) const | llvm::TargetLowering | |
BuildUDIV(SDNode *N, SelectionDAG &DAG, std::vector< SDNode * > *Created) const | llvm::TargetLowering | |
C_Memory enum value | llvm::TargetLowering | |
C_Other enum value | llvm::TargetLowering | |
C_Register enum value | llvm::TargetLowering | |
C_RegisterClass enum value | llvm::TargetLowering | |
C_Unknown enum value | llvm::TargetLowering | |
ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const | llvm::TargetLowering | |
computeMaskedBitsForTargetNode(const SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const | llvm::X86TargetLowering | [virtual] |
ComputeNumSignBits(SDOperand Op, unsigned Depth=0) const | llvm::TargetLowering | |
ComputeNumSignBitsForTargetNode(SDOperand Op, unsigned Depth=0) const | llvm::TargetLowering | [virtual] |
computeRegisterProperties() | llvm::TargetLowering | [protected] |
ConstraintType enum name | llvm::TargetLowering | |
Custom enum value | llvm::TargetLowering | |
CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG) | llvm::TargetLowering | [virtual] |
Expand enum value | llvm::TargetLowering | |
Extend enum value | llvm::TargetLowering | |
getBytesCallerReserves() const | llvm::X86TargetLowering | [inline] |
getBytesToPopOnReturn() const | llvm::X86TargetLowering | [inline] |
getConstraintType(char ConstraintLetter) const | llvm::X86TargetLowering | [virtual] |
getMaxStoresPerMemcpy() const | llvm::TargetLowering | [inline] |
getMaxStoresPerMemmove() const | llvm::TargetLowering | [inline] |
getMaxStoresPerMemset() const | llvm::TargetLowering | [inline] |
getNumElements(MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
getOperationAction(unsigned Op, MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
getPackedTypeBreakdown(const PackedType *PTy, MVT::ValueType &PTyElementVT, MVT::ValueType &PTyLegalElementVT) const | llvm::TargetLowering | |
getPointerTy() const | llvm::TargetLowering | [inline] |
getRegClassFor(MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const | llvm::X86TargetLowering | [virtual] |
getRegForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const | llvm::TargetLowering | [virtual] |
getReturnAddressFrameIndex(SelectionDAG &DAG) | llvm::X86TargetLowering | |
getSchedulingPreference() const | llvm::TargetLowering | [inline] |
getSetCCResultContents() const | llvm::TargetLowering | [inline] |
getSetCCResultTy() const | llvm::TargetLowering | [inline] |
getShiftAmountFlavor() const | llvm::TargetLowering | [inline] |
getShiftAmountTy() const | llvm::TargetLowering | [inline] |
getStackPointerRegisterToSaveRestore() const | llvm::TargetLowering | [inline] |
getTargetData() const | llvm::TargetLowering | [inline] |
getTargetMachine() const | llvm::TargetLowering | [inline] |
getTargetNodeName(unsigned Opcode) const | llvm::X86TargetLowering | [virtual] |
getTypeAction(MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
getTypeToTransformTo(MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
getValueType(const Type *Ty) const | llvm::TargetLowering | [inline] |
getValueTypeActions() const | llvm::TargetLowering | [inline] |
hasTargetDAGCombine(ISD::NodeType NT) const | llvm::TargetLowering | [inline] |
InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *MBB) | llvm::X86TargetLowering | [virtual] |
isIntDivCheap() const | llvm::TargetLowering | [inline] |
isLegalAddressImmediate(int64_t V) const | llvm::X86TargetLowering | [virtual] |
isLegalAddressImmediate(GlobalValue *GV) const | llvm::X86TargetLowering | [virtual] |
isLittleEndian() const | llvm::TargetLowering | [inline] |
isOperandValidForConstraint(SDOperand Op, char ConstraintLetter) | llvm::TargetLowering | [virtual] |
isOperationLegal(unsigned Op, MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
isPow2DivCheap() const | llvm::TargetLowering | [inline] |
isSetCCExpensive() const | llvm::TargetLowering | [inline] |
isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const | llvm::X86TargetLowering | [virtual] |
isTypeLegal(MVT::ValueType VT) const | llvm::TargetLowering | [inline] |
isVectorClearMaskLegal(std::vector< SDOperand > &BVOps, MVT::ValueType EVT, SelectionDAG &DAG) const | llvm::X86TargetLowering | [virtual] |
Legal enum value | llvm::TargetLowering | |
legal_am_scale_begin() const | llvm::TargetLowering | [inline] |
legal_am_scale_end() const | llvm::TargetLowering | [inline] |
legal_am_scale_iterator typedef | llvm::TargetLowering | |
legal_fpimm_begin() const | llvm::TargetLowering | [inline] |
legal_fpimm_end() const | llvm::TargetLowering | [inline] |
legal_fpimm_iterator typedef | llvm::TargetLowering | |
LegalizeAction enum name | llvm::TargetLowering | |
LowerArguments(Function &F, SelectionDAG &DAG) | llvm::TargetLowering | [virtual] |
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) | llvm::TargetLowering | [virtual] |
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG) | llvm::X86TargetLowering | [virtual] |
LowerOperation(SDOperand Op, SelectionDAG &DAG) | llvm::X86TargetLowering | [virtual] |
Mask enum value | llvm::TargetLowering | |
MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth=0) const | llvm::TargetLowering | |
maxStoresPerMemcpy | llvm::TargetLowering | [protected] |
maxStoresPerMemmove | llvm::TargetLowering | [protected] |
maxStoresPerMemset | llvm::TargetLowering | [protected] |
OutOfRangeShiftAmount enum name | llvm::TargetLowering | |
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::X86TargetLowering | [virtual] |
llvm::TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::TargetLowering | [virtual] |
Promote enum value | llvm::TargetLowering | |
SchedPreference enum name | llvm::TargetLowering | |
SchedulingForLatency enum value | llvm::TargetLowering | |
SchedulingForRegPressure enum value | llvm::TargetLowering | |
SetCCResultValue enum name | llvm::TargetLowering | |
setIntDivIsCheap(bool isCheap=true) | llvm::TargetLowering | [inline, protected] |
setOperationAction(unsigned Op, MVT::ValueType VT, LegalizeAction Action) | llvm::TargetLowering | [inline, protected] |
setPow2DivIsCheap(bool isCheap=true) | llvm::TargetLowering | [inline, protected] |
setSchedulingPreference(SchedPreference Pref) | llvm::TargetLowering | [inline, protected] |
setSetCCIsExpensive() | llvm::TargetLowering | [inline, protected] |
setSetCCResultContents(SetCCResultValue Ty) | llvm::TargetLowering | [inline, protected] |
setSetCCResultType(MVT::ValueType VT) | llvm::TargetLowering | [inline, protected] |
setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) | llvm::TargetLowering | [inline, protected] |
setShiftAmountType(MVT::ValueType VT) | llvm::TargetLowering | [inline, protected] |
setStackPointerRegisterToSaveRestore(unsigned R) | llvm::TargetLowering | [inline, protected] |
setTargetDAGCombine(ISD::NodeType NT) | llvm::TargetLowering | [inline, protected] |
setUseUnderscoreSetJmpLongJmp(bool Val) | llvm::TargetLowering | [inline, protected] |
SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, uint64_t &KnownZero, uint64_t &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | |
TargetLowering(TargetMachine &TM) | llvm::TargetLowering | |
Undefined enum value | llvm::TargetLowering | |
UndefinedSetCCResult enum value | llvm::TargetLowering | |
usesUnderscoreSetJmpLongJmp() const | llvm::TargetLowering | [inline] |
X86TargetLowering(TargetMachine &TM) | llvm::X86TargetLowering | |
ZeroOrNegativeOneSetCCResult enum value | llvm::TargetLowering | |
ZeroOrOneSetCCResult enum value | llvm::TargetLowering | |
~TargetLowering() | llvm::TargetLowering | [virtual] |