LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // IntRegs Register Class... 00013 static const unsigned IntRegs[] = { 00014 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::R13, ARM::R14, ARM::R15, 00015 }; 00016 00017 // IntRegsVTs Register Class Value Types... 00018 static const MVT::ValueType IntRegsVTs[] = { 00019 MVT::i32, MVT::Other 00020 }; 00021 00022 } // end anonymous namespace 00023 00024 namespace ARM { // Register class instances 00025 IntRegsClass IntRegsRegClass; 00026 00027 // IntRegs Register Class sub-classes... 00028 static const TargetRegisterClass* const IntRegsSubclasses [] = { 00029 NULL 00030 }; 00031 00032 // IntRegs Register Class super-classes... 00033 static const TargetRegisterClass* const IntRegsSuperclasses [] = { 00034 NULL 00035 }; 00036 00037 00038 IntRegsClass::iterator 00039 IntRegsClass::allocation_order_end(MachineFunction &MF) const { 00040 // r15 == Program Counter 00041 // r14 == Link Register 00042 // r13 == Stack Pointer 00043 // r12 == ip (scratch) 00044 // r11 == Frame Pointer 00045 // r10 == Stack Limit 00046 return end() - 4; 00047 } 00048 00049 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID, IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, 4, 4, IntRegs, IntRegs + 16) {} 00050 } 00051 00052 namespace { 00053 const TargetRegisterClass* const RegisterClasses[] = { 00054 &ARM::IntRegsRegClass, 00055 }; 00056 const unsigned Empty_AliasSet[] = { 0 }; 00057 00058 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00059 { "NOREG", 0 }, 00060 { "R0", Empty_AliasSet }, 00061 { "R1", Empty_AliasSet }, 00062 { "R10", Empty_AliasSet }, 00063 { "R11", Empty_AliasSet }, 00064 { "R12", Empty_AliasSet }, 00065 { "R13", Empty_AliasSet }, 00066 { "R14", Empty_AliasSet }, 00067 { "R15", Empty_AliasSet }, 00068 { "R2", Empty_AliasSet }, 00069 { "R3", Empty_AliasSet }, 00070 { "R4", Empty_AliasSet }, 00071 { "R5", Empty_AliasSet }, 00072 { "R6", Empty_AliasSet }, 00073 { "R7", Empty_AliasSet }, 00074 { "R8", Empty_AliasSet }, 00075 { "R9", Empty_AliasSet }, 00076 }; 00077 } 00078 00079 ARMGenRegisterInfo::ARMGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00080 : MRegisterInfo(RegisterDescriptors, 17, RegisterClasses, RegisterClasses+1, 00081 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00082 00083 int ARMGenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00084 static const int DwarfRegNums[] = { -1, // NoRegister 00085 0, 1, 10, 11, 12, 13, 14, 15, 2, 3, 4, 5, 6, 7, 8, 9 00086 }; 00087 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00088 "RegNum exceeds number of registers"); 00089 return DwarfRegNums[RegNum]; 00090 } 00091 00092 } // End llvm namespace