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SparcISelDAGToDAG.cpp

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00001 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Chris Lattner and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines an instruction selector for the SPARC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "Sparc.h"
00015 #include "SparcTargetMachine.h"
00016 #include "llvm/DerivedTypes.h"
00017 #include "llvm/Function.h"
00018 #include "llvm/Intrinsics.h"
00019 #include "llvm/CodeGen/MachineFrameInfo.h"
00020 #include "llvm/CodeGen/MachineFunction.h"
00021 #include "llvm/CodeGen/MachineInstrBuilder.h"
00022 #include "llvm/CodeGen/SelectionDAG.h"
00023 #include "llvm/CodeGen/SelectionDAGISel.h"
00024 #include "llvm/CodeGen/SSARegMap.h"
00025 #include "llvm/Target/TargetLowering.h"
00026 #include "llvm/Support/Debug.h"
00027 #include <iostream>
00028 #include <set>
00029 using namespace llvm;
00030 
00031 //===----------------------------------------------------------------------===//
00032 // TargetLowering Implementation
00033 //===----------------------------------------------------------------------===//
00034 
00035 namespace SPISD {
00036   enum {
00037     FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
00038     CMPICC,      // Compare two GPR operands, set icc.
00039     CMPFCC,      // Compare two FP operands, set fcc.
00040     BRICC,       // Branch to dest on icc condition
00041     BRFCC,       // Branch to dest on fcc condition
00042     SELECT_ICC,  // Select between two values using the current ICC flags.
00043     SELECT_FCC,  // Select between two values using the current FCC flags.
00044     
00045     Hi, Lo,      // Hi/Lo operations, typically on a global address.
00046     
00047     FTOI,        // FP to Int within a FP register.
00048     ITOF,        // Int to FP within a FP register.
00049 
00050     CALL,        // A call instruction.
00051     RET_FLAG     // Return with a flag operand.
00052   };
00053 }
00054 
00055 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
00056 /// condition.
00057 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
00058   switch (CC) {
00059   default: assert(0 && "Unknown integer condition code!");
00060   case ISD::SETEQ:  return SPCC::ICC_E;
00061   case ISD::SETNE:  return SPCC::ICC_NE;
00062   case ISD::SETLT:  return SPCC::ICC_L;
00063   case ISD::SETGT:  return SPCC::ICC_G;
00064   case ISD::SETLE:  return SPCC::ICC_LE;
00065   case ISD::SETGE:  return SPCC::ICC_GE;
00066   case ISD::SETULT: return SPCC::ICC_CS;
00067   case ISD::SETULE: return SPCC::ICC_LEU;
00068   case ISD::SETUGT: return SPCC::ICC_GU;
00069   case ISD::SETUGE: return SPCC::ICC_CC;
00070   }
00071 }
00072 
00073 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
00074 /// FCC condition.
00075 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
00076   switch (CC) {
00077   default: assert(0 && "Unknown fp condition code!");
00078   case ISD::SETEQ:
00079   case ISD::SETOEQ: return SPCC::FCC_E;
00080   case ISD::SETNE:
00081   case ISD::SETUNE: return SPCC::FCC_NE;
00082   case ISD::SETLT:
00083   case ISD::SETOLT: return SPCC::FCC_L;
00084   case ISD::SETGT:
00085   case ISD::SETOGT: return SPCC::FCC_G;
00086   case ISD::SETLE:
00087   case ISD::SETOLE: return SPCC::FCC_LE;
00088   case ISD::SETGE:
00089   case ISD::SETOGE: return SPCC::FCC_GE;
00090   case ISD::SETULT: return SPCC::FCC_UL;
00091   case ISD::SETULE: return SPCC::FCC_ULE;
00092   case ISD::SETUGT: return SPCC::FCC_UG;
00093   case ISD::SETUGE: return SPCC::FCC_UGE;
00094   case ISD::SETUO:  return SPCC::FCC_U;
00095   case ISD::SETO:   return SPCC::FCC_O;
00096   case ISD::SETONE: return SPCC::FCC_LG;
00097   case ISD::SETUEQ: return SPCC::FCC_UE;
00098   }
00099 }
00100 
00101 namespace {
00102   class SparcTargetLowering : public TargetLowering {
00103     int VarArgsFrameOffset;   // Frame offset to start of varargs area.
00104   public:
00105     SparcTargetLowering(TargetMachine &TM);
00106     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
00107     
00108     /// computeMaskedBitsForTargetNode - Determine which of the bits specified 
00109     /// in Mask are known to be either zero or one and return them in the 
00110     /// KnownZero/KnownOne bitsets.
00111     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
00112                                                 uint64_t Mask,
00113                                                 uint64_t &KnownZero, 
00114                                                 uint64_t &KnownOne,
00115                                                 unsigned Depth = 0) const;
00116     
00117     virtual std::vector<SDOperand>
00118       LowerArguments(Function &F, SelectionDAG &DAG);
00119     virtual std::pair<SDOperand, SDOperand>
00120       LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
00121                   unsigned CC,
00122                   bool isTailCall, SDOperand Callee, ArgListTy &Args,
00123                   SelectionDAG &DAG);
00124     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
00125                                                        MachineBasicBlock *MBB);
00126     
00127     virtual const char *getTargetNodeName(unsigned Opcode) const;
00128   };
00129 }
00130 
00131 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
00132   : TargetLowering(TM) {
00133   
00134   // Set up the register classes.
00135   addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
00136   addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
00137   addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
00138 
00139   // Custom legalize GlobalAddress nodes into LO/HI parts.
00140   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
00141   setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
00142   
00143   // Sparc doesn't have sext_inreg, replace them with shl/sra
00144   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
00145   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
00146   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
00147 
00148   // Sparc has no REM operation.
00149   setOperationAction(ISD::UREM, MVT::i32, Expand);
00150   setOperationAction(ISD::SREM, MVT::i32, Expand);
00151 
00152   // Custom expand fp<->sint
00153   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
00154   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
00155 
00156   // Expand fp<->uint
00157   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
00158   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
00159   
00160   setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
00161   setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
00162   
00163   // Turn FP extload into load/fextend
00164   setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
00165   
00166   // Sparc has no select or setcc: expand to SELECT_CC.
00167   setOperationAction(ISD::SELECT, MVT::i32, Expand);
00168   setOperationAction(ISD::SELECT, MVT::f32, Expand);
00169   setOperationAction(ISD::SELECT, MVT::f64, Expand);
00170   setOperationAction(ISD::SETCC, MVT::i32, Expand);
00171   setOperationAction(ISD::SETCC, MVT::f32, Expand);
00172   setOperationAction(ISD::SETCC, MVT::f64, Expand);
00173   
00174   // Sparc doesn't have BRCOND either, it has BR_CC.
00175   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
00176   setOperationAction(ISD::BRIND, MVT::i32, Expand);
00177   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
00178   setOperationAction(ISD::BR_CC, MVT::f32, Custom);
00179   setOperationAction(ISD::BR_CC, MVT::f64, Custom);
00180   
00181   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
00182   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
00183   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
00184   
00185   // SPARC has no intrinsics for these particular operations.
00186   setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
00187   setOperationAction(ISD::MEMSET, MVT::Other, Expand);
00188   setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
00189   
00190   setOperationAction(ISD::FSIN , MVT::f64, Expand);
00191   setOperationAction(ISD::FCOS , MVT::f64, Expand);
00192   setOperationAction(ISD::FSIN , MVT::f32, Expand);
00193   setOperationAction(ISD::FCOS , MVT::f32, Expand);
00194   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
00195   setOperationAction(ISD::CTTZ , MVT::i32, Expand);
00196   setOperationAction(ISD::CTLZ , MVT::i32, Expand);
00197   setOperationAction(ISD::ROTL , MVT::i32, Expand);
00198   setOperationAction(ISD::ROTR , MVT::i32, Expand);
00199   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
00200   setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
00201   setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
00202 
00203   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
00204   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
00205   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
00206 
00207   // We don't have line number support yet.
00208   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
00209   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
00210   setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
00211 
00212   // RET must be custom lowered, to meet ABI requirements
00213   setOperationAction(ISD::RET               , MVT::Other, Custom);
00214   
00215   // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
00216   setOperationAction(ISD::VASTART           , MVT::Other, Custom);
00217   // VAARG needs to be lowered to not do unaligned accesses for doubles.
00218   setOperationAction(ISD::VAARG             , MVT::Other, Custom);
00219   
00220   // Use the default implementation.
00221   setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
00222   setOperationAction(ISD::VAEND             , MVT::Other, Expand);
00223   setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand); 
00224   setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
00225   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
00226 
00227   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
00228   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
00229   
00230   setStackPointerRegisterToSaveRestore(SP::O6);
00231 
00232   if (TM.getSubtarget<SparcSubtarget>().isV9()) {
00233     setOperationAction(ISD::CTPOP, MVT::i32, Legal);
00234   }
00235   
00236   computeRegisterProperties();
00237 }
00238 
00239 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
00240   switch (Opcode) {
00241   default: return 0;
00242   case SPISD::CMPICC:     return "SPISD::CMPICC";
00243   case SPISD::CMPFCC:     return "SPISD::CMPFCC";
00244   case SPISD::BRICC:      return "SPISD::BRICC";
00245   case SPISD::BRFCC:      return "SPISD::BRFCC";
00246   case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
00247   case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
00248   case SPISD::Hi:         return "SPISD::Hi";
00249   case SPISD::Lo:         return "SPISD::Lo";
00250   case SPISD::FTOI:       return "SPISD::FTOI";
00251   case SPISD::ITOF:       return "SPISD::ITOF";
00252   case SPISD::CALL:       return "SPISD::CALL";
00253   case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
00254   }
00255 }
00256 
00257 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
00258 /// be zero. Op is expected to be a target specific node. Used by DAG
00259 /// combiner.
00260 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
00261                                                          uint64_t Mask,
00262                                                          uint64_t &KnownZero, 
00263                                                          uint64_t &KnownOne,
00264                                                          unsigned Depth) const {
00265   uint64_t KnownZero2, KnownOne2;
00266   KnownZero = KnownOne = 0;   // Don't know anything.
00267   
00268   switch (Op.getOpcode()) {
00269   default: break;
00270   case SPISD::SELECT_ICC:
00271   case SPISD::SELECT_FCC:
00272     ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
00273     ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
00274     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 
00275     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 
00276     
00277     // Only known if known in both the LHS and RHS.
00278     KnownOne &= KnownOne2;
00279     KnownZero &= KnownZero2;
00280     break;
00281   }
00282 }
00283 
00284 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
00285 /// either one or two GPRs, including FP values.  TODO: we should pass FP values
00286 /// in FP registers for fastcc functions.
00287 std::vector<SDOperand>
00288 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
00289   MachineFunction &MF = DAG.getMachineFunction();
00290   SSARegMap *RegMap = MF.getSSARegMap();
00291   std::vector<SDOperand> ArgValues;
00292   
00293   static const unsigned ArgRegs[] = {
00294     SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
00295   };
00296   
00297   const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
00298   unsigned ArgOffset = 68;
00299   
00300   SDOperand Root = DAG.getRoot();
00301   std::vector<SDOperand> OutChains;
00302 
00303   for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
00304     MVT::ValueType ObjectVT = getValueType(I->getType());
00305     
00306     switch (ObjectVT) {
00307     default: assert(0 && "Unhandled argument type!");
00308     case MVT::i1:
00309     case MVT::i8:
00310     case MVT::i16:
00311     case MVT::i32:
00312       if (I->use_empty()) {                // Argument is dead.
00313         if (CurArgReg < ArgRegEnd) ++CurArgReg;
00314         ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
00315       } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
00316         unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
00317         MF.addLiveIn(*CurArgReg++, VReg);
00318         SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
00319         if (ObjectVT != MVT::i32) {
00320           unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
00321                                                        : ISD::AssertZext;
00322           Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 
00323                             DAG.getValueType(ObjectVT));
00324           Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
00325         }
00326         ArgValues.push_back(Arg);
00327       } else {
00328         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
00329         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
00330         SDOperand Load;
00331         if (ObjectVT == MVT::i32) {
00332           Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
00333         } else {
00334           unsigned LoadOp =
00335             I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
00336 
00337           // Sparc is big endian, so add an offset based on the ObjectVT.
00338           unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
00339           FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
00340                               DAG.getConstant(Offset, MVT::i32));
00341           Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
00342                                 DAG.getSrcValue(0), ObjectVT);
00343           Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
00344         }
00345         ArgValues.push_back(Load);
00346       }
00347       
00348       ArgOffset += 4;
00349       break;
00350     case MVT::f32:
00351       if (I->use_empty()) {                // Argument is dead.
00352         if (CurArgReg < ArgRegEnd) ++CurArgReg;
00353         ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
00354       } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
00355         // FP value is passed in an integer register.
00356         unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
00357         MF.addLiveIn(*CurArgReg++, VReg);
00358         SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
00359 
00360         Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
00361         ArgValues.push_back(Arg);
00362       } else {
00363         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
00364         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
00365         SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
00366         ArgValues.push_back(Load);
00367       }
00368       ArgOffset += 4;
00369       break;
00370 
00371     case MVT::i64:
00372     case MVT::f64:
00373       if (I->use_empty()) {                // Argument is dead.
00374         if (CurArgReg < ArgRegEnd) ++CurArgReg;
00375         if (CurArgReg < ArgRegEnd) ++CurArgReg;
00376         ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
00377       } else if (/* FIXME: Apparently this isn't safe?? */
00378                  0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
00379                  ((CurArgReg-ArgRegs) & 1) == 0) {
00380         // If this is a double argument and the whole thing lives on the stack,
00381         // and the argument is aligned, load the double straight from the stack.
00382         // We can't do a load in cases like void foo([6ints], int,double),
00383         // because the double wouldn't be aligned!
00384         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
00385         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
00386         ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 
00387                                         DAG.getSrcValue(0)));
00388       } else {
00389         SDOperand HiVal;
00390         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
00391           unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
00392           MF.addLiveIn(*CurArgReg++, VRegHi);
00393           HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
00394         } else {
00395           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
00396           SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
00397           HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
00398         }
00399         
00400         SDOperand LoVal;
00401         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
00402           unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
00403           MF.addLiveIn(*CurArgReg++, VRegLo);
00404           LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
00405         } else {
00406           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
00407           SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
00408           LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
00409         }
00410         
00411         // Compose the two halves together into an i64 unit.
00412         SDOperand WholeValue = 
00413           DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
00414         
00415         // If we want a double, do a bit convert.
00416         if (ObjectVT == MVT::f64)
00417           WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
00418         
00419         ArgValues.push_back(WholeValue);
00420       }
00421       ArgOffset += 8;
00422       break;
00423     }
00424   }
00425   
00426   // Store remaining ArgRegs to the stack if this is a varargs function.
00427   if (F.getFunctionType()->isVarArg()) {
00428     // Remember the vararg offset for the va_start implementation.
00429     VarArgsFrameOffset = ArgOffset;
00430     
00431     for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
00432       unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
00433       MF.addLiveIn(*CurArgReg, VReg);
00434       SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
00435 
00436       int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
00437       SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
00438 
00439       OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
00440                                       Arg, FIPtr, DAG.getSrcValue(0)));
00441       ArgOffset += 4;
00442     }
00443   }
00444   
00445   if (!OutChains.empty())
00446     DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
00447   
00448   // Finally, inform the code generator which regs we return values in.
00449   switch (getValueType(F.getReturnType())) {
00450   default: assert(0 && "Unknown type!");
00451   case MVT::isVoid: break;
00452   case MVT::i1:
00453   case MVT::i8:
00454   case MVT::i16:
00455   case MVT::i32:
00456     MF.addLiveOut(SP::I0);
00457     break;
00458   case MVT::i64:
00459     MF.addLiveOut(SP::I0);
00460     MF.addLiveOut(SP::I1);
00461     break;
00462   case MVT::f32:
00463     MF.addLiveOut(SP::F0);
00464     break;
00465   case MVT::f64:
00466     MF.addLiveOut(SP::D0);
00467     break;
00468   }
00469   
00470   return ArgValues;
00471 }
00472 
00473 std::pair<SDOperand, SDOperand>
00474 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
00475                                  bool isVarArg, unsigned CC,
00476                                  bool isTailCall, SDOperand Callee, 
00477                                  ArgListTy &Args, SelectionDAG &DAG) {
00478   // Count the size of the outgoing arguments.
00479   unsigned ArgsSize = 0;
00480   for (unsigned i = 0, e = Args.size(); i != e; ++i) {
00481     switch (getValueType(Args[i].second)) {
00482     default: assert(0 && "Unknown value type!");
00483     case MVT::i1:
00484     case MVT::i8:
00485     case MVT::i16:
00486     case MVT::i32:
00487     case MVT::f32:
00488       ArgsSize += 4;
00489       break;
00490     case MVT::i64:
00491     case MVT::f64:
00492       ArgsSize += 8;
00493       break;
00494     }
00495   }
00496   if (ArgsSize > 4*6)
00497     ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
00498   else
00499     ArgsSize = 0;
00500 
00501   // Keep stack frames 8-byte aligned.
00502   ArgsSize = (ArgsSize+7) & ~7;
00503 
00504   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
00505   
00506   SDOperand StackPtr, NullSV;
00507   std::vector<SDOperand> Stores;
00508   std::vector<SDOperand> RegValuesToPass;
00509   unsigned ArgOffset = 68;
00510   for (unsigned i = 0, e = Args.size(); i != e; ++i) {
00511     SDOperand Val = Args[i].first;
00512     MVT::ValueType ObjectVT = Val.getValueType();
00513     SDOperand ValToStore(0, 0);
00514     unsigned ObjSize;
00515     switch (ObjectVT) {
00516     default: assert(0 && "Unhandled argument type!");
00517     case MVT::i1:
00518     case MVT::i8:
00519     case MVT::i16:
00520       // Promote the integer to 32-bits.  If the input type is signed, use a
00521       // sign extend, otherwise use a zero extend.
00522       if (Args[i].second->isSigned())
00523         Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
00524       else
00525         Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
00526       // FALL THROUGH
00527     case MVT::i32:
00528       ObjSize = 4;
00529 
00530       if (RegValuesToPass.size() >= 6) {
00531         ValToStore = Val;
00532       } else {
00533         RegValuesToPass.push_back(Val);
00534       }
00535       break;
00536     case MVT::f32:
00537       ObjSize = 4;
00538       if (RegValuesToPass.size() >= 6) {
00539         ValToStore = Val;
00540       } else {
00541         // Convert this to a FP value in an int reg.
00542         Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
00543         RegValuesToPass.push_back(Val);
00544       }
00545       break;
00546     case MVT::f64:
00547       ObjSize = 8;
00548       // If we can store this directly into the outgoing slot, do so.  We can
00549       // do this when all ArgRegs are used and if the outgoing slot is aligned.
00550       // FIXME: McGill/misr fails with this.
00551       if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
00552         ValToStore = Val;
00553         break;
00554       }
00555       
00556       // Otherwise, convert this to a FP value in int regs.
00557       Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
00558       // FALL THROUGH
00559     case MVT::i64:
00560       ObjSize = 8;
00561       if (RegValuesToPass.size() >= 6) {
00562         ValToStore = Val;    // Whole thing is passed in memory.
00563         break;
00564       }
00565       
00566       // Split the value into top and bottom part.  Top part goes in a reg.
00567       SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 
00568                                  DAG.getConstant(1, MVT::i32));
00569       SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
00570                                  DAG.getConstant(0, MVT::i32));
00571       RegValuesToPass.push_back(Hi);
00572       
00573       if (RegValuesToPass.size() >= 6) {
00574         ValToStore = Lo;
00575         ArgOffset += 4;
00576         ObjSize = 4;
00577       } else {
00578         RegValuesToPass.push_back(Lo);
00579       }
00580       break;
00581     }
00582     
00583     if (ValToStore.Val) {
00584       if (!StackPtr.Val) {
00585         StackPtr = DAG.getRegister(SP::O6, MVT::i32);
00586         NullSV = DAG.getSrcValue(NULL);
00587       }
00588       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
00589       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
00590       Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
00591                                    ValToStore, PtrOff, NullSV));
00592     }
00593     ArgOffset += ObjSize;
00594   }
00595   
00596   // Emit all stores, make sure the occur before any copies into physregs.
00597   if (!Stores.empty())
00598     Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
00599   
00600   static const unsigned ArgRegs[] = {
00601     SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
00602   };
00603   
00604   // Build a sequence of copy-to-reg nodes chained together with token chain
00605   // and flag operands which copy the outgoing args into O[0-5].
00606   SDOperand InFlag;
00607   for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
00608     Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
00609     InFlag = Chain.getValue(1);
00610   }
00611 
00612   // If the callee is a GlobalAddress node (quite common, every direct call is)
00613   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
00614   // Likewise ExternalSymbol -> TargetExternalSymbol.
00615   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
00616     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
00617   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
00618     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
00619 
00620   std::vector<MVT::ValueType> NodeTys;
00621   NodeTys.push_back(MVT::Other);   // Returns a chain
00622   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
00623   std::vector<SDOperand> Ops;
00624   Ops.push_back(Chain);
00625   Ops.push_back(Callee);
00626   if (InFlag.Val)
00627     Ops.push_back(InFlag);
00628   Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
00629   InFlag = Chain.getValue(1);
00630   
00631   MVT::ValueType RetTyVT = getValueType(RetTy);
00632   SDOperand RetVal;
00633   if (RetTyVT != MVT::isVoid) {
00634     switch (RetTyVT) {
00635     default: assert(0 && "Unknown value type to return!");
00636     case MVT::i1:
00637     case MVT::i8:
00638     case MVT::i16:
00639       RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
00640       Chain = RetVal.getValue(1);
00641       
00642       // Add a note to keep track of whether it is sign or zero extended.
00643       RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
00644                            MVT::i32, RetVal, DAG.getValueType(RetTyVT));
00645       RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
00646       break;
00647     case MVT::i32:
00648       RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
00649       Chain = RetVal.getValue(1);
00650       break;
00651     case MVT::f32:
00652       RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
00653       Chain = RetVal.getValue(1);
00654       break;
00655     case MVT::f64:
00656       RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
00657       Chain = RetVal.getValue(1);
00658       break;
00659     case MVT::i64:
00660       SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
00661       SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 
00662                                         Lo.getValue(2));
00663       RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
00664       Chain = Hi.getValue(1);
00665       break;
00666     }
00667   }
00668   
00669   Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
00670                       DAG.getConstant(ArgsSize, getPointerTy()));
00671   
00672   return std::make_pair(RetVal, Chain);
00673 }
00674 
00675 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
00676 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
00677 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
00678                              ISD::CondCode CC, unsigned &SPCC) {
00679   if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
00680       CC == ISD::SETNE && 
00681       ((LHS.getOpcode() == SPISD::SELECT_ICC &&
00682         LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
00683        (LHS.getOpcode() == SPISD::SELECT_FCC &&
00684         LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
00685       isa<ConstantSDNode>(LHS.getOperand(0)) &&
00686       isa<ConstantSDNode>(LHS.getOperand(1)) &&
00687       cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
00688       cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
00689     SDOperand CMPCC = LHS.getOperand(3);
00690     SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
00691     LHS = CMPCC.getOperand(0);
00692     RHS = CMPCC.getOperand(1);
00693   }
00694 }
00695 
00696 
00697 SDOperand SparcTargetLowering::
00698 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
00699   switch (Op.getOpcode()) {
00700   default: assert(0 && "Should not custom lower this!");
00701   case ISD::GlobalAddress: {
00702     GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
00703     SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
00704     SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
00705     SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
00706     return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
00707   }
00708   case ISD::ConstantPool: {
00709     Constant *C = cast<ConstantPoolSDNode>(Op)->get();
00710     SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
00711                                   cast<ConstantPoolSDNode>(Op)->getAlignment());
00712     SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
00713     SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
00714     return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
00715   }
00716   case ISD::FP_TO_SINT:
00717     // Convert the fp value to integer in an FP register.
00718     assert(Op.getValueType() == MVT::i32);
00719     Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
00720     return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
00721   case ISD::SINT_TO_FP: {
00722     assert(Op.getOperand(0).getValueType() == MVT::i32);
00723     SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
00724     // Convert the int value to FP in an FP register.
00725     return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
00726   }
00727   case ISD::BR_CC: {
00728     SDOperand Chain = Op.getOperand(0);
00729     ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
00730     SDOperand LHS = Op.getOperand(2);
00731     SDOperand RHS = Op.getOperand(3);
00732     SDOperand Dest = Op.getOperand(4);
00733     unsigned Opc, SPCC = ~0U;
00734     
00735     // If this is a br_cc of a "setcc", and if the setcc got lowered into
00736     // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
00737     LookThroughSetCC(LHS, RHS, CC, SPCC);
00738     
00739     // Get the condition flag.
00740     SDOperand CompareFlag;
00741     if (LHS.getValueType() == MVT::i32) {
00742       std::vector<MVT::ValueType> VTs;
00743       VTs.push_back(MVT::i32);
00744       VTs.push_back(MVT::Flag);
00745       std::vector<SDOperand> Ops;
00746       Ops.push_back(LHS);
00747       Ops.push_back(RHS);
00748       CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
00749       if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
00750       Opc = SPISD::BRICC;
00751     } else {
00752       CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
00753       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
00754       Opc = SPISD::BRFCC;
00755     }
00756     return DAG.getNode(Opc, MVT::Other, Chain, Dest,
00757                        DAG.getConstant(SPCC, MVT::i32), CompareFlag);
00758   }
00759   case ISD::SELECT_CC: {
00760     SDOperand LHS = Op.getOperand(0);
00761     SDOperand RHS = Op.getOperand(1);
00762     ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
00763     SDOperand TrueVal = Op.getOperand(2);
00764     SDOperand FalseVal = Op.getOperand(3);
00765     unsigned Opc, SPCC = ~0U;
00766 
00767     // If this is a select_cc of a "setcc", and if the setcc got lowered into
00768     // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
00769     LookThroughSetCC(LHS, RHS, CC, SPCC);
00770     
00771     SDOperand CompareFlag;
00772     if (LHS.getValueType() == MVT::i32) {
00773       std::vector<MVT::ValueType> VTs;
00774       VTs.push_back(LHS.getValueType());   // subcc returns a value
00775       VTs.push_back(MVT::Flag);
00776       std::vector<SDOperand> Ops;
00777       Ops.push_back(LHS);
00778       Ops.push_back(RHS);
00779       CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
00780       Opc = SPISD::SELECT_ICC;
00781       if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
00782     } else {
00783       CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
00784       Opc = SPISD::SELECT_FCC;
00785       if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
00786     }
00787     return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 
00788                        DAG.getConstant(SPCC, MVT::i32), CompareFlag);
00789   }
00790   case ISD::VASTART: {
00791     // vastart just stores the address of the VarArgsFrameIndex slot into the
00792     // memory location argument.
00793     SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
00794                                    DAG.getRegister(SP::I6, MVT::i32),
00795                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
00796     return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 
00797                        Op.getOperand(1), Op.getOperand(2));
00798   }
00799   case ISD::VAARG: {
00800     SDNode *Node = Op.Val;
00801     MVT::ValueType VT = Node->getValueType(0);
00802     SDOperand InChain = Node->getOperand(0);
00803     SDOperand VAListPtr = Node->getOperand(1);
00804     SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
00805                                    Node->getOperand(2));
00806     // Increment the pointer, VAList, to the next vaarg
00807     SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 
00808                                     DAG.getConstant(MVT::getSizeInBits(VT)/8, 
00809                                                     getPointerTy()));
00810     // Store the incremented VAList to the legalized pointer
00811     InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
00812                           VAListPtr, Node->getOperand(2));
00813     // Load the actual argument out of the pointer VAList, unless this is an
00814     // f64 load.
00815     if (VT != MVT::f64) {
00816       return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
00817     } else {
00818       // Otherwise, load it as i64, then do a bitconvert.
00819       SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
00820       std::vector<MVT::ValueType> Tys;
00821       Tys.push_back(MVT::f64);
00822       Tys.push_back(MVT::Other);
00823       std::vector<SDOperand> Ops;
00824       // Bit-Convert the value to f64.
00825       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
00826       Ops.push_back(V.getValue(1));
00827       return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
00828     }
00829   }
00830   case ISD::DYNAMIC_STACKALLOC: {
00831     SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
00832     SDOperand Size  = Op.getOperand(1);  // Legalize the size.
00833     
00834     unsigned SPReg = SP::O6;
00835     SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
00836     SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
00837     Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
00838 
00839     // The resultant pointer is actually 16 words from the bottom of the stack,
00840     // to provide a register spill area.
00841     SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
00842                                    DAG.getConstant(96, MVT::i32));
00843     std::vector<MVT::ValueType> Tys;
00844     Tys.push_back(MVT::i32);
00845     Tys.push_back(MVT::Other);
00846     std::vector<SDOperand> Ops;
00847     Ops.push_back(NewVal);
00848     Ops.push_back(Chain);
00849     return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
00850   }
00851   case ISD::RET: {
00852     SDOperand Copy;
00853     
00854     switch(Op.getNumOperands()) {
00855     default:
00856       assert(0 && "Do not know how to return this many arguments!");
00857       abort();
00858     case 1: 
00859       return SDOperand(); // ret void is legal
00860     case 3: {
00861       unsigned ArgReg;
00862       switch(Op.getOperand(1).getValueType()) {
00863       default: assert(0 && "Unknown type to return!");
00864       case MVT::i32: ArgReg = SP::I0; break;
00865       case MVT::f32: ArgReg = SP::F0; break;
00866       case MVT::f64: ArgReg = SP::D0; break;
00867       }
00868       Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
00869                               SDOperand());
00870       break;
00871     }
00872     case 5:
00873       Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 
00874                               SDOperand());
00875       Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
00876       break;
00877     }
00878     return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
00879   }
00880   }
00881 }
00882 
00883 MachineBasicBlock *
00884 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
00885                                              MachineBasicBlock *BB) {
00886   unsigned BROpcode;
00887   unsigned CC;
00888   // Figure out the conditional branch opcode to use for this select_cc.
00889   switch (MI->getOpcode()) {
00890   default: assert(0 && "Unknown SELECT_CC!");
00891   case SP::SELECT_CC_Int_ICC:
00892   case SP::SELECT_CC_FP_ICC:
00893   case SP::SELECT_CC_DFP_ICC:
00894     BROpcode = SP::BCOND;
00895     break;
00896   case SP::SELECT_CC_Int_FCC:
00897   case SP::SELECT_CC_FP_FCC:
00898   case SP::SELECT_CC_DFP_FCC:
00899     BROpcode = SP::FBCOND;
00900     break;
00901   }
00902 
00903   CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
00904   
00905   // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
00906   // control-flow pattern.  The incoming instruction knows the destination vreg
00907   // to set, the condition code register to branch on, the true/false values to
00908   // select between, and a branch opcode to use.
00909   const BasicBlock *LLVM_BB = BB->getBasicBlock();
00910   ilist<MachineBasicBlock>::iterator It = BB;
00911   ++It;
00912   
00913   //  thisMBB:
00914   //  ...
00915   //   TrueVal = ...
00916   //   [f]bCC copy1MBB
00917   //   fallthrough --> copy0MBB
00918   MachineBasicBlock *thisMBB = BB;
00919   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
00920   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
00921   BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
00922   MachineFunction *F = BB->getParent();
00923   F->getBasicBlockList().insert(It, copy0MBB);
00924   F->getBasicBlockList().insert(It, sinkMBB);
00925   // Update machine-CFG edges by first adding all successors of the current
00926   // block to the new block which will contain the Phi node for the select.
00927   for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 
00928       e = BB->succ_end(); i != e; ++i)
00929     sinkMBB->addSuccessor(*i);
00930   // Next, remove all successors of the current block, and add the true
00931   // and fallthrough blocks as its successors.
00932   while(!BB->succ_empty())
00933     BB->removeSuccessor(BB->succ_begin());
00934   BB->addSuccessor(copy0MBB);
00935   BB->addSuccessor(sinkMBB);
00936   
00937   //  copy0MBB:
00938   //   %FalseValue = ...
00939   //   # fallthrough to sinkMBB
00940   BB = copy0MBB;
00941   
00942   // Update machine-CFG edges
00943   BB->addSuccessor(sinkMBB);
00944   
00945   //  sinkMBB:
00946   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
00947   //  ...
00948   BB = sinkMBB;
00949   BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
00950     .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
00951     .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
00952   
00953   delete MI;   // The pseudo instruction is gone now.
00954   return BB;
00955 }
00956   
00957 //===----------------------------------------------------------------------===//
00958 // Instruction Selector Implementation
00959 //===----------------------------------------------------------------------===//
00960 
00961 //===--------------------------------------------------------------------===//
00962 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
00963 /// instructions for SelectionDAG operations.
00964 ///
00965 namespace {
00966 class SparcDAGToDAGISel : public SelectionDAGISel {
00967   SparcTargetLowering Lowering;
00968 
00969   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
00970   /// make the right decision when generating code for different targets.
00971   const SparcSubtarget &Subtarget;
00972 public:
00973   SparcDAGToDAGISel(TargetMachine &TM)
00974     : SelectionDAGISel(Lowering), Lowering(TM),
00975       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
00976   }
00977 
00978   void Select(SDOperand &Result, SDOperand Op);
00979 
00980   // Complex Pattern Selectors.
00981   bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
00982   bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
00983   
00984   /// InstructionSelectBasicBlock - This callback is invoked by
00985   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
00986   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
00987   
00988   virtual const char *getPassName() const {
00989     return "SPARC DAG->DAG Pattern Instruction Selection";
00990   } 
00991   
00992   // Include the pieces autogenerated from the target description.
00993 #include "SparcGenDAGISel.inc"
00994 };
00995 }  // end anonymous namespace
00996 
00997 /// InstructionSelectBasicBlock - This callback is invoked by
00998 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
00999 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
01000   DEBUG(BB->dump());
01001   
01002   // Select target instructions for the DAG.
01003   DAG.setRoot(SelectRoot(DAG.getRoot()));
01004   assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
01005   CodeGenMap.clear();
01006   HandleMap.clear();
01007   ReplaceMap.clear();
01008   DAG.RemoveDeadNodes();
01009   
01010   // Emit machine code to BB. 
01011   ScheduleAndEmitDAG(DAG);
01012 }
01013 
01014 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
01015                                      SDOperand &Offset) {
01016   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01017     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01018     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01019     return true;
01020   }
01021   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01022       Addr.getOpcode() == ISD::TargetGlobalAddress)
01023     return false;  // direct calls.
01024   
01025   if (Addr.getOpcode() == ISD::ADD) {
01026     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
01027       if (Predicate_simm13(CN)) {
01028         if (FrameIndexSDNode *FIN = 
01029                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
01030           // Constant offset from frame ref.
01031           Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01032         } else {
01033           Base = Addr.getOperand(0);
01034         }
01035         Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
01036         return true;
01037       }
01038     }
01039     if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
01040       Base = Addr.getOperand(1);
01041       Offset = Addr.getOperand(0).getOperand(0);
01042       return true;
01043     }
01044     if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
01045       Base = Addr.getOperand(0);
01046       Offset = Addr.getOperand(1).getOperand(0);
01047       return true;
01048     }
01049   }
01050   Base = Addr;
01051   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01052   return true;
01053 }
01054 
01055 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 
01056                                      SDOperand &R2) {
01057   if (Addr.getOpcode() == ISD::FrameIndex) return false;
01058   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01059       Addr.getOpcode() == ISD::TargetGlobalAddress)
01060     return false;  // direct calls.
01061   
01062   if (Addr.getOpcode() == ISD::ADD) {
01063     if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
01064         Predicate_simm13(Addr.getOperand(1).Val))
01065       return false;  // Let the reg+imm pattern catch this!
01066     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
01067         Addr.getOperand(1).getOpcode() == SPISD::Lo)
01068       return false;  // Let the reg+imm pattern catch this!
01069     R1 = Addr.getOperand(0);
01070     R2 = Addr.getOperand(1);
01071     return true;
01072   }
01073 
01074   R1 = Addr;
01075   R2 = CurDAG->getRegister(SP::G0, MVT::i32);
01076   return true;
01077 }
01078 
01079 void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
01080   SDNode *N = Op.Val;
01081   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
01082       N->getOpcode() < SPISD::FIRST_NUMBER) {
01083     Result = Op;
01084     return;   // Already selected.
01085   }
01086 
01087                  // If this has already been converted, use it.
01088   std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
01089   if (CGMI != CodeGenMap.end()) {
01090     Result = CGMI->second;
01091     return;
01092   }
01093   
01094   switch (N->getOpcode()) {
01095   default: break;
01096   case ISD::SDIV:
01097   case ISD::UDIV: {
01098     // FIXME: should use a custom expander to expose the SRA to the dag.
01099     SDOperand DivLHS, DivRHS;
01100     Select(DivLHS, N->getOperand(0));
01101     Select(DivRHS, N->getOperand(1));
01102     
01103     // Set the Y register to the high-part.
01104     SDOperand TopPart;
01105     if (N->getOpcode() == ISD::SDIV) {
01106       TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
01107                                    CurDAG->getTargetConstant(31, MVT::i32)), 0);
01108     } else {
01109       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
01110     }
01111     TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
01112                                      CurDAG->getRegister(SP::G0, MVT::i32)), 0);
01113 
01114     // FIXME: Handle div by immediate.
01115     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
01116     Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
01117     return;
01118   }    
01119   case ISD::MULHU:
01120   case ISD::MULHS: {
01121     // FIXME: Handle mul by immediate.
01122     SDOperand MulLHS, MulRHS;
01123     Select(MulLHS, N->getOperand(0));
01124     Select(MulRHS, N->getOperand(1));
01125     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
01126     SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
01127                                         MulLHS, MulRHS);
01128     // The high part is in the Y register.
01129     Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
01130     return;
01131   }
01132   }
01133   
01134   SelectCode(Result, Op);
01135 }
01136 
01137 
01138 /// createSparcISelDag - This pass converts a legalized DAG into a 
01139 /// SPARC-specific DAG, ready for instruction scheduling.
01140 ///
01141 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
01142   return new SparcDAGToDAGISel(TM);
01143 }