LLVM API Documentation

PPCInstrInfo.h

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00001 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the PowerPC implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef POWERPC32_INSTRUCTIONINFO_H
00015 #define POWERPC32_INSTRUCTIONINFO_H
00016 
00017 #include "PPC.h"
00018 #include "llvm/Target/TargetInstrInfo.h"
00019 #include "PPCRegisterInfo.h"
00020 
00021 namespace llvm {
00022 
00023 /// PPCII - This namespace holds all of the PowerPC target-specific
00024 /// per-instruction flags.  These must match the corresponding definitions in
00025 /// PPC.td and PPCInstrFormats.td.
00026 namespace PPCII {
00027 enum {
00028   // PPC970 Instruction Flags.  These flags describe the characteristics of the
00029   // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
00030   // raw machine instructions.
00031 
00032   /// PPC970_First - This instruction starts a new dispatch group, so it will
00033   /// always be the first one in the group.
00034   PPC970_First = 0x1,
00035   
00036   /// PPC970_Single - This instruction starts a new dispatch group and
00037   /// terminates it, so it will be the sole instruction in the group.
00038   PPC970_Single = 0x2,
00039 
00040   /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
00041   /// two dispatch pipes to be available to issue.
00042   PPC970_Cracked = 0x4,
00043   
00044   /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
00045   /// an instruction is issued to.
00046   PPC970_Shift = 3,
00047   PPC970_Mask = 0x07 << PPC970_Shift
00048 };
00049 enum PPC970_Unit {
00050   /// These are the various PPC970 execution unit pipelines.  Each instruction
00051   /// is one of these.
00052   PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
00053   PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
00054   PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
00055   PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
00056   PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
00057   PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
00058   PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
00059   PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
00060 };
00061 }
00062   
00063   
00064 class PPCInstrInfo : public TargetInstrInfo {
00065   PPCTargetMachine &TM;
00066   const PPCRegisterInfo RI;
00067 public:
00068   PPCInstrInfo(PPCTargetMachine &TM);
00069 
00070   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
00071   /// such, whenever a client has an instance of instruction info, it should
00072   /// always be able to get register info as well (through this method).
00073   ///
00074   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
00075 
00076   /// getPointerRegClass - Return the register class to use to hold pointers.
00077   /// This is used for addressing modes.
00078   virtual const TargetRegisterClass *getPointerRegClass() const;  
00079 
00080   // Return true if the instruction is a register to register move and
00081   // leave the source and dest operands in the passed parameters.
00082   //
00083   virtual bool isMoveInstr(const MachineInstr& MI,
00084                            unsigned& sourceReg,
00085                            unsigned& destReg) const;
00086 
00087   unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
00088   unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
00089 
00090   // commuteInstruction - We can commute rlwimi instructions, but only if the
00091   // rotate amt is zero.  We also have to munge the immediates a bit.
00092   virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
00093   
00094   virtual void insertNoop(MachineBasicBlock &MBB, 
00095                           MachineBasicBlock::iterator MI) const;
00096 
00097   static unsigned invertPPCBranchOpcode(unsigned Opcode) {
00098     switch (Opcode) {
00099     default: assert(0 && "Unknown PPC branch opcode!");
00100     case PPC::BEQ: return PPC::BNE;
00101     case PPC::BNE: return PPC::BEQ;
00102     case PPC::BLT: return PPC::BGE;
00103     case PPC::BGE: return PPC::BLT;
00104     case PPC::BGT: return PPC::BLE;
00105     case PPC::BLE: return PPC::BGT;
00106     case PPC::BNU: return PPC::BUN;
00107     case PPC::BUN: return PPC::BNU;
00108     }
00109   }
00110 };
00111 
00112 }
00113 
00114 #endif