LLVM API Documentation
00001 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by Nate Begeman and is distributed under the 00006 // University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 00011 // both before and after the DAG is legalized. 00012 // 00013 // FIXME: Missing folds 00014 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 00015 // a sequence of multiplies, shifts, and adds. This should be controlled by 00016 // some kind of hint from the target that int div is expensive. 00017 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 00018 // 00019 // FIXME: select C, pow2, pow2 -> something smart 00020 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 00021 // FIXME: Dead stores -> nuke 00022 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 00023 // FIXME: mul (x, const) -> shifts + adds 00024 // FIXME: undef values 00025 // FIXME: make truncate see through SIGN_EXTEND and AND 00026 // FIXME: divide by zero is currently left unfolded. do we want to turn this 00027 // into an undef? 00028 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 00029 // 00030 //===----------------------------------------------------------------------===// 00031 00032 #define DEBUG_TYPE "dagcombine" 00033 #include "llvm/ADT/Statistic.h" 00034 #include "llvm/CodeGen/SelectionDAG.h" 00035 #include "llvm/Support/Debug.h" 00036 #include "llvm/Support/MathExtras.h" 00037 #include "llvm/Target/TargetLowering.h" 00038 #include "llvm/Support/Visibility.h" 00039 #include <algorithm> 00040 #include <cmath> 00041 #include <iostream> 00042 using namespace llvm; 00043 00044 namespace { 00045 static Statistic<> NodesCombined ("dagcombiner", 00046 "Number of dag nodes combined"); 00047 00048 class VISIBILITY_HIDDEN DAGCombiner { 00049 SelectionDAG &DAG; 00050 TargetLowering &TLI; 00051 bool AfterLegalize; 00052 00053 // Worklist of all of the nodes that need to be simplified. 00054 std::vector<SDNode*> WorkList; 00055 00056 /// AddUsersToWorkList - When an instruction is simplified, add all users of 00057 /// the instruction to the work lists because they might get more simplified 00058 /// now. 00059 /// 00060 void AddUsersToWorkList(SDNode *N) { 00061 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 00062 UI != UE; ++UI) 00063 WorkList.push_back(*UI); 00064 } 00065 00066 /// removeFromWorkList - remove all instances of N from the worklist. 00067 /// 00068 void removeFromWorkList(SDNode *N) { 00069 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 00070 WorkList.end()); 00071 } 00072 00073 public: 00074 void AddToWorkList(SDNode *N) { 00075 WorkList.push_back(N); 00076 } 00077 00078 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 00079 ++NodesCombined; 00080 DEBUG(std::cerr << "\nReplacing "; N->dump(); 00081 std::cerr << "\nWith: "; To[0].Val->dump(&DAG); 00082 std::cerr << " and " << To.size()-1 << " other values\n"); 00083 std::vector<SDNode*> NowDead; 00084 DAG.ReplaceAllUsesWith(N, To, &NowDead); 00085 00086 // Push the new nodes and any users onto the worklist 00087 for (unsigned i = 0, e = To.size(); i != e; ++i) { 00088 WorkList.push_back(To[i].Val); 00089 AddUsersToWorkList(To[i].Val); 00090 } 00091 00092 // Nodes can end up on the worklist more than once. Make sure we do 00093 // not process a node that has been replaced. 00094 removeFromWorkList(N); 00095 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 00096 removeFromWorkList(NowDead[i]); 00097 00098 // Finally, since the node is now dead, remove it from the graph. 00099 DAG.DeleteNode(N); 00100 return SDOperand(N, 0); 00101 } 00102 00103 SDOperand CombineTo(SDNode *N, SDOperand Res) { 00104 std::vector<SDOperand> To; 00105 To.push_back(Res); 00106 return CombineTo(N, To); 00107 } 00108 00109 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 00110 std::vector<SDOperand> To; 00111 To.push_back(Res0); 00112 To.push_back(Res1); 00113 return CombineTo(N, To); 00114 } 00115 private: 00116 00117 /// SimplifyDemandedBits - Check the specified integer node value to see if 00118 /// it can be simplified or if things it uses can be simplified by bit 00119 /// propagation. If so, return true. 00120 bool SimplifyDemandedBits(SDOperand Op) { 00121 TargetLowering::TargetLoweringOpt TLO(DAG); 00122 uint64_t KnownZero, KnownOne; 00123 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 00124 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 00125 return false; 00126 00127 // Revisit the node. 00128 WorkList.push_back(Op.Val); 00129 00130 // Replace the old value with the new one. 00131 ++NodesCombined; 00132 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 00133 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG)); 00134 00135 std::vector<SDNode*> NowDead; 00136 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 00137 00138 // Push the new node and any (possibly new) users onto the worklist. 00139 WorkList.push_back(TLO.New.Val); 00140 AddUsersToWorkList(TLO.New.Val); 00141 00142 // Nodes can end up on the worklist more than once. Make sure we do 00143 // not process a node that has been replaced. 00144 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 00145 removeFromWorkList(NowDead[i]); 00146 00147 // Finally, if the node is now dead, remove it from the graph. The node 00148 // may not be dead if the replacement process recursively simplified to 00149 // something else needing this node. 00150 if (TLO.Old.Val->use_empty()) { 00151 removeFromWorkList(TLO.Old.Val); 00152 DAG.DeleteNode(TLO.Old.Val); 00153 } 00154 return true; 00155 } 00156 00157 /// visit - call the node-specific routine that knows how to fold each 00158 /// particular type of node. 00159 SDOperand visit(SDNode *N); 00160 00161 // Visitation implementation - Implement dag node combining for different 00162 // node types. The semantics are as follows: 00163 // Return Value: 00164 // SDOperand.Val == 0 - No change was made 00165 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 00166 // otherwise - N should be replaced by the returned Operand. 00167 // 00168 SDOperand visitTokenFactor(SDNode *N); 00169 SDOperand visitADD(SDNode *N); 00170 SDOperand visitSUB(SDNode *N); 00171 SDOperand visitMUL(SDNode *N); 00172 SDOperand visitSDIV(SDNode *N); 00173 SDOperand visitUDIV(SDNode *N); 00174 SDOperand visitSREM(SDNode *N); 00175 SDOperand visitUREM(SDNode *N); 00176 SDOperand visitMULHU(SDNode *N); 00177 SDOperand visitMULHS(SDNode *N); 00178 SDOperand visitAND(SDNode *N); 00179 SDOperand visitOR(SDNode *N); 00180 SDOperand visitXOR(SDNode *N); 00181 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 00182 SDOperand visitSHL(SDNode *N); 00183 SDOperand visitSRA(SDNode *N); 00184 SDOperand visitSRL(SDNode *N); 00185 SDOperand visitCTLZ(SDNode *N); 00186 SDOperand visitCTTZ(SDNode *N); 00187 SDOperand visitCTPOP(SDNode *N); 00188 SDOperand visitSELECT(SDNode *N); 00189 SDOperand visitSELECT_CC(SDNode *N); 00190 SDOperand visitSETCC(SDNode *N); 00191 SDOperand visitSIGN_EXTEND(SDNode *N); 00192 SDOperand visitZERO_EXTEND(SDNode *N); 00193 SDOperand visitANY_EXTEND(SDNode *N); 00194 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 00195 SDOperand visitTRUNCATE(SDNode *N); 00196 SDOperand visitBIT_CONVERT(SDNode *N); 00197 SDOperand visitVBIT_CONVERT(SDNode *N); 00198 SDOperand visitFADD(SDNode *N); 00199 SDOperand visitFSUB(SDNode *N); 00200 SDOperand visitFMUL(SDNode *N); 00201 SDOperand visitFDIV(SDNode *N); 00202 SDOperand visitFREM(SDNode *N); 00203 SDOperand visitFCOPYSIGN(SDNode *N); 00204 SDOperand visitSINT_TO_FP(SDNode *N); 00205 SDOperand visitUINT_TO_FP(SDNode *N); 00206 SDOperand visitFP_TO_SINT(SDNode *N); 00207 SDOperand visitFP_TO_UINT(SDNode *N); 00208 SDOperand visitFP_ROUND(SDNode *N); 00209 SDOperand visitFP_ROUND_INREG(SDNode *N); 00210 SDOperand visitFP_EXTEND(SDNode *N); 00211 SDOperand visitFNEG(SDNode *N); 00212 SDOperand visitFABS(SDNode *N); 00213 SDOperand visitBRCOND(SDNode *N); 00214 SDOperand visitBR_CC(SDNode *N); 00215 SDOperand visitLOAD(SDNode *N); 00216 SDOperand visitXEXTLOAD(SDNode *N); 00217 SDOperand visitSTORE(SDNode *N); 00218 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 00219 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 00220 SDOperand visitVBUILD_VECTOR(SDNode *N); 00221 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 00222 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 00223 00224 SDOperand XformToShuffleWithZero(SDNode *N); 00225 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 00226 00227 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 00228 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 00229 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 00230 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 00231 SDOperand N3, ISD::CondCode CC); 00232 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 00233 ISD::CondCode Cond, bool foldBooleans = true); 00234 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 00235 SDOperand BuildSDIV(SDNode *N); 00236 SDOperand BuildUDIV(SDNode *N); 00237 public: 00238 DAGCombiner(SelectionDAG &D) 00239 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 00240 00241 /// Run - runs the dag combiner on all nodes in the work list 00242 void Run(bool RunningAfterLegalize); 00243 }; 00244 } 00245 00246 //===----------------------------------------------------------------------===// 00247 // TargetLowering::DAGCombinerInfo implementation 00248 //===----------------------------------------------------------------------===// 00249 00250 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 00251 ((DAGCombiner*)DC)->AddToWorkList(N); 00252 } 00253 00254 SDOperand TargetLowering::DAGCombinerInfo:: 00255 CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 00256 return ((DAGCombiner*)DC)->CombineTo(N, To); 00257 } 00258 00259 SDOperand TargetLowering::DAGCombinerInfo:: 00260 CombineTo(SDNode *N, SDOperand Res) { 00261 return ((DAGCombiner*)DC)->CombineTo(N, Res); 00262 } 00263 00264 00265 SDOperand TargetLowering::DAGCombinerInfo:: 00266 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 00267 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 00268 } 00269 00270 00271 00272 00273 //===----------------------------------------------------------------------===// 00274 00275 00276 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 00277 // that selects between the values 1 and 0, making it equivalent to a setcc. 00278 // Also, set the incoming LHS, RHS, and CC references to the appropriate 00279 // nodes based on the type of node we are checking. This simplifies life a 00280 // bit for the callers. 00281 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 00282 SDOperand &CC) { 00283 if (N.getOpcode() == ISD::SETCC) { 00284 LHS = N.getOperand(0); 00285 RHS = N.getOperand(1); 00286 CC = N.getOperand(2); 00287 return true; 00288 } 00289 if (N.getOpcode() == ISD::SELECT_CC && 00290 N.getOperand(2).getOpcode() == ISD::Constant && 00291 N.getOperand(3).getOpcode() == ISD::Constant && 00292 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 00293 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 00294 LHS = N.getOperand(0); 00295 RHS = N.getOperand(1); 00296 CC = N.getOperand(4); 00297 return true; 00298 } 00299 return false; 00300 } 00301 00302 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 00303 // one use. If this is true, it allows the users to invert the operation for 00304 // free when it is profitable to do so. 00305 static bool isOneUseSetCC(SDOperand N) { 00306 SDOperand N0, N1, N2; 00307 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 00308 return true; 00309 return false; 00310 } 00311 00312 // FIXME: This should probably go in the ISD class rather than being duplicated 00313 // in several files. 00314 static bool isCommutativeBinOp(unsigned Opcode) { 00315 switch (Opcode) { 00316 case ISD::ADD: 00317 case ISD::MUL: 00318 case ISD::AND: 00319 case ISD::OR: 00320 case ISD::XOR: return true; 00321 default: return false; // FIXME: Need commutative info for user ops! 00322 } 00323 } 00324 00325 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 00326 MVT::ValueType VT = N0.getValueType(); 00327 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 00328 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 00329 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 00330 if (isa<ConstantSDNode>(N1)) { 00331 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 00332 AddToWorkList(OpNode.Val); 00333 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 00334 } else if (N0.hasOneUse()) { 00335 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 00336 AddToWorkList(OpNode.Val); 00337 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 00338 } 00339 } 00340 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 00341 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 00342 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 00343 if (isa<ConstantSDNode>(N0)) { 00344 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 00345 AddToWorkList(OpNode.Val); 00346 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 00347 } else if (N1.hasOneUse()) { 00348 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 00349 AddToWorkList(OpNode.Val); 00350 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 00351 } 00352 } 00353 return SDOperand(); 00354 } 00355 00356 void DAGCombiner::Run(bool RunningAfterLegalize) { 00357 // set the instance variable, so that the various visit routines may use it. 00358 AfterLegalize = RunningAfterLegalize; 00359 00360 // Add all the dag nodes to the worklist. 00361 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 00362 E = DAG.allnodes_end(); I != E; ++I) 00363 WorkList.push_back(I); 00364 00365 // Create a dummy node (which is not added to allnodes), that adds a reference 00366 // to the root node, preventing it from being deleted, and tracking any 00367 // changes of the root. 00368 HandleSDNode Dummy(DAG.getRoot()); 00369 00370 00371 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 00372 TargetLowering::DAGCombinerInfo 00373 DagCombineInfo(DAG, !RunningAfterLegalize, this); 00374 00375 // while the worklist isn't empty, inspect the node on the end of it and 00376 // try and combine it. 00377 while (!WorkList.empty()) { 00378 SDNode *N = WorkList.back(); 00379 WorkList.pop_back(); 00380 00381 // If N has no uses, it is dead. Make sure to revisit all N's operands once 00382 // N is deleted from the DAG, since they too may now be dead or may have a 00383 // reduced number of uses, allowing other xforms. 00384 if (N->use_empty() && N != &Dummy) { 00385 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 00386 WorkList.push_back(N->getOperand(i).Val); 00387 00388 removeFromWorkList(N); 00389 DAG.DeleteNode(N); 00390 continue; 00391 } 00392 00393 SDOperand RV = visit(N); 00394 00395 // If nothing happened, try a target-specific DAG combine. 00396 if (RV.Val == 0) { 00397 assert(N->getOpcode() != ISD::DELETED_NODE && 00398 "Node was deleted but visit returned NULL!"); 00399 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 00400 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 00401 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 00402 } 00403 00404 if (RV.Val) { 00405 ++NodesCombined; 00406 // If we get back the same node we passed in, rather than a new node or 00407 // zero, we know that the node must have defined multiple values and 00408 // CombineTo was used. Since CombineTo takes care of the worklist 00409 // mechanics for us, we have no work to do in this case. 00410 if (RV.Val != N) { 00411 assert(N->getOpcode() != ISD::DELETED_NODE && 00412 RV.Val->getOpcode() != ISD::DELETED_NODE && 00413 "Node was deleted but visit returned new node!"); 00414 00415 DEBUG(std::cerr << "\nReplacing "; N->dump(); 00416 std::cerr << "\nWith: "; RV.Val->dump(&DAG); 00417 std::cerr << '\n'); 00418 std::vector<SDNode*> NowDead; 00419 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 00420 00421 // Push the new node and any users onto the worklist 00422 WorkList.push_back(RV.Val); 00423 AddUsersToWorkList(RV.Val); 00424 00425 // Nodes can end up on the worklist more than once. Make sure we do 00426 // not process a node that has been replaced. 00427 removeFromWorkList(N); 00428 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 00429 removeFromWorkList(NowDead[i]); 00430 00431 // Finally, since the node is now dead, remove it from the graph. 00432 DAG.DeleteNode(N); 00433 } 00434 } 00435 } 00436 00437 // If the root changed (e.g. it was a dead load, update the root). 00438 DAG.setRoot(Dummy.getValue()); 00439 } 00440 00441 SDOperand DAGCombiner::visit(SDNode *N) { 00442 switch(N->getOpcode()) { 00443 default: break; 00444 case ISD::TokenFactor: return visitTokenFactor(N); 00445 case ISD::ADD: return visitADD(N); 00446 case ISD::SUB: return visitSUB(N); 00447 case ISD::MUL: return visitMUL(N); 00448 case ISD::SDIV: return visitSDIV(N); 00449 case ISD::UDIV: return visitUDIV(N); 00450 case ISD::SREM: return visitSREM(N); 00451 case ISD::UREM: return visitUREM(N); 00452 case ISD::MULHU: return visitMULHU(N); 00453 case ISD::MULHS: return visitMULHS(N); 00454 case ISD::AND: return visitAND(N); 00455 case ISD::OR: return visitOR(N); 00456 case ISD::XOR: return visitXOR(N); 00457 case ISD::SHL: return visitSHL(N); 00458 case ISD::SRA: return visitSRA(N); 00459 case ISD::SRL: return visitSRL(N); 00460 case ISD::CTLZ: return visitCTLZ(N); 00461 case ISD::CTTZ: return visitCTTZ(N); 00462 case ISD::CTPOP: return visitCTPOP(N); 00463 case ISD::SELECT: return visitSELECT(N); 00464 case ISD::SELECT_CC: return visitSELECT_CC(N); 00465 case ISD::SETCC: return visitSETCC(N); 00466 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 00467 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 00468 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 00469 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 00470 case ISD::TRUNCATE: return visitTRUNCATE(N); 00471 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 00472 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 00473 case ISD::FADD: return visitFADD(N); 00474 case ISD::FSUB: return visitFSUB(N); 00475 case ISD::FMUL: return visitFMUL(N); 00476 case ISD::FDIV: return visitFDIV(N); 00477 case ISD::FREM: return visitFREM(N); 00478 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 00479 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 00480 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 00481 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 00482 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 00483 case ISD::FP_ROUND: return visitFP_ROUND(N); 00484 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 00485 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 00486 case ISD::FNEG: return visitFNEG(N); 00487 case ISD::FABS: return visitFABS(N); 00488 case ISD::BRCOND: return visitBRCOND(N); 00489 case ISD::BR_CC: return visitBR_CC(N); 00490 case ISD::LOAD: return visitLOAD(N); 00491 case ISD::EXTLOAD: 00492 case ISD::SEXTLOAD: 00493 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 00494 case ISD::STORE: return visitSTORE(N); 00495 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 00496 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 00497 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 00498 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 00499 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 00500 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 00501 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 00502 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 00503 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 00504 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 00505 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 00506 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 00507 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 00508 } 00509 return SDOperand(); 00510 } 00511 00512 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 00513 std::vector<SDOperand> Ops; 00514 bool Changed = false; 00515 00516 // If the token factor has two operands and one is the entry token, replace 00517 // the token factor with the other operand. 00518 if (N->getNumOperands() == 2) { 00519 if (N->getOperand(0).getOpcode() == ISD::EntryToken || 00520 N->getOperand(0) == N->getOperand(1)) 00521 return N->getOperand(1); 00522 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 00523 return N->getOperand(0); 00524 } 00525 00526 // fold (tokenfactor (tokenfactor)) -> tokenfactor 00527 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 00528 SDOperand Op = N->getOperand(i); 00529 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 00530 AddToWorkList(Op.Val); // Remove dead node. 00531 Changed = true; 00532 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 00533 Ops.push_back(Op.getOperand(j)); 00534 } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) { 00535 Ops.push_back(Op); 00536 } else { 00537 // Deleted an operand that was the same as the last one. 00538 Changed = true; 00539 } 00540 } 00541 if (Changed) 00542 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 00543 return SDOperand(); 00544 } 00545 00546 SDOperand DAGCombiner::visitADD(SDNode *N) { 00547 SDOperand N0 = N->getOperand(0); 00548 SDOperand N1 = N->getOperand(1); 00549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 00550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00551 MVT::ValueType VT = N0.getValueType(); 00552 00553 // fold (add c1, c2) -> c1+c2 00554 if (N0C && N1C) 00555 return DAG.getNode(ISD::ADD, VT, N0, N1); 00556 // canonicalize constant to RHS 00557 if (N0C && !N1C) 00558 return DAG.getNode(ISD::ADD, VT, N1, N0); 00559 // fold (add x, 0) -> x 00560 if (N1C && N1C->isNullValue()) 00561 return N0; 00562 // fold ((c1-A)+c2) -> (c1+c2)-A 00563 if (N1C && N0.getOpcode() == ISD::SUB) 00564 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 00565 return DAG.getNode(ISD::SUB, VT, 00566 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 00567 N0.getOperand(1)); 00568 // reassociate add 00569 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 00570 if (RADD.Val != 0) 00571 return RADD; 00572 // fold ((0-A) + B) -> B-A 00573 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 00574 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 00575 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 00576 // fold (A + (0-B)) -> A-B 00577 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 00578 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 00579 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 00580 // fold (A+(B-A)) -> B 00581 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 00582 return N1.getOperand(0); 00583 00584 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 00585 return SDOperand(N, 0); 00586 00587 // fold (a+b) -> (a|b) iff a and b share no bits. 00588 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 00589 uint64_t LHSZero, LHSOne; 00590 uint64_t RHSZero, RHSOne; 00591 uint64_t Mask = MVT::getIntVTBitMask(VT); 00592 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 00593 if (LHSZero) { 00594 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 00595 00596 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 00597 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 00598 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 00599 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 00600 return DAG.getNode(ISD::OR, VT, N0, N1); 00601 } 00602 } 00603 00604 return SDOperand(); 00605 } 00606 00607 SDOperand DAGCombiner::visitSUB(SDNode *N) { 00608 SDOperand N0 = N->getOperand(0); 00609 SDOperand N1 = N->getOperand(1); 00610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 00611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 00612 MVT::ValueType VT = N0.getValueType(); 00613 00614 // fold (sub x, x) -> 0 00615 if (N0 == N1) 00616 return DAG.getConstant(0, N->getValueType(0)); 00617 // fold (sub c1, c2) -> c1-c2 00618 if (N0C && N1C) 00619 return DAG.getNode(ISD::SUB, VT, N0, N1); 00620 // fold (sub x, c) -> (add x, -c) 00621 if (N1C) 00622 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 00623 // fold (A+B)-A -> B 00624 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 00625 return N0.getOperand(1); 00626 // fold (A+B)-B -> A 00627 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 00628 return N0.getOperand(0); 00629 return SDOperand(); 00630 } 00631 00632 SDOperand DAGCombiner::visitMUL(SDNode *N) { 00633 SDOperand N0 = N->getOperand(0); 00634 SDOperand N1 = N->getOperand(1); 00635 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 00636 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00637 MVT::ValueType VT = N0.getValueType(); 00638 00639 // fold (mul c1, c2) -> c1*c2 00640 if (N0C && N1C) 00641 return DAG.getNode(ISD::MUL, VT, N0, N1); 00642 // canonicalize constant to RHS 00643 if (N0C && !N1C) 00644 return DAG.getNode(ISD::MUL, VT, N1, N0); 00645 // fold (mul x, 0) -> 0 00646 if (N1C && N1C->isNullValue()) 00647 return N1; 00648 // fold (mul x, -1) -> 0-x 00649 if (N1C && N1C->isAllOnesValue()) 00650 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 00651 // fold (mul x, (1 << c)) -> x << c 00652 if (N1C && isPowerOf2_64(N1C->getValue())) 00653 return DAG.getNode(ISD::SHL, VT, N0, 00654 DAG.getConstant(Log2_64(N1C->getValue()), 00655 TLI.getShiftAmountTy())); 00656 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 00657 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 00658 // FIXME: If the input is something that is easily negated (e.g. a 00659 // single-use add), we should put the negate there. 00660 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 00661 DAG.getNode(ISD::SHL, VT, N0, 00662 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 00663 TLI.getShiftAmountTy()))); 00664 } 00665 00666 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 00667 if (N1C && N0.getOpcode() == ISD::SHL && 00668 isa<ConstantSDNode>(N0.getOperand(1))) { 00669 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 00670 AddToWorkList(C3.Val); 00671 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 00672 } 00673 00674 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 00675 // use. 00676 { 00677 SDOperand Sh(0,0), Y(0,0); 00678 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 00679 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 00680 N0.Val->hasOneUse()) { 00681 Sh = N0; Y = N1; 00682 } else if (N1.getOpcode() == ISD::SHL && 00683 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 00684 Sh = N1; Y = N0; 00685 } 00686 if (Sh.Val) { 00687 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 00688 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 00689 } 00690 } 00691 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 00692 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 00693 isa<ConstantSDNode>(N0.getOperand(1))) { 00694 return DAG.getNode(ISD::ADD, VT, 00695 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 00696 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 00697 } 00698 00699 // reassociate mul 00700 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 00701 if (RMUL.Val != 0) 00702 return RMUL; 00703 return SDOperand(); 00704 } 00705 00706 SDOperand DAGCombiner::visitSDIV(SDNode *N) { 00707 SDOperand N0 = N->getOperand(0); 00708 SDOperand N1 = N->getOperand(1); 00709 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 00710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 00711 MVT::ValueType VT = N->getValueType(0); 00712 00713 // fold (sdiv c1, c2) -> c1/c2 00714 if (N0C && N1C && !N1C->isNullValue()) 00715 return DAG.getNode(ISD::SDIV, VT, N0, N1); 00716 // fold (sdiv X, 1) -> X 00717 if (N1C && N1C->getSignExtended() == 1LL) 00718 return N0; 00719 // fold (sdiv X, -1) -> 0-X 00720 if (N1C && N1C->isAllOnesValue()) 00721 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 00722 // If we know the sign bits of both operands are zero, strength reduce to a 00723 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 00724 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 00725 if (TLI.MaskedValueIsZero(N1, SignBit) && 00726 TLI.MaskedValueIsZero(N0, SignBit)) 00727 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 00728 // fold (sdiv X, pow2) -> simple ops after legalize 00729 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 00730 (isPowerOf2_64(N1C->getSignExtended()) || 00731 isPowerOf2_64(-N1C->getSignExtended()))) { 00732 // If dividing by powers of two is cheap, then don't perform the following 00733 // fold. 00734 if (TLI.isPow2DivCheap()) 00735 return SDOperand(); 00736 int64_t pow2 = N1C->getSignExtended(); 00737 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 00738 unsigned lg2 = Log2_64(abs2); 00739 // Splat the sign bit into the register 00740 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 00741 DAG.getConstant(MVT::getSizeInBits(VT)-1, 00742 TLI.getShiftAmountTy())); 00743 AddToWorkList(SGN.Val); 00744 // Add (N0 < 0) ? abs2 - 1 : 0; 00745 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 00746 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 00747 TLI.getShiftAmountTy())); 00748 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 00749 AddToWorkList(SRL.Val); 00750 AddToWorkList(ADD.Val); // Divide by pow2 00751 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 00752 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 00753 // If we're dividing by a positive value, we're done. Otherwise, we must 00754 // negate the result. 00755 if (pow2 > 0) 00756 return SRA; 00757 AddToWorkList(SRA.Val); 00758 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 00759 } 00760 // if integer divide is expensive and we satisfy the requirements, emit an 00761 // alternate sequence. 00762 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 00763 !TLI.isIntDivCheap()) { 00764 SDOperand Op = BuildSDIV(N); 00765 if (Op.Val) return Op; 00766 } 00767 return SDOperand(); 00768 } 00769 00770 SDOperand DAGCombiner::visitUDIV(SDNode *N) { 00771 SDOperand N0 = N->getOperand(0); 00772 SDOperand N1 = N->getOperand(1); 00773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 00774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 00775 MVT::ValueType VT = N->getValueType(0); 00776 00777 // fold (udiv c1, c2) -> c1/c2 00778 if (N0C && N1C && !N1C->isNullValue()) 00779 return DAG.getNode(ISD::UDIV, VT, N0, N1); 00780 // fold (udiv x, (1 << c)) -> x >>u c 00781 if (N1C && isPowerOf2_64(N1C->getValue())) 00782 return DAG.getNode(ISD::SRL, VT, N0, 00783 DAG.getConstant(Log2_64(N1C->getValue()), 00784 TLI.getShiftAmountTy())); 00785 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 00786 if (N1.getOpcode() == ISD::SHL) { 00787 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 00788 if (isPowerOf2_64(SHC->getValue())) { 00789 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 00790 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 00791 DAG.getConstant(Log2_64(SHC->getValue()), 00792 ADDVT)); 00793 AddToWorkList(Add.Val); 00794 return DAG.getNode(ISD::SRL, VT, N0, Add); 00795 } 00796 } 00797 } 00798 // fold (udiv x, c) -> alternate 00799 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 00800 SDOperand Op = BuildUDIV(N); 00801 if (Op.Val) return Op; 00802 } 00803 return SDOperand(); 00804 } 00805 00806 SDOperand DAGCombiner::visitSREM(SDNode *N) { 00807 SDOperand N0 = N->getOperand(0); 00808 SDOperand N1 = N->getOperand(1); 00809 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 00810 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00811 MVT::ValueType VT = N->getValueType(0); 00812 00813 // fold (srem c1, c2) -> c1%c2 00814 if (N0C && N1C && !N1C->isNullValue()) 00815 return DAG.getNode(ISD::SREM, VT, N0, N1); 00816 // If we know the sign bits of both operands are zero, strength reduce to a 00817 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 00818 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 00819 if (TLI.MaskedValueIsZero(N1, SignBit) && 00820 TLI.MaskedValueIsZero(N0, SignBit)) 00821 return DAG.getNode(ISD::UREM, VT, N0, N1); 00822 return SDOperand(); 00823 } 00824 00825 SDOperand DAGCombiner::visitUREM(SDNode *N) { 00826 SDOperand N0 = N->getOperand(0); 00827 SDOperand N1 = N->getOperand(1); 00828 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 00829 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00830 MVT::ValueType VT = N->getValueType(0); 00831 00832 // fold (urem c1, c2) -> c1%c2 00833 if (N0C && N1C && !N1C->isNullValue()) 00834 return DAG.getNode(ISD::UREM, VT, N0, N1); 00835 // fold (urem x, pow2) -> (and x, pow2-1) 00836 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 00837 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 00838 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 00839 if (N1.getOpcode() == ISD::SHL) { 00840 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 00841 if (isPowerOf2_64(SHC->getValue())) { 00842 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 00843 AddToWorkList(Add.Val); 00844 return DAG.getNode(ISD::AND, VT, N0, Add); 00845 } 00846 } 00847 } 00848 return SDOperand(); 00849 } 00850 00851 SDOperand DAGCombiner::visitMULHS(SDNode *N) { 00852 SDOperand N0 = N->getOperand(0); 00853 SDOperand N1 = N->getOperand(1); 00854 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00855 00856 // fold (mulhs x, 0) -> 0 00857 if (N1C && N1C->isNullValue()) 00858 return N1; 00859 // fold (mulhs x, 1) -> (sra x, size(x)-1) 00860 if (N1C && N1C->getValue() == 1) 00861 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 00862 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 00863 TLI.getShiftAmountTy())); 00864 return SDOperand(); 00865 } 00866 00867 SDOperand DAGCombiner::visitMULHU(SDNode *N) { 00868 SDOperand N0 = N->getOperand(0); 00869 SDOperand N1 = N->getOperand(1); 00870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00871 00872 // fold (mulhu x, 0) -> 0 00873 if (N1C && N1C->isNullValue()) 00874 return N1; 00875 // fold (mulhu x, 1) -> 0 00876 if (N1C && N1C->getValue() == 1) 00877 return DAG.getConstant(0, N0.getValueType()); 00878 return SDOperand(); 00879 } 00880 00881 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 00882 /// two operands of the same opcode, try to simplify it. 00883 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 00884 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 00885 MVT::ValueType VT = N0.getValueType(); 00886 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 00887 00888 // For each of OP in AND/OR/XOR: 00889 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 00890 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 00891 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 00892 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 00893 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 00894 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 00895 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 00896 SDOperand ORNode = DAG.getNode(N->getOpcode(), 00897 N0.getOperand(0).getValueType(), 00898 N0.getOperand(0), N1.getOperand(0)); 00899 AddToWorkList(ORNode.Val); 00900 return DAG.getNode(N0.getOpcode(), VT, ORNode); 00901 } 00902 00903 // For each of OP in SHL/SRL/SRA/AND... 00904 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 00905 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 00906 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 00907 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 00908 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 00909 N0.getOperand(1) == N1.getOperand(1)) { 00910 SDOperand ORNode = DAG.getNode(N->getOpcode(), 00911 N0.getOperand(0).getValueType(), 00912 N0.getOperand(0), N1.getOperand(0)); 00913 AddToWorkList(ORNode.Val); 00914 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 00915 } 00916 00917 return SDOperand(); 00918 } 00919 00920 SDOperand DAGCombiner::visitAND(SDNode *N) { 00921 SDOperand N0 = N->getOperand(0); 00922 SDOperand N1 = N->getOperand(1); 00923 SDOperand LL, LR, RL, RR, CC0, CC1; 00924 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 00925 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 00926 MVT::ValueType VT = N1.getValueType(); 00927 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 00928 00929 // fold (and c1, c2) -> c1&c2 00930 if (N0C && N1C) 00931 return DAG.getNode(ISD::AND, VT, N0, N1); 00932 // canonicalize constant to RHS 00933 if (N0C && !N1C) 00934 return DAG.getNode(ISD::AND, VT, N1, N0); 00935 // fold (and x, -1) -> x 00936 if (N1C && N1C->isAllOnesValue()) 00937 return N0; 00938 // if (and x, c) is known to be zero, return 0 00939 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 00940 return DAG.getConstant(0, VT); 00941 // reassociate and 00942 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 00943 if (RAND.Val != 0) 00944 return RAND; 00945 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 00946 if (N1C && N0.getOpcode() == ISD::OR) 00947 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 00948 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 00949 return N1; 00950 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 00951 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 00952 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 00953 if (TLI.MaskedValueIsZero(N0.getOperand(0), 00954 ~N1C->getValue() & InMask)) { 00955 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 00956 N0.getOperand(0)); 00957 00958 // Replace uses of the AND with uses of the Zero extend node. 00959 CombineTo(N, Zext); 00960 00961 // We actually want to replace all uses of the any_extend with the 00962 // zero_extend, to avoid duplicating things. This will later cause this 00963 // AND to be folded. 00964 CombineTo(N0.Val, Zext); 00965 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 00966 } 00967 } 00968 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 00969 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 00970 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 00971 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 00972 00973 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 00974 MVT::isInteger(LL.getValueType())) { 00975 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 00976 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 00977 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 00978 AddToWorkList(ORNode.Val); 00979 return DAG.getSetCC(VT, ORNode, LR, Op1); 00980 } 00981 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 00982 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 00983 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 00984 AddToWorkList(ANDNode.Val); 00985 return DAG.getSetCC(VT, ANDNode, LR, Op1); 00986 } 00987 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 00988 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 00989 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 00990 AddToWorkList(ORNode.Val); 00991 return DAG.getSetCC(VT, ORNode, LR, Op1); 00992 } 00993 } 00994 // canonicalize equivalent to ll == rl 00995 if (LL == RR && LR == RL) { 00996 Op1 = ISD::getSetCCSwappedOperands(Op1); 00997 std::swap(RL, RR); 00998 } 00999 if (LL == RL && LR == RR) { 01000 bool isInteger = MVT::isInteger(LL.getValueType()); 01001 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 01002 if (Result != ISD::SETCC_INVALID) 01003 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 01004 } 01005 } 01006 01007 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 01008 if (N0.getOpcode() == N1.getOpcode()) { 01009 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 01010 if (Tmp.Val) return Tmp; 01011 } 01012 01013 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 01014 // fold (and (sra)) -> (and (srl)) when possible. 01015 if (!MVT::isVector(VT) && 01016 SimplifyDemandedBits(SDOperand(N, 0))) 01017 return SDOperand(N, 0); 01018 // fold (zext_inreg (extload x)) -> (zextload x) 01019 if (N0.getOpcode() == ISD::EXTLOAD) { 01020 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 01021 // If we zero all the possible extended bits, then we can turn this into 01022 // a zextload if we are running before legalize or the operation is legal. 01023 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 01024 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 01025 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 01026 N0.getOperand(1), N0.getOperand(2), 01027 EVT); 01028 AddToWorkList(N); 01029 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 01030 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01031 } 01032 } 01033 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 01034 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 01035 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 01036 // If we zero all the possible extended bits, then we can turn this into 01037 // a zextload if we are running before legalize or the operation is legal. 01038 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 01039 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 01040 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 01041 N0.getOperand(1), N0.getOperand(2), 01042 EVT); 01043 AddToWorkList(N); 01044 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 01045 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01046 } 01047 } 01048 01049 // fold (and (load x), 255) -> (zextload x, i8) 01050 // fold (and (extload x, i16), 255) -> (zextload x, i8) 01051 if (N1C && 01052 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 01053 N0.getOpcode() == ISD::ZEXTLOAD) && 01054 N0.hasOneUse()) { 01055 MVT::ValueType EVT, LoadedVT; 01056 if (N1C->getValue() == 255) 01057 EVT = MVT::i8; 01058 else if (N1C->getValue() == 65535) 01059 EVT = MVT::i16; 01060 else if (N1C->getValue() == ~0U) 01061 EVT = MVT::i32; 01062 else 01063 EVT = MVT::Other; 01064 01065 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 01066 cast<VTSDNode>(N0.getOperand(3))->getVT(); 01067 if (EVT != MVT::Other && LoadedVT > EVT && 01068 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 01069 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 01070 // For big endian targets, we need to add an offset to the pointer to load 01071 // the correct bytes. For little endian systems, we merely need to read 01072 // fewer bytes from the same pointer. 01073 unsigned PtrOff = 01074 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 01075 SDOperand NewPtr = N0.getOperand(1); 01076 if (!TLI.isLittleEndian()) 01077 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 01078 DAG.getConstant(PtrOff, PtrType)); 01079 AddToWorkList(NewPtr.Val); 01080 SDOperand Load = 01081 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 01082 N0.getOperand(2), EVT); 01083 AddToWorkList(N); 01084 CombineTo(N0.Val, Load, Load.getValue(1)); 01085 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01086 } 01087 } 01088 01089 return SDOperand(); 01090 } 01091 01092 SDOperand DAGCombiner::visitOR(SDNode *N) { 01093 SDOperand N0 = N->getOperand(0); 01094 SDOperand N1 = N->getOperand(1); 01095 SDOperand LL, LR, RL, RR, CC0, CC1; 01096 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01097 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01098 MVT::ValueType VT = N1.getValueType(); 01099 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 01100 01101 // fold (or c1, c2) -> c1|c2 01102 if (N0C && N1C) 01103 return DAG.getNode(ISD::OR, VT, N0, N1); 01104 // canonicalize constant to RHS 01105 if (N0C && !N1C) 01106 return DAG.getNode(ISD::OR, VT, N1, N0); 01107 // fold (or x, 0) -> x 01108 if (N1C && N1C->isNullValue()) 01109 return N0; 01110 // fold (or x, -1) -> -1 01111 if (N1C && N1C->isAllOnesValue()) 01112 return N1; 01113 // fold (or x, c) -> c iff (x & ~c) == 0 01114 if (N1C && 01115 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 01116 return N1; 01117 // reassociate or 01118 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 01119 if (ROR.Val != 0) 01120 return ROR; 01121 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 01122 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 01123 isa<ConstantSDNode>(N0.getOperand(1))) { 01124 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 01125 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 01126 N1), 01127 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 01128 } 01129 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 01130 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 01131 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 01132 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 01133 01134 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 01135 MVT::isInteger(LL.getValueType())) { 01136 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 01137 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 01138 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 01139 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 01140 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 01141 AddToWorkList(ORNode.Val); 01142 return DAG.getSetCC(VT, ORNode, LR, Op1); 01143 } 01144 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 01145 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 01146 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 01147 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 01148 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 01149 AddToWorkList(ANDNode.Val); 01150 return DAG.getSetCC(VT, ANDNode, LR, Op1); 01151 } 01152 } 01153 // canonicalize equivalent to ll == rl 01154 if (LL == RR && LR == RL) { 01155 Op1 = ISD::getSetCCSwappedOperands(Op1); 01156 std::swap(RL, RR); 01157 } 01158 if (LL == RL && LR == RR) { 01159 bool isInteger = MVT::isInteger(LL.getValueType()); 01160 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 01161 if (Result != ISD::SETCC_INVALID) 01162 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 01163 } 01164 } 01165 01166 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 01167 if (N0.getOpcode() == N1.getOpcode()) { 01168 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 01169 if (Tmp.Val) return Tmp; 01170 } 01171 01172 // canonicalize shl to left side in a shl/srl pair, to match rotate 01173 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 01174 std::swap(N0, N1); 01175 // check for rotl, rotr 01176 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 01177 N0.getOperand(0) == N1.getOperand(0) && 01178 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 01179 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 01180 if (N0.getOperand(1).getOpcode() == ISD::Constant && 01181 N1.getOperand(1).getOpcode() == ISD::Constant) { 01182 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 01183 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 01184 if ((c1val + c2val) == OpSizeInBits) 01185 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 01186 } 01187 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 01188 if (N1.getOperand(1).getOpcode() == ISD::SUB && 01189 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 01190 if (ConstantSDNode *SUBC = 01191 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 01192 if (SUBC->getValue() == OpSizeInBits) 01193 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 01194 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 01195 if (N0.getOperand(1).getOpcode() == ISD::SUB && 01196 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 01197 if (ConstantSDNode *SUBC = 01198 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 01199 if (SUBC->getValue() == OpSizeInBits) { 01200 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 01201 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 01202 N1.getOperand(1)); 01203 else 01204 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 01205 N0.getOperand(1)); 01206 } 01207 } 01208 return SDOperand(); 01209 } 01210 01211 SDOperand DAGCombiner::visitXOR(SDNode *N) { 01212 SDOperand N0 = N->getOperand(0); 01213 SDOperand N1 = N->getOperand(1); 01214 SDOperand LHS, RHS, CC; 01215 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01216 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01217 MVT::ValueType VT = N0.getValueType(); 01218 01219 // fold (xor c1, c2) -> c1^c2 01220 if (N0C && N1C) 01221 return DAG.getNode(ISD::XOR, VT, N0, N1); 01222 // canonicalize constant to RHS 01223 if (N0C && !N1C) 01224 return DAG.getNode(ISD::XOR, VT, N1, N0); 01225 // fold (xor x, 0) -> x 01226 if (N1C && N1C->isNullValue()) 01227 return N0; 01228 // reassociate xor 01229 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 01230 if (RXOR.Val != 0) 01231 return RXOR; 01232 // fold !(x cc y) -> (x !cc y) 01233 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 01234 bool isInt = MVT::isInteger(LHS.getValueType()); 01235 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 01236 isInt); 01237 if (N0.getOpcode() == ISD::SETCC) 01238 return DAG.getSetCC(VT, LHS, RHS, NotCC); 01239 if (N0.getOpcode() == ISD::SELECT_CC) 01240 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 01241 assert(0 && "Unhandled SetCC Equivalent!"); 01242 abort(); 01243 } 01244 // fold !(x or y) -> (!x and !y) iff x or y are setcc 01245 if (N1C && N1C->getValue() == 1 && 01246 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 01247 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 01248 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 01249 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 01250 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 01251 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 01252 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 01253 return DAG.getNode(NewOpcode, VT, LHS, RHS); 01254 } 01255 } 01256 // fold !(x or y) -> (!x and !y) iff x or y are constants 01257 if (N1C && N1C->isAllOnesValue() && 01258 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 01259 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 01260 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 01261 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 01262 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 01263 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 01264 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 01265 return DAG.getNode(NewOpcode, VT, LHS, RHS); 01266 } 01267 } 01268 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 01269 if (N1C && N0.getOpcode() == ISD::XOR) { 01270 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 01271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 01272 if (N00C) 01273 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 01274 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 01275 if (N01C) 01276 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 01277 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 01278 } 01279 // fold (xor x, x) -> 0 01280 if (N0 == N1) { 01281 if (!MVT::isVector(VT)) { 01282 return DAG.getConstant(0, VT); 01283 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 01284 // Produce a vector of zeros. 01285 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 01286 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 01287 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 01288 } 01289 } 01290 01291 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 01292 if (N0.getOpcode() == N1.getOpcode()) { 01293 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 01294 if (Tmp.Val) return Tmp; 01295 } 01296 01297 // Simplify the expression using non-local knowledge. 01298 if (!MVT::isVector(VT) && 01299 SimplifyDemandedBits(SDOperand(N, 0))) 01300 return SDOperand(N, 0); 01301 01302 return SDOperand(); 01303 } 01304 01305 SDOperand DAGCombiner::visitSHL(SDNode *N) { 01306 SDOperand N0 = N->getOperand(0); 01307 SDOperand N1 = N->getOperand(1); 01308 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01309 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01310 MVT::ValueType VT = N0.getValueType(); 01311 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 01312 01313 // fold (shl c1, c2) -> c1<<c2 01314 if (N0C && N1C) 01315 return DAG.getNode(ISD::SHL, VT, N0, N1); 01316 // fold (shl 0, x) -> 0 01317 if (N0C && N0C->isNullValue()) 01318 return N0; 01319 // fold (shl x, c >= size(x)) -> undef 01320 if (N1C && N1C->getValue() >= OpSizeInBits) 01321 return DAG.getNode(ISD::UNDEF, VT); 01322 // fold (shl x, 0) -> x 01323 if (N1C && N1C->isNullValue()) 01324 return N0; 01325 // if (shl x, c) is known to be zero, return 0 01326 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 01327 return DAG.getConstant(0, VT); 01328 if (SimplifyDemandedBits(SDOperand(N, 0))) 01329 return SDOperand(N, 0); 01330 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 01331 if (N1C && N0.getOpcode() == ISD::SHL && 01332 N0.getOperand(1).getOpcode() == ISD::Constant) { 01333 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 01334 uint64_t c2 = N1C->getValue(); 01335 if (c1 + c2 > OpSizeInBits) 01336 return DAG.getConstant(0, VT); 01337 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 01338 DAG.getConstant(c1 + c2, N1.getValueType())); 01339 } 01340 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 01341 // (srl (and x, -1 << c1), c1-c2) 01342 if (N1C && N0.getOpcode() == ISD::SRL && 01343 N0.getOperand(1).getOpcode() == ISD::Constant) { 01344 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 01345 uint64_t c2 = N1C->getValue(); 01346 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 01347 DAG.getConstant(~0ULL << c1, VT)); 01348 if (c2 > c1) 01349 return DAG.getNode(ISD::SHL, VT, Mask, 01350 DAG.getConstant(c2-c1, N1.getValueType())); 01351 else 01352 return DAG.getNode(ISD::SRL, VT, Mask, 01353 DAG.getConstant(c1-c2, N1.getValueType())); 01354 } 01355 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 01356 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 01357 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 01358 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 01359 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 01360 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 01361 isa<ConstantSDNode>(N0.getOperand(1))) { 01362 return DAG.getNode(ISD::ADD, VT, 01363 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 01364 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 01365 } 01366 return SDOperand(); 01367 } 01368 01369 SDOperand DAGCombiner::visitSRA(SDNode *N) { 01370 SDOperand N0 = N->getOperand(0); 01371 SDOperand N1 = N->getOperand(1); 01372 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01374 MVT::ValueType VT = N0.getValueType(); 01375 01376 // fold (sra c1, c2) -> c1>>c2 01377 if (N0C && N1C) 01378 return DAG.getNode(ISD::SRA, VT, N0, N1); 01379 // fold (sra 0, x) -> 0 01380 if (N0C && N0C->isNullValue()) 01381 return N0; 01382 // fold (sra -1, x) -> -1 01383 if (N0C && N0C->isAllOnesValue()) 01384 return N0; 01385 // fold (sra x, c >= size(x)) -> undef 01386 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 01387 return DAG.getNode(ISD::UNDEF, VT); 01388 // fold (sra x, 0) -> x 01389 if (N1C && N1C->isNullValue()) 01390 return N0; 01391 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 01392 // sext_inreg. 01393 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 01394 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 01395 MVT::ValueType EVT; 01396 switch (LowBits) { 01397 default: EVT = MVT::Other; break; 01398 case 1: EVT = MVT::i1; break; 01399 case 8: EVT = MVT::i8; break; 01400 case 16: EVT = MVT::i16; break; 01401 case 32: EVT = MVT::i32; break; 01402 } 01403 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 01404 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 01405 DAG.getValueType(EVT)); 01406 } 01407 01408 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 01409 if (N1C && N0.getOpcode() == ISD::SRA) { 01410 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 01411 unsigned Sum = N1C->getValue() + C1->getValue(); 01412 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 01413 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 01414 DAG.getConstant(Sum, N1C->getValueType(0))); 01415 } 01416 } 01417 01418 // Simplify, based on bits shifted out of the LHS. 01419 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 01420 return SDOperand(N, 0); 01421 01422 01423 // If the sign bit is known to be zero, switch this to a SRL. 01424 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 01425 return DAG.getNode(ISD::SRL, VT, N0, N1); 01426 return SDOperand(); 01427 } 01428 01429 SDOperand DAGCombiner::visitSRL(SDNode *N) { 01430 SDOperand N0 = N->getOperand(0); 01431 SDOperand N1 = N->getOperand(1); 01432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01434 MVT::ValueType VT = N0.getValueType(); 01435 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 01436 01437 // fold (srl c1, c2) -> c1 >>u c2 01438 if (N0C && N1C) 01439 return DAG.getNode(ISD::SRL, VT, N0, N1); 01440 // fold (srl 0, x) -> 0 01441 if (N0C && N0C->isNullValue()) 01442 return N0; 01443 // fold (srl x, c >= size(x)) -> undef 01444 if (N1C && N1C->getValue() >= OpSizeInBits) 01445 return DAG.getNode(ISD::UNDEF, VT); 01446 // fold (srl x, 0) -> x 01447 if (N1C && N1C->isNullValue()) 01448 return N0; 01449 // if (srl x, c) is known to be zero, return 0 01450 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 01451 return DAG.getConstant(0, VT); 01452 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 01453 if (N1C && N0.getOpcode() == ISD::SRL && 01454 N0.getOperand(1).getOpcode() == ISD::Constant) { 01455 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 01456 uint64_t c2 = N1C->getValue(); 01457 if (c1 + c2 > OpSizeInBits) 01458 return DAG.getConstant(0, VT); 01459 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 01460 DAG.getConstant(c1 + c2, N1.getValueType())); 01461 } 01462 01463 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 01464 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 01465 // Shifting in all undef bits? 01466 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 01467 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 01468 return DAG.getNode(ISD::UNDEF, VT); 01469 01470 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 01471 AddToWorkList(SmallShift.Val); 01472 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 01473 } 01474 01475 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 01476 if (N1C && N0.getOpcode() == ISD::CTLZ && 01477 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 01478 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 01479 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 01480 01481 // If any of the input bits are KnownOne, then the input couldn't be all 01482 // zeros, thus the result of the srl will always be zero. 01483 if (KnownOne) return DAG.getConstant(0, VT); 01484 01485 // If all of the bits input the to ctlz node are known to be zero, then 01486 // the result of the ctlz is "32" and the result of the shift is one. 01487 uint64_t UnknownBits = ~KnownZero & Mask; 01488 if (UnknownBits == 0) return DAG.getConstant(1, VT); 01489 01490 // Otherwise, check to see if there is exactly one bit input to the ctlz. 01491 if ((UnknownBits & (UnknownBits-1)) == 0) { 01492 // Okay, we know that only that the single bit specified by UnknownBits 01493 // could be set on input to the CTLZ node. If this bit is set, the SRL 01494 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 01495 // to an SRL,XOR pair, which is likely to simplify more. 01496 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 01497 SDOperand Op = N0.getOperand(0); 01498 if (ShAmt) { 01499 Op = DAG.getNode(ISD::SRL, VT, Op, 01500 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 01501 AddToWorkList(Op.Val); 01502 } 01503 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 01504 } 01505 } 01506 01507 return SDOperand(); 01508 } 01509 01510 SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 01511 SDOperand N0 = N->getOperand(0); 01512 MVT::ValueType VT = N->getValueType(0); 01513 01514 // fold (ctlz c1) -> c2 01515 if (isa<ConstantSDNode>(N0)) 01516 return DAG.getNode(ISD::CTLZ, VT, N0); 01517 return SDOperand(); 01518 } 01519 01520 SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 01521 SDOperand N0 = N->getOperand(0); 01522 MVT::ValueType VT = N->getValueType(0); 01523 01524 // fold (cttz c1) -> c2 01525 if (isa<ConstantSDNode>(N0)) 01526 return DAG.getNode(ISD::CTTZ, VT, N0); 01527 return SDOperand(); 01528 } 01529 01530 SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 01531 SDOperand N0 = N->getOperand(0); 01532 MVT::ValueType VT = N->getValueType(0); 01533 01534 // fold (ctpop c1) -> c2 01535 if (isa<ConstantSDNode>(N0)) 01536 return DAG.getNode(ISD::CTPOP, VT, N0); 01537 return SDOperand(); 01538 } 01539 01540 SDOperand DAGCombiner::visitSELECT(SDNode *N) { 01541 SDOperand N0 = N->getOperand(0); 01542 SDOperand N1 = N->getOperand(1); 01543 SDOperand N2 = N->getOperand(2); 01544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01546 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 01547 MVT::ValueType VT = N->getValueType(0); 01548 01549 // fold select C, X, X -> X 01550 if (N1 == N2) 01551 return N1; 01552 // fold select true, X, Y -> X 01553 if (N0C && !N0C->isNullValue()) 01554 return N1; 01555 // fold select false, X, Y -> Y 01556 if (N0C && N0C->isNullValue()) 01557 return N2; 01558 // fold select C, 1, X -> C | X 01559 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 01560 return DAG.getNode(ISD::OR, VT, N0, N2); 01561 // fold select C, 0, X -> ~C & X 01562 // FIXME: this should check for C type == X type, not i1? 01563 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 01564 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 01565 AddToWorkList(XORNode.Val); 01566 return DAG.getNode(ISD::AND, VT, XORNode, N2); 01567 } 01568 // fold select C, X, 1 -> ~C | X 01569 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 01570 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 01571 AddToWorkList(XORNode.Val); 01572 return DAG.getNode(ISD::OR, VT, XORNode, N1); 01573 } 01574 // fold select C, X, 0 -> C & X 01575 // FIXME: this should check for C type == X type, not i1? 01576 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 01577 return DAG.getNode(ISD::AND, VT, N0, N1); 01578 // fold X ? X : Y --> X ? 1 : Y --> X | Y 01579 if (MVT::i1 == VT && N0 == N1) 01580 return DAG.getNode(ISD::OR, VT, N0, N2); 01581 // fold X ? Y : X --> X ? Y : 0 --> X & Y 01582 if (MVT::i1 == VT && N0 == N2) 01583 return DAG.getNode(ISD::AND, VT, N0, N1); 01584 01585 // If we can fold this based on the true/false value, do so. 01586 if (SimplifySelectOps(N, N1, N2)) 01587 return SDOperand(N, 0); // Don't revisit N. 01588 01589 // fold selects based on a setcc into other things, such as min/max/abs 01590 if (N0.getOpcode() == ISD::SETCC) 01591 // FIXME: 01592 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 01593 // having to say they don't support SELECT_CC on every type the DAG knows 01594 // about, since there is no way to mark an opcode illegal at all value types 01595 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 01596 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 01597 N1, N2, N0.getOperand(2)); 01598 else 01599 return SimplifySelect(N0, N1, N2); 01600 return SDOperand(); 01601 } 01602 01603 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 01604 SDOperand N0 = N->getOperand(0); 01605 SDOperand N1 = N->getOperand(1); 01606 SDOperand N2 = N->getOperand(2); 01607 SDOperand N3 = N->getOperand(3); 01608 SDOperand N4 = N->getOperand(4); 01609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 01610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 01611 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 01612 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 01613 01614 // Determine if the condition we're dealing with is constant 01615 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 01616 //ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 01617 01618 // fold select_cc lhs, rhs, x, x, cc -> x 01619 if (N2 == N3) 01620 return N2; 01621 01622 // If we can fold this based on the true/false value, do so. 01623 if (SimplifySelectOps(N, N2, N3)) 01624 return SDOperand(N, 0); // Don't revisit N. 01625 01626 // fold select_cc into other things, such as min/max/abs 01627 return SimplifySelectCC(N0, N1, N2, N3, CC); 01628 } 01629 01630 SDOperand DAGCombiner::visitSETCC(SDNode *N) { 01631 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 01632 cast<CondCodeSDNode>(N->getOperand(2))->get()); 01633 } 01634 01635 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 01636 SDOperand N0 = N->getOperand(0); 01637 MVT::ValueType VT = N->getValueType(0); 01638 01639 // fold (sext c1) -> c1 01640 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 01641 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 01642 01643 // fold (sext (sext x)) -> (sext x) 01644 // fold (sext (aext x)) -> (sext x) 01645 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 01646 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 01647 01648 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 01649 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 01650 (!AfterLegalize || 01651 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 01652 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 01653 DAG.getValueType(N0.getValueType())); 01654 01655 // fold (sext (load x)) -> (sext (truncate (sextload x))) 01656 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 01657 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 01658 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 01659 N0.getOperand(1), N0.getOperand(2), 01660 N0.getValueType()); 01661 CombineTo(N, ExtLoad); 01662 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 01663 ExtLoad.getValue(1)); 01664 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01665 } 01666 01667 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 01668 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 01669 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 01670 N0.hasOneUse()) { 01671 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 01672 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 01673 N0.getOperand(1), N0.getOperand(2), EVT); 01674 CombineTo(N, ExtLoad); 01675 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 01676 ExtLoad.getValue(1)); 01677 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01678 } 01679 01680 return SDOperand(); 01681 } 01682 01683 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 01684 SDOperand N0 = N->getOperand(0); 01685 MVT::ValueType VT = N->getValueType(0); 01686 01687 // fold (zext c1) -> c1 01688 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 01689 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 01690 // fold (zext (zext x)) -> (zext x) 01691 // fold (zext (aext x)) -> (zext x) 01692 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 01693 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 01694 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 01695 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 01696 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 01697 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 01698 // fold (zext (load x)) -> (zext (truncate (zextload x))) 01699 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 01700 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 01701 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 01702 N0.getOperand(1), N0.getOperand(2), 01703 N0.getValueType()); 01704 CombineTo(N, ExtLoad); 01705 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 01706 ExtLoad.getValue(1)); 01707 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01708 } 01709 01710 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 01711 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 01712 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 01713 N0.hasOneUse()) { 01714 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 01715 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 01716 N0.getOperand(1), N0.getOperand(2), EVT); 01717 CombineTo(N, ExtLoad); 01718 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 01719 ExtLoad.getValue(1)); 01720 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01721 } 01722 return SDOperand(); 01723 } 01724 01725 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 01726 SDOperand N0 = N->getOperand(0); 01727 MVT::ValueType VT = N->getValueType(0); 01728 01729 // fold (aext c1) -> c1 01730 if (isa<ConstantSDNode>(N0)) 01731 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 01732 // fold (aext (aext x)) -> (aext x) 01733 // fold (aext (zext x)) -> (zext x) 01734 // fold (aext (sext x)) -> (sext x) 01735 if (N0.getOpcode() == ISD::ANY_EXTEND || 01736 N0.getOpcode() == ISD::ZERO_EXTEND || 01737 N0.getOpcode() == ISD::SIGN_EXTEND) 01738 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 01739 01740 // fold (aext (truncate x)) -> x iff x size == zext size. 01741 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) 01742 return N0.getOperand(0); 01743 // fold (aext (load x)) -> (aext (truncate (extload x))) 01744 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 01745 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 01746 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 01747 N0.getOperand(1), N0.getOperand(2), 01748 N0.getValueType()); 01749 CombineTo(N, ExtLoad); 01750 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 01751 ExtLoad.getValue(1)); 01752 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01753 } 01754 01755 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 01756 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 01757 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 01758 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || 01759 N0.getOpcode() == ISD::SEXTLOAD) && 01760 N0.hasOneUse()) { 01761 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 01762 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), 01763 N0.getOperand(1), N0.getOperand(2), EVT); 01764 CombineTo(N, ExtLoad); 01765 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 01766 ExtLoad.getValue(1)); 01767 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01768 } 01769 return SDOperand(); 01770 } 01771 01772 01773 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 01774 SDOperand N0 = N->getOperand(0); 01775 SDOperand N1 = N->getOperand(1); 01776 MVT::ValueType VT = N->getValueType(0); 01777 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 01778 unsigned EVTBits = MVT::getSizeInBits(EVT); 01779 01780 // fold (sext_in_reg c1) -> c1 01781 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 01782 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 01783 01784 // If the input is already sign extended, just drop the extension. 01785 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 01786 return N0; 01787 01788 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 01789 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 01790 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 01791 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 01792 } 01793 01794 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 01795 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 01796 return DAG.getZeroExtendInReg(N0, EVT); 01797 01798 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 01799 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 01800 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 01801 if (N0.getOpcode() == ISD::SRL) { 01802 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 01803 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 01804 // We can turn this into an SRA iff the input to the SRL is already sign 01805 // extended enough. 01806 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 01807 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 01808 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 01809 } 01810 } 01811 01812 // fold (sext_inreg (extload x)) -> (sextload x) 01813 if (N0.getOpcode() == ISD::EXTLOAD && 01814 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 01815 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 01816 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 01817 N0.getOperand(1), N0.getOperand(2), 01818 EVT); 01819 CombineTo(N, ExtLoad); 01820 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 01821 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01822 } 01823 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 01824 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 01825 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 01826 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 01827 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 01828 N0.getOperand(1), N0.getOperand(2), 01829 EVT); 01830 CombineTo(N, ExtLoad); 01831 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 01832 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01833 } 01834 return SDOperand(); 01835 } 01836 01837 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 01838 SDOperand N0 = N->getOperand(0); 01839 MVT::ValueType VT = N->getValueType(0); 01840 01841 // noop truncate 01842 if (N0.getValueType() == N->getValueType(0)) 01843 return N0; 01844 // fold (truncate c1) -> c1 01845 if (isa<ConstantSDNode>(N0)) 01846 return DAG.getNode(ISD::TRUNCATE, VT, N0); 01847 // fold (truncate (truncate x)) -> (truncate x) 01848 if (N0.getOpcode() == ISD::TRUNCATE) 01849 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 01850 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 01851 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 01852 N0.getOpcode() == ISD::ANY_EXTEND) { 01853 if (N0.getValueType() < VT) 01854 // if the source is smaller than the dest, we still need an extend 01855 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 01856 else if (N0.getValueType() > VT) 01857 // if the source is larger than the dest, than we just need the truncate 01858 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 01859 else 01860 // if the source and dest are the same type, we can drop both the extend 01861 // and the truncate 01862 return N0.getOperand(0); 01863 } 01864 // fold (truncate (load x)) -> (smaller load x) 01865 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 01866 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 01867 "Cannot truncate to larger type!"); 01868 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 01869 // For big endian targets, we need to add an offset to the pointer to load 01870 // the correct bytes. For little endian systems, we merely need to read 01871 // fewer bytes from the same pointer. 01872 uint64_t PtrOff = 01873 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 01874 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 01875 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 01876 DAG.getConstant(PtrOff, PtrType)); 01877 AddToWorkList(NewPtr.Val); 01878 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 01879 AddToWorkList(N); 01880 CombineTo(N0.Val, Load, Load.getValue(1)); 01881 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 01882 } 01883 return SDOperand(); 01884 } 01885 01886 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 01887 SDOperand N0 = N->getOperand(0); 01888 MVT::ValueType VT = N->getValueType(0); 01889 01890 // If the input is a constant, let getNode() fold it. 01891 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 01892 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 01893 if (Res.Val != N) return Res; 01894 } 01895 01896 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 01897 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 01898 01899 // fold (conv (load x)) -> (load (conv*)x) 01900 // FIXME: These xforms need to know that the resultant load doesn't need a 01901 // higher alignment than the original! 01902 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 01903 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 01904 N0.getOperand(2)); 01905 AddToWorkList(N); 01906 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 01907 Load.getValue(1)); 01908 return Load; 01909 } 01910 01911 return SDOperand(); 01912 } 01913 01914 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 01915 SDOperand N0 = N->getOperand(0); 01916 MVT::ValueType VT = N->getValueType(0); 01917 01918 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 01919 // First check to see if this is all constant. 01920 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 01921 VT == MVT::Vector) { 01922 bool isSimple = true; 01923 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 01924 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 01925 N0.getOperand(i).getOpcode() != ISD::Constant && 01926 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 01927 isSimple = false; 01928 break; 01929 } 01930 01931 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 01932 if (isSimple && !MVT::isVector(DestEltVT)) { 01933 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 01934 } 01935 } 01936 01937 return SDOperand(); 01938 } 01939 01940 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 01941 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 01942 /// destination element value type. 01943 SDOperand DAGCombiner:: 01944 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 01945 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 01946 01947 // If this is already the right type, we're done. 01948 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 01949 01950 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 01951 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 01952 01953 // If this is a conversion of N elements of one type to N elements of another 01954 // type, convert each element. This handles FP<->INT cases. 01955 if (SrcBitSize == DstBitSize) { 01956 std::vector<SDOperand> Ops; 01957 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 01958 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 01959 AddToWorkList(Ops.back().Val); 01960 } 01961 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 01962 Ops.push_back(DAG.getValueType(DstEltVT)); 01963 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 01964 } 01965 01966 // Otherwise, we're growing or shrinking the elements. To avoid having to 01967 // handle annoying details of growing/shrinking FP values, we convert them to 01968 // int first. 01969 if (MVT::isFloatingPoint(SrcEltVT)) { 01970 // Convert the input float vector to a int vector where the elements are the 01971 // same sizes. 01972 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 01973 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 01974 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 01975 SrcEltVT = IntVT; 01976 } 01977 01978 // Now we know the input is an integer vector. If the output is a FP type, 01979 // convert to integer first, then to FP of the right size. 01980 if (MVT::isFloatingPoint(DstEltVT)) { 01981 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 01982 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 01983 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 01984 01985 // Next, convert to FP elements of the same size. 01986 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 01987 } 01988 01989 // Okay, we know the src/dst types are both integers of differing types. 01990 // Handling growing first. 01991 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 01992 if (SrcBitSize < DstBitSize) { 01993 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 01994 01995 std::vector<SDOperand> Ops; 01996 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 01997 i += NumInputsPerOutput) { 01998 bool isLE = TLI.isLittleEndian(); 01999 uint64_t NewBits = 0; 02000 bool EltIsUndef = true; 02001 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 02002 // Shift the previously computed bits over. 02003 NewBits <<= SrcBitSize; 02004 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 02005 if (Op.getOpcode() == ISD::UNDEF) continue; 02006 EltIsUndef = false; 02007 02008 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 02009 } 02010 02011 if (EltIsUndef) 02012 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 02013 else 02014 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 02015 } 02016 02017 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 02018 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 02019 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 02020 } 02021 02022 // Finally, this must be the case where we are shrinking elements: each input 02023 // turns into multiple outputs. 02024 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 02025 std::vector<SDOperand> Ops; 02026 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 02027 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 02028 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 02029 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 02030 continue; 02031 } 02032 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 02033 02034 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 02035 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 02036 OpVal >>= DstBitSize; 02037 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 02038 } 02039 02040 // For big endian targets, swap the order of the pieces of each element. 02041 if (!TLI.isLittleEndian()) 02042 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 02043 } 02044 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 02045 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 02046 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 02047 } 02048 02049 02050 02051 SDOperand DAGCombiner::visitFADD(SDNode *N) { 02052 SDOperand N0 = N->getOperand(0); 02053 SDOperand N1 = N->getOperand(1); 02054 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02055 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 02056 MVT::ValueType VT = N->getValueType(0); 02057 02058 // fold (fadd c1, c2) -> c1+c2 02059 if (N0CFP && N1CFP) 02060 return DAG.getNode(ISD::FADD, VT, N0, N1); 02061 // canonicalize constant to RHS 02062 if (N0CFP && !N1CFP) 02063 return DAG.getNode(ISD::FADD, VT, N1, N0); 02064 // fold (A + (-B)) -> A-B 02065 if (N1.getOpcode() == ISD::FNEG) 02066 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 02067 // fold ((-A) + B) -> B-A 02068 if (N0.getOpcode() == ISD::FNEG) 02069 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 02070 return SDOperand(); 02071 } 02072 02073 SDOperand DAGCombiner::visitFSUB(SDNode *N) { 02074 SDOperand N0 = N->getOperand(0); 02075 SDOperand N1 = N->getOperand(1); 02076 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02077 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 02078 MVT::ValueType VT = N->getValueType(0); 02079 02080 // fold (fsub c1, c2) -> c1-c2 02081 if (N0CFP && N1CFP) 02082 return DAG.getNode(ISD::FSUB, VT, N0, N1); 02083 // fold (A-(-B)) -> A+B 02084 if (N1.getOpcode() == ISD::FNEG) 02085 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 02086 return SDOperand(); 02087 } 02088 02089 SDOperand DAGCombiner::visitFMUL(SDNode *N) { 02090 SDOperand N0 = N->getOperand(0); 02091 SDOperand N1 = N->getOperand(1); 02092 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02093 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 02094 MVT::ValueType VT = N->getValueType(0); 02095 02096 // fold (fmul c1, c2) -> c1*c2 02097 if (N0CFP && N1CFP) 02098 return DAG.getNode(ISD::FMUL, VT, N0, N1); 02099 // canonicalize constant to RHS 02100 if (N0CFP && !N1CFP) 02101 return DAG.getNode(ISD::FMUL, VT, N1, N0); 02102 // fold (fmul X, 2.0) -> (fadd X, X) 02103 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 02104 return DAG.getNode(ISD::FADD, VT, N0, N0); 02105 return SDOperand(); 02106 } 02107 02108 SDOperand DAGCombiner::visitFDIV(SDNode *N) { 02109 SDOperand N0 = N->getOperand(0); 02110 SDOperand N1 = N->getOperand(1); 02111 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02112 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 02113 MVT::ValueType VT = N->getValueType(0); 02114 02115 // fold (fdiv c1, c2) -> c1/c2 02116 if (N0CFP && N1CFP) 02117 return DAG.getNode(ISD::FDIV, VT, N0, N1); 02118 return SDOperand(); 02119 } 02120 02121 SDOperand DAGCombiner::visitFREM(SDNode *N) { 02122 SDOperand N0 = N->getOperand(0); 02123 SDOperand N1 = N->getOperand(1); 02124 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02125 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 02126 MVT::ValueType VT = N->getValueType(0); 02127 02128 // fold (frem c1, c2) -> fmod(c1,c2) 02129 if (N0CFP && N1CFP) 02130 return DAG.getNode(ISD::FREM, VT, N0, N1); 02131 return SDOperand(); 02132 } 02133 02134 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 02135 SDOperand N0 = N->getOperand(0); 02136 SDOperand N1 = N->getOperand(1); 02137 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02138 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 02139 MVT::ValueType VT = N->getValueType(0); 02140 02141 if (N0CFP && N1CFP) // Constant fold 02142 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 02143 02144 if (N1CFP) { 02145 // copysign(x, c1) -> fabs(x) iff ispos(c1) 02146 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 02147 union { 02148 double d; 02149 int64_t i; 02150 } u; 02151 u.d = N1CFP->getValue(); 02152 if (u.i >= 0) 02153 return DAG.getNode(ISD::FABS, VT, N0); 02154 else 02155 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 02156 } 02157 02158 // copysign(fabs(x), y) -> copysign(x, y) 02159 // copysign(fneg(x), y) -> copysign(x, y) 02160 // copysign(copysign(x,z), y) -> copysign(x, y) 02161 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 02162 N0.getOpcode() == ISD::FCOPYSIGN) 02163 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 02164 02165 // copysign(x, abs(y)) -> abs(x) 02166 if (N1.getOpcode() == ISD::FABS) 02167 return DAG.getNode(ISD::FABS, VT, N0); 02168 02169 // copysign(x, copysign(y,z)) -> copysign(x, z) 02170 if (N1.getOpcode() == ISD::FCOPYSIGN) 02171 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 02172 02173 // copysign(x, fp_extend(y)) -> copysign(x, y) 02174 // copysign(x, fp_round(y)) -> copysign(x, y) 02175 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 02176 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 02177 02178 return SDOperand(); 02179 } 02180 02181 02182 02183 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 02184 SDOperand N0 = N->getOperand(0); 02185 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 02186 MVT::ValueType VT = N->getValueType(0); 02187 02188 // fold (sint_to_fp c1) -> c1fp 02189 if (N0C) 02190 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 02191 return SDOperand(); 02192 } 02193 02194 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 02195 SDOperand N0 = N->getOperand(0); 02196 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 02197 MVT::ValueType VT = N->getValueType(0); 02198 02199 // fold (uint_to_fp c1) -> c1fp 02200 if (N0C) 02201 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 02202 return SDOperand(); 02203 } 02204 02205 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 02206 SDOperand N0 = N->getOperand(0); 02207 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02208 MVT::ValueType VT = N->getValueType(0); 02209 02210 // fold (fp_to_sint c1fp) -> c1 02211 if (N0CFP) 02212 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 02213 return SDOperand(); 02214 } 02215 02216 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 02217 SDOperand N0 = N->getOperand(0); 02218 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02219 MVT::ValueType VT = N->getValueType(0); 02220 02221 // fold (fp_to_uint c1fp) -> c1 02222 if (N0CFP) 02223 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 02224 return SDOperand(); 02225 } 02226 02227 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 02228 SDOperand N0 = N->getOperand(0); 02229 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02230 MVT::ValueType VT = N->getValueType(0); 02231 02232 // fold (fp_round c1fp) -> c1fp 02233 if (N0CFP) 02234 return DAG.getNode(ISD::FP_ROUND, VT, N0); 02235 02236 // fold (fp_round (fp_extend x)) -> x 02237 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 02238 return N0.getOperand(0); 02239 02240 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 02241 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 02242 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 02243 AddToWorkList(Tmp.Val); 02244 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 02245 } 02246 02247 return SDOperand(); 02248 } 02249 02250 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 02251 SDOperand N0 = N->getOperand(0); 02252 MVT::ValueType VT = N->getValueType(0); 02253 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 02254 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02255 02256 // fold (fp_round_inreg c1fp) -> c1fp 02257 if (N0CFP) { 02258 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 02259 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 02260 } 02261 return SDOperand(); 02262 } 02263 02264 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 02265 SDOperand N0 = N->getOperand(0); 02266 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02267 MVT::ValueType VT = N->getValueType(0); 02268 02269 // fold (fp_extend c1fp) -> c1fp 02270 if (N0CFP) 02271 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 02272 02273 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 02274 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 02275 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 02276 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 02277 N0.getOperand(1), N0.getOperand(2), 02278 N0.getValueType()); 02279 CombineTo(N, ExtLoad); 02280 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 02281 ExtLoad.getValue(1)); 02282 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 02283 } 02284 02285 02286 return SDOperand(); 02287 } 02288 02289 SDOperand DAGCombiner::visitFNEG(SDNode *N) { 02290 SDOperand N0 = N->getOperand(0); 02291 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02292 MVT::ValueType VT = N->getValueType(0); 02293 02294 // fold (fneg c1) -> -c1 02295 if (N0CFP) 02296 return DAG.getNode(ISD::FNEG, VT, N0); 02297 // fold (fneg (sub x, y)) -> (sub y, x) 02298 if (N0.getOpcode() == ISD::SUB) 02299 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 02300 // fold (fneg (fneg x)) -> x 02301 if (N0.getOpcode() == ISD::FNEG) 02302 return N0.getOperand(0); 02303 return SDOperand(); 02304 } 02305 02306 SDOperand DAGCombiner::visitFABS(SDNode *N) { 02307 SDOperand N0 = N->getOperand(0); 02308 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 02309 MVT::ValueType VT = N->getValueType(0); 02310 02311 // fold (fabs c1) -> fabs(c1) 02312 if (N0CFP) 02313 return DAG.getNode(ISD::FABS, VT, N0); 02314 // fold (fabs (fabs x)) -> (fabs x) 02315 if (N0.getOpcode() == ISD::FABS) 02316 return N->getOperand(0); 02317 // fold (fabs (fneg x)) -> (fabs x) 02318 // fold (fabs (fcopysign x, y)) -> (fabs x) 02319 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 02320 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 02321 02322 return SDOperand(); 02323 } 02324 02325 SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 02326 SDOperand Chain = N->getOperand(0); 02327 SDOperand N1 = N->getOperand(1); 02328 SDOperand N2 = N->getOperand(2); 02329 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 02330 02331 // never taken branch, fold to chain 02332 if (N1C && N1C->isNullValue()) 02333 return Chain; 02334 // unconditional branch 02335 if (N1C && N1C->getValue() == 1) 02336 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 02337 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 02338 // on the target. 02339 if (N1.getOpcode() == ISD::SETCC && 02340 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 02341 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 02342 N1.getOperand(0), N1.getOperand(1), N2); 02343 } 02344 return SDOperand(); 02345 } 02346 02347 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 02348 // 02349 SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 02350 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 02351 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 02352 02353 // Use SimplifySetCC to simplify SETCC's. 02354 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 02355 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 02356 02357 // fold br_cc true, dest -> br dest (unconditional branch) 02358 if (SCCC && SCCC->getValue()) 02359 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 02360 N->getOperand(4)); 02361 // fold br_cc false, dest -> unconditional fall through 02362 if (SCCC && SCCC->isNullValue()) 02363 return N->getOperand(0); 02364 // fold to a simpler setcc 02365 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 02366 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 02367 Simp.getOperand(2), Simp.getOperand(0), 02368 Simp.getOperand(1), N->getOperand(4)); 02369 return SDOperand(); 02370 } 02371 02372 SDOperand DAGCombiner::visitLOAD(SDNode *N) { 02373 SDOperand Chain = N->getOperand(0); 02374 SDOperand Ptr = N->getOperand(1); 02375 SDOperand SrcValue = N->getOperand(2); 02376 02377 // If there are no uses of the loaded value, change uses of the chain value 02378 // into uses of the chain input (i.e. delete the dead load). 02379 if (N->hasNUsesOfValue(0, 0)) 02380 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 02381 02382 // If this load is directly stored, replace the load value with the stored 02383 // value. 02384 // TODO: Handle store large -> read small portion. 02385 // TODO: Handle TRUNCSTORE/EXTLOAD 02386 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 02387 Chain.getOperand(1).getValueType() == N->getValueType(0)) 02388 return CombineTo(N, Chain.getOperand(1), Chain); 02389 02390 return SDOperand(); 02391 } 02392 02393 /// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 02394 SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 02395 SDOperand Chain = N->getOperand(0); 02396 SDOperand Ptr = N->getOperand(1); 02397 SDOperand SrcValue = N->getOperand(2); 02398 SDOperand EVT = N->getOperand(3); 02399 02400 // If there are no uses of the loaded value, change uses of the chain value 02401 // into uses of the chain input (i.e. delete the dead load). 02402 if (N->hasNUsesOfValue(0, 0)) 02403 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 02404 02405 return SDOperand(); 02406 } 02407 02408 SDOperand DAGCombiner::visitSTORE(SDNode *N) { 02409 SDOperand Chain = N->getOperand(0); 02410 SDOperand Value = N->getOperand(1); 02411 SDOperand Ptr = N->getOperand(2); 02412 SDOperand SrcValue = N->getOperand(3); 02413 02414 // If this is a store that kills a previous store, remove the previous store. 02415 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 02416 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 02417 // Make sure that these stores are the same value type: 02418 // FIXME: we really care that the second store is >= size of the first. 02419 Value.getValueType() == Chain.getOperand(1).getValueType()) { 02420 // Create a new store of Value that replaces both stores. 02421 SDNode *PrevStore = Chain.Val; 02422 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 02423 return Chain; 02424 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 02425 PrevStore->getOperand(0), Value, Ptr, 02426 SrcValue); 02427 CombineTo(N, NewStore); // Nuke this store. 02428 CombineTo(PrevStore, NewStore); // Nuke the previous store. 02429 return SDOperand(N, 0); 02430 } 02431 02432 // If this is a store of a bit convert, store the input value. 02433 // FIXME: This needs to know that the resultant store does not need a 02434 // higher alignment than the original. 02435 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 02436 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 02437 Ptr, SrcValue); 02438 02439 return SDOperand(); 02440 } 02441 02442 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 02443 SDOperand InVec = N->getOperand(0); 02444 SDOperand InVal = N->getOperand(1); 02445 SDOperand EltNo = N->getOperand(2); 02446 02447 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 02448 // vector with the inserted element. 02449 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 02450 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 02451 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 02452 if (Elt < Ops.size()) 02453 Ops[Elt] = InVal; 02454 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops); 02455 } 02456 02457 return SDOperand(); 02458 } 02459 02460 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 02461 SDOperand InVec = N->getOperand(0); 02462 SDOperand InVal = N->getOperand(1); 02463 SDOperand EltNo = N->getOperand(2); 02464 SDOperand NumElts = N->getOperand(3); 02465 SDOperand EltType = N->getOperand(4); 02466 02467 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 02468 // vector with the inserted element. 02469 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 02470 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 02471 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 02472 if (Elt < Ops.size()-2) 02473 Ops[Elt] = InVal; 02474 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops); 02475 } 02476 02477 return SDOperand(); 02478 } 02479 02480 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 02481 unsigned NumInScalars = N->getNumOperands()-2; 02482 SDOperand NumElts = N->getOperand(NumInScalars); 02483 SDOperand EltType = N->getOperand(NumInScalars+1); 02484 02485 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 02486 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 02487 // two distinct vectors, turn this into a shuffle node. 02488 SDOperand VecIn1, VecIn2; 02489 for (unsigned i = 0; i != NumInScalars; ++i) { 02490 // Ignore undef inputs. 02491 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 02492 02493 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 02494 // constant index, bail out. 02495 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 02496 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 02497 VecIn1 = VecIn2 = SDOperand(0, 0); 02498 break; 02499 } 02500 02501 // If the input vector type disagrees with the result of the vbuild_vector, 02502 // we can't make a shuffle. 02503 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 02504 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 02505 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 02506 VecIn1 = VecIn2 = SDOperand(0, 0); 02507 break; 02508 } 02509 02510 // Otherwise, remember this. We allow up to two distinct input vectors. 02511 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 02512 continue; 02513 02514 if (VecIn1.Val == 0) { 02515 VecIn1 = ExtractedFromVec; 02516 } else if (VecIn2.Val == 0) { 02517 VecIn2 = ExtractedFromVec; 02518 } else { 02519 // Too many inputs. 02520 VecIn1 = VecIn2 = SDOperand(0, 0); 02521 break; 02522 } 02523 } 02524 02525 // If everything is good, we can make a shuffle operation. 02526 if (VecIn1.Val) { 02527 std::vector<SDOperand> BuildVecIndices; 02528 for (unsigned i = 0; i != NumInScalars; ++i) { 02529 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 02530 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 02531 continue; 02532 } 02533 02534 SDOperand Extract = N->getOperand(i); 02535 02536 // If extracting from the first vector, just use the index directly. 02537 if (Extract.getOperand(0) == VecIn1) { 02538 BuildVecIndices.push_back(Extract.getOperand(1)); 02539 continue; 02540 } 02541 02542 // Otherwise, use InIdx + VecSize 02543 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 02544 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 02545 } 02546 02547 // Add count and size info. 02548 BuildVecIndices.push_back(NumElts); 02549 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 02550 02551 // Return the new VVECTOR_SHUFFLE node. 02552 std::vector<SDOperand> Ops; 02553 Ops.push_back(VecIn1); 02554 if (VecIn2.Val) { 02555 Ops.push_back(VecIn2); 02556 } else { 02557 // Use an undef vbuild_vector as input for the second operand. 02558 std::vector<SDOperand> UnOps(NumInScalars, 02559 DAG.getNode(ISD::UNDEF, 02560 cast<VTSDNode>(EltType)->getVT())); 02561 UnOps.push_back(NumElts); 02562 UnOps.push_back(EltType); 02563 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps)); 02564 AddToWorkList(Ops.back().Val); 02565 } 02566 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices)); 02567 Ops.push_back(NumElts); 02568 Ops.push_back(EltType); 02569 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 02570 } 02571 02572 return SDOperand(); 02573 } 02574 02575 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 02576 SDOperand ShufMask = N->getOperand(2); 02577 unsigned NumElts = ShufMask.getNumOperands(); 02578 02579 // If the shuffle mask is an identity operation on the LHS, return the LHS. 02580 bool isIdentity = true; 02581 for (unsigned i = 0; i != NumElts; ++i) { 02582 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 02583 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 02584 isIdentity = false; 02585 break; 02586 } 02587 } 02588 if (isIdentity) return N->getOperand(0); 02589 02590 // If the shuffle mask is an identity operation on the RHS, return the RHS. 02591 isIdentity = true; 02592 for (unsigned i = 0; i != NumElts; ++i) { 02593 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 02594 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 02595 isIdentity = false; 02596 break; 02597 } 02598 } 02599 if (isIdentity) return N->getOperand(1); 02600 02601 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 02602 // needed at all. 02603 bool isUnary = true; 02604 bool isSplat = true; 02605 int VecNum = -1; 02606 unsigned BaseIdx = 0; 02607 for (unsigned i = 0; i != NumElts; ++i) 02608 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 02609 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 02610 int V = (Idx < NumElts) ? 0 : 1; 02611 if (VecNum == -1) { 02612 VecNum = V; 02613 BaseIdx = Idx; 02614 } else { 02615 if (BaseIdx != Idx) 02616 isSplat = false; 02617 if (VecNum != V) { 02618 isUnary = false; 02619 break; 02620 } 02621 } 02622 } 02623 02624 SDOperand N0 = N->getOperand(0); 02625 SDOperand N1 = N->getOperand(1); 02626 // Normalize unary shuffle so the RHS is undef. 02627 if (isUnary && VecNum == 1) 02628 std::swap(N0, N1); 02629 02630 // If it is a splat, check if the argument vector is a build_vector with 02631 // all scalar elements the same. 02632 if (isSplat) { 02633 SDNode *V = N0.Val; 02634 if (V->getOpcode() == ISD::BIT_CONVERT) 02635 V = V->getOperand(0).Val; 02636 if (V->getOpcode() == ISD::BUILD_VECTOR) { 02637 unsigned NumElems = V->getNumOperands()-2; 02638 if (NumElems > BaseIdx) { 02639 SDOperand Base; 02640 bool AllSame = true; 02641 for (unsigned i = 0; i != NumElems; ++i) { 02642 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 02643 Base = V->getOperand(i); 02644 break; 02645 } 02646 } 02647 // Splat of <u, u, u, u>, return <u, u, u, u> 02648 if (!Base.Val) 02649 return N0; 02650 for (unsigned i = 0; i != NumElems; ++i) { 02651 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 02652 V->getOperand(i) != Base) { 02653 AllSame = false; 02654 break; 02655 } 02656 } 02657 // Splat of <x, x, x, x>, return <x, x, x, x> 02658 if (AllSame) 02659 return N0; 02660 } 02661 } 02662 } 02663 02664 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 02665 // into an undef. 02666 if (isUnary || N0 == N1) { 02667 if (N0.getOpcode() == ISD::UNDEF) 02668 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 02669 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 02670 // first operand. 02671 std::vector<SDOperand> MappedOps; 02672 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 02673 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 02674 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 02675 MappedOps.push_back(ShufMask.getOperand(i)); 02676 } else { 02677 unsigned NewIdx = 02678 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 02679 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 02680 } 02681 } 02682 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 02683 MappedOps); 02684 AddToWorkList(ShufMask.Val); 02685 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 02686 N0, 02687 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 02688 ShufMask); 02689 } 02690 02691 return SDOperand(); 02692 } 02693 02694 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 02695 SDOperand ShufMask = N->getOperand(2); 02696 unsigned NumElts = ShufMask.getNumOperands()-2; 02697 02698 // If the shuffle mask is an identity operation on the LHS, return the LHS. 02699 bool isIdentity = true; 02700 for (unsigned i = 0; i != NumElts; ++i) { 02701 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 02702 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 02703 isIdentity = false; 02704 break; 02705 } 02706 } 02707 if (isIdentity) return N->getOperand(0); 02708 02709 // If the shuffle mask is an identity operation on the RHS, return the RHS. 02710 isIdentity = true; 02711 for (unsigned i = 0; i != NumElts; ++i) { 02712 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 02713 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 02714 isIdentity = false; 02715 break; 02716 } 02717 } 02718 if (isIdentity) return N->getOperand(1); 02719 02720 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 02721 // needed at all. 02722 bool isUnary = true; 02723 bool isSplat = true; 02724 int VecNum = -1; 02725 unsigned BaseIdx = 0; 02726 for (unsigned i = 0; i != NumElts; ++i) 02727 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 02728 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 02729 int V = (Idx < NumElts) ? 0 : 1; 02730 if (VecNum == -1) { 02731 VecNum = V; 02732 BaseIdx = Idx; 02733 } else { 02734 if (BaseIdx != Idx) 02735 isSplat = false; 02736 if (VecNum != V) { 02737 isUnary = false; 02738 break; 02739 } 02740 } 02741 } 02742 02743 SDOperand N0 = N->getOperand(0); 02744 SDOperand N1 = N->getOperand(1); 02745 // Normalize unary shuffle so the RHS is undef. 02746 if (isUnary && VecNum == 1) 02747 std::swap(N0, N1); 02748 02749 // If it is a splat, check if the argument vector is a build_vector with 02750 // all scalar elements the same. 02751 if (isSplat) { 02752 SDNode *V = N0.Val; 02753 if (V->getOpcode() == ISD::VBIT_CONVERT) 02754 V = V->getOperand(0).Val; 02755 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 02756 unsigned NumElems = V->getNumOperands()-2; 02757 if (NumElems > BaseIdx) { 02758 SDOperand Base; 02759 bool AllSame = true; 02760 for (unsigned i = 0; i != NumElems; ++i) { 02761 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 02762 Base = V->getOperand(i); 02763 break; 02764 } 02765 } 02766 // Splat of <u, u, u, u>, return <u, u, u, u> 02767 if (!Base.Val) 02768 return N0; 02769 for (unsigned i = 0; i != NumElems; ++i) { 02770 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 02771 V->getOperand(i) != Base) { 02772 AllSame = false; 02773 break; 02774 } 02775 } 02776 // Splat of <x, x, x, x>, return <x, x, x, x> 02777 if (AllSame) 02778 return N0; 02779 } 02780 } 02781 } 02782 02783 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 02784 // into an undef. 02785 if (isUnary || N0 == N1) { 02786 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 02787 // first operand. 02788 std::vector<SDOperand> MappedOps; 02789 for (unsigned i = 0; i != NumElts; ++i) { 02790 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 02791 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 02792 MappedOps.push_back(ShufMask.getOperand(i)); 02793 } else { 02794 unsigned NewIdx = 02795 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 02796 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 02797 } 02798 } 02799 // Add the type/#elts values. 02800 MappedOps.push_back(ShufMask.getOperand(NumElts)); 02801 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 02802 02803 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 02804 MappedOps); 02805 AddToWorkList(ShufMask.Val); 02806 02807 // Build the undef vector. 02808 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 02809 for (unsigned i = 0; i != NumElts; ++i) 02810 MappedOps[i] = UDVal; 02811 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 02812 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 02813 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps); 02814 02815 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 02816 N0, UDVal, ShufMask, 02817 MappedOps[NumElts], MappedOps[NumElts+1]); 02818 } 02819 02820 return SDOperand(); 02821 } 02822 02823 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 02824 /// a VAND to a vector_shuffle with the destination vector and a zero vector. 02825 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 02826 /// vector_shuffle V, Zero, <0, 4, 2, 4> 02827 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 02828 SDOperand LHS = N->getOperand(0); 02829 SDOperand RHS = N->getOperand(1); 02830 if (N->getOpcode() == ISD::VAND) { 02831 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 02832 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 02833 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 02834 RHS = RHS.getOperand(0); 02835 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 02836 std::vector<SDOperand> IdxOps; 02837 unsigned NumOps = RHS.getNumOperands(); 02838 unsigned NumElts = NumOps-2; 02839 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 02840 for (unsigned i = 0; i != NumElts; ++i) { 02841 SDOperand Elt = RHS.getOperand(i); 02842 if (!isa<ConstantSDNode>(Elt)) 02843 return SDOperand(); 02844 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 02845 IdxOps.push_back(DAG.getConstant(i, EVT)); 02846 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 02847 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 02848 else 02849 return SDOperand(); 02850 } 02851 02852 // Let's see if the target supports this vector_shuffle. 02853 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 02854 return SDOperand(); 02855 02856 // Return the new VVECTOR_SHUFFLE node. 02857 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 02858 SDOperand EVTNode = DAG.getValueType(EVT); 02859 std::vector<SDOperand> Ops; 02860 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode); 02861 Ops.push_back(LHS); 02862 AddToWorkList(LHS.Val); 02863 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 02864 ZeroOps.push_back(NumEltsNode); 02865 ZeroOps.push_back(EVTNode); 02866 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps)); 02867 IdxOps.push_back(NumEltsNode); 02868 IdxOps.push_back(EVTNode); 02869 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps)); 02870 Ops.push_back(NumEltsNode); 02871 Ops.push_back(EVTNode); 02872 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 02873 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 02874 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 02875 DstVecSize, DstVecEVT); 02876 } 02877 return Result; 02878 } 02879 } 02880 return SDOperand(); 02881 } 02882 02883 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 02884 /// the scalar operation of the vop if it is operating on an integer vector 02885 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 02886 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 02887 ISD::NodeType FPOp) { 02888 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 02889 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 02890 SDOperand LHS = N->getOperand(0); 02891 SDOperand RHS = N->getOperand(1); 02892 SDOperand Shuffle = XformToShuffleWithZero(N); 02893 if (Shuffle.Val) return Shuffle; 02894 02895 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 02896 // this operation. 02897 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 02898 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 02899 std::vector<SDOperand> Ops; 02900 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 02901 SDOperand LHSOp = LHS.getOperand(i); 02902 SDOperand RHSOp = RHS.getOperand(i); 02903 // If these two elements can't be folded, bail out. 02904 if ((LHSOp.getOpcode() != ISD::UNDEF && 02905 LHSOp.getOpcode() != ISD::Constant && 02906 LHSOp.getOpcode() != ISD::ConstantFP) || 02907 (RHSOp.getOpcode() != ISD::UNDEF && 02908 RHSOp.getOpcode() != ISD::Constant && 02909 RHSOp.getOpcode() != ISD::ConstantFP)) 02910 break; 02911 // Can't fold divide by zero. 02912 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 02913 if ((RHSOp.getOpcode() == ISD::Constant && 02914 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 02915 (RHSOp.getOpcode() == ISD::ConstantFP && 02916 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 02917 break; 02918 } 02919 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 02920 AddToWorkList(Ops.back().Val); 02921 assert((Ops.back().getOpcode() == ISD::UNDEF || 02922 Ops.back().getOpcode() == ISD::Constant || 02923 Ops.back().getOpcode() == ISD::ConstantFP) && 02924 "Scalar binop didn't fold!"); 02925 } 02926 02927 if (Ops.size() == LHS.getNumOperands()-2) { 02928 Ops.push_back(*(LHS.Val->op_end()-2)); 02929 Ops.push_back(*(LHS.Val->op_end()-1)); 02930 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 02931 } 02932 } 02933 02934 return SDOperand(); 02935 } 02936 02937 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 02938 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 02939 02940 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 02941 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 02942 // If we got a simplified select_cc node back from SimplifySelectCC, then 02943 // break it down into a new SETCC node, and a new SELECT node, and then return 02944 // the SELECT node, since we were called with a SELECT node. 02945 if (SCC.Val) { 02946 // Check to see if we got a select_cc back (to turn into setcc/select). 02947 // Otherwise, just return whatever node we got back, like fabs. 02948 if (SCC.getOpcode() == ISD::SELECT_CC) { 02949 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 02950 SCC.getOperand(0), SCC.getOperand(1), 02951 SCC.getOperand(4)); 02952 AddToWorkList(SETCC.Val); 02953 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 02954 SCC.getOperand(3), SETCC); 02955 } 02956 return SCC; 02957 } 02958 return SDOperand(); 02959 } 02960 02961 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 02962 /// are the two values being selected between, see if we can simplify the 02963 /// select. Callers of this should assume that TheSelect is deleted if this 02964 /// returns true. As such, they should return the appropriate thing (e.g. the 02965 /// node) back to the top-level of the DAG combiner loop to avoid it being 02966 /// looked at. 02967 /// 02968 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 02969 SDOperand RHS) { 02970 02971 // If this is a select from two identical things, try to pull the operation 02972 // through the select. 02973 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 02974 #if 0 02975 std::cerr << "SELECT: ["; LHS.Val->dump(); 02976 std::cerr << "] ["; RHS.Val->dump(); 02977 std::cerr << "]\n"; 02978 #endif 02979 02980 // If this is a load and the token chain is identical, replace the select 02981 // of two loads with a load through a select of the address to load from. 02982 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 02983 // constants have been dropped into the constant pool. 02984 if ((LHS.getOpcode() == ISD::LOAD || 02985 LHS.getOpcode() == ISD::EXTLOAD || 02986 LHS.getOpcode() == ISD::ZEXTLOAD || 02987 LHS.getOpcode() == ISD::SEXTLOAD) && 02988 // Token chains must be identical. 02989 LHS.getOperand(0) == RHS.getOperand(0) && 02990 // If this is an EXTLOAD, the VT's must match. 02991 (LHS.getOpcode() == ISD::LOAD || 02992 LHS.getOperand(3) == RHS.getOperand(3))) { 02993 // FIXME: this conflates two src values, discarding one. This is not 02994 // the right thing to do, but nothing uses srcvalues now. When they do, 02995 // turn SrcValue into a list of locations. 02996 SDOperand Addr; 02997 if (TheSelect->getOpcode() == ISD::SELECT) 02998 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 02999 TheSelect->getOperand(0), LHS.getOperand(1), 03000 RHS.getOperand(1)); 03001 else 03002 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 03003 TheSelect->getOperand(0), 03004 TheSelect->getOperand(1), 03005 LHS.getOperand(1), RHS.getOperand(1), 03006 TheSelect->getOperand(4)); 03007 03008 SDOperand Load; 03009 if (LHS.getOpcode() == ISD::LOAD) 03010 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 03011 Addr, LHS.getOperand(2)); 03012 else 03013 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 03014 LHS.getOperand(0), Addr, LHS.getOperand(2), 03015 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 03016 // Users of the select now use the result of the load. 03017 CombineTo(TheSelect, Load); 03018 03019 // Users of the old loads now use the new load's chain. We know the 03020 // old-load value is dead now. 03021 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 03022 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 03023 return true; 03024 } 03025 } 03026 03027 return false; 03028 } 03029 03030 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 03031 SDOperand N2, SDOperand N3, 03032 ISD::CondCode CC) { 03033 03034 MVT::ValueType VT = N2.getValueType(); 03035 //ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 03036 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 03037 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 03038 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 03039 03040 // Determine if the condition we're dealing with is constant 03041 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 03042 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 03043 03044 // fold select_cc true, x, y -> x 03045 if (SCCC && SCCC->getValue()) 03046 return N2; 03047 // fold select_cc false, x, y -> y 03048 if (SCCC && SCCC->getValue() == 0) 03049 return N3; 03050 03051 // Check to see if we can simplify the select into an fabs node 03052 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 03053 // Allow either -0.0 or 0.0 03054 if (CFP->getValue() == 0.0) { 03055 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 03056 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 03057 N0 == N2 && N3.getOpcode() == ISD::FNEG && 03058 N2 == N3.getOperand(0)) 03059 return DAG.getNode(ISD::FABS, VT, N0); 03060 03061 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 03062 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 03063 N0 == N3 && N2.getOpcode() == ISD::FNEG && 03064 N2.getOperand(0) == N3) 03065 return DAG.getNode(ISD::FABS, VT, N3); 03066 } 03067 } 03068 03069 // Check to see if we can perform the "gzip trick", transforming 03070 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 03071 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 03072 MVT::isInteger(N0.getValueType()) && 03073 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 03074 MVT::ValueType XType = N0.getValueType(); 03075 MVT::ValueType AType = N2.getValueType(); 03076 if (XType >= AType) { 03077 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 03078 // single-bit constant. 03079 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 03080 unsigned ShCtV = Log2_64(N2C->getValue()); 03081 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 03082 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 03083 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 03084 AddToWorkList(Shift.Val); 03085 if (XType > AType) { 03086 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 03087 AddToWorkList(Shift.Val); 03088 } 03089 return DAG.getNode(ISD::AND, AType, Shift, N2); 03090 } 03091 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 03092 DAG.getConstant(MVT::getSizeInBits(XType)-1, 03093 TLI.getShiftAmountTy())); 03094 AddToWorkList(Shift.Val); 03095 if (XType > AType) { 03096 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 03097 AddToWorkList(Shift.Val); 03098 } 03099 return DAG.getNode(ISD::AND, AType, Shift, N2); 03100 } 03101 } 03102 03103 // fold select C, 16, 0 -> shl C, 4 03104 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 03105 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 03106 // Get a SetCC of the condition 03107 // FIXME: Should probably make sure that setcc is legal if we ever have a 03108 // target where it isn't. 03109 SDOperand Temp, SCC; 03110 // cast from setcc result type to select result type 03111 if (AfterLegalize) { 03112 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 03113 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 03114 } else { 03115 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 03116 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 03117 } 03118 AddToWorkList(SCC.Val); 03119 AddToWorkList(Temp.Val); 03120 // shl setcc result by log2 n2c 03121 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 03122 DAG.getConstant(Log2_64(N2C->getValue()), 03123 TLI.getShiftAmountTy())); 03124 } 03125 03126 // Check to see if this is the equivalent of setcc 03127 // FIXME: Turn all of these into setcc if setcc if setcc is legal 03128 // otherwise, go ahead with the folds. 03129 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 03130 MVT::ValueType XType = N0.getValueType(); 03131 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 03132 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 03133 if (Res.getValueType() != VT) 03134 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 03135 return Res; 03136 } 03137 03138 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 03139 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 03140 TLI.isOperationLegal(ISD::CTLZ, XType)) { 03141 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 03142 return DAG.getNode(ISD::SRL, XType, Ctlz, 03143 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 03144 TLI.getShiftAmountTy())); 03145 } 03146 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 03147 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 03148 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 03149 N0); 03150 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 03151 DAG.getConstant(~0ULL, XType)); 03152 return DAG.getNode(ISD::SRL, XType, 03153 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 03154 DAG.getConstant(MVT::getSizeInBits(XType)-1, 03155 TLI.getShiftAmountTy())); 03156 } 03157 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 03158 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 03159 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 03160 DAG.getConstant(MVT::getSizeInBits(XType)-1, 03161 TLI.getShiftAmountTy())); 03162 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 03163 } 03164 } 03165 03166 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 03167 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 03168 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 03169 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 03170 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 03171 MVT::ValueType XType = N0.getValueType(); 03172 if (SubC->isNullValue() && MVT::isInteger(XType)) { 03173 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 03174 DAG.getConstant(MVT::getSizeInBits(XType)-1, 03175 TLI.getShiftAmountTy())); 03176 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 03177 AddToWorkList(Shift.Val); 03178 AddToWorkList(Add.Val); 03179 return DAG.getNode(ISD::XOR, XType, Add, Shift); 03180 } 03181 } 03182 } 03183 03184 return SDOperand(); 03185 } 03186 03187 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 03188 SDOperand N1, ISD::CondCode Cond, 03189 bool foldBooleans) { 03190 // These setcc operations always fold. 03191 switch (Cond) { 03192 default: break; 03193 case ISD::SETFALSE: 03194 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 03195 case ISD::SETTRUE: 03196 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 03197 } 03198 03199 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 03200 uint64_t C1 = N1C->getValue(); 03201 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 03202 uint64_t C0 = N0C->getValue(); 03203 03204 // Sign extend the operands if required 03205 if (ISD::isSignedIntSetCC(Cond)) { 03206 C0 = N0C->getSignExtended(); 03207 C1 = N1C->getSignExtended(); 03208 } 03209 03210 switch (Cond) { 03211 default: assert(0 && "Unknown integer setcc!"); 03212 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 03213 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 03214 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 03215 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 03216 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 03217 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 03218 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 03219 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 03220 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 03221 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 03222 } 03223 } else { 03224 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 03225 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 03226 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 03227 03228 // If the comparison constant has bits in the upper part, the 03229 // zero-extended value could never match. 03230 if (C1 & (~0ULL << InSize)) { 03231 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 03232 switch (Cond) { 03233 case ISD::SETUGT: 03234 case ISD::SETUGE: 03235 case ISD::SETEQ: return DAG.getConstant(0, VT); 03236 case ISD::SETULT: 03237 case ISD::SETULE: 03238 case ISD::SETNE: return DAG.getConstant(1, VT); 03239 case ISD::SETGT: 03240 case ISD::SETGE: 03241 // True if the sign bit of C1 is set. 03242 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 03243 case ISD::SETLT: 03244 case ISD::SETLE: 03245 // True if the sign bit of C1 isn't set. 03246 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 03247 default: 03248 break; 03249 } 03250 } 03251 03252 // Otherwise, we can perform the comparison with the low bits. 03253 switch (Cond) { 03254 case ISD::SETEQ: 03255 case ISD::SETNE: 03256 case ISD::SETUGT: 03257 case ISD::SETUGE: 03258 case ISD::SETULT: 03259 case ISD::SETULE: 03260 return DAG.getSetCC(VT, N0.getOperand(0), 03261 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 03262 Cond); 03263 default: 03264 break; // todo, be more careful with signed comparisons 03265 } 03266 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 03267 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 03268 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 03269 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 03270 MVT::ValueType ExtDstTy = N0.getValueType(); 03271 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 03272 03273 // If the extended part has any inconsistent bits, it cannot ever 03274 // compare equal. In other words, they have to be all ones or all 03275 // zeros. 03276 uint64_t ExtBits = 03277 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 03278 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 03279 return DAG.getConstant(Cond == ISD::SETNE, VT); 03280 03281 SDOperand ZextOp; 03282 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 03283 if (Op0Ty == ExtSrcTy) { 03284 ZextOp = N0.getOperand(0); 03285 } else { 03286 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 03287 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 03288 DAG.getConstant(Imm, Op0Ty)); 03289 } 03290 AddToWorkList(ZextOp.Val); 03291 // Otherwise, make this a use of a zext. 03292 return DAG.getSetCC(VT, ZextOp, 03293 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 03294 ExtDstTy), 03295 Cond); 03296 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 03297 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 03298 (N0.getOpcode() == ISD::XOR || 03299 (N0.getOpcode() == ISD::AND && 03300 N0.getOperand(0).getOpcode() == ISD::XOR && 03301 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 03302 isa<ConstantSDNode>(N0.getOperand(1)) && 03303 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 03304 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 03305 // only do this if the top bits are known zero. 03306 if (TLI.MaskedValueIsZero(N1, 03307 MVT::getIntVTBitMask(N0.getValueType())-1)) { 03308 // Okay, get the un-inverted input value. 03309 SDOperand Val; 03310 if (N0.getOpcode() == ISD::XOR) 03311 Val = N0.getOperand(0); 03312 else { 03313 assert(N0.getOpcode() == ISD::AND && 03314 N0.getOperand(0).getOpcode() == ISD::XOR); 03315 // ((X^1)&1)^1 -> X & 1 03316 Val = DAG.getNode(ISD::AND, N0.getValueType(), 03317 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 03318 } 03319 return DAG.getSetCC(VT, Val, N1, 03320 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 03321 } 03322 } 03323 03324 uint64_t MinVal, MaxVal; 03325 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 03326 if (ISD::isSignedIntSetCC(Cond)) { 03327 MinVal = 1ULL << (OperandBitSize-1); 03328 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 03329 MaxVal = ~0ULL >> (65-OperandBitSize); 03330 else 03331 MaxVal = 0; 03332 } else { 03333 MinVal = 0; 03334 MaxVal = ~0ULL >> (64-OperandBitSize); 03335 } 03336 03337 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 03338 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 03339 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 03340 --C1; // X >= C0 --> X > (C0-1) 03341 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 03342 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 03343 } 03344 03345 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 03346 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 03347 ++C1; // X <= C0 --> X < (C0+1) 03348 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 03349 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 03350 } 03351 03352 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 03353 return DAG.getConstant(0, VT); // X < MIN --> false 03354 03355 // Canonicalize setgt X, Min --> setne X, Min 03356 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 03357 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 03358 // Canonicalize setlt X, Max --> setne X, Max 03359 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 03360 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 03361 03362 // If we have setult X, 1, turn it into seteq X, 0 03363 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 03364 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 03365 ISD::SETEQ); 03366 // If we have setugt X, Max-1, turn it into seteq X, Max 03367 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 03368 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 03369 ISD::SETEQ); 03370 03371 // If we have "setcc X, C0", check to see if we can shrink the immediate 03372 // by changing cc. 03373 03374 // SETUGT X, SINTMAX -> SETLT X, 0 03375 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 03376 C1 == (~0ULL >> (65-OperandBitSize))) 03377 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 03378 ISD::SETLT); 03379 03380 // FIXME: Implement the rest of these. 03381 03382 // Fold bit comparisons when we can. 03383 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 03384 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 03385 if (ConstantSDNode *AndRHS = 03386 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 03387 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 03388 // Perform the xform if the AND RHS is a single bit. 03389 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 03390 return DAG.getNode(ISD::SRL, VT, N0, 03391 DAG.getConstant(Log2_64(AndRHS->getValue()), 03392 TLI.getShiftAmountTy())); 03393 } 03394 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 03395 // (X & 8) == 8 --> (X & 8) >> 3 03396 // Perform the xform if C1 is a single bit. 03397 if ((C1 & (C1-1)) == 0) { 03398 return DAG.getNode(ISD::SRL, VT, N0, 03399 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 03400 } 03401 } 03402 } 03403 } 03404 } else if (isa<ConstantSDNode>(N0.Val)) { 03405 // Ensure that the constant occurs on the RHS. 03406 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 03407 } 03408 03409 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 03410 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 03411 double C0 = N0C->getValue(), C1 = N1C->getValue(); 03412 03413 switch (Cond) { 03414 default: break; // FIXME: Implement the rest of these! 03415 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 03416 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 03417 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 03418 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 03419 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 03420 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 03421 } 03422 } else { 03423 // Ensure that the constant occurs on the RHS. 03424 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 03425 } 03426 03427 if (N0 == N1) { 03428 // We can always fold X == Y for integer setcc's. 03429 if (MVT::isInteger(N0.getValueType())) 03430 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 03431 unsigned UOF = ISD::getUnorderedFlavor(Cond); 03432 if (UOF == 2) // FP operators that are undefined on NaNs. 03433 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 03434 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 03435 return DAG.getConstant(UOF, VT); 03436 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 03437 // if it is not already. 03438 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 03439 if (NewCond != Cond) 03440 return DAG.getSetCC(VT, N0, N1, NewCond); 03441 } 03442 03443 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 03444 MVT::isInteger(N0.getValueType())) { 03445 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 03446 N0.getOpcode() == ISD::XOR) { 03447 // Simplify (X+Y) == (X+Z) --> Y == Z 03448 if (N0.getOpcode() == N1.getOpcode()) { 03449 if (N0.getOperand(0) == N1.getOperand(0)) 03450 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 03451 if (N0.getOperand(1) == N1.getOperand(1)) 03452 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 03453 if (isCommutativeBinOp(N0.getOpcode())) { 03454 // If X op Y == Y op X, try other combinations. 03455 if (N0.getOperand(0) == N1.getOperand(1)) 03456 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 03457 if (N0.getOperand(1) == N1.getOperand(0)) 03458 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 03459 } 03460 } 03461 03462 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 03463 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 03464 // Turn (X+C1) == C2 --> X == C2-C1 03465 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 03466 return DAG.getSetCC(VT, N0.getOperand(0), 03467 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 03468 N0.getValueType()), Cond); 03469 } 03470 03471 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 03472 if (N0.getOpcode() == ISD::XOR) 03473 // If we know that all of the inverted bits are zero, don't bother 03474 // performing the inversion. 03475 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 03476 return DAG.getSetCC(VT, N0.getOperand(0), 03477 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 03478 N0.getValueType()), Cond); 03479 } 03480 03481 // Turn (C1-X) == C2 --> X == C1-C2 03482 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 03483 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 03484 return DAG.getSetCC(VT, N0.getOperand(1), 03485 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 03486 N0.getValueType()), Cond); 03487 } 03488 } 03489 } 03490 03491 // Simplify (X+Z) == X --> Z == 0 03492 if (N0.getOperand(0) == N1) 03493 return DAG.getSetCC(VT, N0.getOperand(1), 03494 DAG.getConstant(0, N0.getValueType()), Cond); 03495 if (N0.getOperand(1) == N1) { 03496 if (isCommutativeBinOp(N0.getOpcode())) 03497 return DAG.getSetCC(VT, N0.getOperand(0), 03498 DAG.getConstant(0, N0.getValueType()), Cond); 03499 else { 03500 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 03501 // (Z-X) == X --> Z == X<<1 03502 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 03503 N1, 03504 DAG.getConstant(1,TLI.getShiftAmountTy())); 03505 AddToWorkList(SH.Val); 03506 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 03507 } 03508 } 03509 } 03510 03511 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 03512 N1.getOpcode() == ISD::XOR) { 03513 // Simplify X == (X+Z) --> Z == 0 03514 if (N1.getOperand(0) == N0) { 03515 return DAG.getSetCC(VT, N1.getOperand(1), 03516 DAG.getConstant(0, N1.getValueType()), Cond); 03517 } else if (N1.getOperand(1) == N0) { 03518 if (isCommutativeBinOp(N1.getOpcode())) { 03519 return DAG.getSetCC(VT, N1.getOperand(0), 03520 DAG.getConstant(0, N1.getValueType()), Cond); 03521 } else { 03522 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 03523 // X == (Z-X) --> X<<1 == Z 03524 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 03525 DAG.getConstant(1,TLI.getShiftAmountTy())); 03526 AddToWorkList(SH.Val); 03527 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 03528 } 03529 } 03530 } 03531 } 03532 03533 // Fold away ALL boolean setcc's. 03534 SDOperand Temp; 03535 if (N0.getValueType() == MVT::i1 && foldBooleans) { 03536 switch (Cond) { 03537 default: assert(0 && "Unknown integer setcc!"); 03538 case ISD::SETEQ: // X == Y -> (X^Y)^1 03539 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 03540 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 03541 AddToWorkList(Temp.Val); 03542 break; 03543 case ISD::SETNE: // X != Y --> (X^Y) 03544 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 03545 break; 03546 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 03547 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 03548 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 03549 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 03550 AddToWorkList(Temp.Val); 03551 break; 03552 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 03553 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 03554 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 03555 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 03556 AddToWorkList(Temp.Val); 03557 break; 03558 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 03559 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 03560 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 03561 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 03562 AddToWorkList(Temp.Val); 03563 break; 03564 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 03565 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 03566 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 03567 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 03568 break; 03569 } 03570 if (VT != MVT::i1) { 03571 AddToWorkList(N0.Val); 03572 // FIXME: If running after legalize, we probably can't do this. 03573 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 03574 } 03575 return N0; 03576 } 03577 03578 // Could not fold it. 03579 return SDOperand(); 03580 } 03581 03582 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 03583 /// return a DAG expression to select that will generate the same value by 03584 /// multiplying by a magic number. See: 03585 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 03586 SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 03587 std::vector<SDNode*> Built; 03588 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 03589 03590 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 03591 ii != ee; ++ii) 03592 AddToWorkList(*ii); 03593 return S; 03594 } 03595 03596 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 03597 /// return a DAG expression to select that will generate the same value by 03598 /// multiplying by a magic number. See: 03599 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 03600 SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 03601 std::vector<SDNode*> Built; 03602 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 03603 03604 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 03605 ii != ee; ++ii) 03606 AddToWorkList(*ii); 03607 return S; 03608 } 03609 03610 // SelectionDAG::Combine - This is the entry point for the file. 03611 // 03612 void SelectionDAG::Combine(bool RunningAfterLegalize) { 03613 /// run - This is the main entry point to this class. 03614 /// 03615 DAGCombiner(*this).Run(RunningAfterLegalize); 03616 }