LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // F4RC Register Class... 00013 static const unsigned F4RC[] = { 00014 Alpha::F0, Alpha::F1, Alpha::F10, Alpha::F11, Alpha::F12, Alpha::F13, Alpha::F14, Alpha::F15, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21, Alpha::F22, Alpha::F23, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, Alpha::F2, Alpha::F3, Alpha::F4, Alpha::F5, Alpha::F6, Alpha::F7, Alpha::F8, Alpha::F9, Alpha::F31, 00015 }; 00016 00017 // F8RC Register Class... 00018 static const unsigned F8RC[] = { 00019 Alpha::F0, Alpha::F1, Alpha::F10, Alpha::F11, Alpha::F12, Alpha::F13, Alpha::F14, Alpha::F15, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21, Alpha::F22, Alpha::F23, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, Alpha::F2, Alpha::F3, Alpha::F4, Alpha::F5, Alpha::F6, Alpha::F7, Alpha::F8, Alpha::F9, Alpha::F31, 00020 }; 00021 00022 // GPRC Register Class... 00023 static const unsigned GPRC[] = { 00024 Alpha::R0, Alpha::R1, Alpha::R2, Alpha::R3, Alpha::R4, Alpha::R5, Alpha::R6, Alpha::R7, Alpha::R8, Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21, Alpha::R22, Alpha::R23, Alpha::R24, Alpha::R25, Alpha::R28, Alpha::R27, Alpha::R26, Alpha::R29, Alpha::R9, Alpha::R10, Alpha::R11, Alpha::R12, Alpha::R13, Alpha::R14, Alpha::R15, Alpha::R30, Alpha::R31, 00025 }; 00026 00027 // F4RCVTs Register Class Value Types... 00028 static const MVT::ValueType F4RCVTs[] = { 00029 MVT::f32, MVT::Other 00030 }; 00031 00032 // F8RCVTs Register Class Value Types... 00033 static const MVT::ValueType F8RCVTs[] = { 00034 MVT::f64, MVT::Other 00035 }; 00036 00037 // GPRCVTs Register Class Value Types... 00038 static const MVT::ValueType GPRCVTs[] = { 00039 MVT::i64, MVT::Other 00040 }; 00041 00042 } // end anonymous namespace 00043 00044 namespace Alpha { // Register class instances 00045 F4RCClass F4RCRegClass; 00046 F8RCClass F8RCRegClass; 00047 GPRCClass GPRCRegClass; 00048 00049 // F4RC Register Class sub-classes... 00050 static const TargetRegisterClass* const F4RCSubclasses [] = { 00051 NULL 00052 }; 00053 00054 // F8RC Register Class sub-classes... 00055 static const TargetRegisterClass* const F8RCSubclasses [] = { 00056 NULL 00057 }; 00058 00059 // GPRC Register Class sub-classes... 00060 static const TargetRegisterClass* const GPRCSubclasses [] = { 00061 NULL 00062 }; 00063 00064 // F4RC Register Class super-classes... 00065 static const TargetRegisterClass* const F4RCSuperclasses [] = { 00066 NULL 00067 }; 00068 00069 // F8RC Register Class super-classes... 00070 static const TargetRegisterClass* const F8RCSuperclasses [] = { 00071 NULL 00072 }; 00073 00074 // GPRC Register Class super-classes... 00075 static const TargetRegisterClass* const GPRCSuperclasses [] = { 00076 NULL 00077 }; 00078 00079 00080 F4RCClass::iterator 00081 F4RCClass::allocation_order_end(MachineFunction &MF) const { 00082 return end()-1; 00083 } 00084 00085 F4RCClass::F4RCClass() : TargetRegisterClass(F4RCRegClassID, F4RCVTs, F4RCSubclasses, F4RCSuperclasses, 4, 8, F4RC, F4RC + 32) {} 00086 00087 F8RCClass::iterator 00088 F8RCClass::allocation_order_end(MachineFunction &MF) const { 00089 return end()-1; 00090 } 00091 00092 F8RCClass::F8RCClass() : TargetRegisterClass(F8RCRegClassID, F8RCVTs, F8RCSubclasses, F8RCSuperclasses, 8, 8, F8RC, F8RC + 32) {} 00093 00094 GPRCClass::iterator 00095 GPRCClass::allocation_order_end(MachineFunction &MF) const { 00096 return end()-3; 00097 } 00098 00099 GPRCClass::GPRCClass() : TargetRegisterClass(GPRCRegClassID, GPRCVTs, GPRCSubclasses, GPRCSuperclasses, 8, 8, GPRC, GPRC + 32) {} 00100 } 00101 00102 namespace { 00103 const TargetRegisterClass* const RegisterClasses[] = { 00104 &Alpha::F4RCRegClass, 00105 &Alpha::F8RCRegClass, 00106 &Alpha::GPRCRegClass, 00107 }; 00108 const unsigned Empty_AliasSet[] = { 0 }; 00109 00110 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00111 { "NOREG", 0 }, 00112 { "$f0", Empty_AliasSet }, 00113 { "$f1", Empty_AliasSet }, 00114 { "$f10", Empty_AliasSet }, 00115 { "$f11", Empty_AliasSet }, 00116 { "$f12", Empty_AliasSet }, 00117 { "$f13", Empty_AliasSet }, 00118 { "$f14", Empty_AliasSet }, 00119 { "$f15", Empty_AliasSet }, 00120 { "$f16", Empty_AliasSet }, 00121 { "$f17", Empty_AliasSet }, 00122 { "$f18", Empty_AliasSet }, 00123 { "$f19", Empty_AliasSet }, 00124 { "$f2", Empty_AliasSet }, 00125 { "$f20", Empty_AliasSet }, 00126 { "$f21", Empty_AliasSet }, 00127 { "$f22", Empty_AliasSet }, 00128 { "$f23", Empty_AliasSet }, 00129 { "$f24", Empty_AliasSet }, 00130 { "$f25", Empty_AliasSet }, 00131 { "$f26", Empty_AliasSet }, 00132 { "$f27", Empty_AliasSet }, 00133 { "$f28", Empty_AliasSet }, 00134 { "$f29", Empty_AliasSet }, 00135 { "$f3", Empty_AliasSet }, 00136 { "$f30", Empty_AliasSet }, 00137 { "$f31", Empty_AliasSet }, 00138 { "$f4", Empty_AliasSet }, 00139 { "$f5", Empty_AliasSet }, 00140 { "$f6", Empty_AliasSet }, 00141 { "$f7", Empty_AliasSet }, 00142 { "$f8", Empty_AliasSet }, 00143 { "$f9", Empty_AliasSet }, 00144 { "$0", Empty_AliasSet }, 00145 { "$1", Empty_AliasSet }, 00146 { "$10", Empty_AliasSet }, 00147 { "$11", Empty_AliasSet }, 00148 { "$12", Empty_AliasSet }, 00149 { "$13", Empty_AliasSet }, 00150 { "$14", Empty_AliasSet }, 00151 { "$15", Empty_AliasSet }, 00152 { "$16", Empty_AliasSet }, 00153 { "$17", Empty_AliasSet }, 00154 { "$18", Empty_AliasSet }, 00155 { "$19", Empty_AliasSet }, 00156 { "$2", Empty_AliasSet }, 00157 { "$20", Empty_AliasSet }, 00158 { "$21", Empty_AliasSet }, 00159 { "$22", Empty_AliasSet }, 00160 { "$23", Empty_AliasSet }, 00161 { "$24", Empty_AliasSet }, 00162 { "$25", Empty_AliasSet }, 00163 { "$26", Empty_AliasSet }, 00164 { "$27", Empty_AliasSet }, 00165 { "$28", Empty_AliasSet }, 00166 { "$29", Empty_AliasSet }, 00167 { "$3", Empty_AliasSet }, 00168 { "$30", Empty_AliasSet }, 00169 { "$31", Empty_AliasSet }, 00170 { "$4", Empty_AliasSet }, 00171 { "$5", Empty_AliasSet }, 00172 { "$6", Empty_AliasSet }, 00173 { "$7", Empty_AliasSet }, 00174 { "$8", Empty_AliasSet }, 00175 { "$9", Empty_AliasSet }, 00176 }; 00177 } 00178 00179 AlphaGenRegisterInfo::AlphaGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00180 : MRegisterInfo(RegisterDescriptors, 65, RegisterClasses, RegisterClasses+3, 00181 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00182 00183 int AlphaGenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00184 static const int DwarfRegNums[] = { -1, // NoRegister 00185 33, 34, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 35, 53, 54, 55, 00186 56, 57, 58, 59, 60, 61, 62, 36, 63, 64, 37, 38, 39, 40, 41, 42, 00187 0, 1, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 2, 20, 21, 22, 00188 23, 24, 25, 26, 27, 28, 29, 3, 30, 31, 4, 5, 6, 7, 8, 9 00189 }; 00190 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00191 "RegNum exceeds number of registers"); 00192 return DwarfRegNums[RegNum]; 00193 } 00194 00195 } // End llvm namespace