LLVM API Documentation

X86InstrInfo.h

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00001 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef X86INSTRUCTIONINFO_H
00015 #define X86INSTRUCTIONINFO_H
00016 
00017 #include "llvm/Target/TargetInstrInfo.h"
00018 #include "X86RegisterInfo.h"
00019 
00020 namespace llvm {
00021   class X86TargetMachine;
00022 
00023 /// X86II - This namespace holds all of the target specific flags that
00024 /// instruction info tracks.
00025 ///
00026 namespace X86II {
00027   enum {
00028     //===------------------------------------------------------------------===//
00029     // Instruction types.  These are the standard/most common forms for X86
00030     // instructions.
00031     //
00032 
00033     // PseudoFrm - This represents an instruction that is a pseudo instruction
00034     // or one that has not been implemented yet.  It is illegal to code generate
00035     // it, but tolerated for intermediate implementation stages.
00036     Pseudo         = 0,
00037 
00038     /// Raw - This form is for instructions that don't have any operands, so
00039     /// they are just a fixed opcode value, like 'leave'.
00040     RawFrm         = 1,
00041 
00042     /// AddRegFrm - This form is used for instructions like 'push r32' that have
00043     /// their one register operand added to their opcode.
00044     AddRegFrm      = 2,
00045 
00046     /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
00047     /// to specify a destination, which in this case is a register.
00048     ///
00049     MRMDestReg     = 3,
00050 
00051     /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
00052     /// to specify a destination, which in this case is memory.
00053     ///
00054     MRMDestMem     = 4,
00055 
00056     /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
00057     /// to specify a source, which in this case is a register.
00058     ///
00059     MRMSrcReg      = 5,
00060 
00061     /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
00062     /// to specify a source, which in this case is memory.
00063     ///
00064     MRMSrcMem      = 6,
00065 
00066     /// MRM[0-7][rm] - These forms are used to represent instructions that use
00067     /// a Mod/RM byte, and use the middle field to hold extended opcode
00068     /// information.  In the intel manual these are represented as /0, /1, ...
00069     ///
00070 
00071     // First, instructions that operate on a register r/m operand...
00072     MRM0r = 16,  MRM1r = 17,  MRM2r = 18,  MRM3r = 19, // Format /0 /1 /2 /3
00073     MRM4r = 20,  MRM5r = 21,  MRM6r = 22,  MRM7r = 23, // Format /4 /5 /6 /7
00074 
00075     // Next, instructions that operate on a memory r/m operand...
00076     MRM0m = 24,  MRM1m = 25,  MRM2m = 26,  MRM3m = 27, // Format /0 /1 /2 /3
00077     MRM4m = 28,  MRM5m = 29,  MRM6m = 30,  MRM7m = 31, // Format /4 /5 /6 /7
00078 
00079     // MRMInitReg - This form is used for instructions whose source and
00080     // destinations are the same register.
00081     MRMInitReg = 32,
00082 
00083     FormMask       = 63,
00084 
00085     //===------------------------------------------------------------------===//
00086     // Actual flags...
00087 
00088     // OpSize - Set if this instruction requires an operand size prefix (0x66),
00089     // which most often indicates that the instruction operates on 16 bit data
00090     // instead of 32 bit data.
00091     OpSize      = 1 << 6,
00092 
00093     // Op0Mask - There are several prefix bytes that are used to form two byte
00094     // opcodes.  These are currently 0x0F, 0xF3, and 0xD8-0xDF.  This mask is
00095     // used to obtain the setting of this field.  If no bits in this field is
00096     // set, there is no prefix byte for obtaining a multibyte opcode.
00097     //
00098     Op0Shift    = 7,
00099     Op0Mask     = 0xF << Op0Shift,
00100 
00101     // TB - TwoByte - Set if this instruction has a two byte opcode, which
00102     // starts with a 0x0F byte before the real opcode.
00103     TB          = 1 << Op0Shift,
00104 
00105     // REP - The 0xF3 prefix byte indicating repetition of the following
00106     // instruction.
00107     REP         = 2 << Op0Shift,
00108 
00109     // D8-DF - These escape opcodes are used by the floating point unit.  These
00110     // values must remain sequential.
00111     D8 = 3 << Op0Shift,   D9 = 4 << Op0Shift,
00112     DA = 5 << Op0Shift,   DB = 6 << Op0Shift,
00113     DC = 7 << Op0Shift,   DD = 8 << Op0Shift,
00114     DE = 9 << Op0Shift,   DF = 10 << Op0Shift,
00115 
00116     // XS, XD - These prefix codes are for single and double precision scalar
00117     // floating point operations performed in the SSE registers.
00118     XD = 11 << Op0Shift,   XS = 12 << Op0Shift,
00119 
00120     //===------------------------------------------------------------------===//
00121     // This two-bit field describes the size of an immediate operand.  Zero is
00122     // unused so that we can tell if we forgot to set a value.
00123     ImmShift = 11,
00124     ImmMask  = 3 << ImmShift,
00125     Imm8     = 1 << ImmShift,
00126     Imm16    = 2 << ImmShift,
00127     Imm32    = 3 << ImmShift,
00128 
00129     //===------------------------------------------------------------------===//
00130     // FP Instruction Classification...  Zero is non-fp instruction.
00131 
00132     // FPTypeMask - Mask for all of the FP types...
00133     FPTypeShift = 13,
00134     FPTypeMask  = 7 << FPTypeShift,
00135 
00136     // NotFP - The default, set for instructions that do not use FP registers.
00137     NotFP      = 0 << FPTypeShift,
00138 
00139     // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
00140     ZeroArgFP  = 1 << FPTypeShift,
00141 
00142     // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
00143     OneArgFP   = 2 << FPTypeShift,
00144 
00145     // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
00146     // result back to ST(0).  For example, fcos, fsqrt, etc.
00147     //
00148     OneArgFPRW = 3 << FPTypeShift,
00149 
00150     // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
00151     // explicit argument, storing the result to either ST(0) or the implicit
00152     // argument.  For example: fadd, fsub, fmul, etc...
00153     TwoArgFP   = 4 << FPTypeShift,
00154 
00155     // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
00156     // explicit argument, but have no destination.  Example: fucom, fucomi, ...
00157     CompareFP  = 5 << FPTypeShift,
00158 
00159     // CondMovFP - "2 operand" floating point conditional move instructions.
00160     CondMovFP  = 6 << FPTypeShift,
00161 
00162     // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
00163     SpecialFP  = 7 << FPTypeShift,
00164 
00165     OpcodeShift   = 16,
00166     OpcodeMask    = 0xFF << OpcodeShift
00167     // Bits 25 -> 31 are unused
00168   };
00169 }
00170 
00171 class X86InstrInfo : public TargetInstrInfo {
00172   X86TargetMachine &TM;
00173   const X86RegisterInfo RI;
00174 public:
00175   X86InstrInfo(X86TargetMachine &tm);
00176 
00177   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
00178   /// such, whenever a client has an instance of instruction info, it should
00179   /// always be able to get register info as well (through this method).
00180   ///
00181   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
00182 
00183   // Return true if the instruction is a register to register move and
00184   // leave the source and dest operands in the passed parameters.
00185   //
00186   bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
00187                    unsigned& destReg) const;
00188   unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
00189   unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
00190   
00191   /// convertToThreeAddress - This method must be implemented by targets that
00192   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
00193   /// may be able to convert a two-address instruction into a true
00194   /// three-address instruction on demand.  This allows the X86 target (for
00195   /// example) to convert ADD and SHL instructions into LEA instructions if they
00196   /// would require register copies due to two-addressness.
00197   ///
00198   /// This method returns a null pointer if the transformation cannot be
00199   /// performed, otherwise it returns the new instruction.
00200   ///
00201   virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const;
00202 
00203   /// commuteInstruction - We have a few instructions that must be hacked on to
00204   /// commute them.
00205   ///
00206   virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
00207 
00208 
00209   /// Insert a goto (unconditional branch) sequence to TMBB, at the
00210   /// end of MBB
00211   virtual void insertGoto(MachineBasicBlock& MBB,
00212                           MachineBasicBlock& TMBB) const;
00213 
00214   /// Reverses the branch condition of the MachineInstr pointed by
00215   /// MI. The instruction is replaced and the new MI is returned.
00216   virtual MachineBasicBlock::iterator
00217   reverseBranchCondition(MachineBasicBlock::iterator MI) const;
00218 
00219   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
00220   // specified opcode number.
00221   //
00222   unsigned char getBaseOpcodeFor(unsigned Opcode) const {
00223     return get(Opcode).TSFlags >> X86II::OpcodeShift;
00224   }
00225 };
00226 
00227 } // End llvm namespace
00228 
00229 #endif