LLVM API Documentation
00001 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file describes an abstract interface used to get information about a 00011 // target machines register file. This information is used for a variety of 00012 // purposed, especially register allocation. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #ifndef LLVM_TARGET_MREGISTERINFO_H 00017 #define LLVM_TARGET_MREGISTERINFO_H 00018 00019 #include "llvm/CodeGen/MachineBasicBlock.h" 00020 #include "llvm/CodeGen/ValueTypes.h" 00021 #include <cassert> 00022 #include <functional> 00023 00024 namespace llvm { 00025 00026 class Type; 00027 class MachineFunction; 00028 class MachineInstr; 00029 class MachineLocation; 00030 class MachineMove; 00031 class TargetRegisterClass; 00032 00033 /// TargetRegisterDesc - This record contains all of the information known about 00034 /// a particular register. The AliasSet field (if not null) contains a pointer 00035 /// to a Zero terminated array of registers that this register aliases. This is 00036 /// needed for architectures like X86 which have AL alias AX alias EAX. 00037 /// Registers that this does not apply to simply should set this to null. 00038 /// 00039 struct TargetRegisterDesc { 00040 const char *Name; // Assembly language name for the register 00041 const unsigned *AliasSet; // Register Alias Set, described above 00042 }; 00043 00044 class TargetRegisterClass { 00045 public: 00046 typedef const unsigned* iterator; 00047 typedef const unsigned* const_iterator; 00048 00049 typedef const MVT::ValueType* vt_iterator; 00050 typedef const TargetRegisterClass* const * sc_iterator; 00051 private: 00052 unsigned ID; 00053 bool isSubClass; 00054 const vt_iterator VTs; 00055 const sc_iterator SubClasses; 00056 const sc_iterator SuperClasses; 00057 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 00058 const iterator RegsBegin, RegsEnd; 00059 public: 00060 TargetRegisterClass(unsigned id, 00061 const MVT::ValueType *vts, 00062 const TargetRegisterClass * const *subcs, 00063 const TargetRegisterClass * const *supcs, 00064 unsigned RS, unsigned Al, iterator RB, iterator RE) 00065 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 00066 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {} 00067 virtual ~TargetRegisterClass() {} // Allow subclasses 00068 00069 // getID() - Return the register class ID number. 00070 unsigned getID() const { return ID; } 00071 00072 // begin/end - Return all of the registers in this class. 00073 iterator begin() const { return RegsBegin; } 00074 iterator end() const { return RegsEnd; } 00075 00076 // getNumRegs - Return the number of registers in this class 00077 unsigned getNumRegs() const { return RegsEnd-RegsBegin; } 00078 00079 // getRegister - Return the specified register in the class 00080 unsigned getRegister(unsigned i) const { 00081 assert(i < getNumRegs() && "Register number out of range!"); 00082 return RegsBegin[i]; 00083 } 00084 00085 /// contains - Return true if the specified register is included in this 00086 /// register class. 00087 bool contains(unsigned Reg) const { 00088 for (iterator I = begin(), E = end(); I != E; ++I) 00089 if (*I == Reg) return true; 00090 return false; 00091 } 00092 00093 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 00094 /// 00095 bool hasType(MVT::ValueType vt) const { 00096 for(int i = 0; VTs[i] != MVT::Other; ++i) 00097 if (VTs[i] == vt) 00098 return true; 00099 return false; 00100 } 00101 00102 /// vt_begin / vt_end - Loop over all of the value types that can be 00103 /// represented by values in this register class. 00104 vt_iterator vt_begin() const { 00105 return VTs; 00106 } 00107 00108 vt_iterator vt_end() const { 00109 vt_iterator I = VTs; 00110 while (*I != MVT::Other) ++I; 00111 return I; 00112 } 00113 00114 /// hasSubRegClass - return true if the specified TargetRegisterClass is a 00115 /// sub-register class of this TargetRegisterClass. 00116 bool hasSubRegClass(const TargetRegisterClass *cs) const { 00117 for (int i = 0; SubClasses[i] != NULL; ++i) 00118 if (SubClasses[i] == cs) 00119 return true; 00120 return false; 00121 } 00122 00123 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of 00124 /// this register class. 00125 sc_iterator subclasses_begin() const { 00126 return SubClasses; 00127 } 00128 00129 sc_iterator subclasses_end() const { 00130 sc_iterator I = SubClasses; 00131 while (*I != NULL) ++I; 00132 return I; 00133 } 00134 00135 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a 00136 /// super-register class of this TargetRegisterClass. 00137 bool hasSuperRegClass(const TargetRegisterClass *cs) const { 00138 for (int i = 0; SuperClasses[i] != NULL; ++i) 00139 if (SuperClasses[i] == cs) 00140 return true; 00141 return false; 00142 } 00143 00144 /// superclasses_begin / superclasses_end - Loop over all of the super-classes 00145 /// of this register class. 00146 sc_iterator superclasses_begin() const { 00147 return SuperClasses; 00148 } 00149 00150 sc_iterator superclasses_end() const { 00151 sc_iterator I = SuperClasses; 00152 while (*I != NULL) ++I; 00153 return I; 00154 } 00155 00156 /// allocation_order_begin/end - These methods define a range of registers 00157 /// which specify the registers in this class that are valid to register 00158 /// allocate, and the preferred order to allocate them in. For example, 00159 /// callee saved registers should be at the end of the list, because it is 00160 /// cheaper to allocate caller saved registers. 00161 /// 00162 /// These methods take a MachineFunction argument, which can be used to tune 00163 /// the allocatable registers based on the characteristics of the function. 00164 /// One simple example is that the frame pointer register can be used if 00165 /// frame-pointer-elimination is performed. 00166 /// 00167 /// By default, these methods return all registers in the class. 00168 /// 00169 virtual iterator allocation_order_begin(MachineFunction &MF) const { 00170 return begin(); 00171 } 00172 virtual iterator allocation_order_end(MachineFunction &MF) const { 00173 return end(); 00174 } 00175 00176 00177 00178 /// getSize - Return the size of the register in bytes, which is also the size 00179 /// of a stack slot allocated to hold a spilled copy of this register. 00180 unsigned getSize() const { return RegSize; } 00181 00182 /// getAlignment - Return the minimum required alignment for a register of 00183 /// this class. 00184 unsigned getAlignment() const { return Alignment; } 00185 }; 00186 00187 00188 /// MRegisterInfo base class - We assume that the target defines a static array 00189 /// of TargetRegisterDesc objects that represent all of the machine registers 00190 /// that the target has. As such, we simply have to track a pointer to this 00191 /// array so that we can turn register number into a register descriptor. 00192 /// 00193 class MRegisterInfo { 00194 public: 00195 typedef const TargetRegisterClass * const * regclass_iterator; 00196 private: 00197 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 00198 unsigned NumRegs; // Number of entries in the array 00199 00200 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 00201 00202 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 00203 protected: 00204 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 00205 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, 00206 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1); 00207 virtual ~MRegisterInfo(); 00208 public: 00209 00210 enum { // Define some target independent constants 00211 /// NoRegister - This 'hard' register is a 'noop' register for all backends. 00212 /// This is used as the destination register for instructions that do not 00213 /// produce a value. Some frontends may use this as an operand register to 00214 /// mean special things, for example, the Sparc backend uses R0 to mean %g0 00215 /// which always PRODUCES the value 0. The X86 backend does not use this 00216 /// value as an operand register, except for memory references. 00217 /// 00218 NoRegister = 0, 00219 00220 /// FirstVirtualRegister - This is the first register number that is 00221 /// considered to be a 'virtual' register, which is part of the SSA 00222 /// namespace. This must be the same for all targets, which means that each 00223 /// target is limited to 1024 registers. 00224 /// 00225 FirstVirtualRegister = 1024 00226 }; 00227 00228 /// isPhysicalRegister - Return true if the specified register number is in 00229 /// the physical register namespace. 00230 static bool isPhysicalRegister(unsigned Reg) { 00231 assert(Reg && "this is not a register!"); 00232 return Reg < FirstVirtualRegister; 00233 } 00234 00235 /// isVirtualRegister - Return true if the specified register number is in 00236 /// the virtual register namespace. 00237 static bool isVirtualRegister(unsigned Reg) { 00238 assert(Reg && "this is not a register!"); 00239 return Reg >= FirstVirtualRegister; 00240 } 00241 00242 /// getAllocatableSet - Returns a bitset indexed by register number 00243 /// indicating if a register is allocatable or not. 00244 std::vector<bool> getAllocatableSet(MachineFunction &MF) const; 00245 00246 const TargetRegisterDesc &operator[](unsigned RegNo) const { 00247 assert(RegNo < NumRegs && 00248 "Attempting to access record for invalid register number!"); 00249 return Desc[RegNo]; 00250 } 00251 00252 /// Provide a get method, equivalent to [], but more useful if we have a 00253 /// pointer to this object. 00254 /// 00255 const TargetRegisterDesc &get(unsigned RegNo) const { 00256 return operator[](RegNo); 00257 } 00258 00259 /// getAliasSet - Return the set of registers aliased by the specified 00260 /// register, or a null list of there are none. The list returned is zero 00261 /// terminated. 00262 /// 00263 const unsigned *getAliasSet(unsigned RegNo) const { 00264 return get(RegNo).AliasSet; 00265 } 00266 00267 /// getName - Return the symbolic target specific name for the specified 00268 /// physical register. 00269 const char *getName(unsigned RegNo) const { 00270 return get(RegNo).Name; 00271 } 00272 00273 /// getNumRegs - Return the number of registers this target has 00274 /// (useful for sizing arrays holding per register information) 00275 unsigned getNumRegs() const { 00276 return NumRegs; 00277 } 00278 00279 /// areAliases - Returns true if the two registers alias each other, 00280 /// false otherwise 00281 bool areAliases(unsigned regA, unsigned regB) const { 00282 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) 00283 if (*Alias == regB) return true; 00284 return false; 00285 } 00286 00287 /// getCalleeSaveRegs - Return a null-terminated list of all of the 00288 /// callee-save registers on this target. 00289 virtual const unsigned* getCalleeSaveRegs() const = 0; 00290 00291 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred 00292 /// register classes to spill each callee-saved register with. The order and 00293 /// length of this list match the getCalleeSaveRegs() list. 00294 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0; 00295 00296 //===--------------------------------------------------------------------===// 00297 // Register Class Information 00298 // 00299 00300 /// Register class iterators 00301 /// 00302 regclass_iterator regclass_begin() const { return RegClassBegin; } 00303 regclass_iterator regclass_end() const { return RegClassEnd; } 00304 00305 unsigned getNumRegClasses() const { 00306 return regclass_end()-regclass_begin(); 00307 } 00308 00309 /// getRegClass - Returns the register class associated with the enumeration 00310 /// value. See class TargetOperandInfo. 00311 const TargetRegisterClass *getRegClass(unsigned i) const { 00312 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 00313 return i ? RegClassBegin[i - 1] : NULL; 00314 } 00315 00316 //===--------------------------------------------------------------------===// 00317 // Interfaces used by the register allocator and stack frame 00318 // manipulation passes to move data around between registers, 00319 // immediates and memory. The return value is the number of 00320 // instructions added to (negative if removed from) the basic block. 00321 // 00322 00323 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 00324 MachineBasicBlock::iterator MI, 00325 unsigned SrcReg, int FrameIndex, 00326 const TargetRegisterClass *RC) const = 0; 00327 00328 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 00329 MachineBasicBlock::iterator MI, 00330 unsigned DestReg, int FrameIndex, 00331 const TargetRegisterClass *RC) const = 0; 00332 00333 virtual void copyRegToReg(MachineBasicBlock &MBB, 00334 MachineBasicBlock::iterator MI, 00335 unsigned DestReg, unsigned SrcReg, 00336 const TargetRegisterClass *RC) const = 0; 00337 00338 /// foldMemoryOperand - Attempt to fold a load or store of the 00339 /// specified stack slot into the specified machine instruction for 00340 /// the specified operand. If this is possible, a new instruction 00341 /// is returned with the specified operand folded, otherwise NULL is 00342 /// returned. The client is responsible for removing the old 00343 /// instruction and adding the new one in the instruction stream 00344 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 00345 unsigned OpNum, 00346 int FrameIndex) const { 00347 return 0; 00348 } 00349 00350 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 00351 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 00352 /// targets use pseudo instructions in order to abstract away the difference 00353 /// between operating with a frame pointer and operating without, through the 00354 /// use of these two instructions. 00355 /// 00356 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 00357 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 00358 00359 00360 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 00361 /// code insertion to eliminate call frame setup and destroy pseudo 00362 /// instructions (but only if the Target is using them). It is responsible 00363 /// for eliminating these instructions, replacing them with concrete 00364 /// instructions. This method need only be implemented if using call frame 00365 /// setup/destroy pseudo instructions. 00366 /// 00367 virtual void 00368 eliminateCallFramePseudoInstr(MachineFunction &MF, 00369 MachineBasicBlock &MBB, 00370 MachineBasicBlock::iterator MI) const { 00371 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 00372 "eliminateCallFramePseudoInstr must be implemented if using" 00373 " call frame setup/destroy pseudo instructions!"); 00374 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 00375 } 00376 00377 /// processFunctionBeforeFrameFinalized - This method is called immediately 00378 /// before the specified functions frame layout (MF.getFrameInfo()) is 00379 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 00380 /// replaced with direct constants. This method is optional. The return value 00381 /// is the number of instructions added to (negative if removed from) the 00382 /// basic block 00383 /// 00384 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 00385 } 00386 00387 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 00388 /// frame indices from instructions which may use them. The instruction 00389 /// referenced by the iterator contains an MO_FrameIndex operand which must be 00390 /// eliminated by this method. This method may modify or replace the 00391 /// specified instruction, as long as it keeps the iterator pointing the the 00392 /// finished product. The return value is the number of instructions 00393 /// added to (negative if removed from) the basic block. 00394 /// 00395 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0; 00396 00397 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 00398 /// the function. The return value is the number of instructions 00399 /// added to (negative if removed from) the basic block (entry for prologue). 00400 /// 00401 virtual void emitPrologue(MachineFunction &MF) const = 0; 00402 virtual void emitEpilogue(MachineFunction &MF, 00403 MachineBasicBlock &MBB) const = 0; 00404 00405 //===--------------------------------------------------------------------===// 00406 /// Debug information queries. 00407 00408 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 00409 /// number. Returns -1 if there is no equivalent value. 00410 virtual int getDwarfRegNum(unsigned RegNum) const = 0; 00411 00412 /// getFrameRegister - This method should return the register used as a base 00413 /// for values allocated in the current stack frame. 00414 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 00415 00416 /// getRARegister - This method should return the register where the return 00417 /// address can be found. 00418 virtual unsigned getRARegister() const = 0; 00419 00420 /// getLocation - This method should return the actual location of a frame 00421 /// variable given the frame index. The location is returned in ML. 00422 /// Subclasses should override this method for special handling of frame 00423 /// variables and call MRegisterInfo::getLocation for the default action. 00424 virtual void getLocation(MachineFunction &MF, unsigned Index, 00425 MachineLocation &ML) const; 00426 00427 /// getInitialFrameState - Returns a list of machine moves that are assumed 00428 /// on entry to all functions. Note that LabelID is ignored (assumed to be 00429 /// the beginning of the function.) 00430 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const; 00431 }; 00432 00433 // This is useful when building DenseMaps keyed on virtual registers 00434 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 00435 unsigned operator()(unsigned Reg) const { 00436 return Reg - MRegisterInfo::FirstVirtualRegister; 00437 } 00438 }; 00439 00440 } // End llvm namespace 00441 00442 #endif