LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned ImplicitList1[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 }; 00012 static const unsigned ImplicitList2[] = { X86::AL, 0 }; 00013 static const unsigned ImplicitList3[] = { X86::AX, 0 }; 00014 static const unsigned ImplicitList4[] = { X86::EAX, 0 }; 00015 static const unsigned ImplicitList5[] = { X86::EAX, X86::EDX, 0 }; 00016 static const unsigned ImplicitList6[] = { X86::AX, X86::DX, 0 }; 00017 static const unsigned ImplicitList7[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 }; 00018 static const unsigned ImplicitList8[] = { X86::ST0, 0 }; 00019 static const unsigned ImplicitList9[] = { X86::DX, 0 }; 00020 static const unsigned ImplicitList10[] = { X86::AH, 0 }; 00021 static const unsigned ImplicitList11[] = { X86::EBP, X86::ESP, 0 }; 00022 static const unsigned ImplicitList12[] = { X86::EDI, 0 }; 00023 static const unsigned ImplicitList13[] = { X86::DX, X86::AX, 0 }; 00024 static const unsigned ImplicitList14[] = { X86::DX, X86::EAX, 0 }; 00025 static const unsigned ImplicitList15[] = { X86::DX, X86::AL, 0 }; 00026 static const unsigned ImplicitList16[] = { X86::ESP, 0 }; 00027 static const unsigned ImplicitList17[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00028 static const unsigned ImplicitList18[] = { X86::AL, X86::ECX, X86::EDI, 0 }; 00029 static const unsigned ImplicitList19[] = { X86::ECX, X86::EDI, 0 }; 00030 static const unsigned ImplicitList20[] = { X86::EAX, X86::ECX, X86::EDI, 0 }; 00031 static const unsigned ImplicitList21[] = { X86::AX, X86::ECX, X86::EDI, 0 }; 00032 static const unsigned ImplicitList22[] = { X86::CL, 0 }; 00033 00034 static const TargetOperandInfo OperandInfo2[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00035 static const TargetOperandInfo OperandInfo3[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, }; 00036 static const TargetOperandInfo OperandInfo4[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00037 static const TargetOperandInfo OperandInfo5[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00038 static const TargetOperandInfo OperandInfo6[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00039 static const TargetOperandInfo OperandInfo7[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR16RegClassID, 0 }, }; 00040 static const TargetOperandInfo OperandInfo8[] = { { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, { 0, 0 }, }; 00041 static const TargetOperandInfo OperandInfo9[] = { { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00042 static const TargetOperandInfo OperandInfo10[] = { { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, }; 00043 static const TargetOperandInfo OperandInfo11[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR8RegClassID, 0 }, }; 00044 static const TargetOperandInfo OperandInfo12[] = { { X86::GR8RegClassID, 0 }, { X86::GR8RegClassID, 0 }, { 0, 0 }, }; 00045 static const TargetOperandInfo OperandInfo13[] = { { X86::GR8RegClassID, 0 }, { X86::GR8RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00046 static const TargetOperandInfo OperandInfo14[] = { { X86::GR8RegClassID, 0 }, { X86::GR8RegClassID, 0 }, { X86::GR8RegClassID, 0 }, }; 00047 static const TargetOperandInfo OperandInfo15[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00048 static const TargetOperandInfo OperandInfo16[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, }; 00049 static const TargetOperandInfo OperandInfo17[] = { { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00050 static const TargetOperandInfo OperandInfo18[] = { { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00051 static const TargetOperandInfo OperandInfo19[] = { { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00052 static const TargetOperandInfo OperandInfo20[] = { { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, }; 00053 static const TargetOperandInfo OperandInfo21[] = { { 0, 0 }, }; 00054 static const TargetOperandInfo OperandInfo22[] = { { 0, 0 }, { 0, 0 }, }; 00055 static const TargetOperandInfo OperandInfo23[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00056 static const TargetOperandInfo OperandInfo24[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00057 static const TargetOperandInfo OperandInfo25[] = { { X86::GR32RegClassID, 0 }, }; 00058 static const TargetOperandInfo OperandInfo26[] = { { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { 0, 0 }, }; 00059 static const TargetOperandInfo OperandInfo27[] = { { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, { 0, 0 }, }; 00060 static const TargetOperandInfo OperandInfo28[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { 0, 0 }, }; 00061 static const TargetOperandInfo OperandInfo29[] = { { X86::GR16RegClassID, 0 }, { 0, 0 }, }; 00062 static const TargetOperandInfo OperandInfo30[] = { { X86::GR16RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00063 static const TargetOperandInfo OperandInfo31[] = { { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, }; 00064 static const TargetOperandInfo OperandInfo32[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00065 static const TargetOperandInfo OperandInfo33[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00066 static const TargetOperandInfo OperandInfo34[] = { { X86::GR8RegClassID, 0 }, { 0, 0 }, }; 00067 static const TargetOperandInfo OperandInfo35[] = { { X86::GR8RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00068 static const TargetOperandInfo OperandInfo36[] = { { X86::GR8RegClassID, 0 }, { X86::GR8RegClassID, 0 }, }; 00069 static const TargetOperandInfo OperandInfo37[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00070 static const TargetOperandInfo OperandInfo38[] = { { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00071 static const TargetOperandInfo OperandInfo39[] = { { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00072 static const TargetOperandInfo OperandInfo40[] = { { X86::VR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00073 static const TargetOperandInfo OperandInfo41[] = { { X86::VR64RegClassID, 0 }, { X86::VR128RegClassID, 0 }, }; 00074 static const TargetOperandInfo OperandInfo42[] = { { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00075 static const TargetOperandInfo OperandInfo43[] = { { X86::VR128RegClassID, 0 }, { X86::VR64RegClassID, 0 }, }; 00076 static const TargetOperandInfo OperandInfo44[] = { { X86::FR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00077 static const TargetOperandInfo OperandInfo45[] = { { X86::FR32RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00078 static const TargetOperandInfo OperandInfo46[] = { { X86::FR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00079 static const TargetOperandInfo OperandInfo47[] = { { X86::FR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00080 static const TargetOperandInfo OperandInfo48[] = { { X86::FR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00081 static const TargetOperandInfo OperandInfo49[] = { { X86::FR64RegClassID, 0 }, { X86::FR32RegClassID, 0 }, }; 00082 static const TargetOperandInfo OperandInfo50[] = { { X86::GR32RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00083 static const TargetOperandInfo OperandInfo51[] = { { X86::GR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, }; 00084 static const TargetOperandInfo OperandInfo52[] = { { X86::GR16RegClassID, 0 }, }; 00085 static const TargetOperandInfo OperandInfo53[] = { { X86::GR8RegClassID, 0 }, }; 00086 static const TargetOperandInfo OperandInfo54[] = { { 0, 0 }, { 0, 0 }, { 0, 0 }, }; 00087 static const TargetOperandInfo OperandInfo55[] = { { X86::RSTRegClassID, 0 }, }; 00088 static const TargetOperandInfo OperandInfo56[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::RFPRegClassID, 0 }, }; 00089 static const TargetOperandInfo OperandInfo57[] = { { X86::RFPRegClassID, 0 }, { X86::RFPRegClassID, 0 }, }; 00090 static const TargetOperandInfo OperandInfo58[] = { { X86::RFPRegClassID, 0 }, { X86::RFPRegClassID, 0 }, { X86::RFPRegClassID, 0 }, }; 00091 static const TargetOperandInfo OperandInfo59[] = { { X86::RFPRegClassID, 0 }, { X86::RFPRegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00092 static const TargetOperandInfo OperandInfo60[] = { { X86::RFPRegClassID, 0 }, }; 00093 static const TargetOperandInfo OperandInfo61[] = { { X86::RFPRegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00094 static const TargetOperandInfo OperandInfo62[] = { { X86::FR64RegClassID, 0 }, }; 00095 static const TargetOperandInfo OperandInfo63[] = { { X86::FR32RegClassID, 0 }, }; 00096 static const TargetOperandInfo OperandInfo64[] = { { X86::FR64RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00097 static const TargetOperandInfo OperandInfo65[] = { { X86::FR32RegClassID, 0 }, { X86::FR32RegClassID, 0 }, }; 00098 static const TargetOperandInfo OperandInfo66[] = { { X86::VR128RegClassID, 0 }, }; 00099 static const TargetOperandInfo OperandInfo67[] = { { X86::VR64RegClassID, 0 }, }; 00100 static const TargetOperandInfo OperandInfo68[] = { { X86::GR16RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00101 static const TargetOperandInfo OperandInfo69[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00102 static const TargetOperandInfo OperandInfo70[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, }; 00103 static const TargetOperandInfo OperandInfo71[] = { { X86::GR32RegClassID, 0 }, { X86::VR128RegClassID, 0 }, }; 00104 static const TargetOperandInfo OperandInfo72[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00105 static const TargetOperandInfo OperandInfo73[] = { { X86::VR64RegClassID, 0 }, { X86::VR64RegClassID, 0 }, }; 00106 static const TargetOperandInfo OperandInfo74[] = { { X86::FR64RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00107 static const TargetOperandInfo OperandInfo75[] = { { X86::FR64RegClassID, 0 }, { X86::FR32RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00108 static const TargetOperandInfo OperandInfo76[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR16_RegClassID, 0 }, }; 00109 static const TargetOperandInfo OperandInfo77[] = { { X86::GR16_RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00110 static const TargetOperandInfo OperandInfo78[] = { { X86::GR16_RegClassID, 0 }, { X86::GR16_RegClassID, 0 }, }; 00111 static const TargetOperandInfo OperandInfo79[] = { { X86::GR16_RegClassID, 0 }, { X86::GR16RegClassID, 0 }, }; 00112 static const TargetOperandInfo OperandInfo80[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32_RegClassID, 0 }, }; 00113 static const TargetOperandInfo OperandInfo81[] = { { X86::GR32_RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00114 static const TargetOperandInfo OperandInfo82[] = { { X86::GR32_RegClassID, 0 }, { X86::GR32_RegClassID, 0 }, }; 00115 static const TargetOperandInfo OperandInfo83[] = { { X86::GR32_RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00116 static const TargetOperandInfo OperandInfo84[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::VR128RegClassID, 0 }, }; 00117 static const TargetOperandInfo OperandInfo85[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::VR64RegClassID, 0 }, }; 00118 static const TargetOperandInfo OperandInfo86[] = { { X86::VR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00119 static const TargetOperandInfo OperandInfo87[] = { { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00120 static const TargetOperandInfo OperandInfo88[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00121 static const TargetOperandInfo OperandInfo89[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::FR32RegClassID, 0 }, }; 00122 static const TargetOperandInfo OperandInfo90[] = { { X86::FR64RegClassID, 0 }, { X86::VR128RegClassID, 0 }, }; 00123 static const TargetOperandInfo OperandInfo91[] = { { X86::FR32RegClassID, 0 }, { X86::VR128RegClassID, 0 }, }; 00124 static const TargetOperandInfo OperandInfo92[] = { { X86::VR128RegClassID, 0 }, { X86::FR64RegClassID, 0 }, }; 00125 static const TargetOperandInfo OperandInfo93[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::FR64RegClassID, 0 }, }; 00126 static const TargetOperandInfo OperandInfo94[] = { { X86::VR128RegClassID, 0 }, { X86::FR32RegClassID, 0 }, }; 00127 static const TargetOperandInfo OperandInfo95[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::FR32RegClassID, 0 }, }; 00128 static const TargetOperandInfo OperandInfo96[] = { { X86::GR16RegClassID, 0 }, { X86::GR8RegClassID, 0 }, }; 00129 static const TargetOperandInfo OperandInfo97[] = { { X86::GR32RegClassID, 0 }, { X86::GR16RegClassID, 0 }, }; 00130 static const TargetOperandInfo OperandInfo98[] = { { X86::GR32RegClassID, 0 }, { X86::GR8RegClassID, 0 }, }; 00131 static const TargetOperandInfo OperandInfo99[] = { { X86::GR32RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { 0, 0 }, }; 00132 static const TargetOperandInfo OperandInfo100[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00133 static const TargetOperandInfo OperandInfo101[] = { { X86::VR128RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00134 static const TargetOperandInfo OperandInfo102[] = { { X86::VR128RegClassID, 0 }, { X86::VR128RegClassID, 0 }, { 0, 0 }, }; 00135 static const TargetOperandInfo OperandInfo103[] = { { X86::VR64RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00136 static const TargetOperandInfo OperandInfo104[] = { { X86::VR64RegClassID, 0 }, { X86::VR64RegClassID, 0 }, { 0, 0 }, }; 00137 static const TargetOperandInfo OperandInfo105[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR16RegClassID, 0 }, { 0, 0 }, }; 00138 static const TargetOperandInfo OperandInfo106[] = { { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, { X86::GR16RegClassID, 0 }, { 0, 0 }, }; 00139 static const TargetOperandInfo OperandInfo107[] = { { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00140 static const TargetOperandInfo OperandInfo108[] = { { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { X86::GR32RegClassID, 0 }, { 0, 0 }, }; 00141 static const TargetOperandInfo OperandInfo109[] = { { X86::GR8RegClassID, 0 }, { X86::GR16_RegClassID, 0 }, }; 00142 static const TargetOperandInfo OperandInfo110[] = { { X86::GR16RegClassID, 0 }, { X86::GR32RegClassID, 0 }, }; 00143 static const TargetOperandInfo OperandInfo111[] = { { X86::GR8RegClassID, 0 }, { X86::GR32_RegClassID, 0 }, }; 00144 00145 static const TargetInstrDescriptor X86Insts[] = { 00146 { "PHI", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #0 = PHI 00147 { "INLINEASM", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #1 = INLINEASM 00148 { "ADC32mi", 5, 0, 0|M_STORE_FLAG, 0|26|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #2 = ADC32mi 00149 { "ADC32mi8", 5, 0, 0|M_STORE_FLAG, 0|26|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #3 = ADC32mi8 00150 { "ADC32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(17<<16), NULL, NULL, OperandInfo3 }, // Inst #4 = ADC32mr 00151 { "ADC32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|18|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #5 = ADC32ri 00152 { "ADC32ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #6 = ADC32ri8 00153 { "ADC32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(19<<16), NULL, NULL, OperandInfo5 }, // Inst #7 = ADC32rm 00154 { "ADC32rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(17<<16), NULL, NULL, OperandInfo6 }, // Inst #8 = ADC32rr 00155 { "ADD16mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #9 = ADD16mi 00156 { "ADD16mi8", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #10 = ADD16mi8 00157 { "ADD16mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<16), NULL, NULL, OperandInfo7 }, // Inst #11 = ADD16mr 00158 { "ADD16ri", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo8 }, // Inst #12 = ADD16ri 00159 { "ADD16ri8", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo8 }, // Inst #13 = ADD16ri8 00160 { "ADD16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(3<<16), NULL, NULL, OperandInfo9 }, // Inst #14 = ADD16rm 00161 { "ADD16rr", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR|M_COMMUTABLE, 0|3|(1<<6)|(1<<16), NULL, NULL, OperandInfo10 }, // Inst #15 = ADD16rr 00162 { "ADD32mi", 5, 0, 0|M_STORE_FLAG, 0|24|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #16 = ADD32mi 00163 { "ADD32mi8", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #17 = ADD32mi8 00164 { "ADD32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<16), NULL, NULL, OperandInfo3 }, // Inst #18 = ADD32mr 00165 { "ADD32ri", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #19 = ADD32ri 00166 { "ADD32ri8", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #20 = ADD32ri8 00167 { "ADD32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(3<<16), NULL, NULL, OperandInfo5 }, // Inst #21 = ADD32rm 00168 { "ADD32rr", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR|M_COMMUTABLE, 0|3|(1<<16), NULL, NULL, OperandInfo6 }, // Inst #22 = ADD32rr 00169 { "ADD8mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #23 = ADD8mi 00170 { "ADD8mr", 5, 0, 0|M_STORE_FLAG, 0|4, NULL, NULL, OperandInfo11 }, // Inst #24 = ADD8mr 00171 { "ADD8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(128<<16), NULL, NULL, OperandInfo12 }, // Inst #25 = ADD8ri 00172 { "ADD8rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(2<<16), NULL, NULL, OperandInfo13 }, // Inst #26 = ADD8rm 00173 { "ADD8rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3, NULL, NULL, OperandInfo14 }, // Inst #27 = ADD8rr 00174 { "ADDPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(88<<16), NULL, NULL, OperandInfo15 }, // Inst #28 = ADDPDrm 00175 { "ADDPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(88<<16), NULL, NULL, OperandInfo16 }, // Inst #29 = ADDPDrr 00176 { "ADDPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(88<<16), NULL, NULL, OperandInfo15 }, // Inst #30 = ADDPSrm 00177 { "ADDPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(88<<16), NULL, NULL, OperandInfo16 }, // Inst #31 = ADDPSrr 00178 { "ADDSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(88<<16), NULL, NULL, OperandInfo17 }, // Inst #32 = ADDSDrm 00179 { "ADDSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(88<<16), NULL, NULL, OperandInfo18 }, // Inst #33 = ADDSDrr 00180 { "ADDSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(88<<16), NULL, NULL, OperandInfo19 }, // Inst #34 = ADDSSrm 00181 { "ADDSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(88<<16), NULL, NULL, OperandInfo20 }, // Inst #35 = ADDSSrr 00182 { "ADDSUBPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(208<<16), NULL, NULL, OperandInfo15 }, // Inst #36 = ADDSUBPDrm 00183 { "ADDSUBPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(208<<16), NULL, NULL, OperandInfo16 }, // Inst #37 = ADDSUBPDrr 00184 { "ADDSUBPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(208<<16), NULL, NULL, OperandInfo15 }, // Inst #38 = ADDSUBPSrm 00185 { "ADDSUBPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(208<<16), NULL, NULL, OperandInfo16 }, // Inst #39 = ADDSUBPSrr 00186 { "ADJCALLSTACKDOWN", 1, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #40 = ADJCALLSTACKDOWN 00187 { "ADJCALLSTACKUP", 2, 0, 0, 0, NULL, NULL, OperandInfo22 }, // Inst #41 = ADJCALLSTACKUP 00188 { "ADJSTACKPTRri", 3, 0, 0|M_2_ADDR_FLAG|M_TERMINATOR_FLAG, 0|16|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #42 = ADJSTACKPTRri 00189 { "AND16mi", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #43 = AND16mi 00190 { "AND16mi8", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #44 = AND16mi8 00191 { "AND16mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(33<<16), NULL, NULL, OperandInfo7 }, // Inst #45 = AND16mr 00192 { "AND16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo8 }, // Inst #46 = AND16ri 00193 { "AND16ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo8 }, // Inst #47 = AND16ri8 00194 { "AND16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(35<<16), NULL, NULL, OperandInfo9 }, // Inst #48 = AND16rm 00195 { "AND16rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(33<<16), NULL, NULL, OperandInfo10 }, // Inst #49 = AND16rr 00196 { "AND32mi", 5, 0, 0|M_STORE_FLAG, 0|28|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #50 = AND32mi 00197 { "AND32mi8", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #51 = AND32mi8 00198 { "AND32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(33<<16), NULL, NULL, OperandInfo3 }, // Inst #52 = AND32mr 00199 { "AND32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #53 = AND32ri 00200 { "AND32ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #54 = AND32ri8 00201 { "AND32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(35<<16), NULL, NULL, OperandInfo5 }, // Inst #55 = AND32rm 00202 { "AND32rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(33<<16), NULL, NULL, OperandInfo6 }, // Inst #56 = AND32rr 00203 { "AND8mi", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #57 = AND8mi 00204 { "AND8mr", 5, 0, 0|M_STORE_FLAG, 0|4|(32<<16), NULL, NULL, OperandInfo11 }, // Inst #58 = AND8mr 00205 { "AND8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<11)|(128<<16), NULL, NULL, OperandInfo12 }, // Inst #59 = AND8ri 00206 { "AND8rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(34<<16), NULL, NULL, OperandInfo13 }, // Inst #60 = AND8rm 00207 { "AND8rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(32<<16), NULL, NULL, OperandInfo14 }, // Inst #61 = AND8rr 00208 { "ANDNPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(85<<16), NULL, NULL, OperandInfo15 }, // Inst #62 = ANDNPDrm 00209 { "ANDNPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(85<<16), NULL, NULL, OperandInfo16 }, // Inst #63 = ANDNPDrr 00210 { "ANDNPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(85<<16), NULL, NULL, OperandInfo15 }, // Inst #64 = ANDNPSrm 00211 { "ANDNPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(85<<16), NULL, NULL, OperandInfo16 }, // Inst #65 = ANDNPSrr 00212 { "ANDPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(84<<16), NULL, NULL, OperandInfo15 }, // Inst #66 = ANDPDrm 00213 { "ANDPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(84<<16), NULL, NULL, OperandInfo16 }, // Inst #67 = ANDPDrr 00214 { "ANDPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(84<<16), NULL, NULL, OperandInfo15 }, // Inst #68 = ANDPSrm 00215 { "ANDPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(84<<16), NULL, NULL, OperandInfo16 }, // Inst #69 = ANDPSrr 00216 { "BSWAP32r", 2, 0, 0|M_2_ADDR_FLAG, 0|2|(1<<7)|(200<<16), NULL, NULL, OperandInfo23 }, // Inst #70 = BSWAP32r 00217 { "CALL32m", 4, 0, 0|M_CALL_FLAG|M_VARIABLE_OPS, 0|26|(255<<16), NULL, ImplicitList1, OperandInfo24 }, // Inst #71 = CALL32m 00218 { "CALL32r", 1, 0, 0|M_CALL_FLAG|M_VARIABLE_OPS, 0|18|(255<<16), NULL, ImplicitList1, OperandInfo25 }, // Inst #72 = CALL32r 00219 { "CALLpcrel32", 1, 0, 0|M_CALL_FLAG|M_VARIABLE_OPS, 0|1|(232<<16), NULL, ImplicitList1, OperandInfo21 }, // Inst #73 = CALLpcrel32 00220 { "CBW", 0, 0, 0, 0|1|(152<<16), ImplicitList2, ImplicitList3, 0 }, // Inst #74 = CBW 00221 { "CDQ", 0, 0, 0, 0|1|(153<<16), ImplicitList4, ImplicitList5, 0 }, // Inst #75 = CDQ 00222 { "CLFLUSH", 4, 0, 0, 0|31|(1<<7)|(174<<16), NULL, NULL, OperandInfo24 }, // Inst #76 = CLFLUSH 00223 { "CMOVA16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(71<<16), NULL, NULL, OperandInfo9 }, // Inst #77 = CMOVA16rm 00224 { "CMOVA16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(71<<16), NULL, NULL, OperandInfo10 }, // Inst #78 = CMOVA16rr 00225 { "CMOVA32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(71<<16), NULL, NULL, OperandInfo5 }, // Inst #79 = CMOVA32rm 00226 { "CMOVA32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(71<<16), NULL, NULL, OperandInfo6 }, // Inst #80 = CMOVA32rr 00227 { "CMOVAE16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(67<<16), NULL, NULL, OperandInfo9 }, // Inst #81 = CMOVAE16rm 00228 { "CMOVAE16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(67<<16), NULL, NULL, OperandInfo10 }, // Inst #82 = CMOVAE16rr 00229 { "CMOVAE32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(67<<16), NULL, NULL, OperandInfo5 }, // Inst #83 = CMOVAE32rm 00230 { "CMOVAE32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(67<<16), NULL, NULL, OperandInfo6 }, // Inst #84 = CMOVAE32rr 00231 { "CMOVB16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(66<<16), NULL, NULL, OperandInfo9 }, // Inst #85 = CMOVB16rm 00232 { "CMOVB16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(66<<16), NULL, NULL, OperandInfo10 }, // Inst #86 = CMOVB16rr 00233 { "CMOVB32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(66<<16), NULL, NULL, OperandInfo5 }, // Inst #87 = CMOVB32rm 00234 { "CMOVB32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(66<<16), NULL, NULL, OperandInfo6 }, // Inst #88 = CMOVB32rr 00235 { "CMOVBE16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(70<<16), NULL, NULL, OperandInfo9 }, // Inst #89 = CMOVBE16rm 00236 { "CMOVBE16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(70<<16), NULL, NULL, OperandInfo10 }, // Inst #90 = CMOVBE16rr 00237 { "CMOVBE32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(70<<16), NULL, NULL, OperandInfo5 }, // Inst #91 = CMOVBE32rm 00238 { "CMOVBE32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(70<<16), NULL, NULL, OperandInfo6 }, // Inst #92 = CMOVBE32rr 00239 { "CMOVE16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(68<<16), NULL, NULL, OperandInfo9 }, // Inst #93 = CMOVE16rm 00240 { "CMOVE16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(68<<16), NULL, NULL, OperandInfo10 }, // Inst #94 = CMOVE16rr 00241 { "CMOVE32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(68<<16), NULL, NULL, OperandInfo5 }, // Inst #95 = CMOVE32rm 00242 { "CMOVE32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(68<<16), NULL, NULL, OperandInfo6 }, // Inst #96 = CMOVE32rr 00243 { "CMOVG16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(79<<16), NULL, NULL, OperandInfo9 }, // Inst #97 = CMOVG16rm 00244 { "CMOVG16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(79<<16), NULL, NULL, OperandInfo10 }, // Inst #98 = CMOVG16rr 00245 { "CMOVG32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(79<<16), NULL, NULL, OperandInfo5 }, // Inst #99 = CMOVG32rm 00246 { "CMOVG32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(79<<16), NULL, NULL, OperandInfo6 }, // Inst #100 = CMOVG32rr 00247 { "CMOVGE16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(77<<16), NULL, NULL, OperandInfo9 }, // Inst #101 = CMOVGE16rm 00248 { "CMOVGE16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(77<<16), NULL, NULL, OperandInfo10 }, // Inst #102 = CMOVGE16rr 00249 { "CMOVGE32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(77<<16), NULL, NULL, OperandInfo5 }, // Inst #103 = CMOVGE32rm 00250 { "CMOVGE32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(77<<16), NULL, NULL, OperandInfo6 }, // Inst #104 = CMOVGE32rr 00251 { "CMOVL16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(76<<16), NULL, NULL, OperandInfo9 }, // Inst #105 = CMOVL16rm 00252 { "CMOVL16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(76<<16), NULL, NULL, OperandInfo10 }, // Inst #106 = CMOVL16rr 00253 { "CMOVL32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(76<<16), NULL, NULL, OperandInfo5 }, // Inst #107 = CMOVL32rm 00254 { "CMOVL32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(76<<16), NULL, NULL, OperandInfo6 }, // Inst #108 = CMOVL32rr 00255 { "CMOVLE16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(78<<16), NULL, NULL, OperandInfo9 }, // Inst #109 = CMOVLE16rm 00256 { "CMOVLE16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(78<<16), NULL, NULL, OperandInfo10 }, // Inst #110 = CMOVLE16rr 00257 { "CMOVLE32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(78<<16), NULL, NULL, OperandInfo5 }, // Inst #111 = CMOVLE32rm 00258 { "CMOVLE32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(78<<16), NULL, NULL, OperandInfo6 }, // Inst #112 = CMOVLE32rr 00259 { "CMOVNE16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(69<<16), NULL, NULL, OperandInfo9 }, // Inst #113 = CMOVNE16rm 00260 { "CMOVNE16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(69<<16), NULL, NULL, OperandInfo10 }, // Inst #114 = CMOVNE16rr 00261 { "CMOVNE32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(69<<16), NULL, NULL, OperandInfo5 }, // Inst #115 = CMOVNE32rm 00262 { "CMOVNE32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(69<<16), NULL, NULL, OperandInfo6 }, // Inst #116 = CMOVNE32rr 00263 { "CMOVNP16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(75<<16), NULL, NULL, OperandInfo9 }, // Inst #117 = CMOVNP16rm 00264 { "CMOVNP16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(75<<16), NULL, NULL, OperandInfo10 }, // Inst #118 = CMOVNP16rr 00265 { "CMOVNP32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(75<<16), NULL, NULL, OperandInfo5 }, // Inst #119 = CMOVNP32rm 00266 { "CMOVNP32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(75<<16), NULL, NULL, OperandInfo6 }, // Inst #120 = CMOVNP32rr 00267 { "CMOVNS16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(73<<16), NULL, NULL, OperandInfo9 }, // Inst #121 = CMOVNS16rm 00268 { "CMOVNS16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(73<<16), NULL, NULL, OperandInfo10 }, // Inst #122 = CMOVNS16rr 00269 { "CMOVNS32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(73<<16), NULL, NULL, OperandInfo5 }, // Inst #123 = CMOVNS32rm 00270 { "CMOVNS32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(73<<16), NULL, NULL, OperandInfo6 }, // Inst #124 = CMOVNS32rr 00271 { "CMOVP16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(74<<16), NULL, NULL, OperandInfo9 }, // Inst #125 = CMOVP16rm 00272 { "CMOVP16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(74<<16), NULL, NULL, OperandInfo10 }, // Inst #126 = CMOVP16rr 00273 { "CMOVP32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(74<<16), NULL, NULL, OperandInfo5 }, // Inst #127 = CMOVP32rm 00274 { "CMOVP32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(74<<16), NULL, NULL, OperandInfo6 }, // Inst #128 = CMOVP32rr 00275 { "CMOVS16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(72<<16), NULL, NULL, OperandInfo9 }, // Inst #129 = CMOVS16rm 00276 { "CMOVS16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(72<<16), NULL, NULL, OperandInfo10 }, // Inst #130 = CMOVS16rr 00277 { "CMOVS32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(72<<16), NULL, NULL, OperandInfo5 }, // Inst #131 = CMOVS32rm 00278 { "CMOVS32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(72<<16), NULL, NULL, OperandInfo6 }, // Inst #132 = CMOVS32rr 00279 { "CMOV_FR32", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo26 }, // Inst #133 = CMOV_FR32 00280 { "CMOV_FR64", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo27 }, // Inst #134 = CMOV_FR64 00281 { "CMOV_V2F64", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo28 }, // Inst #135 = CMOV_V2F64 00282 { "CMOV_V2I64", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo28 }, // Inst #136 = CMOV_V2I64 00283 { "CMOV_V4F32", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo28 }, // Inst #137 = CMOV_V4F32 00284 { "CMP16mi", 5, 0, 0, 0|31|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #138 = CMP16mi 00285 { "CMP16mi8", 5, 0, 0, 0|31|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #139 = CMP16mi8 00286 { "CMP16mr", 5, 0, 0, 0|4|(1<<6)|(57<<16), NULL, NULL, OperandInfo7 }, // Inst #140 = CMP16mr 00287 { "CMP16ri", 2, 0, 0, 0|23|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo29 }, // Inst #141 = CMP16ri 00288 { "CMP16ri8", 2, 0, 0, 0|23|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo29 }, // Inst #142 = CMP16ri8 00289 { "CMP16rm", 5, 0, 0, 0|6|(1<<6)|(59<<16), NULL, NULL, OperandInfo30 }, // Inst #143 = CMP16rm 00290 { "CMP16rr", 2, 0, 0, 0|3|(1<<6)|(57<<16), NULL, NULL, OperandInfo31 }, // Inst #144 = CMP16rr 00291 { "CMP32mi", 5, 0, 0, 0|31|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #145 = CMP32mi 00292 { "CMP32mi8", 5, 0, 0, 0|31|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #146 = CMP32mi8 00293 { "CMP32mr", 5, 0, 0, 0|4|(57<<16), NULL, NULL, OperandInfo3 }, // Inst #147 = CMP32mr 00294 { "CMP32ri", 2, 0, 0, 0|23|(3<<11)|(129<<16), NULL, NULL, OperandInfo32 }, // Inst #148 = CMP32ri 00295 { "CMP32ri8", 2, 0, 0, 0|23|(1<<11)|(131<<16), NULL, NULL, OperandInfo32 }, // Inst #149 = CMP32ri8 00296 { "CMP32rm", 5, 0, 0, 0|6|(59<<16), NULL, NULL, OperandInfo33 }, // Inst #150 = CMP32rm 00297 { "CMP32rr", 2, 0, 0, 0|3|(57<<16), NULL, NULL, OperandInfo23 }, // Inst #151 = CMP32rr 00298 { "CMP8mi", 5, 0, 0, 0|31|(1<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #152 = CMP8mi 00299 { "CMP8mr", 5, 0, 0, 0|4|(56<<16), NULL, NULL, OperandInfo11 }, // Inst #153 = CMP8mr 00300 { "CMP8ri", 2, 0, 0, 0|23|(1<<11)|(128<<16), NULL, NULL, OperandInfo34 }, // Inst #154 = CMP8ri 00301 { "CMP8rm", 5, 0, 0, 0|6|(58<<16), NULL, NULL, OperandInfo35 }, // Inst #155 = CMP8rm 00302 { "CMP8rr", 2, 0, 0, 0|3|(56<<16), NULL, NULL, OperandInfo36 }, // Inst #156 = CMP8rr 00303 { "CMPPDrmi", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(194<<16), NULL, NULL, OperandInfo37 }, // Inst #157 = CMPPDrmi 00304 { "CMPPDrri", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(194<<16), NULL, NULL, OperandInfo28 }, // Inst #158 = CMPPDrri 00305 { "CMPPSrmi", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(1<<11)|(194<<16), NULL, NULL, OperandInfo37 }, // Inst #159 = CMPPSrmi 00306 { "CMPPSrri", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(1<<11)|(194<<16), NULL, NULL, OperandInfo28 }, // Inst #160 = CMPPSrri 00307 { "CMPSDrm", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(194<<16), NULL, NULL, OperandInfo38 }, // Inst #161 = CMPSDrm 00308 { "CMPSDrr", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(194<<16), NULL, NULL, OperandInfo27 }, // Inst #162 = CMPSDrr 00309 { "CMPSSrm", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(194<<16), NULL, NULL, OperandInfo39 }, // Inst #163 = CMPSSrm 00310 { "CMPSSrr", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(194<<16), NULL, NULL, OperandInfo26 }, // Inst #164 = CMPSSrr 00311 { "CVTPD2PIrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(45<<16), NULL, NULL, OperandInfo40 }, // Inst #165 = CVTPD2PIrm 00312 { "CVTPD2PIrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(45<<16), NULL, NULL, OperandInfo41 }, // Inst #166 = CVTPD2PIrr 00313 { "CVTPI2PDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(42<<16), NULL, NULL, OperandInfo42 }, // Inst #167 = CVTPI2PDrm 00314 { "CVTPI2PDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(42<<16), NULL, NULL, OperandInfo43 }, // Inst #168 = CVTPI2PDrr 00315 { "CVTPI2PSrm", 5, 0, 0, 0|6|(1<<7)|(42<<16), NULL, NULL, OperandInfo42 }, // Inst #169 = CVTPI2PSrm 00316 { "CVTPI2PSrr", 2, 0, 0, 0|5|(1<<7)|(42<<16), NULL, NULL, OperandInfo43 }, // Inst #170 = CVTPI2PSrr 00317 { "CVTPS2PIrm", 5, 0, 0, 0|6|(1<<7)|(45<<16), NULL, NULL, OperandInfo40 }, // Inst #171 = CVTPS2PIrm 00318 { "CVTPS2PIrr", 2, 0, 0, 0|5|(1<<7)|(45<<16), NULL, NULL, OperandInfo41 }, // Inst #172 = CVTPS2PIrr 00319 { "CVTSD2SSrm", 5, 0, 0, 0|6|(11<<7)|(90<<16), NULL, NULL, OperandInfo44 }, // Inst #173 = CVTSD2SSrm 00320 { "CVTSD2SSrr", 2, 0, 0, 0|5|(11<<7)|(90<<16), NULL, NULL, OperandInfo45 }, // Inst #174 = CVTSD2SSrr 00321 { "CVTSI2SDrm", 5, 0, 0, 0|6|(11<<7)|(42<<16), NULL, NULL, OperandInfo46 }, // Inst #175 = CVTSI2SDrm 00322 { "CVTSI2SDrr", 2, 0, 0, 0|5|(11<<7)|(42<<16), NULL, NULL, OperandInfo47 }, // Inst #176 = CVTSI2SDrr 00323 { "CVTSI2SSrm", 5, 0, 0, 0|6|(12<<7)|(42<<16), NULL, NULL, OperandInfo44 }, // Inst #177 = CVTSI2SSrm 00324 { "CVTSI2SSrr", 2, 0, 0, 0|5|(12<<7)|(42<<16), NULL, NULL, OperandInfo48 }, // Inst #178 = CVTSI2SSrr 00325 { "CVTSS2SDrm", 5, 0, 0, 0|6|(12<<7)|(90<<16), NULL, NULL, OperandInfo46 }, // Inst #179 = CVTSS2SDrm 00326 { "CVTSS2SDrr", 2, 0, 0, 0|5|(12<<7)|(90<<16), NULL, NULL, OperandInfo49 }, // Inst #180 = CVTSS2SDrr 00327 { "CVTTPS2PIrm", 5, 0, 0, 0|6|(1<<7)|(44<<16), NULL, NULL, OperandInfo40 }, // Inst #181 = CVTTPS2PIrm 00328 { "CVTTPS2PIrr", 2, 0, 0, 0|5|(1<<7)|(44<<16), NULL, NULL, OperandInfo41 }, // Inst #182 = CVTTPS2PIrr 00329 { "CVTTSD2SIrm", 5, 0, 0, 0|6|(11<<7)|(44<<16), NULL, NULL, OperandInfo33 }, // Inst #183 = CVTTSD2SIrm 00330 { "CVTTSD2SIrr", 2, 0, 0, 0|5|(11<<7)|(44<<16), NULL, NULL, OperandInfo50 }, // Inst #184 = CVTTSD2SIrr 00331 { "CVTTSS2SIrm", 5, 0, 0, 0|6|(12<<7)|(44<<16), NULL, NULL, OperandInfo33 }, // Inst #185 = CVTTSS2SIrm 00332 { "CVTTSS2SIrr", 2, 0, 0, 0|5|(12<<7)|(44<<16), NULL, NULL, OperandInfo51 }, // Inst #186 = CVTTSS2SIrr 00333 { "CWD", 0, 0, 0, 0|1|(153<<16), ImplicitList3, ImplicitList6, 0 }, // Inst #187 = CWD 00334 { "CWDE", 0, 0, 0, 0|1|(152<<16), ImplicitList3, ImplicitList4, 0 }, // Inst #188 = CWDE 00335 { "DEC16m", 4, 0, 0|M_STORE_FLAG, 0|25|(1<<6)|(255<<16), NULL, NULL, OperandInfo24 }, // Inst #189 = DEC16m 00336 { "DEC16r", 2, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|2|(1<<6)|(72<<16), NULL, NULL, OperandInfo31 }, // Inst #190 = DEC16r 00337 { "DEC32m", 4, 0, 0|M_STORE_FLAG, 0|25|(255<<16), NULL, NULL, OperandInfo24 }, // Inst #191 = DEC32m 00338 { "DEC32r", 2, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|2|(72<<16), NULL, NULL, OperandInfo23 }, // Inst #192 = DEC32r 00339 { "DEC8m", 4, 0, 0|M_STORE_FLAG, 0|25|(254<<16), NULL, NULL, OperandInfo24 }, // Inst #193 = DEC8m 00340 { "DEC8r", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(254<<16), NULL, NULL, OperandInfo36 }, // Inst #194 = DEC8r 00341 { "DIV16m", 4, 0, 0, 0|30|(1<<6)|(247<<16), ImplicitList6, ImplicitList6, OperandInfo24 }, // Inst #195 = DIV16m 00342 { "DIV16r", 1, 0, 0, 0|22|(1<<6)|(247<<16), ImplicitList6, ImplicitList6, OperandInfo52 }, // Inst #196 = DIV16r 00343 { "DIV32m", 4, 0, 0, 0|30|(247<<16), ImplicitList5, ImplicitList5, OperandInfo24 }, // Inst #197 = DIV32m 00344 { "DIV32r", 1, 0, 0, 0|22|(247<<16), ImplicitList5, ImplicitList5, OperandInfo25 }, // Inst #198 = DIV32r 00345 { "DIV8m", 4, 0, 0, 0|30|(246<<16), ImplicitList3, ImplicitList3, OperandInfo24 }, // Inst #199 = DIV8m 00346 { "DIV8r", 1, 0, 0, 0|22|(246<<16), ImplicitList3, ImplicitList3, OperandInfo53 }, // Inst #200 = DIV8r 00347 { "DIVPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(94<<16), NULL, NULL, OperandInfo15 }, // Inst #201 = DIVPDrm 00348 { "DIVPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(94<<16), NULL, NULL, OperandInfo16 }, // Inst #202 = DIVPDrr 00349 { "DIVPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(94<<16), NULL, NULL, OperandInfo15 }, // Inst #203 = DIVPSrm 00350 { "DIVPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(94<<16), NULL, NULL, OperandInfo16 }, // Inst #204 = DIVPSrr 00351 { "DIVSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(94<<16), NULL, NULL, OperandInfo17 }, // Inst #205 = DIVSDrm 00352 { "DIVSDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(94<<16), NULL, NULL, OperandInfo18 }, // Inst #206 = DIVSDrr 00353 { "DIVSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(94<<16), NULL, NULL, OperandInfo19 }, // Inst #207 = DIVSSrm 00354 { "DIVSSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(94<<16), NULL, NULL, OperandInfo20 }, // Inst #208 = DIVSSrr 00355 { "DWARF_LABEL", 1, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #209 = DWARF_LABEL 00356 { "DWARF_LOC", 3, 0, 0, 0, NULL, NULL, OperandInfo54 }, // Inst #210 = DWARF_LOC 00357 { "FABS", 0, 0, 0, 0|1|(4<<7)|(225<<16), NULL, NULL, 0 }, // Inst #211 = FABS 00358 { "FADD32m", 4, 0, 0, 0|24|(216<<16), NULL, NULL, OperandInfo24 }, // Inst #212 = FADD32m 00359 { "FADD64m", 4, 0, 0, 0|24|(220<<16), NULL, NULL, OperandInfo24 }, // Inst #213 = FADD64m 00360 { "FADDPrST0", 1, 0, 0, 0|2|(9<<7)|(192<<16), NULL, NULL, OperandInfo55 }, // Inst #214 = FADDPrST0 00361 { "FADDST0r", 1, 0, 0, 0|2|(3<<7)|(192<<16), NULL, NULL, OperandInfo55 }, // Inst #215 = FADDST0r 00362 { "FADDrST0", 1, 0, 0, 0|2|(7<<7)|(192<<16), NULL, NULL, OperandInfo55 }, // Inst #216 = FADDrST0 00363 { "FCHS", 0, 0, 0, 0|1|(4<<7)|(224<<16), NULL, NULL, 0 }, // Inst #217 = FCHS 00364 { "FCMOVB", 1, 0, 0, 0|2|(5<<7)|(192<<16), NULL, NULL, OperandInfo55 }, // Inst #218 = FCMOVB 00365 { "FCMOVBE", 1, 0, 0, 0|2|(5<<7)|(208<<16), NULL, NULL, OperandInfo55 }, // Inst #219 = FCMOVBE 00366 { "FCMOVE", 1, 0, 0, 0|2|(5<<7)|(200<<16), NULL, NULL, OperandInfo55 }, // Inst #220 = FCMOVE 00367 { "FCMOVNB", 1, 0, 0, 0|2|(6<<7)|(192<<16), NULL, NULL, OperandInfo55 }, // Inst #221 = FCMOVNB 00368 { "FCMOVNBE", 1, 0, 0, 0|2|(6<<7)|(208<<16), NULL, NULL, OperandInfo55 }, // Inst #222 = FCMOVNBE 00369 { "FCMOVNE", 1, 0, 0, 0|2|(6<<7)|(200<<16), NULL, NULL, OperandInfo55 }, // Inst #223 = FCMOVNE 00370 { "FCMOVNP", 1, 0, 0, 0|2|(6<<7)|(216<<16), NULL, NULL, OperandInfo55 }, // Inst #224 = FCMOVNP 00371 { "FCMOVP", 1, 0, 0, 0|2|(5<<7)|(216<<16), NULL, NULL, OperandInfo55 }, // Inst #225 = FCMOVP 00372 { "FCOS", 0, 0, 0, 0|1|(4<<7)|(255<<16), NULL, NULL, 0 }, // Inst #226 = FCOS 00373 { "FDIV32m", 4, 0, 0, 0|30|(216<<16), NULL, NULL, OperandInfo24 }, // Inst #227 = FDIV32m 00374 { "FDIV64m", 4, 0, 0, 0|30|(220<<16), NULL, NULL, OperandInfo24 }, // Inst #228 = FDIV64m 00375 { "FDIVPrST0", 1, 0, 0, 0|2|(9<<7)|(248<<16), NULL, NULL, OperandInfo55 }, // Inst #229 = FDIVPrST0 00376 { "FDIVR32m", 4, 0, 0, 0|31|(216<<16), NULL, NULL, OperandInfo24 }, // Inst #230 = FDIVR32m 00377 { "FDIVR64m", 4, 0, 0, 0|31|(220<<16), NULL, NULL, OperandInfo24 }, // Inst #231 = FDIVR64m 00378 { "FDIVRPrST0", 1, 0, 0, 0|2|(9<<7)|(240<<16), NULL, NULL, OperandInfo55 }, // Inst #232 = FDIVRPrST0 00379 { "FDIVRST0r", 1, 0, 0, 0|2|(3<<7)|(248<<16), NULL, NULL, OperandInfo55 }, // Inst #233 = FDIVRST0r 00380 { "FDIVRrST0", 1, 0, 0, 0|2|(7<<7)|(240<<16), NULL, NULL, OperandInfo55 }, // Inst #234 = FDIVRrST0 00381 { "FDIVST0r", 1, 0, 0, 0|2|(3<<7)|(240<<16), NULL, NULL, OperandInfo55 }, // Inst #235 = FDIVST0r 00382 { "FDIVrST0", 1, 0, 0, 0|2|(7<<7)|(248<<16), NULL, NULL, OperandInfo55 }, // Inst #236 = FDIVrST0 00383 { "FIADD16m", 4, 0, 0, 0|24|(222<<16), NULL, NULL, OperandInfo24 }, // Inst #237 = FIADD16m 00384 { "FIADD32m", 4, 0, 0, 0|24|(218<<16), NULL, NULL, OperandInfo24 }, // Inst #238 = FIADD32m 00385 { "FIDIV16m", 4, 0, 0, 0|30|(222<<16), NULL, NULL, OperandInfo24 }, // Inst #239 = FIDIV16m 00386 { "FIDIV32m", 4, 0, 0, 0|30|(218<<16), NULL, NULL, OperandInfo24 }, // Inst #240 = FIDIV32m 00387 { "FIDIVR16m", 4, 0, 0, 0|31|(222<<16), NULL, NULL, OperandInfo24 }, // Inst #241 = FIDIVR16m 00388 { "FIDIVR32m", 4, 0, 0, 0|31|(218<<16), NULL, NULL, OperandInfo24 }, // Inst #242 = FIDIVR32m 00389 { "FILD16m", 4, 0, 0, 0|24|(223<<16), NULL, NULL, OperandInfo24 }, // Inst #243 = FILD16m 00390 { "FILD32m", 4, 0, 0, 0|24|(219<<16), NULL, NULL, OperandInfo24 }, // Inst #244 = FILD32m 00391 { "FILD64m", 4, 0, 0, 0|29|(223<<16), NULL, NULL, OperandInfo24 }, // Inst #245 = FILD64m 00392 { "FIMUL16m", 4, 0, 0, 0|25|(222<<16), NULL, NULL, OperandInfo24 }, // Inst #246 = FIMUL16m 00393 { "FIMUL32m", 4, 0, 0, 0|25|(218<<16), NULL, NULL, OperandInfo24 }, // Inst #247 = FIMUL32m 00394 { "FIST16m", 4, 0, 0, 0|26|(223<<16), NULL, NULL, OperandInfo24 }, // Inst #248 = FIST16m 00395 { "FIST32m", 4, 0, 0, 0|26|(219<<16), NULL, NULL, OperandInfo24 }, // Inst #249 = FIST32m 00396 { "FISTP16m", 4, 0, 0, 0|27|(223<<16), NULL, NULL, OperandInfo24 }, // Inst #250 = FISTP16m 00397 { "FISTP32m", 4, 0, 0, 0|27|(219<<16), NULL, NULL, OperandInfo24 }, // Inst #251 = FISTP32m 00398 { "FISTP64m", 4, 0, 0, 0|31|(223<<16), NULL, NULL, OperandInfo24 }, // Inst #252 = FISTP64m 00399 { "FISTTP16m", 4, 0, 0, 0|25|(223<<16), NULL, NULL, OperandInfo24 }, // Inst #253 = FISTTP16m 00400 { "FISTTP32m", 4, 0, 0, 0|25|(219<<16), NULL, NULL, OperandInfo24 }, // Inst #254 = FISTTP32m 00401 { "FISTTP64m", 4, 0, 0, 0|25|(221<<16), NULL, NULL, OperandInfo24 }, // Inst #255 = FISTTP64m 00402 { "FISUB16m", 4, 0, 0, 0|28|(222<<16), NULL, NULL, OperandInfo24 }, // Inst #256 = FISUB16m 00403 { "FISUB32m", 4, 0, 0, 0|28|(218<<16), NULL, NULL, OperandInfo24 }, // Inst #257 = FISUB32m 00404 { "FISUBR16m", 4, 0, 0, 0|29|(222<<16), NULL, NULL, OperandInfo24 }, // Inst #258 = FISUBR16m 00405 { "FISUBR32m", 4, 0, 0, 0|29|(218<<16), NULL, NULL, OperandInfo24 }, // Inst #259 = FISUBR32m 00406 { "FLD0", 0, 0, 0, 0|1|(4<<7)|(238<<16), NULL, NULL, 0 }, // Inst #260 = FLD0 00407 { "FLD1", 0, 0, 0, 0|1|(4<<7)|(232<<16), NULL, NULL, 0 }, // Inst #261 = FLD1 00408 { "FLD32m", 4, 0, 0, 0|24|(217<<16), NULL, NULL, OperandInfo24 }, // Inst #262 = FLD32m 00409 { "FLD64m", 4, 0, 0, 0|24|(221<<16), NULL, NULL, OperandInfo24 }, // Inst #263 = FLD64m 00410 { "FLDCW16m", 4, 0, 0, 0|29|(217<<16), NULL, NULL, OperandInfo24 }, // Inst #264 = FLDCW16m 00411 { "FLDrr", 1, 0, 0, 0|2|(4<<7)|(192<<16), NULL, NULL, OperandInfo55 }, // Inst #265 = FLDrr 00412 { "FMUL32m", 4, 0, 0, 0|25|(216<<16), NULL, NULL, OperandInfo24 }, // Inst #266 = FMUL32m 00413 { "FMUL64m", 4, 0, 0, 0|25|(220<<16), NULL, NULL, OperandInfo24 }, // Inst #267 = FMUL64m 00414 { "FMULPrST0", 1, 0, 0, 0|2|(9<<7)|(200<<16), NULL, NULL, OperandInfo55 }, // Inst #268 = FMULPrST0 00415 { "FMULST0r", 1, 0, 0, 0|2|(3<<7)|(200<<16), NULL, NULL, OperandInfo55 }, // Inst #269 = FMULST0r 00416 { "FMULrST0", 1, 0, 0, 0|2|(7<<7)|(200<<16), NULL, NULL, OperandInfo55 }, // Inst #270 = FMULrST0 00417 { "FNSTCW16m", 4, 0, 0, 0|31|(217<<16), NULL, NULL, OperandInfo24 }, // Inst #271 = FNSTCW16m 00418 { "FNSTSW8r", 0, 0, 0, 0|1|(10<<7)|(224<<16), NULL, ImplicitList3, 0 }, // Inst #272 = FNSTSW8r 00419 { "FP_REG_KILL", 0, 0, 0|M_TERMINATOR_FLAG, 0, NULL, ImplicitList7, 0 }, // Inst #273 = FP_REG_KILL 00420 { "FP_TO_INT16_IN_MEM", 5, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo56 }, // Inst #274 = FP_TO_INT16_IN_MEM 00421 { "FP_TO_INT32_IN_MEM", 5, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo56 }, // Inst #275 = FP_TO_INT32_IN_MEM 00422 { "FP_TO_INT64_IN_MEM", 5, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo56 }, // Inst #276 = FP_TO_INT64_IN_MEM 00423 { "FSIN", 0, 0, 0, 0|1|(4<<7)|(254<<16), NULL, NULL, 0 }, // Inst #277 = FSIN 00424 { "FSQRT", 0, 0, 0, 0|1|(4<<7)|(250<<16), NULL, NULL, 0 }, // Inst #278 = FSQRT 00425 { "FST32m", 4, 0, 0, 0|26|(217<<16), NULL, NULL, OperandInfo24 }, // Inst #279 = FST32m 00426 { "FST64m", 4, 0, 0, 0|26|(221<<16), NULL, NULL, OperandInfo24 }, // Inst #280 = FST64m 00427 { "FSTP32m", 4, 0, 0, 0|27|(217<<16), NULL, NULL, OperandInfo24 }, // Inst #281 = FSTP32m 00428 { "FSTP64m", 4, 0, 0, 0|27|(221<<16), NULL, NULL, OperandInfo24 }, // Inst #282 = FSTP64m 00429 { "FSTPrr", 1, 0, 0, 0|2|(8<<7)|(216<<16), NULL, NULL, OperandInfo55 }, // Inst #283 = FSTPrr 00430 { "FSTrr", 1, 0, 0, 0|2|(8<<7)|(208<<16), NULL, NULL, OperandInfo55 }, // Inst #284 = FSTrr 00431 { "FSUB32m", 4, 0, 0, 0|28|(216<<16), NULL, NULL, OperandInfo24 }, // Inst #285 = FSUB32m 00432 { "FSUB64m", 4, 0, 0, 0|28|(220<<16), NULL, NULL, OperandInfo24 }, // Inst #286 = FSUB64m 00433 { "FSUBPrST0", 1, 0, 0, 0|2|(9<<7)|(232<<16), NULL, NULL, OperandInfo55 }, // Inst #287 = FSUBPrST0 00434 { "FSUBR32m", 4, 0, 0, 0|29|(216<<16), NULL, NULL, OperandInfo24 }, // Inst #288 = FSUBR32m 00435 { "FSUBR64m", 4, 0, 0, 0|29|(220<<16), NULL, NULL, OperandInfo24 }, // Inst #289 = FSUBR64m 00436 { "FSUBRPrST0", 1, 0, 0, 0|2|(9<<7)|(224<<16), NULL, NULL, OperandInfo55 }, // Inst #290 = FSUBRPrST0 00437 { "FSUBRST0r", 1, 0, 0, 0|2|(3<<7)|(232<<16), NULL, NULL, OperandInfo55 }, // Inst #291 = FSUBRST0r 00438 { "FSUBRrST0", 1, 0, 0, 0|2|(7<<7)|(224<<16), NULL, NULL, OperandInfo55 }, // Inst #292 = FSUBRrST0 00439 { "FSUBST0r", 1, 0, 0, 0|2|(3<<7)|(224<<16), NULL, NULL, OperandInfo55 }, // Inst #293 = FSUBST0r 00440 { "FSUBrST0", 1, 0, 0, 0|2|(7<<7)|(232<<16), NULL, NULL, OperandInfo55 }, // Inst #294 = FSUBrST0 00441 { "FTST", 0, 0, 0, 0|1|(4<<7)|(228<<16), NULL, NULL, 0 }, // Inst #295 = FTST 00442 { "FUCOMIPr", 1, 0, 0, 0|2|(10<<7)|(232<<16), ImplicitList8, NULL, OperandInfo55 }, // Inst #296 = FUCOMIPr 00443 { "FUCOMIr", 1, 0, 0, 0|2|(6<<7)|(232<<16), ImplicitList8, NULL, OperandInfo55 }, // Inst #297 = FUCOMIr 00444 { "FUCOMPPr", 0, 0, 0, 0|1|(5<<7)|(233<<16), ImplicitList8, NULL, 0 }, // Inst #298 = FUCOMPPr 00445 { "FUCOMPr", 1, 0, 0, 0|2|(8<<7)|(232<<16), ImplicitList8, NULL, OperandInfo55 }, // Inst #299 = FUCOMPr 00446 { "FUCOMr", 1, 0, 0, 0|2|(8<<7)|(224<<16), ImplicitList8, NULL, OperandInfo55 }, // Inst #300 = FUCOMr 00447 { "FXCH", 1, 0, 0, 0|2|(4<<7)|(200<<16), NULL, NULL, OperandInfo55 }, // Inst #301 = FXCH 00448 { "FpABS", 2, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo57 }, // Inst #302 = FpABS 00449 { "FpADD", 3, 0, 0, 0|(4<<13), NULL, NULL, OperandInfo58 }, // Inst #303 = FpADD 00450 { "FpADD32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #304 = FpADD32m 00451 { "FpADD64m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #305 = FpADD64m 00452 { "FpCHS", 2, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo57 }, // Inst #306 = FpCHS 00453 { "FpCMOVB", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #307 = FpCMOVB 00454 { "FpCMOVBE", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #308 = FpCMOVBE 00455 { "FpCMOVE", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #309 = FpCMOVE 00456 { "FpCMOVNB", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #310 = FpCMOVNB 00457 { "FpCMOVNBE", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #311 = FpCMOVNBE 00458 { "FpCMOVNE", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #312 = FpCMOVNE 00459 { "FpCMOVNP", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #313 = FpCMOVNP 00460 { "FpCMOVP", 3, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), NULL, NULL, OperandInfo58 }, // Inst #314 = FpCMOVP 00461 { "FpCOS", 2, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo57 }, // Inst #315 = FpCOS 00462 { "FpDIV", 3, 0, 0, 0|(4<<13), NULL, NULL, OperandInfo58 }, // Inst #316 = FpDIV 00463 { "FpDIV32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #317 = FpDIV32m 00464 { "FpDIV64m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #318 = FpDIV64m 00465 { "FpDIVR32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #319 = FpDIVR32m 00466 { "FpDIVR64m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #320 = FpDIVR64m 00467 { "FpGETRESULT", 1, 0, 0, 0|(7<<13), NULL, NULL, OperandInfo60 }, // Inst #321 = FpGETRESULT 00468 { "FpIADD16m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #322 = FpIADD16m 00469 { "FpIADD32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #323 = FpIADD32m 00470 { "FpIDIV16m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #324 = FpIDIV16m 00471 { "FpIDIV32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #325 = FpIDIV32m 00472 { "FpIDIVR16m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #326 = FpIDIVR16m 00473 { "FpIDIVR32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #327 = FpIDIVR32m 00474 { "FpILD16m", 5, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo61 }, // Inst #328 = FpILD16m 00475 { "FpILD32m", 5, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo61 }, // Inst #329 = FpILD32m 00476 { "FpILD64m", 5, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo61 }, // Inst #330 = FpILD64m 00477 { "FpIMUL16m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #331 = FpIMUL16m 00478 { "FpIMUL32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #332 = FpIMUL32m 00479 { "FpIST16m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #333 = FpIST16m 00480 { "FpIST32m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #334 = FpIST32m 00481 { "FpIST64m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #335 = FpIST64m 00482 { "FpISTT16m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #336 = FpISTT16m 00483 { "FpISTT32m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #337 = FpISTT32m 00484 { "FpISTT64m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #338 = FpISTT64m 00485 { "FpISUB16m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #339 = FpISUB16m 00486 { "FpISUB32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #340 = FpISUB32m 00487 { "FpISUBR16m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #341 = FpISUBR16m 00488 { "FpISUBR32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #342 = FpISUBR32m 00489 { "FpLD0", 1, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo60 }, // Inst #343 = FpLD0 00490 { "FpLD1", 1, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo60 }, // Inst #344 = FpLD1 00491 { "FpLD32m", 5, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo61 }, // Inst #345 = FpLD32m 00492 { "FpLD64m", 5, 0, 0, 0|(1<<13), NULL, NULL, OperandInfo61 }, // Inst #346 = FpLD64m 00493 { "FpMOV", 2, 0, 0, 0|(7<<13), NULL, NULL, OperandInfo57 }, // Inst #347 = FpMOV 00494 { "FpMUL", 3, 0, 0, 0|(4<<13), NULL, NULL, OperandInfo58 }, // Inst #348 = FpMUL 00495 { "FpMUL32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #349 = FpMUL32m 00496 { "FpMUL64m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #350 = FpMUL64m 00497 { "FpSETRESULT", 1, 0, 0, 0|(7<<13), NULL, ImplicitList8, OperandInfo60 }, // Inst #351 = FpSETRESULT 00498 { "FpSIN", 2, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo57 }, // Inst #352 = FpSIN 00499 { "FpSQRT", 2, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo57 }, // Inst #353 = FpSQRT 00500 { "FpST32m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #354 = FpST32m 00501 { "FpST64m", 5, 0, 0|M_STORE_FLAG, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #355 = FpST64m 00502 { "FpSTP32m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #356 = FpSTP32m 00503 { "FpSTP64m", 5, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo56 }, // Inst #357 = FpSTP64m 00504 { "FpSUB", 3, 0, 0, 0|(4<<13), NULL, NULL, OperandInfo58 }, // Inst #358 = FpSUB 00505 { "FpSUB32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #359 = FpSUB32m 00506 { "FpSUB64m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #360 = FpSUB64m 00507 { "FpSUBR32m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #361 = FpSUBR32m 00508 { "FpSUBR64m", 6, 0, 0, 0|(3<<13), NULL, NULL, OperandInfo59 }, // Inst #362 = FpSUBR64m 00509 { "FpTST", 1, 0, 0, 0|(2<<13), NULL, NULL, OperandInfo60 }, // Inst #363 = FpTST 00510 { "FpUCOMIr", 2, 0, 0, 0|(5<<13), NULL, NULL, OperandInfo57 }, // Inst #364 = FpUCOMIr 00511 { "FpUCOMr", 2, 0, 0, 0|(5<<13), NULL, NULL, OperandInfo57 }, // Inst #365 = FpUCOMr 00512 { "FsANDNPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(85<<16), NULL, NULL, OperandInfo17 }, // Inst #366 = FsANDNPDrm 00513 { "FsANDNPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(85<<16), NULL, NULL, OperandInfo18 }, // Inst #367 = FsANDNPDrr 00514 { "FsANDNPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(85<<16), NULL, NULL, OperandInfo19 }, // Inst #368 = FsANDNPSrm 00515 { "FsANDNPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(85<<16), NULL, NULL, OperandInfo20 }, // Inst #369 = FsANDNPSrr 00516 { "FsANDPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(84<<16), NULL, NULL, OperandInfo17 }, // Inst #370 = FsANDPDrm 00517 { "FsANDPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(84<<16), NULL, NULL, OperandInfo18 }, // Inst #371 = FsANDPDrr 00518 { "FsANDPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(84<<16), NULL, NULL, OperandInfo19 }, // Inst #372 = FsANDPSrm 00519 { "FsANDPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(84<<16), NULL, NULL, OperandInfo20 }, // Inst #373 = FsANDPSrr 00520 { "FsFLD0SD", 1, 0, 0, 0|32|(1<<6)|(1<<7)|(239<<16), NULL, NULL, OperandInfo62 }, // Inst #374 = FsFLD0SD 00521 { "FsFLD0SS", 1, 0, 0, 0|32|(1<<6)|(1<<7)|(239<<16), NULL, NULL, OperandInfo63 }, // Inst #375 = FsFLD0SS 00522 { "FsMOVAPDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(40<<16), NULL, NULL, OperandInfo46 }, // Inst #376 = FsMOVAPDrm 00523 { "FsMOVAPDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(40<<16), NULL, NULL, OperandInfo64 }, // Inst #377 = FsMOVAPDrr 00524 { "FsMOVAPSrm", 5, 0, 0, 0|6|(1<<7)|(40<<16), NULL, NULL, OperandInfo44 }, // Inst #378 = FsMOVAPSrm 00525 { "FsMOVAPSrr", 2, 0, 0, 0|5|(1<<7)|(40<<16), NULL, NULL, OperandInfo65 }, // Inst #379 = FsMOVAPSrr 00526 { "FsORPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(86<<16), NULL, NULL, OperandInfo17 }, // Inst #380 = FsORPDrm 00527 { "FsORPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(86<<16), NULL, NULL, OperandInfo18 }, // Inst #381 = FsORPDrr 00528 { "FsORPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(86<<16), NULL, NULL, OperandInfo19 }, // Inst #382 = FsORPSrm 00529 { "FsORPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(86<<16), NULL, NULL, OperandInfo20 }, // Inst #383 = FsORPSrr 00530 { "FsXORPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(87<<16), NULL, NULL, OperandInfo17 }, // Inst #384 = FsXORPDrm 00531 { "FsXORPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(87<<16), NULL, NULL, OperandInfo18 }, // Inst #385 = FsXORPDrr 00532 { "FsXORPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(87<<16), NULL, NULL, OperandInfo19 }, // Inst #386 = FsXORPSrm 00533 { "FsXORPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(87<<16), NULL, NULL, OperandInfo20 }, // Inst #387 = FsXORPSrr 00534 { "HADDPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(124<<16), NULL, NULL, OperandInfo15 }, // Inst #388 = HADDPDrm 00535 { "HADDPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(124<<16), NULL, NULL, OperandInfo16 }, // Inst #389 = HADDPDrr 00536 { "HADDPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(124<<16), NULL, NULL, OperandInfo15 }, // Inst #390 = HADDPSrm 00537 { "HADDPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(124<<16), NULL, NULL, OperandInfo16 }, // Inst #391 = HADDPSrr 00538 { "HSUBPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(125<<16), NULL, NULL, OperandInfo15 }, // Inst #392 = HSUBPDrm 00539 { "HSUBPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(125<<16), NULL, NULL, OperandInfo16 }, // Inst #393 = HSUBPDrr 00540 { "HSUBPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(125<<16), NULL, NULL, OperandInfo15 }, // Inst #394 = HSUBPSrm 00541 { "HSUBPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(125<<16), NULL, NULL, OperandInfo16 }, // Inst #395 = HSUBPSrr 00542 { "IDIV16m", 4, 0, 0, 0|31|(1<<6)|(247<<16), ImplicitList6, ImplicitList6, OperandInfo24 }, // Inst #396 = IDIV16m 00543 { "IDIV16r", 1, 0, 0, 0|23|(1<<6)|(247<<16), ImplicitList6, ImplicitList6, OperandInfo52 }, // Inst #397 = IDIV16r 00544 { "IDIV32m", 4, 0, 0, 0|31|(247<<16), ImplicitList5, ImplicitList5, OperandInfo24 }, // Inst #398 = IDIV32m 00545 { "IDIV32r", 1, 0, 0, 0|23|(247<<16), ImplicitList5, ImplicitList5, OperandInfo25 }, // Inst #399 = IDIV32r 00546 { "IDIV8m", 4, 0, 0, 0|31|(246<<16), ImplicitList3, ImplicitList3, OperandInfo24 }, // Inst #400 = IDIV8m 00547 { "IDIV8r", 1, 0, 0, 0|23|(246<<16), ImplicitList3, ImplicitList3, OperandInfo53 }, // Inst #401 = IDIV8r 00548 { "IMPLICIT_DEF", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #402 = IMPLICIT_DEF 00549 { "IMPLICIT_DEF_FR32", 1, 0, 0, 0, NULL, NULL, OperandInfo63 }, // Inst #403 = IMPLICIT_DEF_FR32 00550 { "IMPLICIT_DEF_FR64", 1, 0, 0, 0, NULL, NULL, OperandInfo62 }, // Inst #404 = IMPLICIT_DEF_FR64 00551 { "IMPLICIT_DEF_GR16", 1, 0, 0, 0, NULL, NULL, OperandInfo52 }, // Inst #405 = IMPLICIT_DEF_GR16 00552 { "IMPLICIT_DEF_GR32", 1, 0, 0, 0, NULL, NULL, OperandInfo25 }, // Inst #406 = IMPLICIT_DEF_GR32 00553 { "IMPLICIT_DEF_GR8", 1, 0, 0, 0, NULL, NULL, OperandInfo53 }, // Inst #407 = IMPLICIT_DEF_GR8 00554 { "IMPLICIT_DEF_VR128", 1, 0, 0, 0, NULL, NULL, OperandInfo66 }, // Inst #408 = IMPLICIT_DEF_VR128 00555 { "IMPLICIT_DEF_VR64", 1, 0, 0, 0, NULL, NULL, OperandInfo67 }, // Inst #409 = IMPLICIT_DEF_VR64 00556 { "IMPLICIT_USE", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #410 = IMPLICIT_USE 00557 { "IMUL16m", 4, 0, 0, 0|29|(1<<6)|(247<<16), ImplicitList3, ImplicitList6, OperandInfo24 }, // Inst #411 = IMUL16m 00558 { "IMUL16r", 1, 0, 0, 0|21|(1<<6)|(247<<16), ImplicitList3, ImplicitList6, OperandInfo52 }, // Inst #412 = IMUL16r 00559 { "IMUL16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(175<<16), NULL, NULL, OperandInfo9 }, // Inst #413 = IMUL16rm 00560 { "IMUL16rmi", 6, 0, 0, 0|6|(1<<6)|(2<<11)|(105<<16), NULL, NULL, OperandInfo68 }, // Inst #414 = IMUL16rmi 00561 { "IMUL16rmi8", 6, 0, 0, 0|6|(1<<6)|(1<<11)|(107<<16), NULL, NULL, OperandInfo68 }, // Inst #415 = IMUL16rmi8 00562 { "IMUL16rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(175<<16), NULL, NULL, OperandInfo10 }, // Inst #416 = IMUL16rr 00563 { "IMUL16rri", 3, 0, 0, 0|5|(1<<6)|(2<<11)|(105<<16), NULL, NULL, OperandInfo8 }, // Inst #417 = IMUL16rri 00564 { "IMUL16rri8", 3, 0, 0, 0|5|(1<<6)|(1<<11)|(107<<16), NULL, NULL, OperandInfo8 }, // Inst #418 = IMUL16rri8 00565 { "IMUL32m", 4, 0, 0, 0|29|(247<<16), ImplicitList4, ImplicitList5, OperandInfo24 }, // Inst #419 = IMUL32m 00566 { "IMUL32r", 1, 0, 0, 0|21|(247<<16), ImplicitList4, ImplicitList5, OperandInfo25 }, // Inst #420 = IMUL32r 00567 { "IMUL32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(175<<16), NULL, NULL, OperandInfo5 }, // Inst #421 = IMUL32rm 00568 { "IMUL32rmi", 6, 0, 0, 0|6|(3<<11)|(105<<16), NULL, NULL, OperandInfo69 }, // Inst #422 = IMUL32rmi 00569 { "IMUL32rmi8", 6, 0, 0, 0|6|(1<<11)|(107<<16), NULL, NULL, OperandInfo69 }, // Inst #423 = IMUL32rmi8 00570 { "IMUL32rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(175<<16), NULL, NULL, OperandInfo6 }, // Inst #424 = IMUL32rr 00571 { "IMUL32rri", 3, 0, 0, 0|5|(3<<11)|(105<<16), NULL, NULL, OperandInfo4 }, // Inst #425 = IMUL32rri 00572 { "IMUL32rri8", 3, 0, 0, 0|5|(1<<11)|(107<<16), NULL, NULL, OperandInfo4 }, // Inst #426 = IMUL32rri8 00573 { "IMUL8m", 4, 0, 0, 0|29|(246<<16), ImplicitList2, ImplicitList3, OperandInfo24 }, // Inst #427 = IMUL8m 00574 { "IMUL8r", 1, 0, 0, 0|21|(246<<16), ImplicitList2, ImplicitList3, OperandInfo53 }, // Inst #428 = IMUL8r 00575 { "IN16ri", 1, 0, 0, 0|1|(1<<6)|(1<<11)|(229<<16), NULL, ImplicitList3, OperandInfo21 }, // Inst #429 = IN16ri 00576 { "IN16rr", 0, 0, 0, 0|1|(1<<6)|(237<<16), ImplicitList9, ImplicitList3, 0 }, // Inst #430 = IN16rr 00577 { "IN32ri", 1, 0, 0, 0|1|(1<<11)|(229<<16), NULL, ImplicitList4, OperandInfo21 }, // Inst #431 = IN32ri 00578 { "IN32rr", 0, 0, 0, 0|1|(237<<16), ImplicitList9, ImplicitList4, 0 }, // Inst #432 = IN32rr 00579 { "IN8ri", 1, 0, 0, 0|1|(1<<11)|(228<<16), NULL, ImplicitList2, OperandInfo21 }, // Inst #433 = IN8ri 00580 { "IN8rr", 0, 0, 0, 0|1|(236<<16), ImplicitList9, ImplicitList2, 0 }, // Inst #434 = IN8rr 00581 { "INC16m", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(255<<16), NULL, NULL, OperandInfo24 }, // Inst #435 = INC16m 00582 { "INC16r", 2, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|2|(1<<6)|(64<<16), NULL, NULL, OperandInfo31 }, // Inst #436 = INC16r 00583 { "INC32m", 4, 0, 0|M_STORE_FLAG, 0|24|(255<<16), NULL, NULL, OperandInfo24 }, // Inst #437 = INC32m 00584 { "INC32r", 2, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|2|(64<<16), NULL, NULL, OperandInfo23 }, // Inst #438 = INC32r 00585 { "INC8m", 4, 0, 0|M_STORE_FLAG, 0|24|(254<<16), NULL, NULL, OperandInfo24 }, // Inst #439 = INC8m 00586 { "INC8r", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(254<<16), NULL, NULL, OperandInfo36 }, // Inst #440 = INC8r 00587 { "Int_ADDSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(88<<16), NULL, NULL, OperandInfo15 }, // Inst #441 = Int_ADDSDrm 00588 { "Int_ADDSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(88<<16), NULL, NULL, OperandInfo16 }, // Inst #442 = Int_ADDSDrr 00589 { "Int_ADDSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(88<<16), NULL, NULL, OperandInfo15 }, // Inst #443 = Int_ADDSSrm 00590 { "Int_ADDSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(88<<16), NULL, NULL, OperandInfo16 }, // Inst #444 = Int_ADDSSrr 00591 { "Int_CMPSDrm", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(194<<16), NULL, NULL, OperandInfo37 }, // Inst #445 = Int_CMPSDrm 00592 { "Int_CMPSDrr", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(194<<16), NULL, NULL, OperandInfo28 }, // Inst #446 = Int_CMPSDrr 00593 { "Int_CMPSSrm", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(194<<16), NULL, NULL, OperandInfo37 }, // Inst #447 = Int_CMPSSrm 00594 { "Int_CMPSSrr", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(194<<16), NULL, NULL, OperandInfo28 }, // Inst #448 = Int_CMPSSrr 00595 { "Int_COMISDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(47<<16), NULL, NULL, OperandInfo42 }, // Inst #449 = Int_COMISDrm 00596 { "Int_COMISDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(47<<16), NULL, NULL, OperandInfo70 }, // Inst #450 = Int_COMISDrr 00597 { "Int_COMISSrm", 5, 0, 0, 0|6|(1<<7)|(47<<16), NULL, NULL, OperandInfo42 }, // Inst #451 = Int_COMISSrm 00598 { "Int_COMISSrr", 2, 0, 0, 0|5|(1<<7)|(47<<16), NULL, NULL, OperandInfo70 }, // Inst #452 = Int_COMISSrr 00599 { "Int_CVTDQ2PDrm", 5, 0, 0, 0|6|(12<<7)|(230<<16), NULL, NULL, OperandInfo42 }, // Inst #453 = Int_CVTDQ2PDrm 00600 { "Int_CVTDQ2PDrr", 2, 0, 0, 0|5|(12<<7)|(230<<16), NULL, NULL, OperandInfo70 }, // Inst #454 = Int_CVTDQ2PDrr 00601 { "Int_CVTDQ2PSrm", 5, 0, 0, 0|6|(1<<7)|(91<<16), NULL, NULL, OperandInfo42 }, // Inst #455 = Int_CVTDQ2PSrm 00602 { "Int_CVTDQ2PSrr", 2, 0, 0, 0|5|(1<<7)|(91<<16), NULL, NULL, OperandInfo70 }, // Inst #456 = Int_CVTDQ2PSrr 00603 { "Int_CVTPD2DQrm", 5, 0, 0, 0|6|(11<<7)|(230<<16), NULL, NULL, OperandInfo42 }, // Inst #457 = Int_CVTPD2DQrm 00604 { "Int_CVTPD2DQrr", 2, 0, 0, 0|5|(11<<7)|(230<<16), NULL, NULL, OperandInfo70 }, // Inst #458 = Int_CVTPD2DQrr 00605 { "Int_CVTPD2PSrm", 5, 0, 0, 0|5|(1<<6)|(1<<7)|(90<<16), NULL, NULL, OperandInfo42 }, // Inst #459 = Int_CVTPD2PSrm 00606 { "Int_CVTPD2PSrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(90<<16), NULL, NULL, OperandInfo70 }, // Inst #460 = Int_CVTPD2PSrr 00607 { "Int_CVTPS2DQrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(91<<16), NULL, NULL, OperandInfo42 }, // Inst #461 = Int_CVTPS2DQrm 00608 { "Int_CVTPS2DQrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(91<<16), NULL, NULL, OperandInfo70 }, // Inst #462 = Int_CVTPS2DQrr 00609 { "Int_CVTPS2PDrm", 5, 0, 0, 0|5|(1<<7)|(90<<16), NULL, NULL, OperandInfo42 }, // Inst #463 = Int_CVTPS2PDrm 00610 { "Int_CVTPS2PDrr", 2, 0, 0, 0|5|(1<<7)|(90<<16), NULL, NULL, OperandInfo70 }, // Inst #464 = Int_CVTPS2PDrr 00611 { "Int_CVTSD2SIrm", 5, 0, 0, 0|6|(11<<7)|(45<<16), NULL, NULL, OperandInfo33 }, // Inst #465 = Int_CVTSD2SIrm 00612 { "Int_CVTSD2SIrr", 2, 0, 0, 0|5|(11<<7)|(45<<16), NULL, NULL, OperandInfo71 }, // Inst #466 = Int_CVTSD2SIrr 00613 { "Int_CVTSD2SSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(90<<16), NULL, NULL, OperandInfo15 }, // Inst #467 = Int_CVTSD2SSrm 00614 { "Int_CVTSD2SSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(90<<16), NULL, NULL, OperandInfo16 }, // Inst #468 = Int_CVTSD2SSrr 00615 { "Int_CVTSI2SDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(42<<16), NULL, NULL, OperandInfo15 }, // Inst #469 = Int_CVTSI2SDrm 00616 { "Int_CVTSI2SDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(42<<16), NULL, NULL, OperandInfo72 }, // Inst #470 = Int_CVTSI2SDrr 00617 { "Int_CVTSI2SSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(42<<16), NULL, NULL, OperandInfo15 }, // Inst #471 = Int_CVTSI2SSrm 00618 { "Int_CVTSI2SSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(42<<16), NULL, NULL, OperandInfo72 }, // Inst #472 = Int_CVTSI2SSrr 00619 { "Int_CVTSS2SDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(90<<16), NULL, NULL, OperandInfo15 }, // Inst #473 = Int_CVTSS2SDrm 00620 { "Int_CVTSS2SDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(90<<16), NULL, NULL, OperandInfo16 }, // Inst #474 = Int_CVTSS2SDrr 00621 { "Int_CVTSS2SIrm", 5, 0, 0, 0|6|(12<<7)|(45<<16), NULL, NULL, OperandInfo33 }, // Inst #475 = Int_CVTSS2SIrm 00622 { "Int_CVTSS2SIrr", 2, 0, 0, 0|5|(12<<7)|(45<<16), NULL, NULL, OperandInfo71 }, // Inst #476 = Int_CVTSS2SIrr 00623 { "Int_CVTTPD2DQrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(230<<16), NULL, NULL, OperandInfo42 }, // Inst #477 = Int_CVTTPD2DQrm 00624 { "Int_CVTTPD2DQrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(230<<16), NULL, NULL, OperandInfo70 }, // Inst #478 = Int_CVTTPD2DQrr 00625 { "Int_CVTTPS2DQrm", 5, 0, 0, 0|6|(12<<7)|(91<<16), NULL, NULL, OperandInfo42 }, // Inst #479 = Int_CVTTPS2DQrm 00626 { "Int_CVTTPS2DQrr", 2, 0, 0, 0|5|(12<<7)|(91<<16), NULL, NULL, OperandInfo70 }, // Inst #480 = Int_CVTTPS2DQrr 00627 { "Int_CVTTSD2SIrm", 5, 0, 0, 0|6|(11<<7)|(44<<16), NULL, NULL, OperandInfo33 }, // Inst #481 = Int_CVTTSD2SIrm 00628 { "Int_CVTTSD2SIrr", 2, 0, 0, 0|5|(11<<7)|(44<<16), NULL, NULL, OperandInfo71 }, // Inst #482 = Int_CVTTSD2SIrr 00629 { "Int_CVTTSS2SIrm", 5, 0, 0, 0|6|(12<<7)|(44<<16), NULL, NULL, OperandInfo33 }, // Inst #483 = Int_CVTTSS2SIrm 00630 { "Int_CVTTSS2SIrr", 2, 0, 0, 0|5|(12<<7)|(44<<16), NULL, NULL, OperandInfo71 }, // Inst #484 = Int_CVTTSS2SIrr 00631 { "Int_DIVSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(94<<16), NULL, NULL, OperandInfo15 }, // Inst #485 = Int_DIVSDrm 00632 { "Int_DIVSDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(94<<16), NULL, NULL, OperandInfo16 }, // Inst #486 = Int_DIVSDrr 00633 { "Int_DIVSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(94<<16), NULL, NULL, OperandInfo15 }, // Inst #487 = Int_DIVSSrm 00634 { "Int_DIVSSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(94<<16), NULL, NULL, OperandInfo16 }, // Inst #488 = Int_DIVSSrr 00635 { "Int_MAXSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(95<<16), NULL, NULL, OperandInfo15 }, // Inst #489 = Int_MAXSDrm 00636 { "Int_MAXSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(95<<16), NULL, NULL, OperandInfo16 }, // Inst #490 = Int_MAXSDrr 00637 { "Int_MAXSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(95<<16), NULL, NULL, OperandInfo15 }, // Inst #491 = Int_MAXSSrm 00638 { "Int_MAXSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(95<<16), NULL, NULL, OperandInfo16 }, // Inst #492 = Int_MAXSSrr 00639 { "Int_MINSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(93<<16), NULL, NULL, OperandInfo15 }, // Inst #493 = Int_MINSDrm 00640 { "Int_MINSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(93<<16), NULL, NULL, OperandInfo16 }, // Inst #494 = Int_MINSDrr 00641 { "Int_MINSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(93<<16), NULL, NULL, OperandInfo15 }, // Inst #495 = Int_MINSSrm 00642 { "Int_MINSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(93<<16), NULL, NULL, OperandInfo16 }, // Inst #496 = Int_MINSSrr 00643 { "Int_MULSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(89<<16), NULL, NULL, OperandInfo15 }, // Inst #497 = Int_MULSDrm 00644 { "Int_MULSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(89<<16), NULL, NULL, OperandInfo16 }, // Inst #498 = Int_MULSDrr 00645 { "Int_MULSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(89<<16), NULL, NULL, OperandInfo15 }, // Inst #499 = Int_MULSSrm 00646 { "Int_MULSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(89<<16), NULL, NULL, OperandInfo16 }, // Inst #500 = Int_MULSSrr 00647 { "Int_RCPSSm", 5, 0, 0, 0|6|(12<<7)|(83<<16), NULL, NULL, OperandInfo42 }, // Inst #501 = Int_RCPSSm 00648 { "Int_RCPSSr", 2, 0, 0, 0|5|(12<<7)|(83<<16), NULL, NULL, OperandInfo70 }, // Inst #502 = Int_RCPSSr 00649 { "Int_RSQRTSSm", 5, 0, 0, 0|6|(12<<7)|(82<<16), NULL, NULL, OperandInfo42 }, // Inst #503 = Int_RSQRTSSm 00650 { "Int_RSQRTSSr", 2, 0, 0, 0|5|(12<<7)|(82<<16), NULL, NULL, OperandInfo70 }, // Inst #504 = Int_RSQRTSSr 00651 { "Int_SQRTSDm", 5, 0, 0, 0|6|(11<<7)|(81<<16), NULL, NULL, OperandInfo42 }, // Inst #505 = Int_SQRTSDm 00652 { "Int_SQRTSDr", 2, 0, 0, 0|5|(11<<7)|(81<<16), NULL, NULL, OperandInfo70 }, // Inst #506 = Int_SQRTSDr 00653 { "Int_SQRTSSm", 5, 0, 0, 0|6|(12<<7)|(81<<16), NULL, NULL, OperandInfo42 }, // Inst #507 = Int_SQRTSSm 00654 { "Int_SQRTSSr", 2, 0, 0, 0|5|(12<<7)|(81<<16), NULL, NULL, OperandInfo70 }, // Inst #508 = Int_SQRTSSr 00655 { "Int_SUBSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(92<<16), NULL, NULL, OperandInfo15 }, // Inst #509 = Int_SUBSDrm 00656 { "Int_SUBSDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(92<<16), NULL, NULL, OperandInfo16 }, // Inst #510 = Int_SUBSDrr 00657 { "Int_SUBSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(92<<16), NULL, NULL, OperandInfo15 }, // Inst #511 = Int_SUBSSrm 00658 { "Int_SUBSSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(92<<16), NULL, NULL, OperandInfo16 }, // Inst #512 = Int_SUBSSrr 00659 { "Int_UCOMISDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(46<<16), NULL, NULL, OperandInfo42 }, // Inst #513 = Int_UCOMISDrm 00660 { "Int_UCOMISDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(46<<16), NULL, NULL, OperandInfo70 }, // Inst #514 = Int_UCOMISDrr 00661 { "Int_UCOMISSrm", 5, 0, 0, 0|6|(1<<7)|(46<<16), NULL, NULL, OperandInfo42 }, // Inst #515 = Int_UCOMISSrm 00662 { "Int_UCOMISSrr", 2, 0, 0, 0|5|(1<<7)|(46<<16), NULL, NULL, OperandInfo70 }, // Inst #516 = Int_UCOMISSrr 00663 { "JA", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(135<<16), NULL, NULL, OperandInfo21 }, // Inst #517 = JA 00664 { "JAE", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(131<<16), NULL, NULL, OperandInfo21 }, // Inst #518 = JAE 00665 { "JB", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(130<<16), NULL, NULL, OperandInfo21 }, // Inst #519 = JB 00666 { "JBE", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(134<<16), NULL, NULL, OperandInfo21 }, // Inst #520 = JBE 00667 { "JE", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(132<<16), NULL, NULL, OperandInfo21 }, // Inst #521 = JE 00668 { "JG", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(143<<16), NULL, NULL, OperandInfo21 }, // Inst #522 = JG 00669 { "JGE", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(141<<16), NULL, NULL, OperandInfo21 }, // Inst #523 = JGE 00670 { "JL", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(140<<16), NULL, NULL, OperandInfo21 }, // Inst #524 = JL 00671 { "JLE", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(142<<16), NULL, NULL, OperandInfo21 }, // Inst #525 = JLE 00672 { "JMP", 1, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|1|(233<<16), NULL, NULL, OperandInfo21 }, // Inst #526 = JMP 00673 { "JMP32m", 4, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|28|(255<<16), NULL, NULL, OperandInfo24 }, // Inst #527 = JMP32m 00674 { "JMP32r", 1, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|20|(255<<16), NULL, NULL, OperandInfo25 }, // Inst #528 = JMP32r 00675 { "JNE", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(133<<16), NULL, NULL, OperandInfo21 }, // Inst #529 = JNE 00676 { "JNO", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(129<<16), NULL, NULL, OperandInfo21 }, // Inst #530 = JNO 00677 { "JNP", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(139<<16), NULL, NULL, OperandInfo21 }, // Inst #531 = JNP 00678 { "JNS", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(137<<16), NULL, NULL, OperandInfo21 }, // Inst #532 = JNS 00679 { "JO", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(128<<16), NULL, NULL, OperandInfo21 }, // Inst #533 = JO 00680 { "JP", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(138<<16), NULL, NULL, OperandInfo21 }, // Inst #534 = JP 00681 { "JS", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(136<<16), NULL, NULL, OperandInfo21 }, // Inst #535 = JS 00682 { "LAHF", 0, 0, 0, 0|1|(159<<16), NULL, ImplicitList10, 0 }, // Inst #536 = LAHF 00683 { "LDDQUrm", 5, 0, 0, 0|6|(11<<7)|(240<<16), NULL, NULL, OperandInfo42 }, // Inst #537 = LDDQUrm 00684 { "LDMXCSR", 4, 0, 0, 0|29|(1<<7)|(174<<16), NULL, NULL, OperandInfo24 }, // Inst #538 = LDMXCSR 00685 { "LEA16r", 5, 0, 0, 0|6|(1<<6)|(141<<16), NULL, NULL, OperandInfo30 }, // Inst #539 = LEA16r 00686 { "LEA32r", 5, 0, 0, 0|6|(141<<16), NULL, NULL, OperandInfo33 }, // Inst #540 = LEA32r 00687 { "LEAVE", 0, 0, 0, 0|1|(201<<16), ImplicitList11, ImplicitList11, 0 }, // Inst #541 = LEAVE 00688 { "LFENCE", 0, 0, 0, 0|29|(1<<7)|(174<<16), NULL, NULL, 0 }, // Inst #542 = LFENCE 00689 { "MASKMOVDQU", 2, 0, 0, 0|1|(1<<6)|(1<<7)|(247<<16), ImplicitList12, NULL, OperandInfo70 }, // Inst #543 = MASKMOVDQU 00690 { "MASKMOVQ", 2, 0, 0, 0|4|(1<<7)|(247<<16), NULL, NULL, OperandInfo73 }, // Inst #544 = MASKMOVQ 00691 { "MAXPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(95<<16), NULL, NULL, OperandInfo15 }, // Inst #545 = MAXPDrm 00692 { "MAXPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(95<<16), NULL, NULL, OperandInfo16 }, // Inst #546 = MAXPDrr 00693 { "MAXPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(95<<16), NULL, NULL, OperandInfo15 }, // Inst #547 = MAXPSrm 00694 { "MAXPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(95<<16), NULL, NULL, OperandInfo16 }, // Inst #548 = MAXPSrr 00695 { "MAXSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(95<<16), NULL, NULL, OperandInfo74 }, // Inst #549 = MAXSDrm 00696 { "MAXSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(95<<16), NULL, NULL, OperandInfo75 }, // Inst #550 = MAXSDrr 00697 { "MAXSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(95<<16), NULL, NULL, OperandInfo19 }, // Inst #551 = MAXSSrm 00698 { "MAXSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(95<<16), NULL, NULL, OperandInfo20 }, // Inst #552 = MAXSSrr 00699 { "MFENCE", 0, 0, 0, 0|30|(1<<7)|(174<<16), NULL, NULL, 0 }, // Inst #553 = MFENCE 00700 { "MINPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(93<<16), NULL, NULL, OperandInfo15 }, // Inst #554 = MINPDrm 00701 { "MINPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(93<<16), NULL, NULL, OperandInfo16 }, // Inst #555 = MINPDrr 00702 { "MINPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(93<<16), NULL, NULL, OperandInfo15 }, // Inst #556 = MINPSrm 00703 { "MINPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(93<<16), NULL, NULL, OperandInfo16 }, // Inst #557 = MINPSrr 00704 { "MINSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(93<<16), NULL, NULL, OperandInfo74 }, // Inst #558 = MINSDrm 00705 { "MINSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(93<<16), NULL, NULL, OperandInfo75 }, // Inst #559 = MINSDrr 00706 { "MINSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(93<<16), NULL, NULL, OperandInfo19 }, // Inst #560 = MINSSrm 00707 { "MINSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(93<<16), NULL, NULL, OperandInfo20 }, // Inst #561 = MINSSrr 00708 { "MONITOR", 0, 0, 0, 0|1|(1<<7)|(200<<16), NULL, NULL, 0 }, // Inst #562 = MONITOR 00709 { "MOV16_mr", 5, 0, 0, 0|4|(1<<6)|(137<<16), NULL, NULL, OperandInfo76 }, // Inst #563 = MOV16_mr 00710 { "MOV16_rm", 5, 0, 0, 0|6|(1<<6)|(139<<16), NULL, NULL, OperandInfo77 }, // Inst #564 = MOV16_rm 00711 { "MOV16_rr", 2, 0, 0, 0|3|(1<<6)|(137<<16), NULL, NULL, OperandInfo78 }, // Inst #565 = MOV16_rr 00712 { "MOV16mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(2<<11)|(199<<16), NULL, NULL, OperandInfo2 }, // Inst #566 = MOV16mi 00713 { "MOV16mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(137<<16), NULL, NULL, OperandInfo7 }, // Inst #567 = MOV16mr 00714 { "MOV16r0", 1, 0, 0, 0|32|(1<<6)|(49<<16), NULL, NULL, OperandInfo52 }, // Inst #568 = MOV16r0 00715 { "MOV16ri", 2, 0, 0, 0|2|(1<<6)|(2<<11)|(184<<16), NULL, NULL, OperandInfo29 }, // Inst #569 = MOV16ri 00716 { "MOV16rm", 5, 0, 0, 0|6|(1<<6)|(139<<16), NULL, NULL, OperandInfo30 }, // Inst #570 = MOV16rm 00717 { "MOV16rr", 2, 0, 0, 0|3|(1<<6)|(137<<16), NULL, NULL, OperandInfo31 }, // Inst #571 = MOV16rr 00718 { "MOV16to16_", 2, 0, 0, 0|3|(1<<6)|(137<<16), NULL, NULL, OperandInfo79 }, // Inst #572 = MOV16to16_ 00719 { "MOV32_mr", 5, 0, 0, 0|4|(137<<16), NULL, NULL, OperandInfo80 }, // Inst #573 = MOV32_mr 00720 { "MOV32_rm", 5, 0, 0, 0|6|(139<<16), NULL, NULL, OperandInfo81 }, // Inst #574 = MOV32_rm 00721 { "MOV32_rr", 2, 0, 0, 0|3|(137<<16), NULL, NULL, OperandInfo82 }, // Inst #575 = MOV32_rr 00722 { "MOV32mi", 5, 0, 0|M_STORE_FLAG, 0|24|(3<<11)|(199<<16), NULL, NULL, OperandInfo2 }, // Inst #576 = MOV32mi 00723 { "MOV32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(137<<16), NULL, NULL, OperandInfo3 }, // Inst #577 = MOV32mr 00724 { "MOV32r0", 1, 0, 0, 0|32|(49<<16), NULL, NULL, OperandInfo25 }, // Inst #578 = MOV32r0 00725 { "MOV32ri", 2, 0, 0, 0|2|(3<<11)|(184<<16), NULL, NULL, OperandInfo32 }, // Inst #579 = MOV32ri 00726 { "MOV32rm", 5, 0, 0, 0|6|(139<<16), NULL, NULL, OperandInfo33 }, // Inst #580 = MOV32rm 00727 { "MOV32rr", 2, 0, 0, 0|3|(137<<16), NULL, NULL, OperandInfo23 }, // Inst #581 = MOV32rr 00728 { "MOV32to32_", 2, 0, 0, 0|3|(137<<16), NULL, NULL, OperandInfo83 }, // Inst #582 = MOV32to32_ 00729 { "MOV8mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<11)|(198<<16), NULL, NULL, OperandInfo2 }, // Inst #583 = MOV8mi 00730 { "MOV8mr", 5, 0, 0|M_STORE_FLAG, 0|4|(136<<16), NULL, NULL, OperandInfo11 }, // Inst #584 = MOV8mr 00731 { "MOV8r0", 1, 0, 0, 0|32|(48<<16), NULL, NULL, OperandInfo53 }, // Inst #585 = MOV8r0 00732 { "MOV8ri", 2, 0, 0, 0|2|(1<<11)|(176<<16), NULL, NULL, OperandInfo34 }, // Inst #586 = MOV8ri 00733 { "MOV8rm", 5, 0, 0, 0|6|(138<<16), NULL, NULL, OperandInfo35 }, // Inst #587 = MOV8rm 00734 { "MOV8rr", 2, 0, 0, 0|3|(136<<16), NULL, NULL, OperandInfo36 }, // Inst #588 = MOV8rr 00735 { "MOVAPDmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(41<<16), NULL, NULL, OperandInfo84 }, // Inst #589 = MOVAPDmr 00736 { "MOVAPDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(40<<16), NULL, NULL, OperandInfo42 }, // Inst #590 = MOVAPDrm 00737 { "MOVAPDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(40<<16), NULL, NULL, OperandInfo70 }, // Inst #591 = MOVAPDrr 00738 { "MOVAPSmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(41<<16), NULL, NULL, OperandInfo84 }, // Inst #592 = MOVAPSmr 00739 { "MOVAPSrm", 5, 0, 0, 0|6|(1<<7)|(40<<16), NULL, NULL, OperandInfo42 }, // Inst #593 = MOVAPSrm 00740 { "MOVAPSrr", 2, 0, 0, 0|5|(1<<7)|(40<<16), NULL, NULL, OperandInfo70 }, // Inst #594 = MOVAPSrr 00741 { "MOVD64mr", 5, 0, 0, 0|4|(1<<7)|(126<<16), NULL, NULL, OperandInfo85 }, // Inst #595 = MOVD64mr 00742 { "MOVD64rm", 5, 0, 0, 0|6|(1<<7)|(110<<16), NULL, NULL, OperandInfo40 }, // Inst #596 = MOVD64rm 00743 { "MOVD64rr", 2, 0, 0, 0|5|(1<<7)|(110<<16), NULL, NULL, OperandInfo86 }, // Inst #597 = MOVD64rr 00744 { "MOVDDUPrm", 5, 0, 0, 0|6|(11<<7)|(18<<16), NULL, NULL, OperandInfo42 }, // Inst #598 = MOVDDUPrm 00745 { "MOVDDUPrr", 2, 0, 0, 0|5|(11<<7)|(18<<16), NULL, NULL, OperandInfo70 }, // Inst #599 = MOVDDUPrr 00746 { "MOVDI2PDIrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(110<<16), NULL, NULL, OperandInfo42 }, // Inst #600 = MOVDI2PDIrm 00747 { "MOVDI2PDIrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(110<<16), NULL, NULL, OperandInfo87 }, // Inst #601 = MOVDI2PDIrr 00748 { "MOVDQAmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(127<<16), NULL, NULL, OperandInfo84 }, // Inst #602 = MOVDQAmr 00749 { "MOVDQArm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(111<<16), NULL, NULL, OperandInfo42 }, // Inst #603 = MOVDQArm 00750 { "MOVDQArr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(111<<16), NULL, NULL, OperandInfo70 }, // Inst #604 = MOVDQArr 00751 { "MOVDQUmr", 5, 0, 0, 0|4|(12<<7)|(127<<16), NULL, NULL, OperandInfo84 }, // Inst #605 = MOVDQUmr 00752 { "MOVDQUrm", 5, 0, 0, 0|6|(12<<7)|(111<<16), NULL, NULL, OperandInfo42 }, // Inst #606 = MOVDQUrm 00753 { "MOVHLPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(18<<16), NULL, NULL, OperandInfo16 }, // Inst #607 = MOVHLPSrr 00754 { "MOVHPDmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(23<<16), NULL, NULL, OperandInfo84 }, // Inst #608 = MOVHPDmr 00755 { "MOVHPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(22<<16), NULL, NULL, OperandInfo15 }, // Inst #609 = MOVHPDrm 00756 { "MOVHPSmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(23<<16), NULL, NULL, OperandInfo84 }, // Inst #610 = MOVHPSmr 00757 { "MOVHPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(22<<16), NULL, NULL, OperandInfo15 }, // Inst #611 = MOVHPSrm 00758 { "MOVLHPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(22<<16), NULL, NULL, OperandInfo16 }, // Inst #612 = MOVLHPSrr 00759 { "MOVLPDmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(19<<16), NULL, NULL, OperandInfo84 }, // Inst #613 = MOVLPDmr 00760 { "MOVLPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(18<<16), NULL, NULL, OperandInfo15 }, // Inst #614 = MOVLPDrm 00761 { "MOVLPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(16<<16), NULL, NULL, OperandInfo16 }, // Inst #615 = MOVLPDrr 00762 { "MOVLPSmr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(19<<16), NULL, NULL, OperandInfo84 }, // Inst #616 = MOVLPSmr 00763 { "MOVLPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(18<<16), NULL, NULL, OperandInfo15 }, // Inst #617 = MOVLPSrm 00764 { "MOVLPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(16<<16), NULL, NULL, OperandInfo16 }, // Inst #618 = MOVLPSrr 00765 { "MOVLQ128mr", 5, 0, 0, 0|4|(1<<6)|(1<<7)|(214<<16), NULL, NULL, OperandInfo84 }, // Inst #619 = MOVLQ128mr 00766 { "MOVLSD2PDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(16<<16), NULL, NULL, OperandInfo88 }, // Inst #620 = MOVLSD2PDrr 00767 { "MOVLSS2PSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(16<<16), NULL, NULL, OperandInfo89 }, // Inst #621 = MOVLSS2PSrr 00768 { "MOVMSKPDrr", 2, 0, 0, 0|5|(1<<7)|(80<<16), NULL, NULL, OperandInfo71 }, // Inst #622 = MOVMSKPDrr 00769 { "MOVMSKPSrr", 2, 0, 0, 0|5|(1<<7)|(80<<16), NULL, NULL, OperandInfo71 }, // Inst #623 = MOVMSKPSrr 00770 { "MOVNTDQmr", 5, 0, 0, 0|4|(1<<6)|(1<<7)|(231<<16), NULL, NULL, OperandInfo84 }, // Inst #624 = MOVNTDQmr 00771 { "MOVNTImr", 5, 0, 0, 0|4|(1<<7)|(195<<16), NULL, NULL, OperandInfo3 }, // Inst #625 = MOVNTImr 00772 { "MOVNTPDmr", 5, 0, 0, 0|4|(1<<6)|(1<<7)|(43<<16), NULL, NULL, OperandInfo84 }, // Inst #626 = MOVNTPDmr 00773 { "MOVNTPSmr", 5, 0, 0, 0|4|(1<<7)|(43<<16), NULL, NULL, OperandInfo84 }, // Inst #627 = MOVNTPSmr 00774 { "MOVNTQ", 5, 0, 0, 0|4|(1<<7)|(231<<16), NULL, NULL, OperandInfo85 }, // Inst #628 = MOVNTQ 00775 { "MOVPD2SDmr", 5, 0, 0|M_STORE_FLAG, 0|4|(11<<7)|(17<<16), NULL, NULL, OperandInfo84 }, // Inst #629 = MOVPD2SDmr 00776 { "MOVPD2SDrr", 2, 0, 0, 0|5|(11<<7)|(16<<16), NULL, NULL, OperandInfo90 }, // Inst #630 = MOVPD2SDrr 00777 { "MOVPDI2DImr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(126<<16), NULL, NULL, OperandInfo84 }, // Inst #631 = MOVPDI2DImr 00778 { "MOVPDI2DIrr", 2, 0, 0, 0|3|(1<<6)|(1<<7)|(126<<16), NULL, NULL, OperandInfo71 }, // Inst #632 = MOVPDI2DIrr 00779 { "MOVPS2SSmr", 5, 0, 0|M_STORE_FLAG, 0|4|(12<<7)|(17<<16), NULL, NULL, OperandInfo84 }, // Inst #633 = MOVPS2SSmr 00780 { "MOVPS2SSrr", 2, 0, 0, 0|5|(12<<7)|(16<<16), NULL, NULL, OperandInfo91 }, // Inst #634 = MOVPS2SSrr 00781 { "MOVQ64mr", 5, 0, 0, 0|4|(1<<7)|(127<<16), NULL, NULL, OperandInfo85 }, // Inst #635 = MOVQ64mr 00782 { "MOVQ64rm", 5, 0, 0, 0|6|(1<<7)|(111<<16), NULL, NULL, OperandInfo40 }, // Inst #636 = MOVQ64rm 00783 { "MOVQ64rr", 2, 0, 0, 0|5|(1<<7)|(111<<16), NULL, NULL, OperandInfo73 }, // Inst #637 = MOVQ64rr 00784 { "MOVQI2PQIrm", 5, 0, 0, 0|6|(12<<7)|(126<<16), NULL, NULL, OperandInfo42 }, // Inst #638 = MOVQI2PQIrm 00785 { "MOVQI2PQIrr", 2, 0, 0, 0|5|(12<<7)|(126<<16), NULL, NULL, OperandInfo43 }, // Inst #639 = MOVQI2PQIrr 00786 { "MOVSD2PDrm", 5, 0, 0, 0|6|(11<<7)|(16<<16), NULL, NULL, OperandInfo42 }, // Inst #640 = MOVSD2PDrm 00787 { "MOVSD2PDrr", 2, 0, 0, 0|5|(11<<7)|(16<<16), NULL, NULL, OperandInfo92 }, // Inst #641 = MOVSD2PDrr 00788 { "MOVSDmr", 5, 0, 0|M_STORE_FLAG, 0|4|(11<<7)|(17<<16), NULL, NULL, OperandInfo93 }, // Inst #642 = MOVSDmr 00789 { "MOVSDrm", 5, 0, 0, 0|6|(11<<7)|(16<<16), NULL, NULL, OperandInfo46 }, // Inst #643 = MOVSDrm 00790 { "MOVSDrr", 2, 0, 0, 0|5|(11<<7)|(16<<16), NULL, NULL, OperandInfo64 }, // Inst #644 = MOVSDrr 00791 { "MOVSHDUPrm", 5, 0, 0, 0|6|(12<<7)|(22<<16), NULL, NULL, OperandInfo42 }, // Inst #645 = MOVSHDUPrm 00792 { "MOVSHDUPrr", 2, 0, 0, 0|5|(12<<7)|(22<<16), NULL, NULL, OperandInfo70 }, // Inst #646 = MOVSHDUPrr 00793 { "MOVSLDUPrm", 5, 0, 0, 0|6|(12<<7)|(18<<16), NULL, NULL, OperandInfo42 }, // Inst #647 = MOVSLDUPrm 00794 { "MOVSLDUPrr", 2, 0, 0, 0|5|(12<<7)|(18<<16), NULL, NULL, OperandInfo70 }, // Inst #648 = MOVSLDUPrr 00795 { "MOVSS2PSrm", 5, 0, 0, 0|6|(12<<7)|(16<<16), NULL, NULL, OperandInfo42 }, // Inst #649 = MOVSS2PSrm 00796 { "MOVSS2PSrr", 2, 0, 0, 0|5|(12<<7)|(16<<16), NULL, NULL, OperandInfo94 }, // Inst #650 = MOVSS2PSrr 00797 { "MOVSSmr", 5, 0, 0|M_STORE_FLAG, 0|4|(12<<7)|(17<<16), NULL, NULL, OperandInfo95 }, // Inst #651 = MOVSSmr 00798 { "MOVSSrm", 5, 0, 0, 0|6|(12<<7)|(16<<16), NULL, NULL, OperandInfo44 }, // Inst #652 = MOVSSrm 00799 { "MOVSSrr", 2, 0, 0, 0|5|(12<<7)|(16<<16), NULL, NULL, OperandInfo65 }, // Inst #653 = MOVSSrr 00800 { "MOVSX16rm8", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(190<<16), NULL, NULL, OperandInfo30 }, // Inst #654 = MOVSX16rm8 00801 { "MOVSX16rr8", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(190<<16), NULL, NULL, OperandInfo96 }, // Inst #655 = MOVSX16rr8 00802 { "MOVSX32rm16", 5, 0, 0, 0|6|(1<<7)|(191<<16), NULL, NULL, OperandInfo33 }, // Inst #656 = MOVSX32rm16 00803 { "MOVSX32rm8", 5, 0, 0, 0|6|(1<<7)|(190<<16), NULL, NULL, OperandInfo33 }, // Inst #657 = MOVSX32rm8 00804 { "MOVSX32rr16", 2, 0, 0, 0|5|(1<<7)|(191<<16), NULL, NULL, OperandInfo97 }, // Inst #658 = MOVSX32rr16 00805 { "MOVSX32rr8", 2, 0, 0, 0|5|(1<<7)|(190<<16), NULL, NULL, OperandInfo98 }, // Inst #659 = MOVSX32rr8 00806 { "MOVUPDmr", 5, 0, 0, 0|4|(1<<6)|(1<<7)|(17<<16), NULL, NULL, OperandInfo84 }, // Inst #660 = MOVUPDmr 00807 { "MOVUPDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(16<<16), NULL, NULL, OperandInfo42 }, // Inst #661 = MOVUPDrm 00808 { "MOVUPDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(16<<16), NULL, NULL, OperandInfo70 }, // Inst #662 = MOVUPDrr 00809 { "MOVUPSmr", 5, 0, 0, 0|4|(1<<7)|(17<<16), NULL, NULL, OperandInfo84 }, // Inst #663 = MOVUPSmr 00810 { "MOVUPSrm", 5, 0, 0, 0|6|(1<<7)|(16<<16), NULL, NULL, OperandInfo42 }, // Inst #664 = MOVUPSrm 00811 { "MOVUPSrr", 2, 0, 0, 0|5|(1<<7)|(16<<16), NULL, NULL, OperandInfo70 }, // Inst #665 = MOVUPSrr 00812 { "MOVZDI2PDIrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(110<<16), NULL, NULL, OperandInfo42 }, // Inst #666 = MOVZDI2PDIrm 00813 { "MOVZDI2PDIrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(110<<16), NULL, NULL, OperandInfo87 }, // Inst #667 = MOVZDI2PDIrr 00814 { "MOVZQI2PQIrm", 5, 0, 0, 0|6|(12<<7)|(126<<16), NULL, NULL, OperandInfo42 }, // Inst #668 = MOVZQI2PQIrm 00815 { "MOVZQI2PQIrr", 2, 0, 0, 0|5|(12<<7)|(126<<16), NULL, NULL, OperandInfo70 }, // Inst #669 = MOVZQI2PQIrr 00816 { "MOVZSD2PDrm", 5, 0, 0, 0|6|(11<<7)|(16<<16), NULL, NULL, OperandInfo42 }, // Inst #670 = MOVZSD2PDrm 00817 { "MOVZSS2PSrm", 5, 0, 0, 0|6|(12<<7)|(16<<16), NULL, NULL, OperandInfo42 }, // Inst #671 = MOVZSS2PSrm 00818 { "MOVZX16rm8", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(182<<16), NULL, NULL, OperandInfo30 }, // Inst #672 = MOVZX16rm8 00819 { "MOVZX16rr8", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(182<<16), NULL, NULL, OperandInfo96 }, // Inst #673 = MOVZX16rr8 00820 { "MOVZX32rm16", 5, 0, 0, 0|6|(1<<7)|(183<<16), NULL, NULL, OperandInfo33 }, // Inst #674 = MOVZX32rm16 00821 { "MOVZX32rm8", 5, 0, 0, 0|6|(1<<7)|(182<<16), NULL, NULL, OperandInfo33 }, // Inst #675 = MOVZX32rm8 00822 { "MOVZX32rr16", 2, 0, 0, 0|5|(1<<7)|(183<<16), NULL, NULL, OperandInfo97 }, // Inst #676 = MOVZX32rr16 00823 { "MOVZX32rr8", 2, 0, 0, 0|5|(1<<7)|(182<<16), NULL, NULL, OperandInfo98 }, // Inst #677 = MOVZX32rr8 00824 { "MUL16m", 4, 0, 0, 0|28|(1<<6)|(247<<16), ImplicitList3, ImplicitList6, OperandInfo24 }, // Inst #678 = MUL16m 00825 { "MUL16r", 1, 0, 0, 0|20|(1<<6)|(247<<16), ImplicitList3, ImplicitList6, OperandInfo52 }, // Inst #679 = MUL16r 00826 { "MUL32m", 4, 0, 0, 0|28|(247<<16), ImplicitList4, ImplicitList5, OperandInfo24 }, // Inst #680 = MUL32m 00827 { "MUL32r", 1, 0, 0, 0|20|(247<<16), ImplicitList4, ImplicitList5, OperandInfo25 }, // Inst #681 = MUL32r 00828 { "MUL8m", 4, 0, 0, 0|28|(246<<16), ImplicitList2, ImplicitList3, OperandInfo24 }, // Inst #682 = MUL8m 00829 { "MUL8r", 1, 0, 0, 0|20|(246<<16), ImplicitList2, ImplicitList3, OperandInfo53 }, // Inst #683 = MUL8r 00830 { "MULPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(89<<16), NULL, NULL, OperandInfo15 }, // Inst #684 = MULPDrm 00831 { "MULPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(89<<16), NULL, NULL, OperandInfo16 }, // Inst #685 = MULPDrr 00832 { "MULPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(89<<16), NULL, NULL, OperandInfo15 }, // Inst #686 = MULPSrm 00833 { "MULPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(89<<16), NULL, NULL, OperandInfo16 }, // Inst #687 = MULPSrr 00834 { "MULSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(89<<16), NULL, NULL, OperandInfo17 }, // Inst #688 = MULSDrm 00835 { "MULSDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(89<<16), NULL, NULL, OperandInfo18 }, // Inst #689 = MULSDrr 00836 { "MULSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(89<<16), NULL, NULL, OperandInfo19 }, // Inst #690 = MULSSrm 00837 { "MULSSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(89<<16), NULL, NULL, OperandInfo20 }, // Inst #691 = MULSSrr 00838 { "MWAIT", 0, 0, 0, 0|1|(1<<7)|(201<<16), NULL, NULL, 0 }, // Inst #692 = MWAIT 00839 { "MovePCtoStack", 1, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #693 = MovePCtoStack 00840 { "NEG16m", 4, 0, 0|M_STORE_FLAG, 0|27|(1<<6)|(247<<16), NULL, NULL, OperandInfo24 }, // Inst #694 = NEG16m 00841 { "NEG16r", 2, 0, 0|M_2_ADDR_FLAG, 0|19|(1<<6)|(247<<16), NULL, NULL, OperandInfo31 }, // Inst #695 = NEG16r 00842 { "NEG32m", 4, 0, 0|M_STORE_FLAG, 0|27|(247<<16), NULL, NULL, OperandInfo24 }, // Inst #696 = NEG32m 00843 { "NEG32r", 2, 0, 0|M_2_ADDR_FLAG, 0|19|(247<<16), NULL, NULL, OperandInfo23 }, // Inst #697 = NEG32r 00844 { "NEG8m", 4, 0, 0|M_STORE_FLAG, 0|27|(246<<16), NULL, NULL, OperandInfo24 }, // Inst #698 = NEG8m 00845 { "NEG8r", 2, 0, 0|M_2_ADDR_FLAG, 0|19|(246<<16), NULL, NULL, OperandInfo36 }, // Inst #699 = NEG8r 00846 { "NOOP", 0, 0, 0, 0|1|(144<<16), NULL, NULL, 0 }, // Inst #700 = NOOP 00847 { "NOT16m", 4, 0, 0|M_STORE_FLAG, 0|26|(1<<6)|(247<<16), NULL, NULL, OperandInfo24 }, // Inst #701 = NOT16m 00848 { "NOT16r", 2, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<6)|(247<<16), NULL, NULL, OperandInfo31 }, // Inst #702 = NOT16r 00849 { "NOT32m", 4, 0, 0|M_STORE_FLAG, 0|26|(247<<16), NULL, NULL, OperandInfo24 }, // Inst #703 = NOT32m 00850 { "NOT32r", 2, 0, 0|M_2_ADDR_FLAG, 0|18|(247<<16), NULL, NULL, OperandInfo23 }, // Inst #704 = NOT32r 00851 { "NOT8m", 4, 0, 0|M_STORE_FLAG, 0|26|(246<<16), NULL, NULL, OperandInfo24 }, // Inst #705 = NOT8m 00852 { "NOT8r", 2, 0, 0|M_2_ADDR_FLAG, 0|18|(246<<16), NULL, NULL, OperandInfo36 }, // Inst #706 = NOT8r 00853 { "OR16mi", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #707 = OR16mi 00854 { "OR16mi8", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #708 = OR16mi8 00855 { "OR16mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(9<<16), NULL, NULL, OperandInfo7 }, // Inst #709 = OR16mr 00856 { "OR16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo8 }, // Inst #710 = OR16ri 00857 { "OR16ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo8 }, // Inst #711 = OR16ri8 00858 { "OR16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(11<<16), NULL, NULL, OperandInfo9 }, // Inst #712 = OR16rm 00859 { "OR16rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(9<<16), NULL, NULL, OperandInfo10 }, // Inst #713 = OR16rr 00860 { "OR32mi", 5, 0, 0|M_STORE_FLAG, 0|25|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #714 = OR32mi 00861 { "OR32mi8", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #715 = OR32mi8 00862 { "OR32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(9<<16), NULL, NULL, OperandInfo3 }, // Inst #716 = OR32mr 00863 { "OR32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #717 = OR32ri 00864 { "OR32ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #718 = OR32ri8 00865 { "OR32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<16), NULL, NULL, OperandInfo5 }, // Inst #719 = OR32rm 00866 { "OR32rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(9<<16), NULL, NULL, OperandInfo6 }, // Inst #720 = OR32rr 00867 { "OR8mi", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #721 = OR8mi 00868 { "OR8mr", 5, 0, 0|M_STORE_FLAG, 0|4|(8<<16), NULL, NULL, OperandInfo11 }, // Inst #722 = OR8mr 00869 { "OR8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(128<<16), NULL, NULL, OperandInfo12 }, // Inst #723 = OR8ri 00870 { "OR8rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(10<<16), NULL, NULL, OperandInfo13 }, // Inst #724 = OR8rm 00871 { "OR8rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(8<<16), NULL, NULL, OperandInfo14 }, // Inst #725 = OR8rr 00872 { "ORPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(86<<16), NULL, NULL, OperandInfo15 }, // Inst #726 = ORPDrm 00873 { "ORPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(86<<16), NULL, NULL, OperandInfo16 }, // Inst #727 = ORPDrr 00874 { "ORPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(86<<16), NULL, NULL, OperandInfo15 }, // Inst #728 = ORPSrm 00875 { "ORPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(86<<16), NULL, NULL, OperandInfo16 }, // Inst #729 = ORPSrr 00876 { "OUT16ir", 1, 0, 0, 0|1|(1<<6)|(1<<11)|(231<<16), ImplicitList3, NULL, OperandInfo21 }, // Inst #730 = OUT16ir 00877 { "OUT16rr", 0, 0, 0, 0|1|(1<<6)|(239<<16), ImplicitList13, NULL, 0 }, // Inst #731 = OUT16rr 00878 { "OUT32ir", 1, 0, 0, 0|1|(1<<11)|(231<<16), ImplicitList4, NULL, OperandInfo21 }, // Inst #732 = OUT32ir 00879 { "OUT32rr", 0, 0, 0, 0|1|(239<<16), ImplicitList14, NULL, 0 }, // Inst #733 = OUT32rr 00880 { "OUT8ir", 1, 0, 0, 0|1|(1<<11)|(230<<16), ImplicitList2, NULL, OperandInfo21 }, // Inst #734 = OUT8ir 00881 { "OUT8rr", 0, 0, 0, 0|1|(238<<16), ImplicitList15, NULL, 0 }, // Inst #735 = OUT8rr 00882 { "PACKSSDWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(107<<16), NULL, NULL, OperandInfo15 }, // Inst #736 = PACKSSDWrm 00883 { "PACKSSDWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(107<<16), NULL, NULL, OperandInfo16 }, // Inst #737 = PACKSSDWrr 00884 { "PACKSSWBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(99<<16), NULL, NULL, OperandInfo15 }, // Inst #738 = PACKSSWBrm 00885 { "PACKSSWBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(99<<16), NULL, NULL, OperandInfo16 }, // Inst #739 = PACKSSWBrr 00886 { "PACKUSWBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(103<<16), NULL, NULL, OperandInfo15 }, // Inst #740 = PACKUSWBrm 00887 { "PACKUSWBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(103<<16), NULL, NULL, OperandInfo16 }, // Inst #741 = PACKUSWBrr 00888 { "PADDBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(252<<16), NULL, NULL, OperandInfo15 }, // Inst #742 = PADDBrm 00889 { "PADDBrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(252<<16), NULL, NULL, OperandInfo16 }, // Inst #743 = PADDBrr 00890 { "PADDDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(254<<16), NULL, NULL, OperandInfo15 }, // Inst #744 = PADDDrm 00891 { "PADDDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(254<<16), NULL, NULL, OperandInfo16 }, // Inst #745 = PADDDrr 00892 { "PADDQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(212<<16), NULL, NULL, OperandInfo15 }, // Inst #746 = PADDQrm 00893 { "PADDQrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(212<<16), NULL, NULL, OperandInfo16 }, // Inst #747 = PADDQrr 00894 { "PADDSBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(236<<16), NULL, NULL, OperandInfo15 }, // Inst #748 = PADDSBrm 00895 { "PADDSBrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(236<<16), NULL, NULL, OperandInfo16 }, // Inst #749 = PADDSBrr 00896 { "PADDSWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(237<<16), NULL, NULL, OperandInfo15 }, // Inst #750 = PADDSWrm 00897 { "PADDSWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(237<<16), NULL, NULL, OperandInfo16 }, // Inst #751 = PADDSWrr 00898 { "PADDUSBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(220<<16), NULL, NULL, OperandInfo15 }, // Inst #752 = PADDUSBrm 00899 { "PADDUSBrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(220<<16), NULL, NULL, OperandInfo16 }, // Inst #753 = PADDUSBrr 00900 { "PADDUSWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(221<<16), NULL, NULL, OperandInfo15 }, // Inst #754 = PADDUSWrm 00901 { "PADDUSWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(221<<16), NULL, NULL, OperandInfo16 }, // Inst #755 = PADDUSWrr 00902 { "PADDWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(253<<16), NULL, NULL, OperandInfo15 }, // Inst #756 = PADDWrm 00903 { "PADDWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(253<<16), NULL, NULL, OperandInfo16 }, // Inst #757 = PADDWrr 00904 { "PANDNrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(223<<16), NULL, NULL, OperandInfo15 }, // Inst #758 = PANDNrm 00905 { "PANDNrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(223<<16), NULL, NULL, OperandInfo16 }, // Inst #759 = PANDNrr 00906 { "PANDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(219<<16), NULL, NULL, OperandInfo15 }, // Inst #760 = PANDrm 00907 { "PANDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(219<<16), NULL, NULL, OperandInfo16 }, // Inst #761 = PANDrr 00908 { "PAVGBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(224<<16), NULL, NULL, OperandInfo15 }, // Inst #762 = PAVGBrm 00909 { "PAVGBrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(224<<16), NULL, NULL, OperandInfo16 }, // Inst #763 = PAVGBrr 00910 { "PAVGWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(227<<16), NULL, NULL, OperandInfo15 }, // Inst #764 = PAVGWrm 00911 { "PAVGWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(227<<16), NULL, NULL, OperandInfo16 }, // Inst #765 = PAVGWrr 00912 { "PCMPEQBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(116<<16), NULL, NULL, OperandInfo15 }, // Inst #766 = PCMPEQBrm 00913 { "PCMPEQBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(116<<16), NULL, NULL, OperandInfo16 }, // Inst #767 = PCMPEQBrr 00914 { "PCMPEQDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(118<<16), NULL, NULL, OperandInfo15 }, // Inst #768 = PCMPEQDrm 00915 { "PCMPEQDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(118<<16), NULL, NULL, OperandInfo16 }, // Inst #769 = PCMPEQDrr 00916 { "PCMPEQWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(117<<16), NULL, NULL, OperandInfo15 }, // Inst #770 = PCMPEQWrm 00917 { "PCMPEQWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(117<<16), NULL, NULL, OperandInfo16 }, // Inst #771 = PCMPEQWrr 00918 { "PCMPGTBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(100<<16), NULL, NULL, OperandInfo15 }, // Inst #772 = PCMPGTBrm 00919 { "PCMPGTBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(100<<16), NULL, NULL, OperandInfo16 }, // Inst #773 = PCMPGTBrr 00920 { "PCMPGTDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(102<<16), NULL, NULL, OperandInfo15 }, // Inst #774 = PCMPGTDrm 00921 { "PCMPGTDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(102<<16), NULL, NULL, OperandInfo16 }, // Inst #775 = PCMPGTDrr 00922 { "PCMPGTWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(101<<16), NULL, NULL, OperandInfo15 }, // Inst #776 = PCMPGTWrm 00923 { "PCMPGTWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(101<<16), NULL, NULL, OperandInfo16 }, // Inst #777 = PCMPGTWrr 00924 { "PEXTRWri", 3, 0, 0, 0|5|(1<<6)|(1<<7)|(1<<11)|(197<<16), NULL, NULL, OperandInfo99 }, // Inst #778 = PEXTRWri 00925 { "PINSRWrmi", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(196<<16), NULL, NULL, OperandInfo37 }, // Inst #779 = PINSRWrmi 00926 { "PINSRWrri", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(196<<16), NULL, NULL, OperandInfo100 }, // Inst #780 = PINSRWrri 00927 { "PMADDWDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(245<<16), NULL, NULL, OperandInfo15 }, // Inst #781 = PMADDWDrm 00928 { "PMADDWDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(245<<16), NULL, NULL, OperandInfo16 }, // Inst #782 = PMADDWDrr 00929 { "PMAXSWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(238<<16), NULL, NULL, OperandInfo15 }, // Inst #783 = PMAXSWrm 00930 { "PMAXSWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(238<<16), NULL, NULL, OperandInfo16 }, // Inst #784 = PMAXSWrr 00931 { "PMAXUBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(222<<16), NULL, NULL, OperandInfo15 }, // Inst #785 = PMAXUBrm 00932 { "PMAXUBrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(222<<16), NULL, NULL, OperandInfo16 }, // Inst #786 = PMAXUBrr 00933 { "PMINSWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(234<<16), NULL, NULL, OperandInfo15 }, // Inst #787 = PMINSWrm 00934 { "PMINSWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(234<<16), NULL, NULL, OperandInfo16 }, // Inst #788 = PMINSWrr 00935 { "PMINUBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(218<<16), NULL, NULL, OperandInfo15 }, // Inst #789 = PMINUBrm 00936 { "PMINUBrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(218<<16), NULL, NULL, OperandInfo16 }, // Inst #790 = PMINUBrr 00937 { "PMOVMSKBrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(215<<16), NULL, NULL, OperandInfo71 }, // Inst #791 = PMOVMSKBrr 00938 { "PMULHUWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(228<<16), NULL, NULL, OperandInfo15 }, // Inst #792 = PMULHUWrm 00939 { "PMULHUWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(228<<16), NULL, NULL, OperandInfo16 }, // Inst #793 = PMULHUWrr 00940 { "PMULHWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(229<<16), NULL, NULL, OperandInfo15 }, // Inst #794 = PMULHWrm 00941 { "PMULHWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(229<<16), NULL, NULL, OperandInfo16 }, // Inst #795 = PMULHWrr 00942 { "PMULLWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(213<<16), NULL, NULL, OperandInfo15 }, // Inst #796 = PMULLWrm 00943 { "PMULLWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(213<<16), NULL, NULL, OperandInfo16 }, // Inst #797 = PMULLWrr 00944 { "PMULUDQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(244<<16), NULL, NULL, OperandInfo15 }, // Inst #798 = PMULUDQrm 00945 { "PMULUDQrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(244<<16), NULL, NULL, OperandInfo16 }, // Inst #799 = PMULUDQrr 00946 { "POP32r", 1, 0, 0, 0|2|(88<<16), ImplicitList16, ImplicitList16, OperandInfo25 }, // Inst #800 = POP32r 00947 { "PORrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(235<<16), NULL, NULL, OperandInfo15 }, // Inst #801 = PORrm 00948 { "PORrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(235<<16), NULL, NULL, OperandInfo16 }, // Inst #802 = PORrr 00949 { "PREFETCHT0", 4, 0, 0, 0|25|(1<<7)|(24<<16), NULL, NULL, OperandInfo24 }, // Inst #803 = PREFETCHT0 00950 { "PREFETCHT1", 4, 0, 0, 0|26|(1<<7)|(24<<16), NULL, NULL, OperandInfo24 }, // Inst #804 = PREFETCHT1 00951 { "PREFETCHT2", 4, 0, 0, 0|27|(1<<7)|(24<<16), NULL, NULL, OperandInfo24 }, // Inst #805 = PREFETCHT2 00952 { "PREFETCHTNTA", 4, 0, 0, 0|24|(1<<7)|(24<<16), NULL, NULL, OperandInfo24 }, // Inst #806 = PREFETCHTNTA 00953 { "PSADBWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(224<<16), NULL, NULL, OperandInfo15 }, // Inst #807 = PSADBWrm 00954 { "PSADBWrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(224<<16), NULL, NULL, OperandInfo16 }, // Inst #808 = PSADBWrr 00955 { "PSHUFDmi", 6, 0, 0, 0|6|(1<<6)|(1<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo101 }, // Inst #809 = PSHUFDmi 00956 { "PSHUFDri", 3, 0, 0, 0|5|(1<<6)|(1<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo102 }, // Inst #810 = PSHUFDri 00957 { "PSHUFHWmi", 6, 0, 0, 0|6|(12<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo101 }, // Inst #811 = PSHUFHWmi 00958 { "PSHUFHWri", 3, 0, 0, 0|5|(12<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo102 }, // Inst #812 = PSHUFHWri 00959 { "PSHUFLWmi", 6, 0, 0, 0|6|(11<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo101 }, // Inst #813 = PSHUFLWmi 00960 { "PSHUFLWri", 3, 0, 0, 0|5|(11<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo102 }, // Inst #814 = PSHUFLWri 00961 { "PSHUFWmi", 6, 0, 0, 0|6|(1<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo103 }, // Inst #815 = PSHUFWmi 00962 { "PSHUFWri", 3, 0, 0, 0|5|(1<<7)|(1<<11)|(112<<16), NULL, NULL, OperandInfo104 }, // Inst #816 = PSHUFWri 00963 { "PSLLDQri", 3, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(1<<7)|(1<<11)|(115<<16), NULL, NULL, OperandInfo102 }, // Inst #817 = PSLLDQri 00964 { "PSLLDri", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(1<<7)|(1<<11)|(114<<16), NULL, NULL, OperandInfo102 }, // Inst #818 = PSLLDri 00965 { "PSLLDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(242<<16), NULL, NULL, OperandInfo15 }, // Inst #819 = PSLLDrm 00966 { "PSLLDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(242<<16), NULL, NULL, OperandInfo16 }, // Inst #820 = PSLLDrr 00967 { "PSLLQri", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(1<<7)|(1<<11)|(115<<16), NULL, NULL, OperandInfo102 }, // Inst #821 = PSLLQri 00968 { "PSLLQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(243<<16), NULL, NULL, OperandInfo15 }, // Inst #822 = PSLLQrm 00969 { "PSLLQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(243<<16), NULL, NULL, OperandInfo16 }, // Inst #823 = PSLLQrr 00970 { "PSLLWri", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(1<<7)|(1<<11)|(113<<16), NULL, NULL, OperandInfo102 }, // Inst #824 = PSLLWri 00971 { "PSLLWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(241<<16), NULL, NULL, OperandInfo15 }, // Inst #825 = PSLLWrm 00972 { "PSLLWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(241<<16), NULL, NULL, OperandInfo16 }, // Inst #826 = PSLLWrr 00973 { "PSRADri", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(1<<7)|(1<<11)|(114<<16), NULL, NULL, OperandInfo102 }, // Inst #827 = PSRADri 00974 { "PSRADrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(226<<16), NULL, NULL, OperandInfo15 }, // Inst #828 = PSRADrm 00975 { "PSRADrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(226<<16), NULL, NULL, OperandInfo16 }, // Inst #829 = PSRADrr 00976 { "PSRAWri", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(1<<7)|(1<<11)|(113<<16), NULL, NULL, OperandInfo102 }, // Inst #830 = PSRAWri 00977 { "PSRAWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(225<<16), NULL, NULL, OperandInfo15 }, // Inst #831 = PSRAWrm 00978 { "PSRAWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(225<<16), NULL, NULL, OperandInfo16 }, // Inst #832 = PSRAWrr 00979 { "PSRLDQri", 3, 0, 0|M_2_ADDR_FLAG, 0|19|(1<<6)|(1<<7)|(1<<11)|(115<<16), NULL, NULL, OperandInfo102 }, // Inst #833 = PSRLDQri 00980 { "PSRLDri", 3, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<6)|(1<<7)|(1<<11)|(114<<16), NULL, NULL, OperandInfo102 }, // Inst #834 = PSRLDri 00981 { "PSRLDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(210<<16), NULL, NULL, OperandInfo15 }, // Inst #835 = PSRLDrm 00982 { "PSRLDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(210<<16), NULL, NULL, OperandInfo16 }, // Inst #836 = PSRLDrr 00983 { "PSRLQri", 3, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<6)|(1<<7)|(1<<11)|(115<<16), NULL, NULL, OperandInfo102 }, // Inst #837 = PSRLQri 00984 { "PSRLQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(211<<16), NULL, NULL, OperandInfo15 }, // Inst #838 = PSRLQrm 00985 { "PSRLQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(211<<16), NULL, NULL, OperandInfo16 }, // Inst #839 = PSRLQrr 00986 { "PSRLWri", 3, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<6)|(1<<7)|(1<<11)|(113<<16), NULL, NULL, OperandInfo102 }, // Inst #840 = PSRLWri 00987 { "PSRLWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(209<<16), NULL, NULL, OperandInfo15 }, // Inst #841 = PSRLWrm 00988 { "PSRLWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(209<<16), NULL, NULL, OperandInfo16 }, // Inst #842 = PSRLWrr 00989 { "PSUBBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(248<<16), NULL, NULL, OperandInfo15 }, // Inst #843 = PSUBBrm 00990 { "PSUBBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(248<<16), NULL, NULL, OperandInfo16 }, // Inst #844 = PSUBBrr 00991 { "PSUBDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(250<<16), NULL, NULL, OperandInfo15 }, // Inst #845 = PSUBDrm 00992 { "PSUBDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(250<<16), NULL, NULL, OperandInfo16 }, // Inst #846 = PSUBDrr 00993 { "PSUBQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(251<<16), NULL, NULL, OperandInfo15 }, // Inst #847 = PSUBQrm 00994 { "PSUBQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(251<<16), NULL, NULL, OperandInfo16 }, // Inst #848 = PSUBQrr 00995 { "PSUBSBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(232<<16), NULL, NULL, OperandInfo15 }, // Inst #849 = PSUBSBrm 00996 { "PSUBSBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(232<<16), NULL, NULL, OperandInfo16 }, // Inst #850 = PSUBSBrr 00997 { "PSUBSWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(233<<16), NULL, NULL, OperandInfo15 }, // Inst #851 = PSUBSWrm 00998 { "PSUBSWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(233<<16), NULL, NULL, OperandInfo16 }, // Inst #852 = PSUBSWrr 00999 { "PSUBUSBrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(216<<16), NULL, NULL, OperandInfo15 }, // Inst #853 = PSUBUSBrm 01000 { "PSUBUSBrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(216<<16), NULL, NULL, OperandInfo16 }, // Inst #854 = PSUBUSBrr 01001 { "PSUBUSWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(217<<16), NULL, NULL, OperandInfo15 }, // Inst #855 = PSUBUSWrm 01002 { "PSUBUSWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(217<<16), NULL, NULL, OperandInfo16 }, // Inst #856 = PSUBUSWrr 01003 { "PSUBWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(249<<16), NULL, NULL, OperandInfo15 }, // Inst #857 = PSUBWrm 01004 { "PSUBWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(249<<16), NULL, NULL, OperandInfo16 }, // Inst #858 = PSUBWrr 01005 { "PUNPCKHBWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(104<<16), NULL, NULL, OperandInfo15 }, // Inst #859 = PUNPCKHBWrm 01006 { "PUNPCKHBWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(104<<16), NULL, NULL, OperandInfo16 }, // Inst #860 = PUNPCKHBWrr 01007 { "PUNPCKHDQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(106<<16), NULL, NULL, OperandInfo15 }, // Inst #861 = PUNPCKHDQrm 01008 { "PUNPCKHDQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(106<<16), NULL, NULL, OperandInfo16 }, // Inst #862 = PUNPCKHDQrr 01009 { "PUNPCKHQDQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(109<<16), NULL, NULL, OperandInfo15 }, // Inst #863 = PUNPCKHQDQrm 01010 { "PUNPCKHQDQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(109<<16), NULL, NULL, OperandInfo16 }, // Inst #864 = PUNPCKHQDQrr 01011 { "PUNPCKHWDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(105<<16), NULL, NULL, OperandInfo15 }, // Inst #865 = PUNPCKHWDrm 01012 { "PUNPCKHWDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(105<<16), NULL, NULL, OperandInfo16 }, // Inst #866 = PUNPCKHWDrr 01013 { "PUNPCKLBWrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(96<<16), NULL, NULL, OperandInfo15 }, // Inst #867 = PUNPCKLBWrm 01014 { "PUNPCKLBWrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(96<<16), NULL, NULL, OperandInfo16 }, // Inst #868 = PUNPCKLBWrr 01015 { "PUNPCKLDQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(98<<16), NULL, NULL, OperandInfo15 }, // Inst #869 = PUNPCKLDQrm 01016 { "PUNPCKLDQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(98<<16), NULL, NULL, OperandInfo16 }, // Inst #870 = PUNPCKLDQrr 01017 { "PUNPCKLQDQrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(108<<16), NULL, NULL, OperandInfo15 }, // Inst #871 = PUNPCKLQDQrm 01018 { "PUNPCKLQDQrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(108<<16), NULL, NULL, OperandInfo16 }, // Inst #872 = PUNPCKLQDQrr 01019 { "PUNPCKLWDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(97<<16), NULL, NULL, OperandInfo15 }, // Inst #873 = PUNPCKLWDrm 01020 { "PUNPCKLWDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(97<<16), NULL, NULL, OperandInfo16 }, // Inst #874 = PUNPCKLWDrr 01021 { "PXORrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(239<<16), NULL, NULL, OperandInfo15 }, // Inst #875 = PXORrm 01022 { "PXORrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(239<<16), NULL, NULL, OperandInfo16 }, // Inst #876 = PXORrr 01023 { "RCPPSm", 5, 0, 0, 0|6|(1<<7)|(83<<16), NULL, NULL, OperandInfo42 }, // Inst #877 = RCPPSm 01024 { "RCPPSr", 2, 0, 0, 0|5|(1<<7)|(83<<16), NULL, NULL, OperandInfo70 }, // Inst #878 = RCPPSr 01025 { "RCPSSm", 5, 0, 0, 0|6|(12<<7)|(83<<16), NULL, NULL, OperandInfo44 }, // Inst #879 = RCPSSm 01026 { "RCPSSr", 2, 0, 0, 0|5|(12<<7)|(83<<16), NULL, NULL, OperandInfo65 }, // Inst #880 = RCPSSr 01027 { "RDTSC", 0, 0, 0, 0|1|(1<<7)|(49<<16), NULL, ImplicitList5, 0 }, // Inst #881 = RDTSC 01028 { "REP_MOVSB", 0, 0, 0, 0|1|(2<<7)|(164<<16), ImplicitList17, ImplicitList17, 0 }, // Inst #882 = REP_MOVSB 01029 { "REP_MOVSD", 0, 0, 0, 0|1|(2<<7)|(165<<16), ImplicitList17, ImplicitList17, 0 }, // Inst #883 = REP_MOVSD 01030 { "REP_MOVSW", 0, 0, 0, 0|1|(1<<6)|(2<<7)|(165<<16), ImplicitList17, ImplicitList17, 0 }, // Inst #884 = REP_MOVSW 01031 { "REP_STOSB", 0, 0, 0, 0|1|(2<<7)|(170<<16), ImplicitList18, ImplicitList19, 0 }, // Inst #885 = REP_STOSB 01032 { "REP_STOSD", 0, 0, 0, 0|1|(2<<7)|(171<<16), ImplicitList20, ImplicitList19, 0 }, // Inst #886 = REP_STOSD 01033 { "REP_STOSW", 0, 0, 0, 0|1|(1<<6)|(2<<7)|(171<<16), ImplicitList21, ImplicitList19, 0 }, // Inst #887 = REP_STOSW 01034 { "RET", 0, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|1|(195<<16), NULL, NULL, 0 }, // Inst #888 = RET 01035 { "RETI", 1, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|1|(2<<11)|(194<<16), NULL, NULL, OperandInfo21 }, // Inst #889 = RETI 01036 { "ROL16m1", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #890 = ROL16m1 01037 { "ROL16mCL", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #891 = ROL16mCL 01038 { "ROL16mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #892 = ROL16mi 01039 { "ROL16r1", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<6)|(209<<16), NULL, NULL, OperandInfo31 }, // Inst #893 = ROL16r1 01040 { "ROL16rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo31 }, // Inst #894 = ROL16rCL 01041 { "ROL16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo8 }, // Inst #895 = ROL16ri 01042 { "ROL32m1", 4, 0, 0|M_STORE_FLAG, 0|24|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #896 = ROL32m1 01043 { "ROL32mCL", 4, 0, 0|M_STORE_FLAG, 0|24|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #897 = ROL32mCL 01044 { "ROL32mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #898 = ROL32mi 01045 { "ROL32r1", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(209<<16), NULL, NULL, OperandInfo23 }, // Inst #899 = ROL32r1 01046 { "ROL32rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(211<<16), ImplicitList22, NULL, OperandInfo23 }, // Inst #900 = ROL32rCL 01047 { "ROL32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(193<<16), NULL, NULL, OperandInfo4 }, // Inst #901 = ROL32ri 01048 { "ROL8m1", 4, 0, 0|M_STORE_FLAG, 0|24|(208<<16), NULL, NULL, OperandInfo24 }, // Inst #902 = ROL8m1 01049 { "ROL8mCL", 4, 0, 0|M_STORE_FLAG, 0|24|(210<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #903 = ROL8mCL 01050 { "ROL8mi", 5, 0, 0|M_STORE_FLAG, 0|24|(1<<11)|(192<<16), NULL, NULL, OperandInfo2 }, // Inst #904 = ROL8mi 01051 { "ROL8r1", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(208<<16), NULL, NULL, OperandInfo36 }, // Inst #905 = ROL8r1 01052 { "ROL8rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|16|(210<<16), ImplicitList22, NULL, OperandInfo36 }, // Inst #906 = ROL8rCL 01053 { "ROL8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(192<<16), NULL, NULL, OperandInfo12 }, // Inst #907 = ROL8ri 01054 { "ROR16m1", 4, 0, 0|M_STORE_FLAG, 0|25|(1<<6)|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #908 = ROR16m1 01055 { "ROR16mCL", 4, 0, 0|M_STORE_FLAG, 0|25|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #909 = ROR16mCL 01056 { "ROR16mi", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #910 = ROR16mi 01057 { "ROR16r1", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(209<<16), NULL, NULL, OperandInfo31 }, // Inst #911 = ROR16r1 01058 { "ROR16rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo31 }, // Inst #912 = ROR16rCL 01059 { "ROR16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo8 }, // Inst #913 = ROR16ri 01060 { "ROR32m1", 4, 0, 0|M_STORE_FLAG, 0|25|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #914 = ROR32m1 01061 { "ROR32mCL", 4, 0, 0|M_STORE_FLAG, 0|25|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #915 = ROR32mCL 01062 { "ROR32mi", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #916 = ROR32mi 01063 { "ROR32r1", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(209<<16), NULL, NULL, OperandInfo23 }, // Inst #917 = ROR32r1 01064 { "ROR32rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(211<<16), ImplicitList22, NULL, OperandInfo23 }, // Inst #918 = ROR32rCL 01065 { "ROR32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(193<<16), NULL, NULL, OperandInfo4 }, // Inst #919 = ROR32ri 01066 { "ROR8m1", 4, 0, 0|M_STORE_FLAG, 0|25|(208<<16), NULL, NULL, OperandInfo24 }, // Inst #920 = ROR8m1 01067 { "ROR8mCL", 4, 0, 0|M_STORE_FLAG, 0|25|(210<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #921 = ROR8mCL 01068 { "ROR8mi", 5, 0, 0|M_STORE_FLAG, 0|25|(1<<11)|(192<<16), NULL, NULL, OperandInfo2 }, // Inst #922 = ROR8mi 01069 { "ROR8r1", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(208<<16), NULL, NULL, OperandInfo36 }, // Inst #923 = ROR8r1 01070 { "ROR8rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|17|(210<<16), ImplicitList22, NULL, OperandInfo36 }, // Inst #924 = ROR8rCL 01071 { "ROR8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(192<<16), NULL, NULL, OperandInfo12 }, // Inst #925 = ROR8ri 01072 { "RSQRTPSm", 5, 0, 0, 0|6|(1<<7)|(82<<16), NULL, NULL, OperandInfo42 }, // Inst #926 = RSQRTPSm 01073 { "RSQRTPSr", 2, 0, 0, 0|5|(1<<7)|(82<<16), NULL, NULL, OperandInfo70 }, // Inst #927 = RSQRTPSr 01074 { "RSQRTSSm", 5, 0, 0, 0|6|(12<<7)|(82<<16), NULL, NULL, OperandInfo44 }, // Inst #928 = RSQRTSSm 01075 { "RSQRTSSr", 2, 0, 0, 0|5|(12<<7)|(82<<16), NULL, NULL, OperandInfo65 }, // Inst #929 = RSQRTSSr 01076 { "SAHF", 0, 0, 0, 0|1|(158<<16), ImplicitList10, NULL, 0 }, // Inst #930 = SAHF 01077 { "SAR16m1", 4, 0, 0|M_STORE_FLAG, 0|31|(1<<6)|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #931 = SAR16m1 01078 { "SAR16mCL", 4, 0, 0|M_STORE_FLAG, 0|31|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #932 = SAR16mCL 01079 { "SAR16mi", 5, 0, 0|M_STORE_FLAG, 0|31|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #933 = SAR16mi 01080 { "SAR16r1", 2, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(209<<16), NULL, NULL, OperandInfo31 }, // Inst #934 = SAR16r1 01081 { "SAR16rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo31 }, // Inst #935 = SAR16rCL 01082 { "SAR16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo8 }, // Inst #936 = SAR16ri 01083 { "SAR32m1", 4, 0, 0|M_STORE_FLAG, 0|31|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #937 = SAR32m1 01084 { "SAR32mCL", 4, 0, 0|M_STORE_FLAG, 0|31|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #938 = SAR32mCL 01085 { "SAR32mi", 5, 0, 0|M_STORE_FLAG, 0|31|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #939 = SAR32mi 01086 { "SAR32r1", 2, 0, 0|M_2_ADDR_FLAG, 0|23|(209<<16), NULL, NULL, OperandInfo23 }, // Inst #940 = SAR32r1 01087 { "SAR32rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|23|(211<<16), ImplicitList22, NULL, OperandInfo23 }, // Inst #941 = SAR32rCL 01088 { "SAR32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<11)|(193<<16), NULL, NULL, OperandInfo4 }, // Inst #942 = SAR32ri 01089 { "SAR8m1", 4, 0, 0|M_STORE_FLAG, 0|31|(208<<16), NULL, NULL, OperandInfo24 }, // Inst #943 = SAR8m1 01090 { "SAR8mCL", 4, 0, 0|M_STORE_FLAG, 0|31|(210<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #944 = SAR8mCL 01091 { "SAR8mi", 5, 0, 0|M_STORE_FLAG, 0|31|(1<<11)|(192<<16), NULL, NULL, OperandInfo2 }, // Inst #945 = SAR8mi 01092 { "SAR8r1", 2, 0, 0|M_2_ADDR_FLAG, 0|23|(208<<16), NULL, NULL, OperandInfo36 }, // Inst #946 = SAR8r1 01093 { "SAR8rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|23|(210<<16), ImplicitList22, NULL, OperandInfo36 }, // Inst #947 = SAR8rCL 01094 { "SAR8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<11)|(192<<16), NULL, NULL, OperandInfo12 }, // Inst #948 = SAR8ri 01095 { "SBB32mi", 5, 0, 0|M_STORE_FLAG, 0|27|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #949 = SBB32mi 01096 { "SBB32mi8", 5, 0, 0|M_STORE_FLAG, 0|27|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #950 = SBB32mi8 01097 { "SBB32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(25<<16), NULL, NULL, OperandInfo3 }, // Inst #951 = SBB32mr 01098 { "SBB32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|19|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #952 = SBB32ri 01099 { "SBB32ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|19|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #953 = SBB32ri8 01100 { "SBB32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(27<<16), NULL, NULL, OperandInfo5 }, // Inst #954 = SBB32rm 01101 { "SBB32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(25<<16), NULL, NULL, OperandInfo6 }, // Inst #955 = SBB32rr 01102 { "SBB8mi", 5, 0, 0|M_STORE_FLAG, 0|27|(3<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #956 = SBB8mi 01103 { "SETAEm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(147<<16), NULL, NULL, OperandInfo24 }, // Inst #957 = SETAEm 01104 { "SETAEr", 1, 0, 0, 0|16|(1<<7)|(147<<16), NULL, NULL, OperandInfo53 }, // Inst #958 = SETAEr 01105 { "SETAm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(151<<16), NULL, NULL, OperandInfo24 }, // Inst #959 = SETAm 01106 { "SETAr", 1, 0, 0, 0|16|(1<<7)|(151<<16), NULL, NULL, OperandInfo53 }, // Inst #960 = SETAr 01107 { "SETBEm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(150<<16), NULL, NULL, OperandInfo24 }, // Inst #961 = SETBEm 01108 { "SETBEr", 1, 0, 0, 0|16|(1<<7)|(150<<16), NULL, NULL, OperandInfo53 }, // Inst #962 = SETBEr 01109 { "SETBm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(146<<16), NULL, NULL, OperandInfo24 }, // Inst #963 = SETBm 01110 { "SETBr", 1, 0, 0, 0|16|(1<<7)|(146<<16), NULL, NULL, OperandInfo53 }, // Inst #964 = SETBr 01111 { "SETEm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(148<<16), NULL, NULL, OperandInfo24 }, // Inst #965 = SETEm 01112 { "SETEr", 1, 0, 0, 0|16|(1<<7)|(148<<16), NULL, NULL, OperandInfo53 }, // Inst #966 = SETEr 01113 { "SETGEm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(157<<16), NULL, NULL, OperandInfo24 }, // Inst #967 = SETGEm 01114 { "SETGEr", 1, 0, 0, 0|16|(1<<7)|(157<<16), NULL, NULL, OperandInfo53 }, // Inst #968 = SETGEr 01115 { "SETGm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(159<<16), NULL, NULL, OperandInfo24 }, // Inst #969 = SETGm 01116 { "SETGr", 1, 0, 0, 0|16|(1<<7)|(159<<16), NULL, NULL, OperandInfo53 }, // Inst #970 = SETGr 01117 { "SETLEm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(158<<16), NULL, NULL, OperandInfo24 }, // Inst #971 = SETLEm 01118 { "SETLEr", 1, 0, 0, 0|16|(1<<7)|(158<<16), NULL, NULL, OperandInfo53 }, // Inst #972 = SETLEr 01119 { "SETLm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(156<<16), NULL, NULL, OperandInfo24 }, // Inst #973 = SETLm 01120 { "SETLr", 1, 0, 0, 0|16|(1<<7)|(156<<16), NULL, NULL, OperandInfo53 }, // Inst #974 = SETLr 01121 { "SETNEm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(149<<16), NULL, NULL, OperandInfo24 }, // Inst #975 = SETNEm 01122 { "SETNEr", 1, 0, 0, 0|16|(1<<7)|(149<<16), NULL, NULL, OperandInfo53 }, // Inst #976 = SETNEr 01123 { "SETNPm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(155<<16), NULL, NULL, OperandInfo24 }, // Inst #977 = SETNPm 01124 { "SETNPr", 1, 0, 0, 0|16|(1<<7)|(155<<16), NULL, NULL, OperandInfo53 }, // Inst #978 = SETNPr 01125 { "SETNSm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(153<<16), NULL, NULL, OperandInfo24 }, // Inst #979 = SETNSm 01126 { "SETNSr", 1, 0, 0, 0|16|(1<<7)|(153<<16), NULL, NULL, OperandInfo53 }, // Inst #980 = SETNSr 01127 { "SETPm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(154<<16), NULL, NULL, OperandInfo24 }, // Inst #981 = SETPm 01128 { "SETPr", 1, 0, 0, 0|16|(1<<7)|(154<<16), NULL, NULL, OperandInfo53 }, // Inst #982 = SETPr 01129 { "SETSm", 4, 0, 0|M_STORE_FLAG, 0|24|(1<<7)|(152<<16), NULL, NULL, OperandInfo24 }, // Inst #983 = SETSm 01130 { "SETSr", 1, 0, 0, 0|16|(1<<7)|(152<<16), NULL, NULL, OperandInfo53 }, // Inst #984 = SETSr 01131 { "SFENCE", 0, 0, 0, 0|31|(1<<7)|(174<<16), NULL, NULL, 0 }, // Inst #985 = SFENCE 01132 { "SHL16m1", 4, 0, 0|M_STORE_FLAG, 0|28|(1<<6)|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #986 = SHL16m1 01133 { "SHL16mCL", 4, 0, 0|M_STORE_FLAG, 0|28|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #987 = SHL16mCL 01134 { "SHL16mi", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #988 = SHL16mi 01135 { "SHL16r1", 2, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(209<<16), NULL, NULL, OperandInfo31 }, // Inst #989 = SHL16r1 01136 { "SHL16rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo31 }, // Inst #990 = SHL16rCL 01137 { "SHL16ri", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|20|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo8 }, // Inst #991 = SHL16ri 01138 { "SHL32m1", 4, 0, 0|M_STORE_FLAG, 0|28|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #992 = SHL32m1 01139 { "SHL32mCL", 4, 0, 0|M_STORE_FLAG, 0|28|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #993 = SHL32mCL 01140 { "SHL32mi", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #994 = SHL32mi 01141 { "SHL32r1", 2, 0, 0|M_2_ADDR_FLAG, 0|20|(209<<16), NULL, NULL, OperandInfo23 }, // Inst #995 = SHL32r1 01142 { "SHL32rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|20|(211<<16), ImplicitList22, NULL, OperandInfo23 }, // Inst #996 = SHL32rCL 01143 { "SHL32ri", 3, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|20|(1<<11)|(193<<16), NULL, NULL, OperandInfo4 }, // Inst #997 = SHL32ri 01144 { "SHL8m1", 4, 0, 0|M_STORE_FLAG, 0|28|(208<<16), NULL, NULL, OperandInfo24 }, // Inst #998 = SHL8m1 01145 { "SHL8mCL", 4, 0, 0|M_STORE_FLAG, 0|28|(210<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #999 = SHL8mCL 01146 { "SHL8mi", 5, 0, 0|M_STORE_FLAG, 0|28|(1<<11)|(192<<16), NULL, NULL, OperandInfo2 }, // Inst #1000 = SHL8mi 01147 { "SHL8r1", 2, 0, 0|M_2_ADDR_FLAG, 0|20|(208<<16), NULL, NULL, OperandInfo36 }, // Inst #1001 = SHL8r1 01148 { "SHL8rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|20|(210<<16), ImplicitList22, NULL, OperandInfo36 }, // Inst #1002 = SHL8rCL 01149 { "SHL8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<11)|(192<<16), NULL, NULL, OperandInfo12 }, // Inst #1003 = SHL8ri 01150 { "SHLD16mrCL", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(165<<16), ImplicitList22, NULL, OperandInfo7 }, // Inst #1004 = SHLD16mrCL 01151 { "SHLD16mri8", 6, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(1<<11)|(164<<16), NULL, NULL, OperandInfo105 }, // Inst #1005 = SHLD16mri8 01152 { "SHLD16rrCL", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<6)|(1<<7)|(165<<16), ImplicitList22, NULL, OperandInfo10 }, // Inst #1006 = SHLD16rrCL 01153 { "SHLD16rri8", 4, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(1<<7)|(1<<11)|(164<<16), NULL, NULL, OperandInfo106 }, // Inst #1007 = SHLD16rri8 01154 { "SHLD32mrCL", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(165<<16), ImplicitList22, NULL, OperandInfo3 }, // Inst #1008 = SHLD32mrCL 01155 { "SHLD32mri8", 6, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(1<<11)|(164<<16), NULL, NULL, OperandInfo107 }, // Inst #1009 = SHLD32mri8 01156 { "SHLD32rrCL", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<7)|(165<<16), ImplicitList22, NULL, OperandInfo6 }, // Inst #1010 = SHLD32rrCL 01157 { "SHLD32rri8", 4, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<7)|(1<<11)|(164<<16), NULL, NULL, OperandInfo108 }, // Inst #1011 = SHLD32rri8 01158 { "SHR16m1", 4, 0, 0|M_STORE_FLAG, 0|29|(1<<6)|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #1012 = SHR16m1 01159 { "SHR16mCL", 4, 0, 0|M_STORE_FLAG, 0|29|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #1013 = SHR16mCL 01160 { "SHR16mi", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #1014 = SHR16mi 01161 { "SHR16r1", 2, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(209<<16), NULL, NULL, OperandInfo31 }, // Inst #1015 = SHR16r1 01162 { "SHR16rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(211<<16), ImplicitList22, NULL, OperandInfo31 }, // Inst #1016 = SHR16rCL 01163 { "SHR16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(1<<11)|(193<<16), NULL, NULL, OperandInfo8 }, // Inst #1017 = SHR16ri 01164 { "SHR32m1", 4, 0, 0|M_STORE_FLAG, 0|29|(209<<16), NULL, NULL, OperandInfo24 }, // Inst #1018 = SHR32m1 01165 { "SHR32mCL", 4, 0, 0|M_STORE_FLAG, 0|29|(211<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #1019 = SHR32mCL 01166 { "SHR32mi", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<11)|(193<<16), NULL, NULL, OperandInfo2 }, // Inst #1020 = SHR32mi 01167 { "SHR32r1", 2, 0, 0|M_2_ADDR_FLAG, 0|21|(209<<16), NULL, NULL, OperandInfo23 }, // Inst #1021 = SHR32r1 01168 { "SHR32rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|21|(211<<16), ImplicitList22, NULL, OperandInfo23 }, // Inst #1022 = SHR32rCL 01169 { "SHR32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(193<<16), NULL, NULL, OperandInfo4 }, // Inst #1023 = SHR32ri 01170 { "SHR8m1", 4, 0, 0|M_STORE_FLAG, 0|29|(208<<16), NULL, NULL, OperandInfo24 }, // Inst #1024 = SHR8m1 01171 { "SHR8mCL", 4, 0, 0|M_STORE_FLAG, 0|29|(210<<16), ImplicitList22, NULL, OperandInfo24 }, // Inst #1025 = SHR8mCL 01172 { "SHR8mi", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<11)|(192<<16), NULL, NULL, OperandInfo2 }, // Inst #1026 = SHR8mi 01173 { "SHR8r1", 2, 0, 0|M_2_ADDR_FLAG, 0|21|(208<<16), NULL, NULL, OperandInfo36 }, // Inst #1027 = SHR8r1 01174 { "SHR8rCL", 2, 0, 0|M_2_ADDR_FLAG, 0|21|(210<<16), ImplicitList22, NULL, OperandInfo36 }, // Inst #1028 = SHR8rCL 01175 { "SHR8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(192<<16), NULL, NULL, OperandInfo12 }, // Inst #1029 = SHR8ri 01176 { "SHRD16mrCL", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(173<<16), ImplicitList22, NULL, OperandInfo7 }, // Inst #1030 = SHRD16mrCL 01177 { "SHRD16mri8", 6, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(1<<7)|(1<<11)|(172<<16), NULL, NULL, OperandInfo105 }, // Inst #1031 = SHRD16mri8 01178 { "SHRD16rrCL", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<6)|(1<<7)|(173<<16), ImplicitList22, NULL, OperandInfo10 }, // Inst #1032 = SHRD16rrCL 01179 { "SHRD16rri8", 4, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(1<<7)|(1<<11)|(172<<16), NULL, NULL, OperandInfo106 }, // Inst #1033 = SHRD16rri8 01180 { "SHRD32mrCL", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(173<<16), ImplicitList22, NULL, OperandInfo3 }, // Inst #1034 = SHRD32mrCL 01181 { "SHRD32mri8", 6, 0, 0|M_STORE_FLAG, 0|4|(1<<7)|(1<<11)|(172<<16), NULL, NULL, OperandInfo107 }, // Inst #1035 = SHRD32mri8 01182 { "SHRD32rrCL", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<7)|(173<<16), ImplicitList22, NULL, OperandInfo6 }, // Inst #1036 = SHRD32rrCL 01183 { "SHRD32rri8", 4, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<7)|(1<<11)|(172<<16), NULL, NULL, OperandInfo108 }, // Inst #1037 = SHRD32rri8 01184 { "SHUFPDrmi", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(198<<16), NULL, NULL, OperandInfo37 }, // Inst #1038 = SHUFPDrmi 01185 { "SHUFPDrri", 4, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(198<<16), NULL, NULL, OperandInfo28 }, // Inst #1039 = SHUFPDrri 01186 { "SHUFPSrmi", 7, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(1<<11)|(198<<16), NULL, NULL, OperandInfo37 }, // Inst #1040 = SHUFPSrmi 01187 { "SHUFPSrri", 4, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|5|(1<<7)|(1<<11)|(198<<16), NULL, NULL, OperandInfo28 }, // Inst #1041 = SHUFPSrri 01188 { "SQRTPDm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(81<<16), NULL, NULL, OperandInfo42 }, // Inst #1042 = SQRTPDm 01189 { "SQRTPDr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(81<<16), NULL, NULL, OperandInfo70 }, // Inst #1043 = SQRTPDr 01190 { "SQRTPSm", 5, 0, 0, 0|6|(1<<7)|(81<<16), NULL, NULL, OperandInfo42 }, // Inst #1044 = SQRTPSm 01191 { "SQRTPSr", 2, 0, 0, 0|5|(1<<7)|(81<<16), NULL, NULL, OperandInfo70 }, // Inst #1045 = SQRTPSr 01192 { "SQRTSDm", 5, 0, 0, 0|6|(11<<7)|(81<<16), NULL, NULL, OperandInfo46 }, // Inst #1046 = SQRTSDm 01193 { "SQRTSDr", 2, 0, 0, 0|5|(11<<7)|(81<<16), NULL, NULL, OperandInfo64 }, // Inst #1047 = SQRTSDr 01194 { "SQRTSSm", 5, 0, 0, 0|6|(12<<7)|(81<<16), NULL, NULL, OperandInfo44 }, // Inst #1048 = SQRTSSm 01195 { "SQRTSSr", 2, 0, 0, 0|5|(12<<7)|(81<<16), NULL, NULL, OperandInfo65 }, // Inst #1049 = SQRTSSr 01196 { "STMXCSR", 4, 0, 0, 0|27|(1<<7)|(174<<16), NULL, NULL, OperandInfo24 }, // Inst #1050 = STMXCSR 01197 { "SUB16mi", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #1051 = SUB16mi 01198 { "SUB16mi8", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #1052 = SUB16mi8 01199 { "SUB16mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(41<<16), NULL, NULL, OperandInfo7 }, // Inst #1053 = SUB16mr 01200 { "SUB16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo8 }, // Inst #1054 = SUB16ri 01201 { "SUB16ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo8 }, // Inst #1055 = SUB16ri8 01202 { "SUB16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(43<<16), NULL, NULL, OperandInfo9 }, // Inst #1056 = SUB16rm 01203 { "SUB16rr", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<6)|(41<<16), NULL, NULL, OperandInfo10 }, // Inst #1057 = SUB16rr 01204 { "SUB32mi", 5, 0, 0|M_STORE_FLAG, 0|29|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #1058 = SUB32mi 01205 { "SUB32mi8", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #1059 = SUB32mi8 01206 { "SUB32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(41<<16), NULL, NULL, OperandInfo3 }, // Inst #1060 = SUB32mr 01207 { "SUB32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #1061 = SUB32ri 01208 { "SUB32ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #1062 = SUB32ri8 01209 { "SUB32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(43<<16), NULL, NULL, OperandInfo5 }, // Inst #1063 = SUB32rm 01210 { "SUB32rr", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(41<<16), NULL, NULL, OperandInfo6 }, // Inst #1064 = SUB32rr 01211 { "SUB8mi", 5, 0, 0|M_STORE_FLAG, 0|29|(1<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #1065 = SUB8mi 01212 { "SUB8mr", 5, 0, 0|M_STORE_FLAG, 0|4|(40<<16), NULL, NULL, OperandInfo11 }, // Inst #1066 = SUB8mr 01213 { "SUB8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(128<<16), NULL, NULL, OperandInfo12 }, // Inst #1067 = SUB8ri 01214 { "SUB8rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(42<<16), NULL, NULL, OperandInfo13 }, // Inst #1068 = SUB8rm 01215 { "SUB8rr", 3, 0, 0|M_2_ADDR_FLAG, 0|3|(40<<16), NULL, NULL, OperandInfo14 }, // Inst #1069 = SUB8rr 01216 { "SUBPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(92<<16), NULL, NULL, OperandInfo15 }, // Inst #1070 = SUBPDrm 01217 { "SUBPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(92<<16), NULL, NULL, OperandInfo16 }, // Inst #1071 = SUBPDrr 01218 { "SUBPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(92<<16), NULL, NULL, OperandInfo15 }, // Inst #1072 = SUBPSrm 01219 { "SUBPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(92<<16), NULL, NULL, OperandInfo16 }, // Inst #1073 = SUBPSrr 01220 { "SUBSDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(92<<16), NULL, NULL, OperandInfo17 }, // Inst #1074 = SUBSDrm 01221 { "SUBSDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(92<<16), NULL, NULL, OperandInfo18 }, // Inst #1075 = SUBSDrr 01222 { "SUBSSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(92<<16), NULL, NULL, OperandInfo19 }, // Inst #1076 = SUBSSrm 01223 { "SUBSSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(92<<16), NULL, NULL, OperandInfo20 }, // Inst #1077 = SUBSSrr 01224 { "TAILJMPd", 1, 0, 0|M_RET_FLAG|M_BRANCH_FLAG|M_BARRIER_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0|1|(233<<16), NULL, NULL, OperandInfo21 }, // Inst #1078 = TAILJMPd 01225 { "TAILJMPm", 4, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0|28|(255<<16), NULL, NULL, OperandInfo24 }, // Inst #1079 = TAILJMPm 01226 { "TAILJMPr", 1, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0|20|(255<<16), NULL, NULL, OperandInfo25 }, // Inst #1080 = TAILJMPr 01227 { "TEST16mi", 5, 0, 0, 0|24|(1<<6)|(2<<11)|(247<<16), NULL, NULL, OperandInfo2 }, // Inst #1081 = TEST16mi 01228 { "TEST16mr", 5, 0, 0, 0|4|(1<<6)|(133<<16), NULL, NULL, OperandInfo7 }, // Inst #1082 = TEST16mr 01229 { "TEST16ri", 2, 0, 0, 0|16|(1<<6)|(2<<11)|(247<<16), NULL, NULL, OperandInfo29 }, // Inst #1083 = TEST16ri 01230 { "TEST16rm", 5, 0, 0, 0|6|(1<<6)|(133<<16), NULL, NULL, OperandInfo30 }, // Inst #1084 = TEST16rm 01231 { "TEST16rr", 2, 0, 0|M_COMMUTABLE, 0|3|(1<<6)|(133<<16), NULL, NULL, OperandInfo31 }, // Inst #1085 = TEST16rr 01232 { "TEST32mi", 5, 0, 0, 0|24|(3<<11)|(247<<16), NULL, NULL, OperandInfo2 }, // Inst #1086 = TEST32mi 01233 { "TEST32mr", 5, 0, 0, 0|4|(133<<16), NULL, NULL, OperandInfo3 }, // Inst #1087 = TEST32mr 01234 { "TEST32ri", 2, 0, 0, 0|16|(3<<11)|(247<<16), NULL, NULL, OperandInfo32 }, // Inst #1088 = TEST32ri 01235 { "TEST32rm", 5, 0, 0, 0|6|(133<<16), NULL, NULL, OperandInfo33 }, // Inst #1089 = TEST32rm 01236 { "TEST32rr", 2, 0, 0|M_COMMUTABLE, 0|3|(133<<16), NULL, NULL, OperandInfo23 }, // Inst #1090 = TEST32rr 01237 { "TEST8mi", 5, 0, 0, 0|24|(1<<11)|(246<<16), NULL, NULL, OperandInfo2 }, // Inst #1091 = TEST8mi 01238 { "TEST8mr", 5, 0, 0, 0|4|(132<<16), NULL, NULL, OperandInfo11 }, // Inst #1092 = TEST8mr 01239 { "TEST8ri", 2, 0, 0, 0|16|(1<<11)|(246<<16), NULL, NULL, OperandInfo34 }, // Inst #1093 = TEST8ri 01240 { "TEST8rm", 5, 0, 0, 0|6|(132<<16), NULL, NULL, OperandInfo35 }, // Inst #1094 = TEST8rm 01241 { "TEST8rr", 2, 0, 0|M_COMMUTABLE, 0|3|(132<<16), NULL, NULL, OperandInfo36 }, // Inst #1095 = TEST8rr 01242 { "TRUNC_GR16_GR8", 2, 0, 0, 0|3|(136<<16), NULL, NULL, OperandInfo109 }, // Inst #1096 = TRUNC_GR16_GR8 01243 { "TRUNC_GR32_GR16", 2, 0, 0, 0|3|(137<<16), NULL, NULL, OperandInfo110 }, // Inst #1097 = TRUNC_GR32_GR16 01244 { "TRUNC_GR32_GR8", 2, 0, 0, 0|3|(136<<16), NULL, NULL, OperandInfo111 }, // Inst #1098 = TRUNC_GR32_GR8 01245 { "UCOMISDrm", 5, 0, 0, 0|6|(1<<6)|(1<<7)|(46<<16), NULL, NULL, OperandInfo46 }, // Inst #1099 = UCOMISDrm 01246 { "UCOMISDrr", 2, 0, 0, 0|5|(1<<6)|(1<<7)|(46<<16), NULL, NULL, OperandInfo64 }, // Inst #1100 = UCOMISDrr 01247 { "UCOMISSrm", 5, 0, 0, 0|6|(1<<7)|(46<<16), NULL, NULL, OperandInfo44 }, // Inst #1101 = UCOMISSrm 01248 { "UCOMISSrr", 2, 0, 0, 0|5|(1<<7)|(46<<16), NULL, NULL, OperandInfo65 }, // Inst #1102 = UCOMISSrr 01249 { "UNPCKHPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(21<<16), NULL, NULL, OperandInfo15 }, // Inst #1103 = UNPCKHPDrm 01250 { "UNPCKHPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(21<<16), NULL, NULL, OperandInfo16 }, // Inst #1104 = UNPCKHPDrr 01251 { "UNPCKHPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(21<<16), NULL, NULL, OperandInfo15 }, // Inst #1105 = UNPCKHPSrm 01252 { "UNPCKHPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(21<<16), NULL, NULL, OperandInfo16 }, // Inst #1106 = UNPCKHPSrr 01253 { "UNPCKLPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(20<<16), NULL, NULL, OperandInfo15 }, // Inst #1107 = UNPCKLPDrm 01254 { "UNPCKLPDrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(20<<16), NULL, NULL, OperandInfo16 }, // Inst #1108 = UNPCKLPDrr 01255 { "UNPCKLPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(20<<16), NULL, NULL, OperandInfo15 }, // Inst #1109 = UNPCKLPSrm 01256 { "UNPCKLPSrr", 3, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(20<<16), NULL, NULL, OperandInfo16 }, // Inst #1110 = UNPCKLPSrr 01257 { "V_SET0", 1, 0, 0, 0|32|(1<<7)|(87<<16), NULL, NULL, OperandInfo66 }, // Inst #1111 = V_SET0 01258 { "V_SETALLONES", 1, 0, 0, 0|32|(1<<6)|(1<<7)|(118<<16), NULL, NULL, OperandInfo66 }, // Inst #1112 = V_SETALLONES 01259 { "XCHG16mr", 5, 0, 0, 0|4|(1<<6)|(135<<16), NULL, NULL, OperandInfo7 }, // Inst #1113 = XCHG16mr 01260 { "XCHG16rm", 5, 0, 0, 0|6|(1<<6)|(135<<16), NULL, NULL, OperandInfo30 }, // Inst #1114 = XCHG16rm 01261 { "XCHG16rr", 2, 0, 0, 0|3|(1<<6)|(135<<16), NULL, NULL, OperandInfo31 }, // Inst #1115 = XCHG16rr 01262 { "XCHG32mr", 5, 0, 0, 0|4|(135<<16), NULL, NULL, OperandInfo3 }, // Inst #1116 = XCHG32mr 01263 { "XCHG32rm", 5, 0, 0, 0|6|(135<<16), NULL, NULL, OperandInfo33 }, // Inst #1117 = XCHG32rm 01264 { "XCHG32rr", 2, 0, 0, 0|3|(135<<16), NULL, NULL, OperandInfo23 }, // Inst #1118 = XCHG32rr 01265 { "XCHG8mr", 5, 0, 0, 0|4|(134<<16), NULL, NULL, OperandInfo11 }, // Inst #1119 = XCHG8mr 01266 { "XCHG8rm", 5, 0, 0, 0|6|(134<<16), NULL, NULL, OperandInfo35 }, // Inst #1120 = XCHG8rm 01267 { "XCHG8rr", 2, 0, 0, 0|3|(134<<16), NULL, NULL, OperandInfo36 }, // Inst #1121 = XCHG8rr 01268 { "XOR16mi", 5, 0, 0|M_STORE_FLAG, 0|30|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #1122 = XOR16mi 01269 { "XOR16mi8", 5, 0, 0|M_STORE_FLAG, 0|30|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #1123 = XOR16mi8 01270 { "XOR16mr", 5, 0, 0|M_STORE_FLAG, 0|4|(1<<6)|(49<<16), NULL, NULL, OperandInfo7 }, // Inst #1124 = XOR16mr 01271 { "XOR16ri", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(2<<11)|(129<<16), NULL, NULL, OperandInfo8 }, // Inst #1125 = XOR16ri 01272 { "XOR16ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(1<<11)|(131<<16), NULL, NULL, OperandInfo8 }, // Inst #1126 = XOR16ri8 01273 { "XOR16rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(51<<16), NULL, NULL, OperandInfo9 }, // Inst #1127 = XOR16rm 01274 { "XOR16rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(49<<16), NULL, NULL, OperandInfo10 }, // Inst #1128 = XOR16rr 01275 { "XOR32mi", 5, 0, 0|M_STORE_FLAG, 0|30|(3<<11)|(129<<16), NULL, NULL, OperandInfo2 }, // Inst #1129 = XOR32mi 01276 { "XOR32mi8", 5, 0, 0|M_STORE_FLAG, 0|30|(1<<11)|(131<<16), NULL, NULL, OperandInfo2 }, // Inst #1130 = XOR32mi8 01277 { "XOR32mr", 5, 0, 0|M_STORE_FLAG, 0|4|(49<<16), NULL, NULL, OperandInfo3 }, // Inst #1131 = XOR32mr 01278 { "XOR32ri", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(3<<11)|(129<<16), NULL, NULL, OperandInfo4 }, // Inst #1132 = XOR32ri 01279 { "XOR32ri8", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<11)|(131<<16), NULL, NULL, OperandInfo4 }, // Inst #1133 = XOR32ri8 01280 { "XOR32rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(51<<16), NULL, NULL, OperandInfo5 }, // Inst #1134 = XOR32rm 01281 { "XOR32rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(49<<16), NULL, NULL, OperandInfo6 }, // Inst #1135 = XOR32rr 01282 { "XOR8mi", 5, 0, 0|M_STORE_FLAG, 0|30|(1<<11)|(128<<16), NULL, NULL, OperandInfo2 }, // Inst #1136 = XOR8mi 01283 { "XOR8mr", 5, 0, 0|M_STORE_FLAG, 0|4|(48<<16), NULL, NULL, OperandInfo11 }, // Inst #1137 = XOR8mr 01284 { "XOR8ri", 3, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<11)|(128<<16), NULL, NULL, OperandInfo12 }, // Inst #1138 = XOR8ri 01285 { "XOR8rm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(50<<16), NULL, NULL, OperandInfo13 }, // Inst #1139 = XOR8rm 01286 { "XOR8rr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(48<<16), NULL, NULL, OperandInfo14 }, // Inst #1140 = XOR8rr 01287 { "XORPDrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(87<<16), NULL, NULL, OperandInfo15 }, // Inst #1141 = XORPDrm 01288 { "XORPDrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(87<<16), NULL, NULL, OperandInfo16 }, // Inst #1142 = XORPDrr 01289 { "XORPSrm", 6, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(87<<16), NULL, NULL, OperandInfo15 }, // Inst #1143 = XORPSrm 01290 { "XORPSrr", 3, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(87<<16), NULL, NULL, OperandInfo16 }, // Inst #1144 = XORPSrr 01291 }; 01292 } // End llvm namespace