LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // DFPRegs Register Class... 00013 static const unsigned DFPRegs[] = { 00014 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, 00015 }; 00016 00017 // FPRegs Register Class... 00018 static const unsigned FPRegs[] = { 00019 SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31, 00020 }; 00021 00022 // IntRegs Register Class... 00023 static const unsigned IntRegs[] = { 00024 SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3, SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5, SP::G6, SP::G7, 00025 }; 00026 00027 // DFPRegsVTs Register Class Value Types... 00028 static const MVT::ValueType DFPRegsVTs[] = { 00029 MVT::f64, MVT::Other 00030 }; 00031 00032 // FPRegsVTs Register Class Value Types... 00033 static const MVT::ValueType FPRegsVTs[] = { 00034 MVT::f32, MVT::Other 00035 }; 00036 00037 // IntRegsVTs Register Class Value Types... 00038 static const MVT::ValueType IntRegsVTs[] = { 00039 MVT::i32, MVT::Other 00040 }; 00041 00042 } // end anonymous namespace 00043 00044 namespace SP { // Register class instances 00045 DFPRegsClass DFPRegsRegClass; 00046 FPRegsClass FPRegsRegClass; 00047 IntRegsClass IntRegsRegClass; 00048 00049 // DFPRegs Register Class sub-classes... 00050 static const TargetRegisterClass* const DFPRegsSubclasses [] = { 00051 NULL 00052 }; 00053 00054 // FPRegs Register Class sub-classes... 00055 static const TargetRegisterClass* const FPRegsSubclasses [] = { 00056 NULL 00057 }; 00058 00059 // IntRegs Register Class sub-classes... 00060 static const TargetRegisterClass* const IntRegsSubclasses [] = { 00061 NULL 00062 }; 00063 00064 // DFPRegs Register Class super-classes... 00065 static const TargetRegisterClass* const DFPRegsSuperclasses [] = { 00066 NULL 00067 }; 00068 00069 // FPRegs Register Class super-classes... 00070 static const TargetRegisterClass* const FPRegsSuperclasses [] = { 00071 NULL 00072 }; 00073 00074 // IntRegs Register Class super-classes... 00075 static const TargetRegisterClass* const IntRegsSuperclasses [] = { 00076 NULL 00077 }; 00078 00079 00080 DFPRegsClass::DFPRegsClass() : TargetRegisterClass(DFPRegsRegClassID, DFPRegsVTs, DFPRegsSubclasses, DFPRegsSuperclasses, 8, 8, DFPRegs, DFPRegs + 16) {} 00081 00082 FPRegsClass::FPRegsClass() : TargetRegisterClass(FPRegsRegClassID, FPRegsVTs, FPRegsSubclasses, FPRegsSuperclasses, 4, 4, FPRegs, FPRegs + 32) {} 00083 00084 IntRegsClass::iterator 00085 IntRegsClass::allocation_order_end(MachineFunction &MF) const { 00086 // FIXME: These special regs should be taken out of the regclass! 00087 return end()-10 // Don't allocate special registers 00088 -1; // FIXME: G1 reserved for large imm generation by frame code. 00089 } 00090 00091 IntRegsClass::IntRegsClass() : TargetRegisterClass(IntRegsRegClassID, IntRegsVTs, IntRegsSubclasses, IntRegsSuperclasses, 4, 4, IntRegs, IntRegs + 32) {} 00092 } 00093 00094 namespace { 00095 const TargetRegisterClass* const RegisterClasses[] = { 00096 &SP::DFPRegsRegClass, 00097 &SP::FPRegsRegClass, 00098 &SP::IntRegsRegClass, 00099 }; 00100 00101 00102 // Register Alias Sets... 00103 const unsigned Empty_AliasSet[] = { 0 }; 00104 const unsigned F0_AliasSet[] = { SP::D0, 0 }; 00105 const unsigned F1_AliasSet[] = { SP::D0, 0 }; 00106 const unsigned F2_AliasSet[] = { SP::D1, 0 }; 00107 const unsigned F3_AliasSet[] = { SP::D1, 0 }; 00108 const unsigned F4_AliasSet[] = { SP::D2, 0 }; 00109 const unsigned F5_AliasSet[] = { SP::D2, 0 }; 00110 const unsigned F6_AliasSet[] = { SP::D3, 0 }; 00111 const unsigned F7_AliasSet[] = { SP::D3, 0 }; 00112 const unsigned F8_AliasSet[] = { SP::D4, 0 }; 00113 const unsigned F9_AliasSet[] = { SP::D4, 0 }; 00114 const unsigned F10_AliasSet[] = { SP::D5, 0 }; 00115 const unsigned F11_AliasSet[] = { SP::D5, 0 }; 00116 const unsigned F12_AliasSet[] = { SP::D6, 0 }; 00117 const unsigned F13_AliasSet[] = { SP::D6, 0 }; 00118 const unsigned F14_AliasSet[] = { SP::D7, 0 }; 00119 const unsigned F15_AliasSet[] = { SP::D7, 0 }; 00120 const unsigned F16_AliasSet[] = { SP::D8, 0 }; 00121 const unsigned F17_AliasSet[] = { SP::D8, 0 }; 00122 const unsigned F18_AliasSet[] = { SP::D9, 0 }; 00123 const unsigned F19_AliasSet[] = { SP::D9, 0 }; 00124 const unsigned F20_AliasSet[] = { SP::D10, 0 }; 00125 const unsigned F21_AliasSet[] = { SP::D10, 0 }; 00126 const unsigned F22_AliasSet[] = { SP::D11, 0 }; 00127 const unsigned F23_AliasSet[] = { SP::D11, 0 }; 00128 const unsigned F24_AliasSet[] = { SP::D12, 0 }; 00129 const unsigned F25_AliasSet[] = { SP::D12, 0 }; 00130 const unsigned F26_AliasSet[] = { SP::D13, 0 }; 00131 const unsigned F27_AliasSet[] = { SP::D13, 0 }; 00132 const unsigned F28_AliasSet[] = { SP::D14, 0 }; 00133 const unsigned F29_AliasSet[] = { SP::D14, 0 }; 00134 const unsigned F30_AliasSet[] = { SP::D15, 0 }; 00135 const unsigned F31_AliasSet[] = { SP::D15, 0 }; 00136 const unsigned D0_AliasSet[] = { SP::F0, SP::F1, 0 }; 00137 const unsigned D1_AliasSet[] = { SP::F2, SP::F3, 0 }; 00138 const unsigned D2_AliasSet[] = { SP::F4, SP::F5, 0 }; 00139 const unsigned D3_AliasSet[] = { SP::F6, SP::F7, 0 }; 00140 const unsigned D4_AliasSet[] = { SP::F8, SP::F9, 0 }; 00141 const unsigned D5_AliasSet[] = { SP::F10, SP::F11, 0 }; 00142 const unsigned D6_AliasSet[] = { SP::F12, SP::F13, 0 }; 00143 const unsigned D7_AliasSet[] = { SP::F14, SP::F15, 0 }; 00144 const unsigned D8_AliasSet[] = { SP::F16, SP::F17, 0 }; 00145 const unsigned D9_AliasSet[] = { SP::F18, SP::F19, 0 }; 00146 const unsigned D10_AliasSet[] = { SP::F20, SP::F21, 0 }; 00147 const unsigned D11_AliasSet[] = { SP::F22, SP::F23, 0 }; 00148 const unsigned D12_AliasSet[] = { SP::F24, SP::F25, 0 }; 00149 const unsigned D13_AliasSet[] = { SP::F26, SP::F27, 0 }; 00150 const unsigned D14_AliasSet[] = { SP::F28, SP::F29, 0 }; 00151 const unsigned D15_AliasSet[] = { SP::F30, SP::F31, 0 }; 00152 00153 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00154 { "NOREG", 0 }, 00155 { "F0", D0_AliasSet }, 00156 { "F2", D1_AliasSet }, 00157 { "F20", D10_AliasSet }, 00158 { "F22", D11_AliasSet }, 00159 { "F24", D12_AliasSet }, 00160 { "F26", D13_AliasSet }, 00161 { "F28", D14_AliasSet }, 00162 { "F30", D15_AliasSet }, 00163 { "F4", D2_AliasSet }, 00164 { "F6", D3_AliasSet }, 00165 { "F8", D4_AliasSet }, 00166 { "F10", D5_AliasSet }, 00167 { "F12", D6_AliasSet }, 00168 { "F14", D7_AliasSet }, 00169 { "F16", D8_AliasSet }, 00170 { "F18", D9_AliasSet }, 00171 { "F0", F0_AliasSet }, 00172 { "F1", F1_AliasSet }, 00173 { "F10", F10_AliasSet }, 00174 { "F11", F11_AliasSet }, 00175 { "F12", F12_AliasSet }, 00176 { "F13", F13_AliasSet }, 00177 { "F14", F14_AliasSet }, 00178 { "F15", F15_AliasSet }, 00179 { "F16", F16_AliasSet }, 00180 { "F17", F17_AliasSet }, 00181 { "F18", F18_AliasSet }, 00182 { "F19", F19_AliasSet }, 00183 { "F2", F2_AliasSet }, 00184 { "F20", F20_AliasSet }, 00185 { "F21", F21_AliasSet }, 00186 { "F22", F22_AliasSet }, 00187 { "F23", F23_AliasSet }, 00188 { "F24", F24_AliasSet }, 00189 { "F25", F25_AliasSet }, 00190 { "F26", F26_AliasSet }, 00191 { "F27", F27_AliasSet }, 00192 { "F28", F28_AliasSet }, 00193 { "F29", F29_AliasSet }, 00194 { "F3", F3_AliasSet }, 00195 { "F30", F30_AliasSet }, 00196 { "F31", F31_AliasSet }, 00197 { "F4", F4_AliasSet }, 00198 { "F5", F5_AliasSet }, 00199 { "F6", F6_AliasSet }, 00200 { "F7", F7_AliasSet }, 00201 { "F8", F8_AliasSet }, 00202 { "F9", F9_AliasSet }, 00203 { "G0", Empty_AliasSet }, 00204 { "G1", Empty_AliasSet }, 00205 { "G2", Empty_AliasSet }, 00206 { "G3", Empty_AliasSet }, 00207 { "G4", Empty_AliasSet }, 00208 { "G5", Empty_AliasSet }, 00209 { "G6", Empty_AliasSet }, 00210 { "G7", Empty_AliasSet }, 00211 { "I0", Empty_AliasSet }, 00212 { "I1", Empty_AliasSet }, 00213 { "I2", Empty_AliasSet }, 00214 { "I3", Empty_AliasSet }, 00215 { "I4", Empty_AliasSet }, 00216 { "I5", Empty_AliasSet }, 00217 { "I6", Empty_AliasSet }, 00218 { "I7", Empty_AliasSet }, 00219 { "L0", Empty_AliasSet }, 00220 { "L1", Empty_AliasSet }, 00221 { "L2", Empty_AliasSet }, 00222 { "L3", Empty_AliasSet }, 00223 { "L4", Empty_AliasSet }, 00224 { "L5", Empty_AliasSet }, 00225 { "L6", Empty_AliasSet }, 00226 { "L7", Empty_AliasSet }, 00227 { "O0", Empty_AliasSet }, 00228 { "O1", Empty_AliasSet }, 00229 { "O2", Empty_AliasSet }, 00230 { "O3", Empty_AliasSet }, 00231 { "O4", Empty_AliasSet }, 00232 { "O5", Empty_AliasSet }, 00233 { "O6", Empty_AliasSet }, 00234 { "O7", Empty_AliasSet }, 00235 }; 00236 } 00237 00238 SparcGenRegisterInfo::SparcGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00239 : MRegisterInfo(RegisterDescriptors, 81, RegisterClasses, RegisterClasses+3, 00240 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00241 00242 int SparcGenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00243 static const int DwarfRegNums[] = { -1, // NoRegister 00244 32, 34, 52, 54, 56, 58, 60, 62, 36, 38, 40, 42, 44, 46, 48, 50, 00245 32, 33, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 34, 52, 53, 54, 00246 55, 56, 57, 58, 59, 60, 61, 35, 62, 63, 36, 37, 38, 39, 40, 41, 00247 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31, 00248 16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 12, 13, 14, 15 00249 }; 00250 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00251 "RegNum exceeds number of registers"); 00252 return DwarfRegNums[RegNum]; 00253 } 00254 00255 } // End llvm namespace