LLVM API Documentation

SparcRegisterInfo.cpp

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00001 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the SPARC implementation of the MRegisterInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "Sparc.h"
00015 #include "SparcRegisterInfo.h"
00016 #include "SparcSubtarget.h"
00017 #include "llvm/CodeGen/MachineInstrBuilder.h"
00018 #include "llvm/CodeGen/MachineFunction.h"
00019 #include "llvm/CodeGen/MachineFrameInfo.h"
00020 #include "llvm/CodeGen/MachineLocation.h"
00021 #include "llvm/Type.h"
00022 #include "llvm/ADT/STLExtras.h"
00023 #include <iostream>
00024 using namespace llvm;
00025 
00026 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
00027   : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
00028     Subtarget(st) {
00029 }
00030 
00031 void SparcRegisterInfo::
00032 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00033                     unsigned SrcReg, int FI,
00034                     const TargetRegisterClass *RC) const {
00035   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
00036   if (RC == SP::IntRegsRegisterClass)
00037     BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
00038   else if (RC == SP::FPRegsRegisterClass)
00039     BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
00040   else if (RC == SP::DFPRegsRegisterClass)
00041     BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
00042   else
00043     assert(0 && "Can't store this register to stack slot");
00044 }
00045 
00046 void SparcRegisterInfo::
00047 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00048                      unsigned DestReg, int FI,
00049                      const TargetRegisterClass *RC) const {
00050   if (RC == SP::IntRegsRegisterClass)
00051     BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
00052   else if (RC == SP::FPRegsRegisterClass)
00053     BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
00054   else if (RC == SP::DFPRegsRegisterClass)
00055     BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
00056   else
00057     assert(0 && "Can't load this register from stack slot");
00058 }
00059 
00060 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
00061                                      MachineBasicBlock::iterator I,
00062                                      unsigned DestReg, unsigned SrcReg,
00063                                      const TargetRegisterClass *RC) const {
00064   if (RC == SP::IntRegsRegisterClass)
00065     BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
00066   else if (RC == SP::FPRegsRegisterClass)
00067     BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
00068   else if (RC == SP::DFPRegsRegisterClass)
00069     BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
00070             1, DestReg).addReg(SrcReg);
00071   else
00072     assert (0 && "Can't copy this register");
00073 }
00074 
00075 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
00076                                                    unsigned OpNum,
00077                                                    int FI) const {
00078   bool isFloat = false;
00079   switch (MI->getOpcode()) {
00080   case SP::ORrr:
00081     if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
00082         MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
00083       if (OpNum == 0)    // COPY -> STORE
00084         return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
00085                                    .addReg(MI->getOperand(2).getReg());
00086       else               // COPY -> LOAD
00087         return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
00088                       .addFrameIndex(FI).addImm(0);
00089     }
00090     break;
00091   case SP::FMOVS:
00092     isFloat = true;
00093     // FALLTHROUGH
00094   case SP::FMOVD:
00095     if (OpNum == 0)  // COPY -> STORE
00096       return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
00097                .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
00098     else             // COPY -> LOAD
00099       return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2, 
00100                      MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
00101     break;
00102   }
00103   return 0;
00104 }
00105 
00106 const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
00107   static const unsigned CalleeSaveRegs[] = { 0 };
00108   return CalleeSaveRegs;
00109 }
00110 
00111 const TargetRegisterClass* const*
00112 SparcRegisterInfo::getCalleeSaveRegClasses() const {
00113   static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
00114   return CalleeSaveRegClasses;
00115 }
00116 
00117 
00118 void SparcRegisterInfo::
00119 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
00120                               MachineBasicBlock::iterator I) const {
00121   MachineInstr &MI = *I;
00122   int Size = MI.getOperand(0).getImmedValue();
00123   if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
00124     Size = -Size;
00125   if (Size)
00126     BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
00127   MBB.erase(I);
00128 }
00129 
00130 void
00131 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
00132   unsigned i = 0;
00133   MachineInstr &MI = *II;
00134   while (!MI.getOperand(i).isFrameIndex()) {
00135     ++i;
00136     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
00137   }
00138 
00139   int FrameIndex = MI.getOperand(i).getFrameIndex();
00140 
00141   // Addressable stack objects are accessed using neg. offsets from %fp
00142   MachineFunction &MF = *MI.getParent()->getParent();
00143   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
00144                MI.getOperand(i+1).getImmedValue();
00145 
00146   // Replace frame index with a frame pointer reference.
00147   if (Offset >= -4096 && Offset <= 4095) {
00148     // If the offset is small enough to fit in the immediate field, directly
00149     // encode it.
00150     MI.getOperand(i).ChangeToRegister(SP::I6);
00151     MI.getOperand(i+1).ChangeToImmediate(Offset);
00152   } else {
00153     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to 
00154     // scavenge a register here instead of reserving G1 all of the time.
00155     unsigned OffHi = (unsigned)Offset >> 10U;
00156     BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
00157     // Emit G1 = G1 + I6
00158     BuildMI(*MI.getParent(), II, SP::ADDrr, 2, 
00159             SP::G1).addReg(SP::G1).addReg(SP::I6);
00160     // Insert: G1+%lo(offset) into the user.
00161     MI.getOperand(i).ChangeToRegister(SP::G1);
00162     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
00163   }
00164 }
00165 
00166 void SparcRegisterInfo::
00167 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
00168 
00169 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
00170   MachineBasicBlock &MBB = MF.front();
00171   MachineFrameInfo *MFI = MF.getFrameInfo();
00172 
00173   // Get the number of bytes to allocate from the FrameInfo
00174   int NumBytes = (int) MFI->getStackSize();
00175 
00176   // Emit the correct save instruction based on the number of bytes in
00177   // the frame. Minimum stack frame size according to V8 ABI is:
00178   //   16 words for register window spill
00179   //    1 word for address of returned aggregate-value
00180   // +  6 words for passing parameters on the stack
00181   // ----------
00182   //   23 words * 4 bytes per word = 92 bytes
00183   NumBytes += 92;
00184   // Round up to next doubleword boundary -- a double-word boundary
00185   // is required by the ABI.
00186   NumBytes = (NumBytes + 7) & ~7;
00187   NumBytes = -NumBytes;
00188   
00189   if (NumBytes >= -4096) {
00190     BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
00191             SP::O6).addImm(NumBytes).addReg(SP::O6);
00192   } else {
00193     MachineBasicBlock::iterator InsertPt = MBB.begin();
00194     // Emit this the hard way.  This clobbers G1 which we always know is 
00195     // available here.
00196     unsigned OffHi = (unsigned)NumBytes >> 10U;
00197     BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
00198     // Emit G1 = G1 + I6
00199     BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
00200       .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
00201     BuildMI(MBB, InsertPt, SP::SAVErr, 2,
00202             SP::O6).addReg(SP::O6).addReg(SP::G1);
00203   }
00204 }
00205 
00206 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
00207                                      MachineBasicBlock &MBB) const {
00208   MachineBasicBlock::iterator MBBI = prior(MBB.end());
00209   assert(MBBI->getOpcode() == SP::RETL &&
00210          "Can only put epilog before 'retl' instruction!");
00211   BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
00212 }
00213 
00214 unsigned SparcRegisterInfo::getRARegister() const {
00215   assert(0 && "What is the return address register");
00216   return 0;
00217 }
00218 
00219 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
00220   assert(0 && "What is the frame register");
00221   return SP::G1;
00222 }
00223 
00224 #include "SparcGenRegisterInfo.inc"
00225