LLVM API Documentation
00001 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the SelectionDAGISel class, which is used as the common 00011 // base class for SelectionDAG-based instruction selectors. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H 00016 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H 00017 00018 #include "llvm/Pass.h" 00019 #include "llvm/Constant.h" 00020 #include "llvm/CodeGen/SelectionDAGNodes.h" 00021 00022 namespace llvm { 00023 class SelectionDAG; 00024 class SelectionDAGLowering; 00025 class SDOperand; 00026 class SSARegMap; 00027 class MachineBasicBlock; 00028 class MachineFunction; 00029 class MachineInstr; 00030 class TargetLowering; 00031 class FunctionLoweringInfo; 00032 class HazardRecognizer; 00033 00034 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 00035 /// pattern-matching instruction selectors. 00036 class SelectionDAGISel : public FunctionPass { 00037 public: 00038 TargetLowering &TLI; 00039 SSARegMap *RegMap; 00040 SelectionDAG *CurDAG; 00041 MachineBasicBlock *BB; 00042 00043 SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {} 00044 00045 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 00046 00047 virtual bool runOnFunction(Function &Fn); 00048 00049 unsigned MakeReg(MVT::ValueType VT); 00050 00051 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {} 00052 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0; 00053 00054 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 00055 /// addressing mode, according to the specified constraint code. If this does 00056 /// not match or is not implemented, return true. The resultant operands 00057 /// (which will appear in the machine instruction) should be added to the 00058 /// OutOps vector. 00059 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, 00060 char ConstraintCode, 00061 std::vector<SDOperand> &OutOps, 00062 SelectionDAG &DAG) { 00063 return true; 00064 } 00065 00066 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer 00067 /// to use for this target when scheduling the DAG. 00068 virtual HazardRecognizer *CreateTargetHazardRecognizer(); 00069 00070 /// CaseBlock - This structure is used to communicate between SDLowering and 00071 /// SDISel for the code generation of additional basic blocks needed by multi- 00072 /// case switch statements. 00073 struct CaseBlock { 00074 CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs, 00075 MachineBasicBlock *rhs, MachineBasicBlock *me) : 00076 CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {} 00077 // CC - the condition code to use for the case block's setcc node 00078 ISD::CondCode CC; 00079 // SwitchV - the value to be switched on, 'foo' in switch(foo) 00080 Value *SwitchV; 00081 // CaseC - the constant the setcc node will compare against SwitchV 00082 Constant *CaseC; 00083 // LHSBB - the block to branch to if the setcc is true 00084 MachineBasicBlock *LHSBB; 00085 // RHSBB - the block to branch to if the setcc is false 00086 MachineBasicBlock *RHSBB; 00087 // ThisBB - the blcok into which to emit the code for the setcc and branches 00088 MachineBasicBlock *ThisBB; 00089 }; 00090 struct JumpTable { 00091 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M, 00092 MachineBasicBlock *D) : Reg(R), JTI(J), MBB(M), Default(D) {} 00093 // Reg - the virtual register containing the index of the jump table entry 00094 // to jump to. 00095 unsigned Reg; 00096 // JTI - the JumpTableIndex for this jump table in the function. 00097 unsigned JTI; 00098 // MBB - the MBB into which to emit the code for the indirect jump. 00099 MachineBasicBlock *MBB; 00100 // Default - the MBB of the default bb, which is a successor of the range 00101 // check MBB. This is when updating PHI nodes in successors. 00102 MachineBasicBlock *Default; 00103 }; 00104 00105 protected: 00106 /// Pick a safe ordering and emit instructions for each target node in the 00107 /// graph. 00108 void ScheduleAndEmitDAG(SelectionDAG &DAG); 00109 00110 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 00111 /// by tblgen. Others should not call it. 00112 void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, 00113 SelectionDAG &DAG); 00114 00115 private: 00116 SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL, 00117 Value *V, unsigned Reg); 00118 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF, 00119 FunctionLoweringInfo &FuncInfo); 00120 00121 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, 00122 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate, 00123 FunctionLoweringInfo &FuncInfo); 00124 void CodeGenAndEmitDAG(SelectionDAG &DAG); 00125 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL, 00126 std::vector<SDOperand> &UnorderedChains); 00127 00128 /// SwitchCases - Vector of CaseBlock structures used to communicate 00129 /// SwitchInst code generation information. 00130 std::vector<CaseBlock> SwitchCases; 00131 00132 /// JT - Record which holds necessary information for emitting a jump table 00133 JumpTable JT; 00134 }; 00135 00136 } 00137 00138 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */