LLVM API Documentation
00001 //===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by Andrew Lenharth and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file defines the interfaces that Alpha uses to lower LLVM code into a 00011 // selection DAG. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H 00016 #define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H 00017 00018 #include "llvm/ADT/VectorExtras.h" 00019 #include "llvm/Target/TargetLowering.h" 00020 #include "llvm/CodeGen/SelectionDAG.h" 00021 #include "Alpha.h" 00022 00023 namespace llvm { 00024 00025 namespace AlphaISD { 00026 enum NodeType { 00027 // Start the numbering where the builting ops and target ops leave off. 00028 FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END, 00029 //These corrospond to the identical Instruction 00030 ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_, 00031 00032 /// GPRelHi/GPRelLo - These represent the high and low 16-bit 00033 /// parts of a global address respectively. 00034 GPRelHi, GPRelLo, 00035 00036 /// RetLit - Literal Relocation of a Global 00037 RelLit, 00038 00039 /// GlobalBaseReg - used to restore the GOT ptr 00040 GlobalBaseReg, 00041 00042 /// GlobalRetAddr - used to restore the return address 00043 GlobalRetAddr, 00044 00045 /// CALL - Normal call. 00046 CALL, 00047 00048 /// DIVCALL - used for special library calls for div and rem 00049 DivCall, 00050 00051 /// return flag operand 00052 RET_FLAG 00053 00054 }; 00055 } 00056 00057 class AlphaTargetLowering : public TargetLowering { 00058 int VarArgsOffset; // What is the offset to the first vaarg 00059 int VarArgsBase; // What is the base FrameIndex 00060 unsigned GP; //GOT vreg 00061 unsigned RA; //Return Address 00062 bool useITOF; 00063 public: 00064 AlphaTargetLowering(TargetMachine &TM); 00065 00066 /// LowerOperation - Provide custom lowering hooks for some operations. 00067 /// 00068 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 00069 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 00070 00071 //Friendly names for dumps 00072 const char *getTargetNodeName(unsigned Opcode) const; 00073 00074 /// LowerCallTo - This hook lowers an abstract call to a function into an 00075 /// actual call. 00076 virtual std::pair<SDOperand, SDOperand> 00077 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC, 00078 bool isTailCall, SDOperand Callee, ArgListTy &Args, 00079 SelectionDAG &DAG); 00080 00081 ConstraintType getConstraintType(char ConstraintLetter) const; 00082 00083 std::vector<unsigned> 00084 getRegClassForInlineAsmConstraint(const std::string &Constraint, 00085 MVT::ValueType VT) const; 00086 00087 void restoreGP(MachineBasicBlock* BB); 00088 void restoreRA(MachineBasicBlock* BB); 00089 unsigned getVRegGP() { return GP; } 00090 unsigned getVRegRA() { return RA; } 00091 bool hasITOF() { return useITOF; } 00092 }; 00093 } 00094 00095 #endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H