LLVM API Documentation
#include <TargetLowering.h>
Inheritance diagram for llvm::TargetLowering:
This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.
Definition at line 49 of file TargetLowering.h.
typedef std::vector<double>::const_iterator llvm::TargetLowering::legal_fpimm_iterator |
Definition at line 187 of file TargetLowering.h.
typedef std::vector<std::pair<SDOperand, const Type*> > llvm::TargetLowering::ArgListTy |
LowerCallTo - This hook lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain.
Definition at line 556 of file TargetLowering.h.
typedef std::vector<unsigned>::const_iterator llvm::TargetLowering::legal_am_scale_iterator |
Definition at line 644 of file TargetLowering.h.
LegalizeAction - This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.
Definition at line 53 of file TargetLowering.h.
Definition at line 66 of file TargetLowering.h.
Definition at line 72 of file TargetLowering.h.
Definition at line 590 of file TargetLowering.h.
TargetLowering::TargetLowering | ( | TargetMachine & | TM | ) |
Definition at line 24 of file TargetLowering.cpp.
References allowUnalignedMemoryAccesses, llvm::ISD::BUILTIN_OP_END, llvm::TargetData::getIntPtrType(), getValueType(), llvm::TargetData::isLittleEndian(), llvm::MVT::LAST_VALUETYPE, maxStoresPerMemcpy, maxStoresPerMemmove, maxStoresPerMemset, SchedulingForLatency, and Undefined.
TargetLowering::~TargetLowering | ( | ) | [virtual] |
Definition at line 46 of file TargetLowering.cpp.
TargetMachine& llvm::TargetLowering::getTargetMachine | ( | ) | const [inline] |
Definition at line 80 of file TargetLowering.h.
Referenced by llvm::SelectionDAG::getTarget(), llvm::X86TargetLowering::isLegalAddressImmediate(), llvm::X86TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::SelectionDAGISel::runOnFunction(), llvm::SelectionDAGLowering::visitAlloca(), llvm::SelectionDAGLowering::visitJumpTable(), and llvm::SelectionDAGLowering::visitSwitch().
const TargetData* llvm::TargetLowering::getTargetData | ( | ) | const [inline] |
Definition at line 81 of file TargetLowering.h.
Referenced by llvm::FunctionLoweringInfo::FunctionLoweringInfo(), llvm::SelectionDAGISel::runOnFunction(), llvm::SelectionDAGLowering::visitAlloca(), llvm::SelectionDAGLowering::visitFree(), and llvm::SelectionDAGLowering::visitMalloc().
bool llvm::TargetLowering::isLittleEndian | ( | ) | const [inline] |
Definition at line 83 of file TargetLowering.h.
Referenced by getMemsetStringVal(), LowerArguments(), and LowerCallTo().
MVT::ValueType llvm::TargetLowering::getPointerTy | ( | ) | const [inline] |
Definition at line 84 of file TargetLowering.h.
Referenced by llvm::SelectionDAGLowering::getValue(), LowerArguments(), LowerCALL(), LowerCallTo(), llvm::IA64TargetLowering::LowerCallTo(), llvm::AlphaTargetLowering::LowerCallTo(), LowerFORMAL_ARGUMENTS(), llvm::X86TargetLowering::LowerFrameReturnAddress(), LowerFrameReturnAddress(), llvm::PPCTargetLowering::LowerOperation(), llvm::IA64TargetLowering::LowerOperation(), llvm::AlphaTargetLowering::LowerOperation(), llvm::SelectionDAGLowering::visitAlloca(), llvm::SelectionDAGLowering::visitCall(), llvm::SelectionDAGLowering::visitExtractElement(), llvm::SelectionDAGLowering::visitFree(), llvm::SelectionDAGLowering::visitInlineAsm(), llvm::SelectionDAGLowering::visitInsertElement(), llvm::SelectionDAGLowering::visitIntrinsicCall(), llvm::SelectionDAGLowering::visitJumpTable(), llvm::SelectionDAGLowering::visitMalloc(), llvm::SelectionDAGLowering::visitSwitch(), and llvm::SelectionDAGLowering::visitTargetIntrinsic().
MVT::ValueType llvm::TargetLowering::getShiftAmountTy | ( | ) | const [inline] |
Definition at line 85 of file TargetLowering.h.
Referenced by BuildSDIV(), BuildUDIV(), llvm::SelectionDAGLowering::visitGetElementPtr(), and llvm::SelectionDAGLowering::visitShift().
OutOfRangeShiftAmount llvm::TargetLowering::getShiftAmountFlavor | ( | ) | const [inline] |
Definition at line 86 of file TargetLowering.h.
bool llvm::TargetLowering::isSetCCExpensive | ( | ) | const [inline] |
isSetCCExpensive - Return true if the setcc operation is expensive for this target.
Definition at line 90 of file TargetLowering.h.
bool llvm::TargetLowering::isIntDivCheap | ( | ) | const [inline] |
isIntDivCheap() - Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
Definition at line 94 of file TargetLowering.h.
bool llvm::TargetLowering::isPow2DivCheap | ( | ) | const [inline] |
isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of srl/add/sra.
Definition at line 98 of file TargetLowering.h.
MVT::ValueType llvm::TargetLowering::getSetCCResultTy | ( | ) | const [inline] |
getSetCCResultTy - Return the ValueType of the result of setcc operations.
Definition at line 102 of file TargetLowering.h.
Referenced by llvm::SelectionDAGLowering::visitSwitch().
SetCCResultValue llvm::TargetLowering::getSetCCResultContents | ( | ) | const [inline] |
getSetCCResultContents - For targets without boolean registers, this flag returns information about the contents of the high-bits in the setcc result register.
Definition at line 107 of file TargetLowering.h.
Referenced by ComputeMaskedBits(), ComputeNumSignBits(), and SimplifyDemandedBits().
SchedPreference llvm::TargetLowering::getSchedulingPreference | ( | ) | const [inline] |
getSchedulingPreference - Return target scheduling preference.
Definition at line 110 of file TargetLowering.h.
Referenced by llvm::SelectionDAGISel::ScheduleAndEmitDAG().
TargetRegisterClass* llvm::TargetLowering::getRegClassFor | ( | MVT::ValueType | VT | ) | const [inline] |
getRegClassFor - Return the register class that should be used for the specified value type. This may only be called on legal types.
Definition at line 116 of file TargetLowering.h.
References RC.
Referenced by llvm::IA64TargetLowering::LowerArguments(), llvm::SelectionDAGISel::MakeReg(), and llvm::FunctionLoweringInfo::MakeReg().
bool llvm::TargetLowering::isTypeLegal | ( | MVT::ValueType | VT | ) | const [inline] |
isTypeLegal - Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.
Definition at line 125 of file TargetLowering.h.
Referenced by BuildSDIV(), BuildUDIV(), computeRegisterProperties(), llvm::FunctionLoweringInfo::CreateRegForValue(), getPackedTypeBreakdown(), getRegForInlineAsmConstraint(), getTypeToPromoteTo(), isAllocatableRegister(), LowerArguments(), LowerCallTo(), MeetsMaxMemopRequirement(), SetValueTypeAction(), and llvm::SelectionDAGLowering::visitTargetIntrinsic().
const ValueTypeActionImpl& llvm::TargetLowering::getValueTypeActions | ( | ) | const [inline] |
Definition at line 153 of file TargetLowering.h.
LegalizeAction llvm::TargetLowering::getTypeAction | ( | MVT::ValueType | VT | ) | const [inline] |
getTypeAction - Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.
Definition at line 161 of file TargetLowering.h.
References llvm::TargetLowering::ValueTypeActionImpl::getTypeAction().
Referenced by LowerArguments(), LowerCallTo(), llvm::SelectionDAGISel::runOnFunction(), and llvm::SelectionDAGLowering::visitUserOp2().
MVT::ValueType llvm::TargetLowering::getTypeToTransformTo | ( | MVT::ValueType | VT | ) | const [inline] |
getTypeToTransformTo - For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register.
Definition at line 170 of file TargetLowering.h.
Referenced by llvm::FunctionLoweringInfo::CreateRegForValue(), getPackedTypeBreakdown(), LowerArguments(), LowerCallTo(), llvm::SelectionDAGISel::runOnFunction(), llvm::SelectionDAGLowering::visitUnwind(), and llvm::SelectionDAGLowering::visitUserOp2().
unsigned TargetLowering::getPackedTypeBreakdown | ( | const PackedType * | PTy, | |
MVT::ValueType & | PTyElementVT, | |||
MVT::ValueType & | PTyLegalElementVT | |||
) | const |
getPackedTypeBreakdown - Packed types are broken down into some number of legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT of the PackedType elements before they are promoted/expanded.
Definition at line 152 of file TargetLowering.cpp.
References llvm::SequentialType::getElementType(), llvm::PackedType::getNumElements(), llvm::MVT::getSizeInBits(), getTypeToTransformTo(), getValueType(), llvm::MVT::getVectorType(), and isTypeLegal().
Referenced by llvm::FunctionLoweringInfo::FunctionLoweringInfo().
legal_fpimm_iterator llvm::TargetLowering::legal_fpimm_begin | ( | ) | const [inline] |
Definition at line 188 of file TargetLowering.h.
legal_fpimm_iterator llvm::TargetLowering::legal_fpimm_end | ( | ) | const [inline] |
Definition at line 191 of file TargetLowering.h.
virtual bool llvm::TargetLowering::isShuffleMaskLegal | ( | SDOperand | Mask, | |
MVT::ValueType | VT | |||
) | const [inline, virtual] |
isShuffleMaskLegal - Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented in llvm::X86TargetLowering.
Definition at line 199 of file TargetLowering.h.
virtual bool llvm::TargetLowering::isVectorClearMaskLegal | ( | std::vector< SDOperand > & | BVOps, | |
MVT::ValueType | EVT, | |||
SelectionDAG & | DAG | |||
) | const [inline, virtual] |
isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented in llvm::X86TargetLowering.
Definition at line 207 of file TargetLowering.h.
LegalizeAction llvm::TargetLowering::getOperationAction | ( | unsigned | Op, | |
MVT::ValueType | VT | |||
) | const [inline] |
getOperationAction - Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 217 of file TargetLowering.h.
Referenced by getTypeToPromoteTo(), and isOperationLegal().
bool llvm::TargetLowering::isOperationLegal | ( | unsigned | Op, | |
MVT::ValueType | VT | |||
) | const [inline] |
isOperationLegal - Return true if the specified operation is legal on this target.
Definition at line 223 of file TargetLowering.h.
References Custom, getOperationAction(), and Legal.
Referenced by BuildSDIV(), BuildUDIV(), and llvm::SelectionDAGLowering::visitSwitch().
MVT::ValueType llvm::TargetLowering::getTypeToPromoteTo | ( | unsigned | Op, | |
MVT::ValueType | VT | |||
) | const [inline] |
getTypeToPromoteTo - If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition at line 230 of file TargetLowering.h.
References getOperationAction(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::isVoid, and Promote.
MVT::ValueType llvm::TargetLowering::getValueType | ( | const Type * | Ty | ) | const [inline] |
getValueType - Return the MVT::ValueType corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size.
Definition at line 255 of file TargetLowering.h.
References llvm::Type::BoolTyID, llvm::Type::DoubleTyID, llvm::MVT::f32, llvm::MVT::f64, llvm::Type::FloatTyID, llvm::Type::getTypeID(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Type::IntTyID, llvm::MVT::isVoid, llvm::Type::LongTyID, llvm::Type::PackedTyID, llvm::Type::PointerTyID, llvm::Type::SByteTyID, llvm::Type::ShortTyID, Ty, llvm::Type::UByteTyID, llvm::Type::UIntTyID, llvm::Type::ULongTyID, llvm::Type::UShortTyID, llvm::MVT::Vector, and llvm::Type::VoidTyID.
Referenced by llvm::FunctionLoweringInfo::CreateRegForValue(), llvm::FunctionLoweringInfo::FunctionLoweringInfo(), llvm::SelectionDAGLowering::getLoadFrom(), getPackedTypeBreakdown(), llvm::SelectionDAGLowering::getValue(), LowerArguments(), llvm::IA64TargetLowering::LowerArguments(), LowerCallTo(), llvm::IA64TargetLowering::LowerCallTo(), llvm::AlphaTargetLowering::LowerCallTo(), llvm::SelectionDAGISel::runOnFunction(), TargetLowering(), llvm::SelectionDAGLowering::visitBinary(), llvm::SelectionDAGLowering::visitCast(), llvm::SelectionDAGLowering::visitExtractElement(), llvm::SelectionDAGLowering::visitInlineAsm(), llvm::SelectionDAGLowering::visitTargetIntrinsic(), and llvm::SelectionDAGLowering::visitVAArg().
unsigned llvm::TargetLowering::getNumElements | ( | MVT::ValueType | VT | ) | const [inline] |
getNumElements - Return the number of registers that this ValueType will eventually require. This is always one for all non-integer types, is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces.
Definition at line 279 of file TargetLowering.h.
Referenced by computeRegisterProperties(), llvm::FunctionLoweringInfo::CreateRegForValue(), llvm::FunctionLoweringInfo::FunctionLoweringInfo(), llvm::SelectionDAGLowering::GetRegistersForValue(), LowerArguments(), and LowerCallTo().
bool llvm::TargetLowering::hasTargetDAGCombine | ( | ISD::NodeType | NT | ) | const [inline] |
hasTargetDAGCombine - If true, the target has custom DAG combine transformations that it can perform for the specified node.
Definition at line 285 of file TargetLowering.h.
unsigned llvm::TargetLowering::getMaxStoresPerMemset | ( | ) | const [inline] |
Get maximum # of store operations permitted for llvm.memset.
This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement.
Definition at line 293 of file TargetLowering.h.
References maxStoresPerMemset.
Referenced by llvm::SelectionDAGLowering::visitMemIntrinsic().
unsigned llvm::TargetLowering::getMaxStoresPerMemcpy | ( | ) | const [inline] |
Get maximum # of store operations permitted for llvm.memcpy.
This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement.
Definition at line 299 of file TargetLowering.h.
References maxStoresPerMemcpy.
Referenced by llvm::SelectionDAGLowering::visitMemIntrinsic().
unsigned llvm::TargetLowering::getMaxStoresPerMemmove | ( | ) | const [inline] |
Get maximum # of store operations permitted for llvm.memmove.
This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement.
Definition at line 305 of file TargetLowering.h.
References maxStoresPerMemmove.
bool llvm::TargetLowering::allowsUnalignedMemoryAccesses | ( | ) | const [inline] |
Determine if the target supports unaligned memory accesses.
This function returns true if the target allows unaligned memory accesses. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. It's use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.
Definition at line 313 of file TargetLowering.h.
References allowUnalignedMemoryAccesses.
Referenced by MeetsMaxMemopRequirement().
bool llvm::TargetLowering::usesUnderscoreSetJmpLongJmp | ( | ) | const [inline] |
usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
Definition at line 319 of file TargetLowering.h.
Referenced by llvm::SelectionDAGLowering::visitIntrinsicCall().
unsigned llvm::TargetLowering::getStackPointerRegisterToSaveRestore | ( | ) | const [inline] |
getStackPointerRegisterToSaveRestore - If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 326 of file TargetLowering.h.
bool TargetLowering::MaskedValueIsZero | ( | SDOperand | Op, | |
uint64_t | Mask, | |||
unsigned | Depth = 0 | |||
) | const |
MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.
Definition at line 690 of file TargetLowering.cpp.
References ComputeMaskedBits(), and Op.
void TargetLowering::ComputeMaskedBits | ( | SDOperand | Op, | |
uint64_t | Mask, | |||
uint64_t & | KnownZero, | |||
uint64_t & | KnownOne, | |||
unsigned | Depth = 0 | |||
) | const |
ComputeMaskedBits - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. This code only analyzes bits in Mask, in order to short-circuit processing. Targets can implement the computeMaskedBitsForTargetNode method, to allow target nodes to be understood.
Definition at line 702 of file TargetLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::AssertZext, llvm::ISD::BUILTIN_OP_END, computeMaskedBitsForTargetNode(), llvm::ISD::Constant, llvm::CountLeadingZeros_64(), llvm::CountTrailingZeros_64(), llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::MVT::getIntVTBitMask(), llvm::MVT::getIntVTSignBit(), getSetCCResultContents(), llvm::MVT::getSizeInBits(), llvm::ConstantSDNode::getValue(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Log2_32(), Op, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, ZeroOrOneSetCCResult, and llvm::ISD::ZEXTLOAD.
Referenced by ComputeNumSignBits(), MaskedValueIsZero(), and SimplifyDemandedBits().
bool TargetLowering::SimplifyDemandedBits | ( | SDOperand | Op, | |
uint64_t | DemandedMask, | |||
uint64_t & | KnownZero, | |||
uint64_t & | KnownOne, | |||
TargetLoweringOpt & | TLO, | |||
unsigned | Depth = 0 | |||
) | const |
SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.
Definition at line 226 of file TargetLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::AssertZext, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), ComputeMaskedBits(), llvm::ISD::Constant, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVTBitMask(), llvm::MVT::getIntVTSignBit(), llvm::SelectionDAG::getNode(), getSetCCResultContents(), llvm::MVT::getSizeInBits(), llvm::Value::hasOneUse(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Log2_32(), Op, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::Use::Val, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, ZeroOrOneSetCCResult, and llvm::ISD::ZEXTLOAD.
void TargetLowering::computeMaskedBitsForTargetNode | ( | const SDOperand | Op, | |
uint64_t | Mask, | |||
uint64_t & | KnownZero, | |||
uint64_t & | KnownOne, | |||
unsigned | Depth = 0 | |||
) | const [virtual] |
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 1011 of file TargetLowering.cpp.
References llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and Op.
Referenced by ComputeMaskedBits().
unsigned TargetLowering::ComputeNumSignBits | ( | SDOperand | Op, | |
unsigned | Depth = 0 | |||
) | const |
ComputeNumSignBits - Return the number of times the sign bit of the register is replicated into the other bits. We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3.
Definition at line 1031 of file TargetLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BUILTIN_OP_END, C, ComputeMaskedBits(), ComputeNumSignBitsForTargetNode(), llvm::ISD::Constant, llvm::CountLeadingZeros_64(), llvm::MVT::getIntVTBitMask(), llvm::MVT::getIntVTSignBit(), getSetCCResultContents(), llvm::MVT::getSizeInBits(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isInteger(), Mask, Op, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SUB, llvm::ISD::TRUNCATE, Val, llvm::ISD::XOR, ZeroOrNegativeOneSetCCResult, and llvm::ISD::ZEXTLOAD.
unsigned TargetLowering::ComputeNumSignBitsForTargetNode | ( | SDOperand | Op, | |
unsigned | Depth = 0 | |||
) | const [virtual] |
ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.
Definition at line 1237 of file TargetLowering.cpp.
References llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and Op.
Referenced by ComputeNumSignBits().
SDOperand TargetLowering::PerformDAGCombine | ( | SDNode * | N, | |
DAGCombinerInfo & | DCI | |||
) | const [virtual] |
PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDOperand.Val == 0 - No change was made SDOperand.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Definition at line 1250 of file TargetLowering.cpp.
void llvm::TargetLowering::setShiftAmountType | ( | MVT::ValueType | VT | ) | [inline, protected] |
setShiftAmountType - Describe the type that should be used for shift amounts. This type defaults to the pointer type.
Definition at line 446 of file TargetLowering.h.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setSetCCResultType | ( | MVT::ValueType | VT | ) | [inline, protected] |
setSetCCResultType - Describe the type that shoudl be used as the result of a setcc operation. This defaults to the pointer type.
Definition at line 450 of file TargetLowering.h.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setSetCCResultContents | ( | SetCCResultValue | Ty | ) | [inline, protected] |
setSetCCResultContents - Specify how the target extends the result of a setcc operation in a register.
Definition at line 454 of file TargetLowering.h.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setSchedulingPreference | ( | SchedPreference | Pref | ) | [inline, protected] |
setSchedulingPreference - Specify the target scheduling preference.
Definition at line 457 of file TargetLowering.h.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setShiftAmountFlavor | ( | OutOfRangeShiftAmount | OORSA | ) | [inline, protected] |
setShiftAmountFlavor - Describe how the target handles out of range shift amounts.
Definition at line 463 of file TargetLowering.h.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setUseUnderscoreSetJmpLongJmp | ( | bool | Val | ) | [inline, protected] |
setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or the non _ versions. Defaults to false.
Definition at line 470 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setStackPointerRegisterToSaveRestore | ( | unsigned | R | ) | [inline, protected] |
setStackPointerRegisterToSaveRestore - If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 477 of file TargetLowering.h.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setSetCCIsExpensive | ( | ) | [inline, protected] |
setSetCCIxExpensive - This is a short term hack for targets that codegen setcc as a conditional branch. This encourages the code generator to fold setcc operations into other operations if possible.
Definition at line 484 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering().
void llvm::TargetLowering::setIntDivIsCheap | ( | bool | isCheap = true |
) | [inline, protected] |
setIntDivIsCheap - Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.
Definition at line 489 of file TargetLowering.h.
void llvm::TargetLowering::setPow2DivIsCheap | ( | bool | isCheap = true |
) | [inline, protected] |
setPow2DivIsCheap - Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.
Definition at line 494 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering().
void llvm::TargetLowering::addRegisterClass | ( | MVT::ValueType | VT, | |
TargetRegisterClass * | RC | |||
) | [inline, protected] |
addRegisterClass - Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.
Definition at line 499 of file TargetLowering.h.
References RC.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void TargetLowering::computeRegisterProperties | ( | ) | [protected] |
computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition at line 86 of file TargetLowering.cpp.
References Expand, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::FIRST_VECTOR_VALUETYPE, getNumElements(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::LAST_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, Promote, SetValueTypeAction(), and llvm::MVT::Vector.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setOperationAction | ( | unsigned | Op, | |
MVT::ValueType | VT, | |||
LegalizeAction | Action | |||
) | [inline, protected] |
setOperationAction - Indicate that the specified operation does not work with the specified type and indicate what to do about it.
Definition at line 510 of file TargetLowering.h.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::AddPromotedToType | ( | unsigned | Opc, | |
MVT::ValueType | OrigVT, | |||
MVT::ValueType | DestVT | |||
) | [inline, protected] |
AddPromotedToType - If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.
Definition at line 522 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::addLegalFPImmediate | ( | double | Imm | ) | [inline, protected] |
addLegalFPImmediate - Indicate that this target can instruction select the specified FP immediate natively.
Definition at line 529 of file TargetLowering.h.
Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
void llvm::TargetLowering::setTargetDAGCombine | ( | ISD::NodeType | NT | ) | [inline, protected] |
setTargetDAGCombine - Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.
Definition at line 536 of file TargetLowering.h.
Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
std::vector< SDOperand > TargetLowering::LowerArguments | ( | Function & | F, | |
SelectionDAG & | DAG | |||
) | [virtual] |
LowerArguments - This hook must be implemented to indicate how we should lower the arguments for the specified function, into the specified DAG.
Reimplemented in llvm::IA64TargetLowering.
Definition at line 2387 of file SelectionDAGISel.cpp.
References llvm::ISD::AssertSext, llvm::ISD::AssertZext, DAG, E, Expand, F, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SequentialType::getElementType(), llvm::SelectionDAG::getNode(), llvm::PackedType::getNumElements(), getNumElements(), llvm::SDNode::getNumValues(), getPointerTy(), llvm::SelectionDAG::getRoot(), llvm::MVT::getSizeInBits(), llvm::Value::getType(), getTypeAction(), getTypeToTransformTo(), llvm::SelectionDAG::getValueType(), getValueType(), llvm::MVT::getVectorType(), SPISD::Hi, llvm::MVT::i32, llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isLittleEndian(), llvm::Type::isSigned(), isTypeLegal(), Legal, SPISD::Lo, Op, llvm::MVT::Other, Promote, RetVals, llvm::SelectionDAG::setRoot(), llvm::SDOperand::Val, llvm::ISD::VBIT_CONVERT, and llvm::MVT::Vector.
std::pair< SDOperand, SDOperand > TargetLowering::LowerCallTo | ( | SDOperand | Chain, | |
const Type * | RetTy, | |||
bool | isVarArg, | |||
unsigned | CallingConv, | |||
bool | isTailCall, | |||
SDOperand | Callee, | |||
ArgListTy & | Args, | |||
SelectionDAG & | DAG | |||
) | [virtual] |
TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just inserts an ISD::CALL node, which is later custom lowered by the target to something concrete. FIXME: When all targets are migrated to using ISD::CALL, this hook should be integrated into SDISel.
Definition at line 2520 of file SelectionDAGISel.cpp.
References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::CALL, DAG, Expand, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SequentialType::getElementType(), llvm::SelectionDAG::getNode(), getNumElements(), llvm::PackedType::getNumElements(), llvm::SDNode::getNumValues(), getPointerTy(), llvm::MVT::getSizeInBits(), getTypeAction(), getTypeToTransformTo(), llvm::SDOperand::getValue(), llvm::SelectionDAG::getValueType(), llvm::SDOperand::getValueType(), getValueType(), llvm::MVT::getVectorType(), SPISD::Hi, llvm::MVT::i32, llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isLittleEndian(), llvm::Type::isSigned(), isTypeLegal(), Legal, SPISD::Lo, Op, llvm::MVT::Other, Promote, RetTy, second, llvm::ISD::SIGN_EXTEND, llvm::SDOperand::Val, llvm::ISD::VBIT_CONVERT, llvm::MVT::Vector, llvm::Type::VoidTy, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::SelectionDAGLowering::visitCall(), llvm::SelectionDAGLowering::visitFree(), and llvm::SelectionDAGLowering::visitMalloc().
std::pair< SDOperand, SDOperand > TargetLowering::LowerFrameReturnAddress | ( | bool | isFrameAddr, | |
SDOperand | Chain, | |||
unsigned | Depth, | |||
SelectionDAG & | DAG | |||
) | [virtual] |
LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or llvm.frameaddress (depending on the value of the first argument). The return values are the result pointer and the resultant token chain. If not implemented, both of these intrinsics will return null.
Reimplemented in llvm::IA64TargetLowering, and llvm::X86TargetLowering.
Definition at line 2707 of file SelectionDAGISel.cpp.
References DAG, llvm::SelectionDAG::getConstant(), and getPointerTy().
Referenced by llvm::SelectionDAGLowering::visitFrameReturnAddress().
SDOperand TargetLowering::LowerOperation | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [virtual] |
LowerOperation - This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.
Reimplemented in llvm::AlphaTargetLowering, llvm::IA64TargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 2712 of file SelectionDAGISel.cpp.
SDOperand TargetLowering::CustomPromoteOperation | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [virtual] |
CustomPromoteOperation - This callback is invoked for operations that are unsupported by the target, are registered to use 'custom' lowering, and whose type needs to be promoted.
Reimplemented in llvm::AlphaTargetLowering.
Definition at line 2718 of file SelectionDAGISel.cpp.
const char * TargetLowering::getTargetNodeName | ( | unsigned | Opcode | ) | const [virtual] |
getTargetNodeName() - This method returns the name of a target specific DAG node.
Reimplemented in llvm::AlphaTargetLowering, llvm::IA64TargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 142 of file TargetLowering.cpp.
Referenced by llvm::SDNode::getOperationName().
TargetLowering::ConstraintType TargetLowering::getConstraintType | ( | char | ConstraintLetter | ) | const [virtual] |
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented in llvm::AlphaTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 1260 of file TargetLowering.cpp.
References C_Memory, C_Other, C_RegisterClass, and C_Unknown.
Referenced by llvm::X86TargetLowering::getConstraintType(), llvm::PPCTargetLowering::getConstraintType(), llvm::AlphaTargetLowering::getConstraintType(), and llvm::SelectionDAGLowering::visitInlineAsm().
std::vector< unsigned > TargetLowering::getRegClassForInlineAsmConstraint | ( | const std::string & | Constraint, | |
MVT::ValueType | VT | |||
) | const [virtual] |
getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.
Reimplemented in llvm::AlphaTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 1297 of file TargetLowering.cpp.
Referenced by llvm::SelectionDAGLowering::GetRegistersForValue().
std::pair< unsigned, const TargetRegisterClass * > TargetLowering::getRegForInlineAsmConstraint | ( | const std::string & | Constraint, | |
MVT::ValueType | VT | |||
) | const [virtual] |
getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.
Definition at line 1304 of file TargetLowering.cpp.
References E, llvm::TargetMachine::getRegisterInfo(), isTypeLegal(), RC, and llvm::StringsEqualNoCase().
Referenced by llvm::SelectionDAGLowering::GetRegistersForValue(), and llvm::SelectionDAGLowering::visitInlineAsm().
bool TargetLowering::isOperandValidForConstraint | ( | SDOperand | Op, | |
char | ConstraintLetter | |||
) | [virtual] |
isOperandValidForConstraint - Return true if the specified SDOperand is valid for the specified target constraint letter.
Reimplemented in llvm::PPCTargetLowering.
Definition at line 1284 of file TargetLowering.cpp.
Referenced by llvm::PPCTargetLowering::isOperandValidForConstraint(), and llvm::SelectionDAGLowering::visitInlineAsm().
MachineBasicBlock * TargetLowering::InsertAtEndOfBasicBlock | ( | MachineInstr * | MI, | |
MachineBasicBlock * | MBB | |||
) | [virtual] |
Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 2345 of file SelectionDAGISel.cpp.
Referenced by llvm::ScheduleDAG::EmitNode().
bool TargetLowering::isLegalAddressImmediate | ( | int64_t | V | ) | const [virtual] |
isLegalAddressImmediate - Return true if the integer value or GlobalValue can be used as the offset of the target addressing mode.
Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.
Definition at line 1348 of file TargetLowering.cpp.
Referenced by isTargetConstant().
bool TargetLowering::isLegalAddressImmediate | ( | GlobalValue * | GV | ) | const [virtual] |
legal_am_scale_iterator llvm::TargetLowering::legal_am_scale_begin | ( | ) | const [inline] |
Definition at line 645 of file TargetLowering.h.
legal_am_scale_iterator llvm::TargetLowering::legal_am_scale_end | ( | ) | const [inline] |
Definition at line 648 of file TargetLowering.h.
SDOperand TargetLowering::BuildSDIV | ( | SDNode * | N, | |
SelectionDAG & | DAG, | |||
std::vector< SDNode * > * | Created | |||
) | const |
BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Definition at line 1534 of file TargetLowering.cpp.
References llvm::ISD::ADD, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), getShiftAmountTy(), llvm::MVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isOperationLegal(), isTypeLegal(), ms::m, magic32(), magic64(), llvm::ISD::MULHS, ms::s, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, T, and llvm::SDOperand::Val.
Referenced by llvm::AlphaTargetLowering::LowerOperation().
SDOperand TargetLowering::BuildUDIV | ( | SDNode * | N, | |
SelectionDAG & | DAG, | |||
std::vector< SDNode * > * | Created | |||
) | const |
BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Definition at line 1582 of file TargetLowering.cpp.
References mu::a, llvm::ISD::ADD, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), getShiftAmountTy(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isOperationLegal(), isTypeLegal(), mu::m, magicu32(), magicu64(), llvm::ISD::MULHU, mu::s, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::SDOperand::Val.
Referenced by llvm::AlphaTargetLowering::LowerOperation().
void llvm::TargetLowering::addLegalAddressScale | ( | unsigned | Scale | ) | [inline, protected] |
addLegalAddressScale - Add a integer (> 1) value which can be used as scale in the target addressing mode. Note: the ordering matters so the least efficient ones should be entered first.
Definition at line 665 of file TargetLowering.h.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
unsigned llvm::TargetLowering::maxStoresPerMemset [protected] |
Specify maximum number of store instructions per memset call.
When lowering llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.
Definition at line 775 of file TargetLowering.h.
Referenced by getMaxStoresPerMemset(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
unsigned llvm::TargetLowering::maxStoresPerMemcpy [protected] |
Specify maximum bytes of store instructions per memcpy call.
When lowering llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.
Definition at line 787 of file TargetLowering.h.
Referenced by getMaxStoresPerMemcpy(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
unsigned llvm::TargetLowering::maxStoresPerMemmove [protected] |
Specify maximum bytes of store instructions per memmove call.
When lowering llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.
Definition at line 798 of file TargetLowering.h.
Referenced by getMaxStoresPerMemmove(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
bool llvm::TargetLowering::allowUnalignedMemoryAccesses [protected] |
Indicate whether the target permits unaligned memory accesses.
This field specifies whether the target machine permits unaligned memory accesses. This is used, for example, to determine the size of store operations when copying small arrays and other similar tasks.
Definition at line 804 of file TargetLowering.h.
Referenced by allowsUnalignedMemoryAccesses(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().