LLVM API Documentation

TargetInstrInfo.h

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00001 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the target machine instructions to the code generator.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
00015 #define LLVM_TARGET_TARGETINSTRINFO_H
00016 
00017 #include "llvm/CodeGen/MachineBasicBlock.h"
00018 #include "llvm/Support/DataTypes.h"
00019 #include <vector>
00020 #include <cassert>
00021 
00022 namespace llvm {
00023 
00024 class MachineInstr;
00025 class TargetMachine;
00026 class Value;
00027 class Type;
00028 class Instruction;
00029 class Constant;
00030 class Function;
00031 class MachineCodeForInstruction;
00032 class TargetRegisterClass;
00033 
00034 //---------------------------------------------------------------------------
00035 // Data types used to define information about a single machine instruction
00036 //---------------------------------------------------------------------------
00037 
00038 typedef short MachineOpCode;
00039 typedef unsigned InstrSchedClass;
00040 
00041 //---------------------------------------------------------------------------
00042 // struct TargetInstrDescriptor:
00043 //  Predefined information about each machine instruction.
00044 //  Designed to initialized statically.
00045 //
00046 
00047 const unsigned M_BRANCH_FLAG           = 1 << 0;
00048 const unsigned M_CALL_FLAG             = 1 << 1;
00049 const unsigned M_RET_FLAG              = 1 << 2;
00050 const unsigned M_BARRIER_FLAG          = 1 << 3;
00051 const unsigned M_DELAY_SLOT_FLAG       = 1 << 4;
00052 const unsigned M_LOAD_FLAG             = 1 << 5;
00053 const unsigned M_STORE_FLAG            = 1 << 6;
00054 
00055 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
00056 const unsigned M_2_ADDR_FLAG           = 1 << 7;
00057 
00058 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
00059 // changed into a 3-address instruction if the first two operands cannot be
00060 // assigned to the same register.  The target must implement the
00061 // TargetInstrInfo::convertToThreeAddress method for this instruction.
00062 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8;
00063 
00064 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
00065 // Z), which produces the same result if Y and Z are exchanged.
00066 const unsigned M_COMMUTABLE            = 1 << 9;
00067 
00068 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
00069 // block?  Typically this is things like return and branch instructions.
00070 // Various passes use this to insert code into the bottom of a basic block, but
00071 // before control flow occurs.
00072 const unsigned M_TERMINATOR_FLAG       = 1 << 10;
00073 
00074 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
00075 // insertion support when the DAG scheduler is inserting it into a machine basic
00076 // block.
00077 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11;
00078 
00079 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
00080 // operands in addition to the minimum number operands specified.
00081 const unsigned M_VARIABLE_OPS = 1 << 12;
00082 
00083 // Machine operand flags
00084 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
00085 // requires a callback to look up its register class.
00086 const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
00087 
00088 /// TargetOperandInfo - This holds information about one operand of a machine
00089 /// instruction, indicating the register class for register operands, etc.
00090 ///
00091 class TargetOperandInfo {
00092 public:
00093   /// RegClass - This specifies the register class enumeration of the operand 
00094   /// if the operand is a register.  If not, this contains 0.
00095   unsigned short RegClass;
00096   unsigned short Flags;
00097   /// Currently no other information.
00098 };
00099 
00100 
00101 class TargetInstrDescriptor {
00102 public:
00103   const char *    Name;          // Assembly language mnemonic for the opcode.
00104   unsigned        numOperands;   // Num of args (may be more if variable_ops).
00105   InstrSchedClass schedClass;    // enum  identifying instr sched class
00106   unsigned        Flags;         // flags identifying machine instr class
00107   unsigned        TSFlags;       // Target Specific Flag values
00108   const unsigned *ImplicitUses;  // Registers implicitly read by this instr
00109   const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
00110   const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
00111 };
00112 
00113 
00114 //---------------------------------------------------------------------------
00115 ///
00116 /// TargetInstrInfo - Interface to description of machine instructions
00117 ///
00118 class TargetInstrInfo {
00119   const TargetInstrDescriptor* desc;    // raw array to allow static init'n
00120   unsigned NumOpcodes;                  // number of entries in the desc array
00121   unsigned numRealOpCodes;              // number of non-dummy op codes
00122 
00123   TargetInstrInfo(const TargetInstrInfo &);  // DO NOT IMPLEMENT
00124   void operator=(const TargetInstrInfo &);   // DO NOT IMPLEMENT
00125 public:
00126   TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
00127   virtual ~TargetInstrInfo();
00128 
00129   // Invariant opcodes: All instruction sets have these as their low opcodes.
00130   enum { 
00131     PHI = 0,
00132     INLINEASM = 1
00133   };
00134 
00135   unsigned getNumOpcodes() const { return NumOpcodes; }
00136 
00137   /// get - Return the machine instruction descriptor that corresponds to the
00138   /// specified instruction opcode.
00139   ///
00140   const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
00141     assert((unsigned)Opcode < NumOpcodes);
00142     return desc[Opcode];
00143   }
00144 
00145   const char *getName(MachineOpCode Opcode) const {
00146     return get(Opcode).Name;
00147   }
00148 
00149   int getNumOperands(MachineOpCode Opcode) const {
00150     return get(Opcode).numOperands;
00151   }
00152 
00153   InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
00154     return get(Opcode).schedClass;
00155   }
00156 
00157   const unsigned *getImplicitUses(MachineOpCode Opcode) const {
00158     return get(Opcode).ImplicitUses;
00159   }
00160 
00161   const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
00162     return get(Opcode).ImplicitDefs;
00163   }
00164 
00165 
00166   //
00167   // Query instruction class flags according to the machine-independent
00168   // flags listed above.
00169   //
00170   bool isReturn(MachineOpCode Opcode) const {
00171     return get(Opcode).Flags & M_RET_FLAG;
00172   }
00173 
00174   bool isTwoAddrInstr(MachineOpCode Opcode) const {
00175     return get(Opcode).Flags & M_2_ADDR_FLAG;
00176   }
00177   bool isCommutableInstr(MachineOpCode Opcode) const {
00178     return get(Opcode).Flags & M_COMMUTABLE;
00179   }
00180   bool isTerminatorInstr(unsigned Opcode) const {
00181     return get(Opcode).Flags & M_TERMINATOR_FLAG;
00182   }
00183   
00184   bool isBranch(MachineOpCode Opcode) const {
00185     return get(Opcode).Flags & M_BRANCH_FLAG;
00186   }
00187   
00188   /// isBarrier - Returns true if the specified instruction stops control flow
00189   /// from executing the instruction immediately following it.  Examples include
00190   /// unconditional branches and return instructions.
00191   bool isBarrier(MachineOpCode Opcode) const {
00192     return get(Opcode).Flags & M_BARRIER_FLAG;
00193   }
00194   
00195   bool isCall(MachineOpCode Opcode) const {
00196     return get(Opcode).Flags & M_CALL_FLAG;
00197   }
00198   bool isLoad(MachineOpCode Opcode) const {
00199     return get(Opcode).Flags & M_LOAD_FLAG;
00200   }
00201   bool isStore(MachineOpCode Opcode) const {
00202     return get(Opcode).Flags & M_STORE_FLAG;
00203   }
00204   
00205   /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
00206   /// custom insertion support when the DAG scheduler is inserting it into a
00207   /// machine basic block.
00208   bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
00209     return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
00210   }
00211 
00212   bool hasVariableOperands(MachineOpCode Opcode) const {
00213     return get(Opcode).Flags & M_VARIABLE_OPS;
00214   }
00215 
00216   /// Return true if the instruction is a register to register move
00217   /// and leave the source and dest operands in the passed parameters.
00218   virtual bool isMoveInstr(const MachineInstr& MI,
00219                            unsigned& sourceReg,
00220                            unsigned& destReg) const {
00221     return false;
00222   }
00223   
00224   /// isLoadFromStackSlot - If the specified machine instruction is a direct
00225   /// load from a stack slot, return the virtual or physical register number of
00226   /// the destination along with the FrameIndex of the loaded stack slot.  If
00227   /// not, return 0.  This predicate must return 0 if the instruction has
00228   /// any side effects other than loading from the stack slot.
00229   virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
00230     return 0;
00231   }
00232   
00233   /// isStoreToStackSlot - If the specified machine instruction is a direct
00234   /// store to a stack slot, return the virtual or physical register number of
00235   /// the source reg along with the FrameIndex of the loaded stack slot.  If
00236   /// not, return 0.  This predicate must return 0 if the instruction has
00237   /// any side effects other than storing to the stack slot.
00238   virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
00239     return 0;
00240   }
00241 
00242   /// convertToThreeAddress - This method must be implemented by targets that
00243   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
00244   /// may be able to convert a two-address instruction into a true
00245   /// three-address instruction on demand.  This allows the X86 target (for
00246   /// example) to convert ADD and SHL instructions into LEA instructions if they
00247   /// would require register copies due to two-addressness.
00248   ///
00249   /// This method returns a null pointer if the transformation cannot be
00250   /// performed, otherwise it returns the new instruction.
00251   ///
00252   virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
00253     return 0;
00254   }
00255 
00256   /// commuteInstruction - If a target has any instructions that are commutable,
00257   /// but require converting to a different instruction or making non-trivial
00258   /// changes to commute them, this method can overloaded to do this.  The
00259   /// default implementation of this method simply swaps the first two operands
00260   /// of MI and returns it.
00261   ///
00262   /// If a target wants to make more aggressive changes, they can construct and
00263   /// return a new machine instruction.  If an instruction cannot commute, it
00264   /// can also return null.
00265   ///
00266   virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
00267 
00268   /// Insert a goto (unconditional branch) sequence to TMBB, at the
00269   /// end of MBB
00270   virtual void insertGoto(MachineBasicBlock& MBB,
00271                           MachineBasicBlock& TMBB) const {
00272     assert(0 && "Target didn't implement insertGoto!");
00273   }
00274 
00275   /// Reverses the branch condition of the MachineInstr pointed by
00276   /// MI. The instruction is replaced and the new MI is returned.
00277   virtual MachineBasicBlock::iterator
00278   reverseBranchCondition(MachineBasicBlock::iterator MI) const {
00279     assert(0 && "Target didn't implement reverseBranchCondition!");
00280     abort();
00281     return MI;
00282   }
00283   
00284   /// insertNoop - Insert a noop into the instruction stream at the specified
00285   /// point.
00286   virtual void insertNoop(MachineBasicBlock &MBB, 
00287                           MachineBasicBlock::iterator MI) const {
00288     assert(0 && "Target didn't implement insertNoop!");
00289     abort();
00290   }
00291 
00292   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
00293   /// values.
00294   virtual const TargetRegisterClass *getPointerRegClass() const {
00295     assert(0 && "Target didn't implement getPointerRegClass!");
00296     abort();
00297   }
00298   
00299   /// hasDelaySlot - Returns true if the specified instruction has a delay slot
00300   /// which must be filled by the code generator.
00301   bool hasDelaySlot(unsigned Opcode) const {
00302     return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
00303   }
00304 };
00305 
00306 } // End llvm namespace
00307 
00308 #endif