LLVM API Documentation
00001 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by Duraid Madina and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the IA64ISelLowering class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "IA64ISelLowering.h" 00015 #include "IA64MachineFunctionInfo.h" 00016 #include "IA64TargetMachine.h" 00017 #include "llvm/CodeGen/MachineFrameInfo.h" 00018 #include "llvm/CodeGen/MachineFunction.h" 00019 #include "llvm/CodeGen/MachineInstrBuilder.h" 00020 #include "llvm/CodeGen/SelectionDAG.h" 00021 #include "llvm/CodeGen/SSARegMap.h" 00022 #include "llvm/Constants.h" 00023 #include "llvm/Function.h" 00024 using namespace llvm; 00025 00026 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) 00027 : TargetLowering(TM) { 00028 00029 // register class for general registers 00030 addRegisterClass(MVT::i64, IA64::GRRegisterClass); 00031 00032 // register class for FP registers 00033 addRegisterClass(MVT::f64, IA64::FPRegisterClass); 00034 00035 // register class for predicate registers 00036 addRegisterClass(MVT::i1, IA64::PRRegisterClass); 00037 00038 setOperationAction(ISD::BRIND , MVT::i64, Expand); 00039 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 00040 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 00041 00042 // ia64 uses SELECT not SELECT_CC 00043 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 00044 00045 // We need to handle ISD::RET for void functions ourselves, 00046 // so we get a chance to restore ar.pfs before adding a 00047 // br.ret insn 00048 setOperationAction(ISD::RET, MVT::Other, Custom); 00049 00050 setSetCCResultType(MVT::i1); 00051 setShiftAmountType(MVT::i64); 00052 00053 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote); 00054 00055 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand); 00056 00057 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); 00058 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand); 00059 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand); 00060 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand); 00061 00062 setOperationAction(ISD::FREM , MVT::f32 , Expand); 00063 setOperationAction(ISD::FREM , MVT::f64 , Expand); 00064 00065 setOperationAction(ISD::UREM , MVT::f32 , Expand); 00066 setOperationAction(ISD::UREM , MVT::f64 , Expand); 00067 00068 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 00069 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 00070 setOperationAction(ISD::MEMCPY , MVT::Other, Expand); 00071 00072 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 00073 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 00074 00075 // We don't support sin/cos/sqrt 00076 setOperationAction(ISD::FSIN , MVT::f64, Expand); 00077 setOperationAction(ISD::FCOS , MVT::f64, Expand); 00078 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 00079 setOperationAction(ISD::FSIN , MVT::f32, Expand); 00080 setOperationAction(ISD::FCOS , MVT::f32, Expand); 00081 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 00082 00083 // FIXME: IA64 supports fcopysign natively! 00084 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 00085 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 00086 00087 // We don't have line number support yet. 00088 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 00089 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 00090 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 00091 00092 //IA64 has these, but they are not implemented 00093 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 00094 setOperationAction(ISD::CTLZ , MVT::i64 , Expand); 00095 setOperationAction(ISD::ROTL , MVT::i64 , Expand); 00096 setOperationAction(ISD::ROTR , MVT::i64 , Expand); 00097 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev 00098 00099 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 00100 setOperationAction(ISD::VAARG , MVT::Other, Custom); 00101 setOperationAction(ISD::VASTART , MVT::Other, Custom); 00102 00103 // Use the default implementation. 00104 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 00105 setOperationAction(ISD::VAEND , MVT::Other, Expand); 00106 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 00107 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 00108 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 00109 00110 setStackPointerRegisterToSaveRestore(IA64::r12); 00111 00112 computeRegisterProperties(); 00113 00114 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 00115 addLegalFPImmediate(+0.0); 00116 addLegalFPImmediate(+1.0); 00117 } 00118 00119 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const { 00120 switch (Opcode) { 00121 default: return 0; 00122 case IA64ISD::GETFD: return "IA64ISD::GETFD"; 00123 case IA64ISD::BRCALL: return "IA64ISD::BRCALL"; 00124 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG"; 00125 } 00126 } 00127 00128 00129 /// isFloatingPointZero - Return true if this is 0.0 or -0.0. 00130 static bool isFloatingPointZero(SDOperand Op) { 00131 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 00132 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 00133 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 00134 // Maybe this has already been legalized into the constant pool? 00135 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 00136 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 00137 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 00138 } 00139 return false; 00140 } 00141 00142 std::vector<SDOperand> 00143 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 00144 std::vector<SDOperand> ArgValues; 00145 // 00146 // add beautiful description of IA64 stack frame format 00147 // here (from intel 24535803.pdf most likely) 00148 // 00149 MachineFunction &MF = DAG.getMachineFunction(); 00150 MachineFrameInfo *MFI = MF.getFrameInfo(); 00151 00152 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); 00153 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); 00154 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); 00155 00156 MachineBasicBlock& BB = MF.front(); 00157 00158 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35, 00159 IA64::r36, IA64::r37, IA64::r38, IA64::r39}; 00160 00161 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11, 00162 IA64::F12,IA64::F13,IA64::F14, IA64::F15}; 00163 00164 unsigned argVreg[8]; 00165 unsigned argPreg[8]; 00166 unsigned argOpc[8]; 00167 00168 unsigned used_FPArgs = 0; // how many FP args have been used so far? 00169 00170 unsigned ArgOffset = 0; 00171 int count = 0; 00172 00173 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) 00174 { 00175 SDOperand newroot, argt; 00176 if(count < 8) { // need to fix this logic? maybe. 00177 00178 switch (getValueType(I->getType())) { 00179 default: 00180 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n"); 00181 case MVT::f32: 00182 // fixme? (well, will need to for weird FP structy stuff, 00183 // see intel ABI docs) 00184 case MVT::f64: 00185 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]); 00186 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn 00187 // floating point args go into f8..f15 as-needed, the increment 00188 argVreg[count] = // is below..: 00189 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64)); 00190 // FP args go into f8..f15 as needed: (hence the ++) 00191 argPreg[count] = args_FP[used_FPArgs++]; 00192 argOpc[count] = IA64::FMOV; 00193 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], 00194 MVT::f64); 00195 if (I->getType() == Type::FloatTy) 00196 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt); 00197 break; 00198 case MVT::i1: // NOTE: as far as C abi stuff goes, 00199 // bools are just boring old ints 00200 case MVT::i8: 00201 case MVT::i16: 00202 case MVT::i32: 00203 case MVT::i64: 00204 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]); 00205 MF.addLiveIn(args_int[count]); // mark this register as liveIn 00206 argVreg[count] = 00207 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); 00208 argPreg[count] = args_int[count]; 00209 argOpc[count] = IA64::MOV; 00210 argt = newroot = 00211 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64); 00212 if ( getValueType(I->getType()) != MVT::i64) 00213 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), 00214 newroot); 00215 break; 00216 } 00217 } else { // more than 8 args go into the frame 00218 // Create the frame index object for this incoming parameter... 00219 ArgOffset = 16 + 8 * (count - 8); 00220 int FI = MFI->CreateFixedObject(8, ArgOffset); 00221 00222 // Create the SelectionDAG nodes corresponding to a load 00223 //from this parameter 00224 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); 00225 argt = newroot = DAG.getLoad(getValueType(I->getType()), 00226 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); 00227 } 00228 ++count; 00229 DAG.setRoot(newroot.getValue(1)); 00230 ArgValues.push_back(argt); 00231 } 00232 00233 00234 // Create a vreg to hold the output of (what will become) 00235 // the "alloc" instruction 00236 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); 00237 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR); 00238 // we create a PSEUDO_ALLOC (pseudo)instruction for now 00239 /* 00240 BuildMI(&BB, IA64::IDEF, 0, IA64::r1); 00241 00242 // hmm: 00243 BuildMI(&BB, IA64::IDEF, 0, IA64::r12); 00244 BuildMI(&BB, IA64::IDEF, 0, IA64::rp); 00245 // ..hmm. 00246 00247 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1); 00248 00249 // hmm: 00250 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12); 00251 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp); 00252 // ..hmm. 00253 */ 00254 00255 unsigned tempOffset=0; 00256 00257 // if this is a varargs function, we simply lower llvm.va_start by 00258 // pointing to the first entry 00259 if(F.isVarArg()) { 00260 tempOffset=0; 00261 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset); 00262 } 00263 00264 // here we actually do the moving of args, and store them to the stack 00265 // too if this is a varargs function: 00266 for (int i = 0; i < count && i < 8; ++i) { 00267 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]); 00268 if(F.isVarArg()) { 00269 // if this is a varargs function, we copy the input registers to the stack 00270 int FI = MFI->CreateFixedObject(8, tempOffset); 00271 tempOffset+=8; //XXX: is it safe to use r22 like this? 00272 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI); 00273 // FIXME: we should use st8.spill here, one day 00274 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]); 00275 } 00276 } 00277 00278 // Finally, inform the code generator which regs we return values in. 00279 // (see the ISD::RET: case in the instruction selector) 00280 switch (getValueType(F.getReturnType())) { 00281 default: assert(0 && "i have no idea where to return this type!"); 00282 case MVT::isVoid: break; 00283 case MVT::i1: 00284 case MVT::i8: 00285 case MVT::i16: 00286 case MVT::i32: 00287 case MVT::i64: 00288 MF.addLiveOut(IA64::r8); 00289 break; 00290 case MVT::f32: 00291 case MVT::f64: 00292 MF.addLiveOut(IA64::F8); 00293 break; 00294 } 00295 00296 return ArgValues; 00297 } 00298 00299 std::pair<SDOperand, SDOperand> 00300 IA64TargetLowering::LowerCallTo(SDOperand Chain, 00301 const Type *RetTy, bool isVarArg, 00302 unsigned CallingConv, bool isTailCall, 00303 SDOperand Callee, ArgListTy &Args, 00304 SelectionDAG &DAG) { 00305 00306 MachineFunction &MF = DAG.getMachineFunction(); 00307 00308 unsigned NumBytes = 16; 00309 unsigned outRegsUsed = 0; 00310 00311 if (Args.size() > 8) { 00312 NumBytes += (Args.size() - 8) * 8; 00313 outRegsUsed = 8; 00314 } else { 00315 outRegsUsed = Args.size(); 00316 } 00317 00318 // FIXME? this WILL fail if we ever try to pass around an arg that 00319 // consumes more than a single output slot (a 'real' double, int128 00320 // some sort of aggregate etc.), as we'll underestimate how many 'outX' 00321 // registers we use. Hopefully, the assembler will notice. 00322 MF.getInfo<IA64FunctionInfo>()->outRegsUsed= 00323 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed); 00324 00325 // keep stack frame 16-byte aligned 00326 //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!"); 00327 NumBytes = (NumBytes+15) & ~15; 00328 00329 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); 00330 00331 SDOperand StackPtr, NullSV; 00332 std::vector<SDOperand> Stores; 00333 std::vector<SDOperand> Converts; 00334 std::vector<SDOperand> RegValuesToPass; 00335 unsigned ArgOffset = 16; 00336 00337 for (unsigned i = 0, e = Args.size(); i != e; ++i) 00338 { 00339 SDOperand Val = Args[i].first; 00340 MVT::ValueType ObjectVT = Val.getValueType(); 00341 SDOperand ValToStore(0, 0), ValToConvert(0, 0); 00342 unsigned ObjSize=8; 00343 switch (ObjectVT) { 00344 default: assert(0 && "unexpected argument type!"); 00345 case MVT::i1: 00346 case MVT::i8: 00347 case MVT::i16: 00348 case MVT::i32: 00349 //promote to 64-bits, sign/zero extending based on type 00350 //of the argument 00351 if(Args[i].second->isSigned()) 00352 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val); 00353 else 00354 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val); 00355 // XXX: fall through 00356 case MVT::i64: 00357 //ObjSize = 8; 00358 if(RegValuesToPass.size() >= 8) { 00359 ValToStore = Val; 00360 } else { 00361 RegValuesToPass.push_back(Val); 00362 } 00363 break; 00364 case MVT::f32: 00365 //promote to 64-bits 00366 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 00367 // XXX: fall through 00368 case MVT::f64: 00369 if(RegValuesToPass.size() >= 8) { 00370 ValToStore = Val; 00371 } else { 00372 RegValuesToPass.push_back(Val); 00373 if(1 /* TODO: if(calling external or varadic function)*/ ) { 00374 ValToConvert = Val; // additionally pass this FP value as an int 00375 } 00376 } 00377 break; 00378 } 00379 00380 if(ValToStore.Val) { 00381 if(!StackPtr.Val) { 00382 StackPtr = DAG.getRegister(IA64::r12, MVT::i64); 00383 NullSV = DAG.getSrcValue(NULL); 00384 } 00385 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 00386 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff); 00387 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 00388 ValToStore, PtrOff, NullSV)); 00389 ArgOffset += ObjSize; 00390 } 00391 00392 if(ValToConvert.Val) { 00393 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 00394 } 00395 } 00396 00397 // Emit all stores, make sure they occur before any copies into physregs. 00398 if (!Stores.empty()) 00399 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 00400 00401 static const unsigned IntArgRegs[] = { 00402 IA64::out0, IA64::out1, IA64::out2, IA64::out3, 00403 IA64::out4, IA64::out5, IA64::out6, IA64::out7 00404 }; 00405 00406 static const unsigned FPArgRegs[] = { 00407 IA64::F8, IA64::F9, IA64::F10, IA64::F11, 00408 IA64::F12, IA64::F13, IA64::F14, IA64::F15 00409 }; 00410 00411 SDOperand InFlag; 00412 00413 // save the current GP, SP and RP : FIXME: do we need to do all 3 always? 00414 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); 00415 Chain = GPBeforeCall.getValue(1); 00416 InFlag = Chain.getValue(2); 00417 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); 00418 Chain = SPBeforeCall.getValue(1); 00419 InFlag = Chain.getValue(2); 00420 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); 00421 Chain = RPBeforeCall.getValue(1); 00422 InFlag = Chain.getValue(2); 00423 00424 // Build a sequence of copy-to-reg nodes chained together with token chain 00425 // and flag operands which copy the outgoing integer args into regs out[0-7] 00426 // mapped 1:1 and the FP args into regs F8-F15 "lazily" 00427 // TODO: for performance, we should only copy FP args into int regs when we 00428 // know this is required (i.e. for varardic or external (unknown) functions) 00429 00430 // first to the FP->(integer representation) conversions, these are 00431 // flagged for now, but shouldn't have to be (TODO) 00432 unsigned seenConverts = 0; 00433 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 00434 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) { 00435 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag); 00436 InFlag = Chain.getValue(1); 00437 } 00438 } 00439 00440 // next copy args into the usual places, these are flagged 00441 unsigned usedFPArgs = 0; 00442 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 00443 Chain = DAG.getCopyToReg(Chain, 00444 MVT::isInteger(RegValuesToPass[i].getValueType()) ? 00445 IntArgRegs[i] : FPArgRegs[usedFPArgs++], 00446 RegValuesToPass[i], InFlag); 00447 InFlag = Chain.getValue(1); 00448 } 00449 00450 // If the callee is a GlobalAddress node (quite common, every direct call is) 00451 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 00452 /* 00453 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 00454 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64); 00455 } 00456 */ 00457 00458 std::vector<MVT::ValueType> NodeTys; 00459 std::vector<SDOperand> CallOperands; 00460 NodeTys.push_back(MVT::Other); // Returns a chain 00461 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 00462 CallOperands.push_back(Chain); 00463 CallOperands.push_back(Callee); 00464 00465 // emit the call itself 00466 if (InFlag.Val) 00467 CallOperands.push_back(InFlag); 00468 else 00469 assert(0 && "this should never happen!\n"); 00470 00471 // to make way for a hack: 00472 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys, CallOperands); 00473 InFlag = Chain.getValue(1); 00474 00475 // restore the GP, SP and RP after the call 00476 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag); 00477 InFlag = Chain.getValue(1); 00478 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag); 00479 InFlag = Chain.getValue(1); 00480 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag); 00481 InFlag = Chain.getValue(1); 00482 00483 std::vector<MVT::ValueType> RetVals; 00484 RetVals.push_back(MVT::Other); 00485 RetVals.push_back(MVT::Flag); 00486 00487 MVT::ValueType RetTyVT = getValueType(RetTy); 00488 SDOperand RetVal; 00489 if (RetTyVT != MVT::isVoid) { 00490 switch (RetTyVT) { 00491 default: assert(0 && "Unknown value type to return!"); 00492 case MVT::i1: { // bools are just like other integers (returned in r8) 00493 // we *could* fall through to the truncate below, but this saves a 00494 // few redundant predicate ops 00495 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); 00496 InFlag = boolInR8.getValue(2); 00497 Chain = boolInR8.getValue(1); 00498 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); 00499 InFlag = zeroReg.getValue(2); 00500 Chain = zeroReg.getValue(1); 00501 00502 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE); 00503 break; 00504 } 00505 case MVT::i8: 00506 case MVT::i16: 00507 case MVT::i32: 00508 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); 00509 Chain = RetVal.getValue(1); 00510 00511 // keep track of whether it is sign or zero extended (todo: bools?) 00512 /* XXX 00513 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 00514 MVT::i64, RetVal, DAG.getValueType(RetTyVT)); 00515 */ 00516 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 00517 break; 00518 case MVT::i64: 00519 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); 00520 Chain = RetVal.getValue(1); 00521 InFlag = RetVal.getValue(2); // XXX dead 00522 break; 00523 case MVT::f32: 00524 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); 00525 Chain = RetVal.getValue(1); 00526 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal); 00527 break; 00528 case MVT::f64: 00529 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); 00530 Chain = RetVal.getValue(1); 00531 InFlag = RetVal.getValue(2); // XXX dead 00532 break; 00533 } 00534 } 00535 00536 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 00537 DAG.getConstant(NumBytes, getPointerTy())); 00538 00539 return std::make_pair(RetVal, Chain); 00540 } 00541 00542 std::pair<SDOperand, SDOperand> IA64TargetLowering:: 00543 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 00544 SelectionDAG &DAG) { 00545 assert(0 && "LowerFrameReturnAddress unimplemented"); 00546 abort(); 00547 } 00548 00549 SDOperand IA64TargetLowering:: 00550 LowerOperation(SDOperand Op, SelectionDAG &DAG) { 00551 switch (Op.getOpcode()) { 00552 default: assert(0 && "Should not custom lower this!"); 00553 case ISD::RET: { 00554 SDOperand AR_PFSVal, Copy; 00555 00556 switch(Op.getNumOperands()) { 00557 default: 00558 assert(0 && "Do not know how to return this many arguments!"); 00559 abort(); 00560 case 1: 00561 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); 00562 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS, 00563 AR_PFSVal); 00564 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal); 00565 case 3: { 00566 // Copy the result into the output register & restore ar.pfs 00567 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 00568 unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8; 00569 00570 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); 00571 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), 00572 SDOperand()); 00573 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal, 00574 Copy.getValue(1)); 00575 std::vector<MVT::ValueType> NodeTys; 00576 std::vector<SDOperand> RetOperands; 00577 NodeTys.push_back(MVT::Other); 00578 NodeTys.push_back(MVT::Flag); 00579 RetOperands.push_back(AR_PFSVal); 00580 RetOperands.push_back(AR_PFSVal.getValue(1)); 00581 return DAG.getNode(IA64ISD::RET_FLAG, NodeTys, RetOperands); 00582 } 00583 } 00584 return SDOperand(); 00585 } 00586 case ISD::VAARG: { 00587 MVT::ValueType VT = getPointerTy(); 00588 SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), 00589 Op.getOperand(2)); 00590 // Increment the pointer, VAList, to the next vaarg 00591 SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, 00592 DAG.getConstant(MVT::getSizeInBits(VT)/8, 00593 VT)); 00594 // Store the incremented VAList to the legalized pointer 00595 VAIncr = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), VAIncr, 00596 Op.getOperand(1), Op.getOperand(2)); 00597 // Load the actual argument out of the pointer VAList 00598 return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0)); 00599 } 00600 case ISD::VASTART: { 00601 // vastart just stores the address of the VarArgsFrameIndex slot into the 00602 // memory location argument. 00603 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); 00604 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 00605 Op.getOperand(1), Op.getOperand(2)); 00606 } 00607 } 00608 }