LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // FR32 Register Class... 00013 static const unsigned FR32[] = { 00014 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 00015 }; 00016 00017 // FR64 Register Class... 00018 static const unsigned FR64[] = { 00019 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 00020 }; 00021 00022 // GR16 Register Class... 00023 static const unsigned GR16[] = { 00024 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 00025 }; 00026 00027 // GR16_ Register Class... 00028 static const unsigned GR16_[] = { 00029 X86::AX, X86::CX, X86::DX, X86::BX, 00030 }; 00031 00032 // GR32 Register Class... 00033 static const unsigned GR32[] = { 00034 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 00035 }; 00036 00037 // GR32_ Register Class... 00038 static const unsigned GR32_[] = { 00039 X86::EAX, X86::ECX, X86::EDX, X86::EBX, 00040 }; 00041 00042 // GR8 Register Class... 00043 static const unsigned GR8[] = { 00044 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 00045 }; 00046 00047 // RFP Register Class... 00048 static const unsigned RFP[] = { 00049 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 00050 }; 00051 00052 // RST Register Class... 00053 static const unsigned RST[] = { 00054 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 00055 }; 00056 00057 // VR128 Register Class... 00058 static const unsigned VR128[] = { 00059 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 00060 }; 00061 00062 // VR64 Register Class... 00063 static const unsigned VR64[] = { 00064 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 00065 }; 00066 00067 // FR32VTs Register Class Value Types... 00068 static const MVT::ValueType FR32VTs[] = { 00069 MVT::f32, MVT::Other 00070 }; 00071 00072 // FR64VTs Register Class Value Types... 00073 static const MVT::ValueType FR64VTs[] = { 00074 MVT::f64, MVT::Other 00075 }; 00076 00077 // GR16VTs Register Class Value Types... 00078 static const MVT::ValueType GR16VTs[] = { 00079 MVT::i16, MVT::Other 00080 }; 00081 00082 // GR16_VTs Register Class Value Types... 00083 static const MVT::ValueType GR16_VTs[] = { 00084 MVT::i16, MVT::Other 00085 }; 00086 00087 // GR32VTs Register Class Value Types... 00088 static const MVT::ValueType GR32VTs[] = { 00089 MVT::i32, MVT::Other 00090 }; 00091 00092 // GR32_VTs Register Class Value Types... 00093 static const MVT::ValueType GR32_VTs[] = { 00094 MVT::i32, MVT::Other 00095 }; 00096 00097 // GR8VTs Register Class Value Types... 00098 static const MVT::ValueType GR8VTs[] = { 00099 MVT::i8, MVT::Other 00100 }; 00101 00102 // RFPVTs Register Class Value Types... 00103 static const MVT::ValueType RFPVTs[] = { 00104 MVT::f64, MVT::Other 00105 }; 00106 00107 // RSTVTs Register Class Value Types... 00108 static const MVT::ValueType RSTVTs[] = { 00109 MVT::f64, MVT::Other 00110 }; 00111 00112 // VR128VTs Register Class Value Types... 00113 static const MVT::ValueType VR128VTs[] = { 00114 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other 00115 }; 00116 00117 // VR64VTs Register Class Value Types... 00118 static const MVT::ValueType VR64VTs[] = { 00119 MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other 00120 }; 00121 00122 } // end anonymous namespace 00123 00124 namespace X86 { // Register class instances 00125 FR32Class FR32RegClass; 00126 FR64Class FR64RegClass; 00127 GR16Class GR16RegClass; 00128 GR16_Class GR16_RegClass; 00129 GR32Class GR32RegClass; 00130 GR32_Class GR32_RegClass; 00131 GR8Class GR8RegClass; 00132 RFPClass RFPRegClass; 00133 RSTClass RSTRegClass; 00134 VR128Class VR128RegClass; 00135 VR64Class VR64RegClass; 00136 00137 // FR32 Register Class sub-classes... 00138 static const TargetRegisterClass* const FR32Subclasses [] = { 00139 NULL 00140 }; 00141 00142 // FR64 Register Class sub-classes... 00143 static const TargetRegisterClass* const FR64Subclasses [] = { 00144 NULL 00145 }; 00146 00147 // GR16 Register Class sub-classes... 00148 static const TargetRegisterClass* const GR16Subclasses [] = { 00149 &X86::GR16_RegClass, NULL 00150 }; 00151 00152 // GR16_ Register Class sub-classes... 00153 static const TargetRegisterClass* const GR16_Subclasses [] = { 00154 NULL 00155 }; 00156 00157 // GR32 Register Class sub-classes... 00158 static const TargetRegisterClass* const GR32Subclasses [] = { 00159 &X86::GR32_RegClass, NULL 00160 }; 00161 00162 // GR32_ Register Class sub-classes... 00163 static const TargetRegisterClass* const GR32_Subclasses [] = { 00164 NULL 00165 }; 00166 00167 // GR8 Register Class sub-classes... 00168 static const TargetRegisterClass* const GR8Subclasses [] = { 00169 NULL 00170 }; 00171 00172 // RFP Register Class sub-classes... 00173 static const TargetRegisterClass* const RFPSubclasses [] = { 00174 NULL 00175 }; 00176 00177 // RST Register Class sub-classes... 00178 static const TargetRegisterClass* const RSTSubclasses [] = { 00179 NULL 00180 }; 00181 00182 // VR128 Register Class sub-classes... 00183 static const TargetRegisterClass* const VR128Subclasses [] = { 00184 NULL 00185 }; 00186 00187 // VR64 Register Class sub-classes... 00188 static const TargetRegisterClass* const VR64Subclasses [] = { 00189 NULL 00190 }; 00191 00192 // FR32 Register Class super-classes... 00193 static const TargetRegisterClass* const FR32Superclasses [] = { 00194 NULL 00195 }; 00196 00197 // FR64 Register Class super-classes... 00198 static const TargetRegisterClass* const FR64Superclasses [] = { 00199 NULL 00200 }; 00201 00202 // GR16 Register Class super-classes... 00203 static const TargetRegisterClass* const GR16Superclasses [] = { 00204 NULL 00205 }; 00206 00207 // GR16_ Register Class super-classes... 00208 static const TargetRegisterClass* const GR16_Superclasses [] = { 00209 &X86::GR16RegClass, NULL 00210 }; 00211 00212 // GR32 Register Class super-classes... 00213 static const TargetRegisterClass* const GR32Superclasses [] = { 00214 NULL 00215 }; 00216 00217 // GR32_ Register Class super-classes... 00218 static const TargetRegisterClass* const GR32_Superclasses [] = { 00219 &X86::GR32RegClass, NULL 00220 }; 00221 00222 // GR8 Register Class super-classes... 00223 static const TargetRegisterClass* const GR8Superclasses [] = { 00224 NULL 00225 }; 00226 00227 // RFP Register Class super-classes... 00228 static const TargetRegisterClass* const RFPSuperclasses [] = { 00229 NULL 00230 }; 00231 00232 // RST Register Class super-classes... 00233 static const TargetRegisterClass* const RSTSuperclasses [] = { 00234 NULL 00235 }; 00236 00237 // VR128 Register Class super-classes... 00238 static const TargetRegisterClass* const VR128Superclasses [] = { 00239 NULL 00240 }; 00241 00242 // VR64 Register Class super-classes... 00243 static const TargetRegisterClass* const VR64Superclasses [] = { 00244 NULL 00245 }; 00246 00247 00248 FR32Class::FR32Class() : TargetRegisterClass(FR32RegClassID, FR32VTs, FR32Subclasses, FR32Superclasses, 4, 4, FR32, FR32 + 8) {} 00249 00250 FR64Class::FR64Class() : TargetRegisterClass(FR64RegClassID, FR64VTs, FR64Subclasses, FR64Superclasses, 8, 8, FR64, FR64 + 8) {} 00251 00252 GR16Class::iterator 00253 GR16Class::allocation_order_end(MachineFunction &MF) const { 00254 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? 00255 return end()-2; // If so, don't allocate SP or BP 00256 else 00257 return end()-1; // If not, just don't allocate SP 00258 } 00259 00260 GR16Class::GR16Class() : TargetRegisterClass(GR16RegClassID, GR16VTs, GR16Subclasses, GR16Superclasses, 2, 2, GR16, GR16 + 8) {} 00261 00262 GR16_Class::GR16_Class() : TargetRegisterClass(GR16_RegClassID, GR16_VTs, GR16_Subclasses, GR16_Superclasses, 2, 2, GR16_, GR16_ + 4) {} 00263 00264 GR32Class::iterator 00265 GR32Class::allocation_order_end(MachineFunction &MF) const { 00266 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? 00267 return end()-2; // If so, don't allocate ESP or EBP 00268 else 00269 return end()-1; // If not, just don't allocate ESP 00270 } 00271 00272 GR32Class::GR32Class() : TargetRegisterClass(GR32RegClassID, GR32VTs, GR32Subclasses, GR32Superclasses, 4, 4, GR32, GR32 + 8) {} 00273 00274 GR32_Class::GR32_Class() : TargetRegisterClass(GR32_RegClassID, GR32_VTs, GR32_Subclasses, GR32_Superclasses, 4, 4, GR32_, GR32_ + 4) {} 00275 00276 GR8Class::GR8Class() : TargetRegisterClass(GR8RegClassID, GR8VTs, GR8Subclasses, GR8Superclasses, 1, 1, GR8, GR8 + 8) {} 00277 00278 RFPClass::RFPClass() : TargetRegisterClass(RFPRegClassID, RFPVTs, RFPSubclasses, RFPSuperclasses, 8, 4, RFP, RFP + 7) {} 00279 00280 RSTClass::iterator 00281 RSTClass::allocation_order_end(MachineFunction &MF) const { 00282 return begin(); 00283 } 00284 00285 RSTClass::RSTClass() : TargetRegisterClass(RSTRegClassID, RSTVTs, RSTSubclasses, RSTSuperclasses, 8, 4, RST, RST + 8) {} 00286 00287 VR128Class::VR128Class() : TargetRegisterClass(VR128RegClassID, VR128VTs, VR128Subclasses, VR128Superclasses, 16, 16, VR128, VR128 + 8) {} 00288 00289 VR64Class::VR64Class() : TargetRegisterClass(VR64RegClassID, VR64VTs, VR64Subclasses, VR64Superclasses, 8, 8, VR64, VR64 + 8) {} 00290 } 00291 00292 namespace { 00293 const TargetRegisterClass* const RegisterClasses[] = { 00294 &X86::FR32RegClass, 00295 &X86::FR64RegClass, 00296 &X86::GR16RegClass, 00297 &X86::GR16_RegClass, 00298 &X86::GR32RegClass, 00299 &X86::GR32_RegClass, 00300 &X86::GR8RegClass, 00301 &X86::RFPRegClass, 00302 &X86::RSTRegClass, 00303 &X86::VR128RegClass, 00304 &X86::VR64RegClass, 00305 }; 00306 00307 00308 // Register Alias Sets... 00309 const unsigned Empty_AliasSet[] = { 0 }; 00310 const unsigned EAX_AliasSet[] = { X86::AX, X86::AL, X86::AH, 0 }; 00311 const unsigned ECX_AliasSet[] = { X86::CX, X86::CL, X86::CH, 0 }; 00312 const unsigned EDX_AliasSet[] = { X86::DX, X86::DL, X86::DH, 0 }; 00313 const unsigned EBX_AliasSet[] = { X86::BX, X86::BL, X86::BH, 0 }; 00314 const unsigned ESP_AliasSet[] = { X86::SP, 0 }; 00315 const unsigned EBP_AliasSet[] = { X86::BP, 0 }; 00316 const unsigned ESI_AliasSet[] = { X86::SI, 0 }; 00317 const unsigned EDI_AliasSet[] = { X86::DI, 0 }; 00318 const unsigned AX_AliasSet[] = { X86::EAX, X86::AL, X86::AH, 0 }; 00319 const unsigned CX_AliasSet[] = { X86::ECX, X86::CL, X86::CH, 0 }; 00320 const unsigned DX_AliasSet[] = { X86::EDX, X86::DL, X86::DH, 0 }; 00321 const unsigned BX_AliasSet[] = { X86::EBX, X86::BL, X86::BH, 0 }; 00322 const unsigned SP_AliasSet[] = { X86::ESP, 0 }; 00323 const unsigned BP_AliasSet[] = { X86::EBP, 0 }; 00324 const unsigned SI_AliasSet[] = { X86::ESI, 0 }; 00325 const unsigned DI_AliasSet[] = { X86::EDI, 0 }; 00326 const unsigned AL_AliasSet[] = { X86::EAX, X86::AX, 0 }; 00327 const unsigned CL_AliasSet[] = { X86::ECX, X86::CX, 0 }; 00328 const unsigned DL_AliasSet[] = { X86::EDX, X86::DX, 0 }; 00329 const unsigned BL_AliasSet[] = { X86::EBX, X86::BX, 0 }; 00330 const unsigned AH_AliasSet[] = { X86::EAX, X86::AX, 0 }; 00331 const unsigned CH_AliasSet[] = { X86::ECX, X86::CX, 0 }; 00332 const unsigned DH_AliasSet[] = { X86::EDX, X86::DX, 0 }; 00333 const unsigned BH_AliasSet[] = { X86::EBX, X86::BX, 0 }; 00334 00335 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00336 { "NOREG", 0 }, 00337 { "AH", AH_AliasSet }, 00338 { "AL", AL_AliasSet }, 00339 { "AX", AX_AliasSet }, 00340 { "BH", BH_AliasSet }, 00341 { "BL", BL_AliasSet }, 00342 { "BP", BP_AliasSet }, 00343 { "BX", BX_AliasSet }, 00344 { "CH", CH_AliasSet }, 00345 { "CL", CL_AliasSet }, 00346 { "CX", CX_AliasSet }, 00347 { "DH", DH_AliasSet }, 00348 { "DI", DI_AliasSet }, 00349 { "DL", DL_AliasSet }, 00350 { "DX", DX_AliasSet }, 00351 { "EAX", EAX_AliasSet }, 00352 { "EBP", EBP_AliasSet }, 00353 { "EBX", EBX_AliasSet }, 00354 { "ECX", ECX_AliasSet }, 00355 { "EDI", EDI_AliasSet }, 00356 { "EDX", EDX_AliasSet }, 00357 { "ESI", ESI_AliasSet }, 00358 { "ESP", ESP_AliasSet }, 00359 { "FP0", Empty_AliasSet }, 00360 { "FP1", Empty_AliasSet }, 00361 { "FP2", Empty_AliasSet }, 00362 { "FP3", Empty_AliasSet }, 00363 { "FP4", Empty_AliasSet }, 00364 { "FP5", Empty_AliasSet }, 00365 { "FP6", Empty_AliasSet }, 00366 { "MM0", Empty_AliasSet }, 00367 { "MM1", Empty_AliasSet }, 00368 { "MM2", Empty_AliasSet }, 00369 { "MM3", Empty_AliasSet }, 00370 { "MM4", Empty_AliasSet }, 00371 { "MM5", Empty_AliasSet }, 00372 { "MM6", Empty_AliasSet }, 00373 { "MM7", Empty_AliasSet }, 00374 { "SI", SI_AliasSet }, 00375 { "SP", SP_AliasSet }, 00376 { "ST(0)", Empty_AliasSet }, 00377 { "ST(1)", Empty_AliasSet }, 00378 { "ST(2)", Empty_AliasSet }, 00379 { "ST(3)", Empty_AliasSet }, 00380 { "ST(4)", Empty_AliasSet }, 00381 { "ST(5)", Empty_AliasSet }, 00382 { "ST(6)", Empty_AliasSet }, 00383 { "ST(7)", Empty_AliasSet }, 00384 { "XMM0", Empty_AliasSet }, 00385 { "XMM1", Empty_AliasSet }, 00386 { "XMM2", Empty_AliasSet }, 00387 { "XMM3", Empty_AliasSet }, 00388 { "XMM4", Empty_AliasSet }, 00389 { "XMM5", Empty_AliasSet }, 00390 { "XMM6", Empty_AliasSet }, 00391 { "XMM7", Empty_AliasSet }, 00392 }; 00393 } 00394 00395 X86GenRegisterInfo::X86GenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00396 : MRegisterInfo(RegisterDescriptors, 56, RegisterClasses, RegisterClasses+11, 00397 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00398 00399 int X86GenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00400 static const int DwarfRegNums[] = { -1, // NoRegister 00401 0, 0, 0, 3, 3, 6, 3, 2, 2, 2, 1, 5, 1, 1, 0, 6, 00402 3, 2, 5, 1, 4, 7, -1, -1, -1, -1, -1, -1, -1, 29, 30, 31, 00403 32, 33, 34, 35, 36, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 00404 22, 23, 24, 25, 26, 27, 28 00405 }; 00406 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00407 "RegNum exceeds number of registers"); 00408 return DwarfRegNums[RegNum]; 00409 } 00410 00411 } // End llvm namespace