LLVM API Documentation

AlphaGenInstrInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Target Instruction Descriptors
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 static const unsigned ImplicitList1[] = { Alpha::R29, 0 };
00012 static const unsigned ImplicitList2[] = { Alpha::R0, Alpha::R1, Alpha::R2, Alpha::R3, Alpha::R4, Alpha::R5, Alpha::R6, Alpha::R7, Alpha::R8, Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21, Alpha::R22, Alpha::R23, Alpha::R24, Alpha::R25, Alpha::R26, Alpha::R27, Alpha::R28, Alpha::R29, Alpha::F0, Alpha::F1, Alpha::F10, Alpha::F11, Alpha::F12, Alpha::F13, Alpha::F14, Alpha::F15, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21, Alpha::F22, Alpha::F23, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, 0 };
00013 static const unsigned ImplicitList3[] = { Alpha::R27, Alpha::R29, 0 };
00014 static const unsigned ImplicitList4[] = { Alpha::R24, Alpha::R25, Alpha::R27, 0 };
00015 static const unsigned ImplicitList5[] = { Alpha::R23, Alpha::R24, Alpha::R25, Alpha::R27, Alpha::R28, 0 };
00016 static const unsigned ImplicitList6[] = { Alpha::R28, 0 };
00017 static const unsigned ImplicitList7[] = { Alpha::R26, 0 };
00018 
00019 static const TargetOperandInfo OperandInfo2[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00020 static const TargetOperandInfo OperandInfo3[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, { 0, 0 }, };
00021 static const TargetOperandInfo OperandInfo4[] = { { Alpha::F4RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, };
00022 static const TargetOperandInfo OperandInfo5[] = { { Alpha::F8RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00023 static const TargetOperandInfo OperandInfo6[] = { { 0, 0 }, };
00024 static const TargetOperandInfo OperandInfo7[] = { { Alpha::GPRCRegClassID, 0 }, { 0, 0 }, };
00025 static const TargetOperandInfo OperandInfo8[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00026 static const TargetOperandInfo OperandInfo9[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, { 0, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00027 static const TargetOperandInfo OperandInfo10[] = { { Alpha::F4RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, };
00028 static const TargetOperandInfo OperandInfo11[] = { { Alpha::F8RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00029 static const TargetOperandInfo OperandInfo12[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00030 static const TargetOperandInfo OperandInfo13[] = { { Alpha::F4RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00031 static const TargetOperandInfo OperandInfo14[] = { { Alpha::F8RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00032 static const TargetOperandInfo OperandInfo15[] = { { Alpha::F8RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, };
00033 static const TargetOperandInfo OperandInfo16[] = { { Alpha::F8RCRegClassID, 0 }, { 0, 0 }, };
00034 static const TargetOperandInfo OperandInfo17[] = { { Alpha::F4RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00035 static const TargetOperandInfo OperandInfo18[] = { { Alpha::F8RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00036 static const TargetOperandInfo OperandInfo19[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, };
00037 static const TargetOperandInfo OperandInfo20[] = { { Alpha::GPRCRegClassID, 0 }, { Alpha::F8RCRegClassID, 0 }, };
00038 static const TargetOperandInfo OperandInfo21[] = { { Alpha::F4RCRegClassID, 0 }, };
00039 static const TargetOperandInfo OperandInfo22[] = { { Alpha::F8RCRegClassID, 0 }, };
00040 static const TargetOperandInfo OperandInfo23[] = { { Alpha::GPRCRegClassID, 0 }, };
00041 static const TargetOperandInfo OperandInfo24[] = { { Alpha::F4RCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00042 static const TargetOperandInfo OperandInfo25[] = { { Alpha::F8RCRegClassID, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00043 static const TargetOperandInfo OperandInfo26[] = { { Alpha::GPRCRegClassID, 0 }, { 0, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00044 static const TargetOperandInfo OperandInfo27[] = { { Alpha::GPRCRegClassID, 0 }, { 0, 0 }, { Alpha::GPRCRegClassID, 0 }, { 0, 0 }, };
00045 static const TargetOperandInfo OperandInfo28[] = { { Alpha::F4RCRegClassID, 0 }, { 0, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00046 static const TargetOperandInfo OperandInfo29[] = { { Alpha::F8RCRegClassID, 0 }, { 0, 0 }, { Alpha::GPRCRegClassID, 0 }, };
00047 static const TargetOperandInfo OperandInfo30[] = { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, };
00048 static const TargetOperandInfo OperandInfo31[] = { { Alpha::F4RCRegClassID, 0 }, { Alpha::F4RCRegClassID, 0 }, };
00049 
00050 static const TargetInstrDescriptor AlphaInsts[] = {
00051   { "PHI",  0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 },  // Inst #0 = PHI
00052   { "INLINEASM",  0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 },  // Inst #1 = INLINEASM
00053   { "ADDL", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #2 = ADDL
00054   { "ADDLi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #3 = ADDLi
00055   { "ADDQ", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #4 = ADDQ
00056   { "ADDQi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #5 = ADDQi
00057   { "ADDS", 3, 2, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #6 = ADDS
00058   { "ADDT", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #7 = ADDT
00059   { "ADJUSTSTACKDOWN",  1, 25, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo6 },  // Inst #8 = ADJUSTSTACKDOWN
00060   { "ADJUSTSTACKUP",  1, 25, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo6 },  // Inst #9 = ADJUSTSTACKUP
00061   { "ALTENT", 1, 25, 0, 0, NULL, NULL, OperandInfo6 },  // Inst #10 = ALTENT
00062   { "AND",  3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #11 = AND
00063   { "ANDi", 3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #12 = ANDi
00064   { "BEQ",  2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #13 = BEQ
00065   { "BGE",  2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #14 = BGE
00066   { "BGT",  2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #15 = BGT
00067   { "BIC",  3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #16 = BIC
00068   { "BICi", 3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #17 = BICi
00069   { "BIS",  3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #18 = BIS
00070   { "BISi", 3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #19 = BISi
00071   { "BLBC", 2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #20 = BLBC
00072   { "BLBS", 2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #21 = BLBS
00073   { "BLE",  2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #22 = BLE
00074   { "BLT",  2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #23 = BLT
00075   { "BNE",  2, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo7 },  // Inst #24 = BNE
00076   { "BR", 1, 28, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo6 },  // Inst #25 = BR
00077   { "BSR",  1, 22, 0|M_BRANCH_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo6 },  // Inst #26 = BSR
00078   { "CMOVEQ", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #27 = CMOVEQ
00079   { "CMOVEQi",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #28 = CMOVEQi
00080   { "CMOVGE", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #29 = CMOVGE
00081   { "CMOVGEi",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #30 = CMOVGEi
00082   { "CMOVGT", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #31 = CMOVGT
00083   { "CMOVGTi",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #32 = CMOVGTi
00084   { "CMOVLBC",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #33 = CMOVLBC
00085   { "CMOVLBCi", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #34 = CMOVLBCi
00086   { "CMOVLBS",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #35 = CMOVLBS
00087   { "CMOVLBSi", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #36 = CMOVLBSi
00088   { "CMOVLE", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #37 = CMOVLE
00089   { "CMOVLEi",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #38 = CMOVLEi
00090   { "CMOVLT", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #39 = CMOVLT
00091   { "CMOVLTi",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #40 = CMOVLTi
00092   { "CMOVNE", 4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo8 },  // Inst #41 = CMOVNE
00093   { "CMOVNEi",  4, 1, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo9 },  // Inst #42 = CMOVNEi
00094   { "CMPBGE", 3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #43 = CMPBGE
00095   { "CMPBGEi",  3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #44 = CMPBGEi
00096   { "CMPEQ",  3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #45 = CMPEQ
00097   { "CMPEQi", 3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #46 = CMPEQi
00098   { "CMPLE",  3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #47 = CMPLE
00099   { "CMPLEi", 3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #48 = CMPLEi
00100   { "CMPLT",  3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #49 = CMPLT
00101   { "CMPLTi", 3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #50 = CMPLTi
00102   { "CMPTEQ", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #51 = CMPTEQ
00103   { "CMPTLE", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #52 = CMPTLE
00104   { "CMPTLT", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #53 = CMPTLT
00105   { "CMPTUN", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #54 = CMPTUN
00106   { "CMPULE", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #55 = CMPULE
00107   { "CMPULEi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #56 = CMPULEi
00108   { "CMPULT", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #57 = CMPULT
00109   { "CMPULTi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #58 = CMPULTi
00110   { "CPYSES", 3, 2, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #59 = CPYSES
00111   { "CPYSESt",  3, 2, 0, 0, NULL, NULL, OperandInfo10 },  // Inst #60 = CPYSESt
00112   { "CPYSET", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #61 = CPYSET
00113   { "CPYSNS", 3, 2, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #62 = CPYSNS
00114   { "CPYSNSt",  3, 2, 0, 0, NULL, NULL, OperandInfo10 },  // Inst #63 = CPYSNSt
00115   { "CPYSNT", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #64 = CPYSNT
00116   { "CPYSNTs",  3, 2, 0, 0, NULL, NULL, OperandInfo11 },  // Inst #65 = CPYSNTs
00117   { "CPYSS",  3, 2, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #66 = CPYSS
00118   { "CPYSSt", 3, 2, 0, 0, NULL, NULL, OperandInfo10 },  // Inst #67 = CPYSSt
00119   { "CPYST",  3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #68 = CPYST
00120   { "CPYSTs", 3, 2, 0, 0, NULL, NULL, OperandInfo11 },  // Inst #69 = CPYSTs
00121   { "CTLZ", 2, 17, 0, 0, NULL, NULL, OperandInfo12 },  // Inst #70 = CTLZ
00122   { "CTPOP",  2, 17, 0, 0, NULL, NULL, OperandInfo12 },  // Inst #71 = CTPOP
00123   { "CTTZ", 2, 17, 0, 0, NULL, NULL, OperandInfo12 },  // Inst #72 = CTTZ
00124   { "CVTQS",  2, 2, 0, 0, NULL, NULL, OperandInfo13 },  // Inst #73 = CVTQS
00125   { "CVTQT",  2, 2, 0, 0, NULL, NULL, OperandInfo14 },  // Inst #74 = CVTQT
00126   { "CVTST",  2, 2, 0, 0, NULL, NULL, OperandInfo15 },  // Inst #75 = CVTST
00127   { "CVTTQ",  2, 2, 0, 0, NULL, NULL, OperandInfo14 },  // Inst #76 = CVTTQ
00128   { "CVTTS",  2, 2, 0, 0, NULL, NULL, OperandInfo13 },  // Inst #77 = CVTTS
00129   { "DIVS", 3, 5, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #78 = DIVS
00130   { "DIVT", 3, 6, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #79 = DIVT
00131   { "EQV",  3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #80 = EQV
00132   { "EQVi", 3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #81 = EQVi
00133   { "EXTBL",  3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #82 = EXTBL
00134   { "EXTLL",  3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #83 = EXTLL
00135   { "EXTWL",  3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #84 = EXTWL
00136   { "FBEQ", 2, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo16 },  // Inst #85 = FBEQ
00137   { "FBGE", 2, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo16 },  // Inst #86 = FBGE
00138   { "FBGT", 2, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo16 },  // Inst #87 = FBGT
00139   { "FBLE", 2, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo16 },  // Inst #88 = FBLE
00140   { "FBLT", 2, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo16 },  // Inst #89 = FBLT
00141   { "FBNE", 2, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo16 },  // Inst #90 = FBNE
00142   { "FCMOVEQS", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo17 },  // Inst #91 = FCMOVEQS
00143   { "FCMOVEQT", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo18 },  // Inst #92 = FCMOVEQT
00144   { "FCMOVGES", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo17 },  // Inst #93 = FCMOVGES
00145   { "FCMOVGET", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo18 },  // Inst #94 = FCMOVGET
00146   { "FCMOVGTS", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo17 },  // Inst #95 = FCMOVGTS
00147   { "FCMOVGTT", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo18 },  // Inst #96 = FCMOVGTT
00148   { "FCMOVLES", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo17 },  // Inst #97 = FCMOVLES
00149   { "FCMOVLET", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo18 },  // Inst #98 = FCMOVLET
00150   { "FCMOVLTS", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo17 },  // Inst #99 = FCMOVLTS
00151   { "FCMOVLTT", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo18 },  // Inst #100 = FCMOVLTT
00152   { "FCMOVNES", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo17 },  // Inst #101 = FCMOVNES
00153   { "FCMOVNET", 4, 4, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo18 },  // Inst #102 = FCMOVNET
00154   { "FTOIS",  2, 12, 0, 0, NULL, NULL, OperandInfo19 },  // Inst #103 = FTOIS
00155   { "FTOIT",  2, 12, 0, 0, NULL, NULL, OperandInfo20 },  // Inst #104 = FTOIT
00156   { "IDEF_F32", 1, 25, 0, 0, NULL, NULL, OperandInfo21 },  // Inst #105 = IDEF_F32
00157   { "IDEF_F64", 1, 25, 0, 0, NULL, NULL, OperandInfo22 },  // Inst #106 = IDEF_F64
00158   { "IDEF_I", 1, 25, 0, 0, NULL, NULL, OperandInfo23 },  // Inst #107 = IDEF_I
00159   { "ITOFS",  2, 21, 0, 0, NULL, NULL, OperandInfo24 },  // Inst #108 = ITOFS
00160   { "ITOFT",  2, 21, 0, 0, NULL, NULL, OperandInfo25 },  // Inst #109 = ITOFT
00161   { "JMP",  3, 22, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #110 = JMP
00162   { "JSR",  0, 22, 0|M_CALL_FLAG, 0, ImplicitList3, ImplicitList2, 0 },  // Inst #111 = JSR
00163   { "JSR_COROUTINE",  3, 22, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #112 = JSR_COROUTINE
00164   { "JSRs", 0, 22, 0|M_CALL_FLAG, 0, ImplicitList4, ImplicitList5, 0 },  // Inst #113 = JSRs
00165   { "LDA",  3, 23, 0, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #114 = LDA
00166   { "LDAH", 3, 23, 0, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #115 = LDAH
00167   { "LDAHg",  4, 23, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo27 },  // Inst #116 = LDAHg
00168   { "LDAHr",  3, 23, 0, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #117 = LDAHr
00169   { "LDAg", 4, 23, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo27 },  // Inst #118 = LDAg
00170   { "LDAr", 3, 23, 0, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #119 = LDAr
00171   { "LDBU", 3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #120 = LDBU
00172   { "LDBUr",  3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #121 = LDBUr
00173   { "LDL",  3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #122 = LDL
00174   { "LDLr", 3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #123 = LDLr
00175   { "LDQ",  3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #124 = LDQ
00176   { "LDQl", 3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #125 = LDQl
00177   { "LDQr", 3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #126 = LDQr
00178   { "LDS",  3, 7, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo28 },  // Inst #127 = LDS
00179   { "LDSr", 3, 7, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo28 },  // Inst #128 = LDSr
00180   { "LDT",  3, 7, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo29 },  // Inst #129 = LDT
00181   { "LDTr", 3, 7, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo29 },  // Inst #130 = LDTr
00182   { "LDWU", 3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #131 = LDWU
00183   { "LDWUr",  3, 15, 0|M_LOAD_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #132 = LDWUr
00184   { "MEMLABEL", 4, 25, 0, 0, NULL, NULL, OperandInfo30 },  // Inst #133 = MEMLABEL
00185   { "MULL", 3, 18, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #134 = MULL
00186   { "MULLi",  3, 18, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #135 = MULLi
00187   { "MULQ", 3, 18, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #136 = MULQ
00188   { "MULQi",  3, 18, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #137 = MULQi
00189   { "MULS", 3, 8, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #138 = MULS
00190   { "MULT", 3, 8, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #139 = MULT
00191   { "ORNOT",  3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #140 = ORNOT
00192   { "ORNOTi", 3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #141 = ORNOTi
00193   { "PCLABEL",  1, 25, 0, 0, NULL, NULL, OperandInfo6 },  // Inst #142 = PCLABEL
00194   { "RETDAG", 0, 22, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0, ImplicitList7, NULL, 0 },  // Inst #143 = RETDAG
00195   { "RETDAGp",  0, 22, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0, ImplicitList7, NULL, 0 },  // Inst #144 = RETDAGp
00196   { "RPCC", 1, 26, 0, 0, NULL, NULL, OperandInfo23 },  // Inst #145 = RPCC
00197   { "S4ADDL", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #146 = S4ADDL
00198   { "S4ADDLi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #147 = S4ADDLi
00199   { "S4ADDQ", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #148 = S4ADDQ
00200   { "S4ADDQi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #149 = S4ADDQi
00201   { "S4SUBL", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #150 = S4SUBL
00202   { "S4SUBLi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #151 = S4SUBLi
00203   { "S4SUBQ", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #152 = S4SUBQ
00204   { "S4SUBQi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #153 = S4SUBQi
00205   { "S8ADDL", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #154 = S8ADDL
00206   { "S8ADDLi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #155 = S8ADDLi
00207   { "S8ADDQ", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #156 = S8ADDQ
00208   { "S8ADDQi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #157 = S8ADDQi
00209   { "S8SUBL", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #158 = S8SUBL
00210   { "S8SUBLi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #159 = S8SUBLi
00211   { "S8SUBQ", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #160 = S8SUBQ
00212   { "S8SUBQi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #161 = S8SUBQi
00213   { "SEXTB",  2, 19, 0, 0, NULL, NULL, OperandInfo12 },  // Inst #162 = SEXTB
00214   { "SEXTW",  2, 19, 0, 0, NULL, NULL, OperandInfo12 },  // Inst #163 = SEXTW
00215   { "SL", 3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #164 = SL
00216   { "SLi",  3, 19, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #165 = SLi
00217   { "SQRTS",  2, 9, 0, 0, NULL, NULL, OperandInfo31 },  // Inst #166 = SQRTS
00218   { "SQRTT",  2, 10, 0, 0, NULL, NULL, OperandInfo14 },  // Inst #167 = SQRTT
00219   { "SRA",  3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #168 = SRA
00220   { "SRAi", 3, 19, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #169 = SRAi
00221   { "SRL",  3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #170 = SRL
00222   { "SRLi", 3, 19, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #171 = SRLi
00223   { "STB",  3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #172 = STB
00224   { "STBr", 3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #173 = STBr
00225   { "STL",  3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #174 = STL
00226   { "STLr", 3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #175 = STLr
00227   { "STQ",  3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #176 = STQ
00228   { "STQr", 3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #177 = STQr
00229   { "STS",  3, 11, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo28 },  // Inst #178 = STS
00230   { "STSr", 3, 11, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo28 },  // Inst #179 = STSr
00231   { "STT",  3, 11, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo29 },  // Inst #180 = STT
00232   { "STTr", 3, 11, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo29 },  // Inst #181 = STTr
00233   { "STW",  3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #182 = STW
00234   { "STWr", 3, 20, 0|M_STORE_FLAG, 0, NULL, ImplicitList6, OperandInfo26 },  // Inst #183 = STWr
00235   { "SUBL", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #184 = SUBL
00236   { "SUBLi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #185 = SUBLi
00237   { "SUBQ", 3, 13, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #186 = SUBQ
00238   { "SUBQi",  3, 13, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #187 = SUBQi
00239   { "SUBS", 3, 2, 0, 0, NULL, NULL, OperandInfo4 },  // Inst #188 = SUBS
00240   { "SUBT", 3, 2, 0, 0, NULL, NULL, OperandInfo5 },  // Inst #189 = SUBT
00241   { "UMULH",  3, 18, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #190 = UMULH
00242   { "UMULHi", 3, 18, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #191 = UMULHi
00243   { "WTF",  0, 25, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 },  // Inst #192 = WTF
00244   { "XOR",  3, 16, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #193 = XOR
00245   { "XORi", 3, 16, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #194 = XORi
00246   { "ZAP",  3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #195 = ZAP
00247   { "ZAPNOT", 3, 19, 0, 0, NULL, NULL, OperandInfo2 },  // Inst #196 = ZAPNOT
00248   { "ZAPNOTi",  3, 19, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #197 = ZAPNOTi
00249   { "ZAPi", 3, 19, 0, 0, NULL, NULL, OperandInfo3 },  // Inst #198 = ZAPi
00250 };
00251 } // End llvm namespace