LLVM API Documentation

X86GenRegisterInfo.h.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Register Information Header Fragment
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 #include "llvm/Target/MRegisterInfo.h"
00010 #include <string>
00011 
00012 namespace llvm {
00013 
00014 struct X86GenRegisterInfo : public MRegisterInfo {
00015   X86GenRegisterInfo(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
00016   int getDwarfRegNum(unsigned RegNum) const;
00017 };
00018 
00019 namespace X86 { // Register classes
00020   enum {
00021     FR32RegClassID = 1,
00022     FR64RegClassID,
00023     GR16RegClassID,
00024     GR16_RegClassID,
00025     GR32RegClassID,
00026     GR32_RegClassID,
00027     GR8RegClassID,
00028     RFPRegClassID,
00029     RSTRegClassID,
00030     VR128RegClassID,
00031     VR64RegClassID
00032   };
00033 
00034   struct FR32Class : public TargetRegisterClass {
00035     FR32Class();
00036   };
00037   extern FR32Class  FR32RegClass;
00038   static TargetRegisterClass * const FR32RegisterClass = &FR32RegClass;
00039   struct FR64Class : public TargetRegisterClass {
00040     FR64Class();
00041   };
00042   extern FR64Class  FR64RegClass;
00043   static TargetRegisterClass * const FR64RegisterClass = &FR64RegClass;
00044   struct GR16Class : public TargetRegisterClass {
00045     GR16Class();
00046 
00047     iterator allocation_order_end(MachineFunction &MF) const;
00048     };
00049   extern GR16Class  GR16RegClass;
00050   static TargetRegisterClass * const GR16RegisterClass = &GR16RegClass;
00051   struct GR16_Class : public TargetRegisterClass {
00052     GR16_Class();
00053   };
00054   extern GR16_Class GR16_RegClass;
00055   static TargetRegisterClass * const GR16_RegisterClass = &GR16_RegClass;
00056   struct GR32Class : public TargetRegisterClass {
00057     GR32Class();
00058 
00059     iterator allocation_order_end(MachineFunction &MF) const;
00060     };
00061   extern GR32Class  GR32RegClass;
00062   static TargetRegisterClass * const GR32RegisterClass = &GR32RegClass;
00063   struct GR32_Class : public TargetRegisterClass {
00064     GR32_Class();
00065   };
00066   extern GR32_Class GR32_RegClass;
00067   static TargetRegisterClass * const GR32_RegisterClass = &GR32_RegClass;
00068   struct GR8Class : public TargetRegisterClass {
00069     GR8Class();
00070   };
00071   extern GR8Class GR8RegClass;
00072   static TargetRegisterClass * const GR8RegisterClass = &GR8RegClass;
00073   struct RFPClass : public TargetRegisterClass {
00074     RFPClass();
00075   };
00076   extern RFPClass RFPRegClass;
00077   static TargetRegisterClass * const RFPRegisterClass = &RFPRegClass;
00078   struct RSTClass : public TargetRegisterClass {
00079     RSTClass();
00080 
00081     iterator allocation_order_end(MachineFunction &MF) const;
00082     };
00083   extern RSTClass RSTRegClass;
00084   static TargetRegisterClass * const RSTRegisterClass = &RSTRegClass;
00085   struct VR128Class : public TargetRegisterClass {
00086     VR128Class();
00087   };
00088   extern VR128Class VR128RegClass;
00089   static TargetRegisterClass * const VR128RegisterClass = &VR128RegClass;
00090   struct VR64Class : public TargetRegisterClass {
00091     VR64Class();
00092   };
00093   extern VR64Class  VR64RegClass;
00094   static TargetRegisterClass * const VR64RegisterClass = &VR64RegClass;
00095 } // end of namespace X86
00096 
00097 } // End llvm namespace