LLVM API Documentation
00001 //===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by Andrew Lenharth and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the AlphaISelLowering class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "AlphaISelLowering.h" 00015 #include "AlphaTargetMachine.h" 00016 #include "llvm/CodeGen/MachineFrameInfo.h" 00017 #include "llvm/CodeGen/MachineFunction.h" 00018 #include "llvm/CodeGen/MachineInstrBuilder.h" 00019 #include "llvm/CodeGen/SelectionDAG.h" 00020 #include "llvm/CodeGen/SSARegMap.h" 00021 #include "llvm/Constants.h" 00022 #include "llvm/Function.h" 00023 #include "llvm/Module.h" 00024 #include "llvm/Support/CommandLine.h" 00025 #include <iostream> 00026 00027 using namespace llvm; 00028 00029 /// AddLiveIn - This helper function adds the specified physical register to the 00030 /// MachineFunction as a live in value. It also creates a corresponding virtual 00031 /// register for it. 00032 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 00033 TargetRegisterClass *RC) { 00034 assert(RC->contains(PReg) && "Not the correct regclass!"); 00035 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 00036 MF.addLiveIn(PReg, VReg); 00037 return VReg; 00038 } 00039 00040 AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) { 00041 // Set up the TargetLowering object. 00042 //I am having problems with shr n ubyte 1 00043 setShiftAmountType(MVT::i64); 00044 setSetCCResultType(MVT::i64); 00045 setSetCCResultContents(ZeroOrOneSetCCResult); 00046 00047 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); 00048 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); 00049 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); 00050 00051 setOperationAction(ISD::BRIND, MVT::i64, Expand); 00052 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 00053 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 00054 00055 setOperationAction(ISD::EXTLOAD, MVT::i1, Promote); 00056 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 00057 00058 setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote); 00059 setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand); 00060 00061 setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote); 00062 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 00063 setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand); 00064 00065 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 00066 00067 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 00068 00069 setOperationAction(ISD::FREM, MVT::f32, Expand); 00070 setOperationAction(ISD::FREM, MVT::f64, Expand); 00071 00072 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 00073 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 00074 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 00075 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 00076 00077 if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) { 00078 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 00079 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 00080 setOperationAction(ISD::CTLZ , MVT::i64 , Expand); 00081 } 00082 setOperationAction(ISD::BSWAP , MVT::i64, Expand); 00083 setOperationAction(ISD::ROTL , MVT::i64, Expand); 00084 setOperationAction(ISD::ROTR , MVT::i64, Expand); 00085 00086 setOperationAction(ISD::SREM , MVT::i64, Custom); 00087 setOperationAction(ISD::UREM , MVT::i64, Custom); 00088 setOperationAction(ISD::SDIV , MVT::i64, Custom); 00089 setOperationAction(ISD::UDIV , MVT::i64, Custom); 00090 00091 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 00092 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 00093 setOperationAction(ISD::MEMCPY , MVT::Other, Expand); 00094 00095 // We don't support sin/cos/sqrt 00096 setOperationAction(ISD::FSIN , MVT::f64, Expand); 00097 setOperationAction(ISD::FCOS , MVT::f64, Expand); 00098 setOperationAction(ISD::FSIN , MVT::f32, Expand); 00099 setOperationAction(ISD::FCOS , MVT::f32, Expand); 00100 00101 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 00102 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 00103 00104 setOperationAction(ISD::SETCC, MVT::f32, Promote); 00105 00106 // We don't have line number support yet. 00107 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 00108 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 00109 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 00110 00111 // Not implemented yet. 00112 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 00113 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 00114 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 00115 00116 // We want to legalize GlobalAddress and ConstantPool and 00117 // ExternalSymbols nodes into the appropriate instructions to 00118 // materialize the address. 00119 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 00120 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 00121 setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom); 00122 00123 setOperationAction(ISD::VASTART, MVT::Other, Custom); 00124 setOperationAction(ISD::VAEND, MVT::Other, Expand); 00125 setOperationAction(ISD::VACOPY, MVT::Other, Custom); 00126 setOperationAction(ISD::VAARG, MVT::Other, Custom); 00127 setOperationAction(ISD::VAARG, MVT::i32, Custom); 00128 00129 setOperationAction(ISD::RET, MVT::Other, Custom); 00130 00131 setStackPointerRegisterToSaveRestore(Alpha::R30); 00132 00133 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 00134 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 00135 addLegalFPImmediate(+0.0); //F31 00136 addLegalFPImmediate(-0.0); //-F31 00137 00138 computeRegisterProperties(); 00139 00140 useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I(); 00141 } 00142 00143 const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { 00144 switch (Opcode) { 00145 default: return 0; 00146 case AlphaISD::ITOFT_: return "Alpha::ITOFT_"; 00147 case AlphaISD::FTOIT_: return "Alpha::FTOIT_"; 00148 case AlphaISD::CVTQT_: return "Alpha::CVTQT_"; 00149 case AlphaISD::CVTQS_: return "Alpha::CVTQS_"; 00150 case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_"; 00151 case AlphaISD::GPRelHi: return "Alpha::GPRelHi"; 00152 case AlphaISD::GPRelLo: return "Alpha::GPRelLo"; 00153 case AlphaISD::RelLit: return "Alpha::RelLit"; 00154 case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg"; 00155 case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr"; 00156 case AlphaISD::CALL: return "Alpha::CALL"; 00157 case AlphaISD::DivCall: return "Alpha::DivCall"; 00158 case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG"; 00159 } 00160 } 00161 00162 //http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21 00163 00164 //For now, just use variable size stack frame format 00165 00166 //In a standard call, the first six items are passed in registers $16 00167 //- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details 00168 //of argument-to-register correspondence.) The remaining items are 00169 //collected in a memory argument list that is a naturally aligned 00170 //array of quadwords. In a standard call, this list, if present, must 00171 //be passed at 0(SP). 00172 //7 ... n 0(SP) ... (n-7)*8(SP) 00173 00174 // //#define FP $15 00175 // //#define RA $26 00176 // //#define PV $27 00177 // //#define GP $29 00178 // //#define SP $30 00179 00180 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 00181 int &VarArgsBase, 00182 int &VarArgsOffset, 00183 unsigned int &GP, 00184 unsigned int &RA) { 00185 MachineFunction &MF = DAG.getMachineFunction(); 00186 MachineFrameInfo *MFI = MF.getFrameInfo(); 00187 SSARegMap *RegMap = MF.getSSARegMap(); 00188 std::vector<SDOperand> ArgValues; 00189 SDOperand Root = Op.getOperand(0); 00190 00191 GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); 00192 RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); 00193 00194 unsigned args_int[] = { 00195 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21}; 00196 unsigned args_float[] = { 00197 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21}; 00198 00199 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 00200 SDOperand argt; 00201 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 00202 SDOperand ArgVal; 00203 00204 if (ArgNo < 6) { 00205 unsigned Vreg; 00206 switch (ObjectVT) { 00207 default: 00208 std::cerr << "Unknown Type " << ObjectVT << "\n"; 00209 abort(); 00210 case MVT::f64: 00211 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], 00212 &Alpha::F8RCRegClass); 00213 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); 00214 break; 00215 case MVT::f32: 00216 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], 00217 &Alpha::F4RCRegClass); 00218 ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT); 00219 break; 00220 case MVT::i64: 00221 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], 00222 &Alpha::GPRCRegClass); 00223 ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64); 00224 break; 00225 } 00226 } else { //more args 00227 // Create the frame index object for this incoming parameter... 00228 int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6)); 00229 00230 // Create the SelectionDAG nodes corresponding to a load 00231 //from this parameter 00232 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); 00233 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL)); 00234 } 00235 ArgValues.push_back(ArgVal); 00236 } 00237 00238 // If the functions takes variable number of arguments, copy all regs to stack 00239 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 00240 if (isVarArg) { 00241 VarArgsOffset = (Op.Val->getNumValues()-1) * 8; 00242 std::vector<SDOperand> LS; 00243 for (int i = 0; i < 6; ++i) { 00244 if (MRegisterInfo::isPhysicalRegister(args_int[i])) 00245 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); 00246 SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); 00247 int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); 00248 if (i == 0) VarArgsBase = FI; 00249 SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); 00250 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt, 00251 SDFI, DAG.getSrcValue(NULL))); 00252 00253 if (MRegisterInfo::isPhysicalRegister(args_float[i])) 00254 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); 00255 argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); 00256 FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); 00257 SDFI = DAG.getFrameIndex(FI, MVT::i64); 00258 LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt, 00259 SDFI, DAG.getSrcValue(NULL))); 00260 } 00261 00262 //Set up a token factor with all the stack traffic 00263 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, LS); 00264 } 00265 00266 ArgValues.push_back(Root); 00267 00268 // Return the new list of results. 00269 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 00270 Op.Val->value_end()); 00271 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues); 00272 } 00273 00274 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) { 00275 SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, 00276 DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64), 00277 SDOperand()); 00278 switch (Op.getNumOperands()) { 00279 default: 00280 assert(0 && "Do not know how to return this many arguments!"); 00281 abort(); 00282 case 1: 00283 break; 00284 //return SDOperand(); // ret void is legal 00285 case 3: { 00286 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 00287 unsigned ArgReg; 00288 if (MVT::isInteger(ArgVT)) 00289 ArgReg = Alpha::R0; 00290 else { 00291 assert(MVT::isFloatingPoint(ArgVT)); 00292 ArgReg = Alpha::F0; 00293 } 00294 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); 00295 if(DAG.getMachineFunction().liveout_empty()) 00296 DAG.getMachineFunction().addLiveOut(ArgReg); 00297 break; 00298 } 00299 } 00300 return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 00301 } 00302 00303 std::pair<SDOperand, SDOperand> 00304 AlphaTargetLowering::LowerCallTo(SDOperand Chain, 00305 const Type *RetTy, bool isVarArg, 00306 unsigned CallingConv, bool isTailCall, 00307 SDOperand Callee, ArgListTy &Args, 00308 SelectionDAG &DAG) { 00309 int NumBytes = 0; 00310 if (Args.size() > 6) 00311 NumBytes = (Args.size() - 6) * 8; 00312 00313 Chain = DAG.getCALLSEQ_START(Chain, 00314 DAG.getConstant(NumBytes, getPointerTy())); 00315 std::vector<SDOperand> args_to_use; 00316 for (unsigned i = 0, e = Args.size(); i != e; ++i) 00317 { 00318 switch (getValueType(Args[i].second)) { 00319 default: assert(0 && "Unexpected ValueType for argument!"); 00320 case MVT::i1: 00321 case MVT::i8: 00322 case MVT::i16: 00323 case MVT::i32: 00324 // Promote the integer to 64 bits. If the input type is signed use a 00325 // sign extend, otherwise use a zero extend. 00326 if (Args[i].second->isSigned()) 00327 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first); 00328 else 00329 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first); 00330 break; 00331 case MVT::i64: 00332 case MVT::f64: 00333 case MVT::f32: 00334 break; 00335 } 00336 args_to_use.push_back(Args[i].first); 00337 } 00338 00339 std::vector<MVT::ValueType> RetVals; 00340 MVT::ValueType RetTyVT = getValueType(RetTy); 00341 MVT::ValueType ActualRetTyVT = RetTyVT; 00342 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32) 00343 ActualRetTyVT = MVT::i64; 00344 00345 if (RetTyVT != MVT::isVoid) 00346 RetVals.push_back(ActualRetTyVT); 00347 RetVals.push_back(MVT::Other); 00348 00349 std::vector<SDOperand> Ops; 00350 Ops.push_back(Chain); 00351 Ops.push_back(Callee); 00352 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); 00353 SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops); 00354 Chain = TheCall.getValue(RetTyVT != MVT::isVoid); 00355 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 00356 DAG.getConstant(NumBytes, getPointerTy())); 00357 SDOperand RetVal = TheCall; 00358 00359 if (RetTyVT != ActualRetTyVT) { 00360 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 00361 MVT::i64, RetVal, DAG.getValueType(RetTyVT)); 00362 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 00363 } 00364 00365 return std::make_pair(RetVal, Chain); 00366 } 00367 00368 void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB) 00369 { 00370 BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP); 00371 } 00372 void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB) 00373 { 00374 BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA); 00375 } 00376 00377 static int getUID() 00378 { 00379 static int id = 0; 00380 return ++id; 00381 } 00382 00383 /// LowerOperation - Provide custom lowering hooks for some operations. 00384 /// 00385 SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 00386 switch (Op.getOpcode()) { 00387 default: assert(0 && "Wasn't expecting to be able to lower this!"); 00388 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, 00389 VarArgsBase, 00390 VarArgsOffset, 00391 GP, RA); 00392 case ISD::RET: return LowerRET(Op,DAG, getVRegRA()); 00393 case ISD::SINT_TO_FP: { 00394 assert(MVT::i64 == Op.getOperand(0).getValueType() && 00395 "Unhandled SINT_TO_FP type in custom expander!"); 00396 SDOperand LD; 00397 bool isDouble = MVT::f64 == Op.getValueType(); 00398 if (useITOF) { 00399 LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0)); 00400 } else { 00401 int FrameIdx = 00402 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); 00403 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64); 00404 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 00405 Op.getOperand(0), FI, DAG.getSrcValue(0)); 00406 LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0)); 00407 } 00408 SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, 00409 isDouble?MVT::f64:MVT::f32, LD); 00410 return FP; 00411 } 00412 case ISD::FP_TO_SINT: { 00413 bool isDouble = MVT::f64 == Op.getOperand(0).getValueType(); 00414 SDOperand src = Op.getOperand(0); 00415 00416 if (!isDouble) //Promote 00417 src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src); 00418 00419 src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src); 00420 00421 if (useITOF) { 00422 return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src); 00423 } else { 00424 int FrameIdx = 00425 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); 00426 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64); 00427 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 00428 src, FI, DAG.getSrcValue(0)); 00429 return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0)); 00430 } 00431 } 00432 case ISD::ConstantPool: { 00433 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 00434 Constant *C = CP->get(); 00435 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); 00436 00437 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI, 00438 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); 00439 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi); 00440 return Lo; 00441 } 00442 case ISD::GlobalAddress: { 00443 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 00444 GlobalValue *GV = GSDN->getGlobal(); 00445 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); 00446 00447 // if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) { 00448 if (GV->hasInternalLinkage()) { 00449 SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA, 00450 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); 00451 SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi); 00452 return Lo; 00453 } else 00454 return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); 00455 } 00456 case ISD::ExternalSymbol: { 00457 return DAG.getNode(AlphaISD::RelLit, MVT::i64, 00458 DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64), 00459 DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64)); 00460 } 00461 00462 case ISD::UREM: 00463 case ISD::SREM: 00464 //Expand only on constant case 00465 if (Op.getOperand(1).getOpcode() == ISD::Constant) { 00466 MVT::ValueType VT = Op.Val->getValueType(0); 00467 unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 00468 SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? 00469 BuildUDIV(Op.Val, DAG, NULL) : 00470 BuildSDIV(Op.Val, DAG, NULL); 00471 Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); 00472 Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); 00473 return Tmp1; 00474 } 00475 //fall through 00476 case ISD::SDIV: 00477 case ISD::UDIV: 00478 if (MVT::isInteger(Op.getValueType())) { 00479 if (Op.getOperand(1).getOpcode() == ISD::Constant) 00480 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) 00481 : BuildUDIV(Op.Val, DAG, NULL); 00482 const char* opstr = 0; 00483 switch(Op.getOpcode()) { 00484 case ISD::UREM: opstr = "__remqu"; break; 00485 case ISD::SREM: opstr = "__remq"; break; 00486 case ISD::UDIV: opstr = "__divqu"; break; 00487 case ISD::SDIV: opstr = "__divq"; break; 00488 } 00489 SDOperand Tmp1 = Op.getOperand(0), 00490 Tmp2 = Op.getOperand(1), 00491 Addr = DAG.getExternalSymbol(opstr, MVT::i64); 00492 return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2); 00493 } 00494 break; 00495 00496 case ISD::VAARG: { 00497 SDOperand Chain = Op.getOperand(0); 00498 SDOperand VAListP = Op.getOperand(1); 00499 SDOperand VAListS = Op.getOperand(2); 00500 00501 SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS); 00502 SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, 00503 DAG.getConstant(8, MVT::i64)); 00504 SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), 00505 Tmp, DAG.getSrcValue(0), MVT::i32); 00506 SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); 00507 if (MVT::isFloatingPoint(Op.getValueType())) 00508 { 00509 //if fp && Offset < 6*8, then subtract 6*8 from DataPtr 00510 SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, 00511 DAG.getConstant(8*6, MVT::i64)); 00512 SDOperand CC = DAG.getSetCC(MVT::i64, Offset, 00513 DAG.getConstant(8*6, MVT::i64), ISD::SETLT); 00514 DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr); 00515 } 00516 00517 SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, 00518 DAG.getConstant(8, MVT::i64)); 00519 SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, 00520 Offset.getValue(1), NewOffset, 00521 Tmp, DAG.getSrcValue(0), 00522 DAG.getValueType(MVT::i32)); 00523 00524 SDOperand Result; 00525 if (Op.getValueType() == MVT::i32) 00526 Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr, 00527 DAG.getSrcValue(0), MVT::i32); 00528 else 00529 Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, 00530 DAG.getSrcValue(0)); 00531 return Result; 00532 } 00533 case ISD::VACOPY: { 00534 SDOperand Chain = Op.getOperand(0); 00535 SDOperand DestP = Op.getOperand(1); 00536 SDOperand SrcP = Op.getOperand(2); 00537 SDOperand DestS = Op.getOperand(3); 00538 SDOperand SrcS = Op.getOperand(4); 00539 00540 SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS); 00541 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val, 00542 DestP, DestS); 00543 SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, 00544 DAG.getConstant(8, MVT::i64)); 00545 Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, 00546 DAG.getSrcValue(0), MVT::i32); 00547 SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, 00548 DAG.getConstant(8, MVT::i64)); 00549 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1), 00550 Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32)); 00551 } 00552 case ISD::VASTART: { 00553 SDOperand Chain = Op.getOperand(0); 00554 SDOperand VAListP = Op.getOperand(1); 00555 SDOperand VAListS = Op.getOperand(2); 00556 00557 // vastart stores the address of the VarArgsBase and VarArgsOffset 00558 SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); 00559 SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 00560 VAListS); 00561 SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, 00562 DAG.getConstant(8, MVT::i64)); 00563 return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1, 00564 DAG.getConstant(VarArgsOffset, MVT::i64), SA2, 00565 DAG.getSrcValue(0), DAG.getValueType(MVT::i32)); 00566 } 00567 } 00568 00569 return SDOperand(); 00570 } 00571 00572 SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op, 00573 SelectionDAG &DAG) { 00574 assert(Op.getValueType() == MVT::i32 && 00575 Op.getOpcode() == ISD::VAARG && 00576 "Unknown node to custom promote!"); 00577 00578 // The code in LowerOperation already handles i32 vaarg 00579 return LowerOperation(Op, DAG); 00580 } 00581 00582 00583 //Inline Asm 00584 00585 /// getConstraintType - Given a constraint letter, return the type of 00586 /// constraint it is for this target. 00587 AlphaTargetLowering::ConstraintType 00588 AlphaTargetLowering::getConstraintType(char ConstraintLetter) const { 00589 switch (ConstraintLetter) { 00590 default: break; 00591 case 'f': 00592 case 'r': 00593 return C_RegisterClass; 00594 } 00595 return TargetLowering::getConstraintType(ConstraintLetter); 00596 } 00597 00598 std::vector<unsigned> AlphaTargetLowering:: 00599 getRegClassForInlineAsmConstraint(const std::string &Constraint, 00600 MVT::ValueType VT) const { 00601 if (Constraint.size() == 1) { 00602 switch (Constraint[0]) { 00603 default: break; // Unknown constriant letter 00604 case 'f': 00605 return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 , 00606 Alpha::F3 , Alpha::F4 , Alpha::F5 , 00607 Alpha::F6 , Alpha::F7 , Alpha::F8 , 00608 Alpha::F9 , Alpha::F10, Alpha::F11, 00609 Alpha::F12, Alpha::F13, Alpha::F14, 00610 Alpha::F15, Alpha::F16, Alpha::F17, 00611 Alpha::F18, Alpha::F19, Alpha::F20, 00612 Alpha::F21, Alpha::F22, Alpha::F23, 00613 Alpha::F24, Alpha::F25, Alpha::F26, 00614 Alpha::F27, Alpha::F28, Alpha::F29, 00615 Alpha::F30, Alpha::F31, 0); 00616 case 'r': 00617 return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 , 00618 Alpha::R3 , Alpha::R4 , Alpha::R5 , 00619 Alpha::R6 , Alpha::R7 , Alpha::R8 , 00620 Alpha::R9 , Alpha::R10, Alpha::R11, 00621 Alpha::R12, Alpha::R13, Alpha::R14, 00622 Alpha::R15, Alpha::R16, Alpha::R17, 00623 Alpha::R18, Alpha::R19, Alpha::R20, 00624 Alpha::R21, Alpha::R22, Alpha::R23, 00625 Alpha::R24, Alpha::R25, Alpha::R26, 00626 Alpha::R27, Alpha::R28, Alpha::R29, 00627 Alpha::R30, Alpha::R31, 0); 00628 00629 } 00630 } 00631 00632 return std::vector<unsigned>(); 00633 }