LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Machine Code Emitter 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 unsigned AlphaCodeEmitter::getBinaryCodeForInstr(MachineInstr &MI) { 00010 static const unsigned InstBits[] = { 00011 0U, 00012 0U, 00013 1073741824U, 00014 1073745920U, 00015 1073742848U, 00016 1073746944U, 00017 1476440064U, 00018 1476441088U, 00019 0U, 00020 0U, 00021 0U, 00022 1140850688U, 00023 1140854784U, 00024 3825205248U, 00025 4160749568U, 00026 4227858432U, 00027 1140850944U, 00028 1140855040U, 00029 1140851712U, 00030 1140855808U, 00031 3758096384U, 00032 4026531840U, 00033 3959422976U, 00034 3892314112U, 00035 4093640704U, 00036 3286237184U, 00037 3544186880U, 00038 1140851840U, 00039 1140855936U, 00040 1140852928U, 00041 1140857024U, 00042 1140853952U, 00043 1140858048U, 00044 1140851392U, 00045 1140855488U, 00046 1140851328U, 00047 1140855424U, 00048 1140853888U, 00049 1140857984U, 00050 1140852864U, 00051 1140856960U, 00052 1140851904U, 00053 1140856000U, 00054 1073742304U, 00055 1073746400U, 00056 1073743264U, 00057 1073747360U, 00058 1073745312U, 00059 1073749408U, 00060 1073744288U, 00061 1073748384U, 00062 1476441248U, 00063 1476441312U, 00064 1476441280U, 00065 1476441216U, 00066 1073743776U, 00067 1073747872U, 00068 1073742752U, 00069 1073746848U, 00070 1543504960U, 00071 1543504960U, 00072 1543504960U, 00073 1543504928U, 00074 1543504928U, 00075 1543504928U, 00076 1543504928U, 00077 1543504896U, 00078 1543504896U, 00079 1543504896U, 00080 1543504896U, 00081 1944061504U, 00082 1944061440U, 00083 1944061536U, 00084 1541470080U, 00085 1541470144U, 00086 1541461376U, 00087 1541449184U, 00088 1541469568U, 00089 1476440160U, 00090 1476441184U, 00091 1140852992U, 00092 1140857088U, 00093 1207959744U, 00094 1207960768U, 00095 1207960256U, 00096 3288334336U, 00097 3623878656U, 00098 3690987520U, 00099 3422552064U, 00100 3355443200U, 00101 3556769792U, 00102 1543505216U, 00103 1543505216U, 00104 1543505312U, 00105 1543505312U, 00106 1543505376U, 00107 1543505376U, 00108 1543505344U, 00109 1543505344U, 00110 1543505280U, 00111 1543505280U, 00112 1543505248U, 00113 1543505248U, 00114 1881083648U, 00115 1881083392U, 00116 0U, 00117 0U, 00118 0U, 00119 1344209024U, 00120 1344210048U, 00121 1744830464U, 00122 1801142272U, 00123 1744879616U, 00124 1794850816U, 00125 536870912U, 00126 603979776U, 00127 603979776U, 00128 603979776U, 00129 536870912U, 00130 536870912U, 00131 671088640U, 00132 671088640U, 00133 2684354560U, 00134 2684354560U, 00135 2751463424U, 00136 2751463424U, 00137 2751463424U, 00138 2281701376U, 00139 2281701376U, 00140 2348810240U, 00141 2348810240U, 00142 805306368U, 00143 805306368U, 00144 0U, 00145 1275068416U, 00146 1275072512U, 00147 1275069440U, 00148 1275073536U, 00149 1476440128U, 00150 1476441152U, 00151 1140851968U, 00152 1140856064U, 00153 0U, 00154 1811578881U, 00155 1811578881U, 00156 1610661888U, 00157 1073741888U, 00158 1073745984U, 00159 1073742912U, 00160 1073747008U, 00161 1073742176U, 00162 1073746272U, 00163 1073743200U, 00164 1073747296U, 00165 1073742400U, 00166 1073746496U, 00167 1073743424U, 00168 1073747520U, 00169 1073742688U, 00170 1073746784U, 00171 1073743712U, 00172 1073747808U, 00173 1944059904U, 00174 1944059936U, 00175 1207961376U, 00176 1207965472U, 00177 1407234400U, 00178 1407235424U, 00179 1207961472U, 00180 1207965568U, 00181 1207961216U, 00182 1207965312U, 00183 939524096U, 00184 939524096U, 00185 2952790016U, 00186 2952790016U, 00187 3019898880U, 00188 3019898880U, 00189 2550136832U, 00190 2550136832U, 00191 2617245696U, 00192 2617245696U, 00193 872415232U, 00194 872415232U, 00195 1073742112U, 00196 1073746208U, 00197 1073743136U, 00198 1073747232U, 00199 1476440096U, 00200 1476441120U, 00201 1275069952U, 00202 1275074048U, 00203 0U, 00204 1140852736U, 00205 1140856832U, 00206 1207961088U, 00207 1207961120U, 00208 1207965216U, 00209 1207965184U 00210 }; 00211 const unsigned opcode = MI.getOpcode(); 00212 unsigned Value = InstBits[opcode]; 00213 unsigned op; 00214 switch (opcode) { 00215 case Alpha::ADJUSTSTACKDOWN: 00216 case Alpha::ADJUSTSTACKUP: 00217 case Alpha::ALTENT: 00218 case Alpha::IDEF_F32: 00219 case Alpha::IDEF_F64: 00220 case Alpha::IDEF_I: 00221 case Alpha::JSR: 00222 case Alpha::JSRs: 00223 case Alpha::MEMLABEL: 00224 case Alpha::PCLABEL: 00225 case Alpha::RETDAG: 00226 case Alpha::RETDAGp: 00227 case Alpha::WTF: { 00228 break; 00229 } 00230 case Alpha::FTOIS: 00231 case Alpha::FTOIT: 00232 case Alpha::ITOFS: 00233 case Alpha::ITOFT: { 00234 // op: Fc 00235 op = getMachineOpValue(MI, MI.getOperand(0)); 00236 Value |= op & 31U; 00237 // op: Fa 00238 op = getMachineOpValue(MI, MI.getOperand(1)); 00239 Value |= (op & 31U) << 21; 00240 break; 00241 } 00242 case Alpha::ADDS: 00243 case Alpha::ADDT: 00244 case Alpha::CMPTEQ: 00245 case Alpha::CMPTLE: 00246 case Alpha::CMPTLT: 00247 case Alpha::CMPTUN: 00248 case Alpha::CPYSES: 00249 case Alpha::CPYSESt: 00250 case Alpha::CPYSET: 00251 case Alpha::CPYSNS: 00252 case Alpha::CPYSNSt: 00253 case Alpha::CPYSNT: 00254 case Alpha::CPYSNTs: 00255 case Alpha::CPYSS: 00256 case Alpha::CPYSSt: 00257 case Alpha::CPYST: 00258 case Alpha::CPYSTs: 00259 case Alpha::DIVS: 00260 case Alpha::DIVT: 00261 case Alpha::FCMOVEQS: 00262 case Alpha::FCMOVEQT: 00263 case Alpha::FCMOVGES: 00264 case Alpha::FCMOVGET: 00265 case Alpha::FCMOVGTS: 00266 case Alpha::FCMOVGTT: 00267 case Alpha::FCMOVLES: 00268 case Alpha::FCMOVLET: 00269 case Alpha::FCMOVLTS: 00270 case Alpha::FCMOVLTT: 00271 case Alpha::FCMOVNES: 00272 case Alpha::FCMOVNET: 00273 case Alpha::MULS: 00274 case Alpha::MULT: 00275 case Alpha::SUBS: 00276 case Alpha::SUBT: { 00277 // op: Fc 00278 op = getMachineOpValue(MI, MI.getOperand(0)); 00279 Value |= op & 31U; 00280 // op: Fa 00281 op = getMachineOpValue(MI, MI.getOperand(1)); 00282 Value |= (op & 31U) << 21; 00283 // op: Fb 00284 op = getMachineOpValue(MI, MI.getOperand(2)); 00285 Value |= (op & 31U) << 16; 00286 break; 00287 } 00288 case Alpha::CVTQS: 00289 case Alpha::CVTQT: 00290 case Alpha::CVTST: 00291 case Alpha::CVTTQ: 00292 case Alpha::CVTTS: 00293 case Alpha::SQRTS: 00294 case Alpha::SQRTT: { 00295 // op: Fc 00296 op = getMachineOpValue(MI, MI.getOperand(0)); 00297 Value |= op & 31U; 00298 // op: Fb 00299 op = getMachineOpValue(MI, MI.getOperand(1)); 00300 Value |= (op & 31U) << 16; 00301 break; 00302 } 00303 case Alpha::RPCC: { 00304 // op: Ra 00305 op = getMachineOpValue(MI, MI.getOperand(0)); 00306 Value |= (op & 31U) << 21; 00307 break; 00308 } 00309 case Alpha::JMP: 00310 case Alpha::JSR_COROUTINE: { 00311 // op: Ra 00312 op = getMachineOpValue(MI, MI.getOperand(0)); 00313 Value |= (op & 31U) << 21; 00314 // op: Rb 00315 op = getMachineOpValue(MI, MI.getOperand(1)); 00316 Value |= (op & 31U) << 16; 00317 // op: disp 00318 op = getMachineOpValue(MI, MI.getOperand(2)); 00319 Value |= op & 16383U; 00320 break; 00321 } 00322 case Alpha::BEQ: 00323 case Alpha::BGE: 00324 case Alpha::BGT: 00325 case Alpha::BLBC: 00326 case Alpha::BLBS: 00327 case Alpha::BLE: 00328 case Alpha::BLT: 00329 case Alpha::BNE: 00330 case Alpha::FBEQ: 00331 case Alpha::FBGE: 00332 case Alpha::FBGT: 00333 case Alpha::FBLE: 00334 case Alpha::FBLT: 00335 case Alpha::FBNE: { 00336 // op: Ra 00337 op = getMachineOpValue(MI, MI.getOperand(0)); 00338 Value |= (op & 31U) << 21; 00339 // op: disp 00340 op = getMachineOpValue(MI, MI.getOperand(1)); 00341 Value |= op & 2097151U; 00342 break; 00343 } 00344 case Alpha::LDA: 00345 case Alpha::LDAH: 00346 case Alpha::LDAHg: 00347 case Alpha::LDAHr: 00348 case Alpha::LDAg: 00349 case Alpha::LDAr: 00350 case Alpha::LDBU: 00351 case Alpha::LDBUr: 00352 case Alpha::LDL: 00353 case Alpha::LDLr: 00354 case Alpha::LDQ: 00355 case Alpha::LDQl: 00356 case Alpha::LDQr: 00357 case Alpha::LDS: 00358 case Alpha::LDSr: 00359 case Alpha::LDT: 00360 case Alpha::LDTr: 00361 case Alpha::LDWU: 00362 case Alpha::LDWUr: 00363 case Alpha::STB: 00364 case Alpha::STBr: 00365 case Alpha::STL: 00366 case Alpha::STLr: 00367 case Alpha::STQ: 00368 case Alpha::STQr: 00369 case Alpha::STS: 00370 case Alpha::STSr: 00371 case Alpha::STT: 00372 case Alpha::STTr: 00373 case Alpha::STW: 00374 case Alpha::STWr: { 00375 // op: Ra 00376 op = getMachineOpValue(MI, MI.getOperand(0)); 00377 Value |= (op & 31U) << 21; 00378 // op: disp 00379 op = getMachineOpValue(MI, MI.getOperand(1)); 00380 Value |= op & 65535U; 00381 // op: Rb 00382 op = getMachineOpValue(MI, MI.getOperand(2)); 00383 Value |= (op & 31U) << 16; 00384 break; 00385 } 00386 case Alpha::CMOVEQi: 00387 case Alpha::CMOVGEi: 00388 case Alpha::CMOVGTi: 00389 case Alpha::CMOVLBCi: 00390 case Alpha::CMOVLBSi: 00391 case Alpha::CMOVLEi: 00392 case Alpha::CMOVLTi: 00393 case Alpha::CMOVNEi: { 00394 // op: Rc 00395 op = getMachineOpValue(MI, MI.getOperand(0)); 00396 Value |= op & 31U; 00397 // op: LIT 00398 op = getMachineOpValue(MI, MI.getOperand(1)); 00399 Value |= (op & 255U) << 13; 00400 // op: Ra 00401 op = getMachineOpValue(MI, MI.getOperand(2)); 00402 Value |= (op & 31U) << 21; 00403 break; 00404 } 00405 case Alpha::ADDLi: 00406 case Alpha::ADDQi: 00407 case Alpha::ANDi: 00408 case Alpha::BICi: 00409 case Alpha::BISi: 00410 case Alpha::CMPBGEi: 00411 case Alpha::CMPEQi: 00412 case Alpha::CMPLEi: 00413 case Alpha::CMPLTi: 00414 case Alpha::CMPULEi: 00415 case Alpha::CMPULTi: 00416 case Alpha::EQVi: 00417 case Alpha::MULLi: 00418 case Alpha::MULQi: 00419 case Alpha::ORNOTi: 00420 case Alpha::S4ADDLi: 00421 case Alpha::S4ADDQi: 00422 case Alpha::S4SUBLi: 00423 case Alpha::S4SUBQi: 00424 case Alpha::S8ADDLi: 00425 case Alpha::S8ADDQi: 00426 case Alpha::S8SUBLi: 00427 case Alpha::S8SUBQi: 00428 case Alpha::SLi: 00429 case Alpha::SRAi: 00430 case Alpha::SRLi: 00431 case Alpha::SUBLi: 00432 case Alpha::SUBQi: 00433 case Alpha::UMULHi: 00434 case Alpha::XORi: 00435 case Alpha::ZAPNOTi: 00436 case Alpha::ZAPi: { 00437 // op: Rc 00438 op = getMachineOpValue(MI, MI.getOperand(0)); 00439 Value |= op & 31U; 00440 // op: Ra 00441 op = getMachineOpValue(MI, MI.getOperand(1)); 00442 Value |= (op & 31U) << 21; 00443 // op: LIT 00444 op = getMachineOpValue(MI, MI.getOperand(2)); 00445 Value |= (op & 255U) << 13; 00446 break; 00447 } 00448 case Alpha::ADDL: 00449 case Alpha::ADDQ: 00450 case Alpha::AND: 00451 case Alpha::BIC: 00452 case Alpha::BIS: 00453 case Alpha::CMPBGE: 00454 case Alpha::CMPEQ: 00455 case Alpha::CMPLE: 00456 case Alpha::CMPLT: 00457 case Alpha::CMPULE: 00458 case Alpha::CMPULT: 00459 case Alpha::EQV: 00460 case Alpha::EXTBL: 00461 case Alpha::EXTLL: 00462 case Alpha::EXTWL: 00463 case Alpha::MULL: 00464 case Alpha::MULQ: 00465 case Alpha::ORNOT: 00466 case Alpha::S4ADDL: 00467 case Alpha::S4ADDQ: 00468 case Alpha::S4SUBL: 00469 case Alpha::S4SUBQ: 00470 case Alpha::S8ADDL: 00471 case Alpha::S8ADDQ: 00472 case Alpha::S8SUBL: 00473 case Alpha::S8SUBQ: 00474 case Alpha::SL: 00475 case Alpha::SRA: 00476 case Alpha::SRL: 00477 case Alpha::SUBL: 00478 case Alpha::SUBQ: 00479 case Alpha::UMULH: 00480 case Alpha::XOR: 00481 case Alpha::ZAP: 00482 case Alpha::ZAPNOT: { 00483 // op: Rc 00484 op = getMachineOpValue(MI, MI.getOperand(0)); 00485 Value |= op & 31U; 00486 // op: Ra 00487 op = getMachineOpValue(MI, MI.getOperand(1)); 00488 Value |= (op & 31U) << 21; 00489 // op: Rb 00490 op = getMachineOpValue(MI, MI.getOperand(2)); 00491 Value |= (op & 31U) << 16; 00492 break; 00493 } 00494 case Alpha::CTLZ: 00495 case Alpha::CTPOP: 00496 case Alpha::CTTZ: 00497 case Alpha::SEXTB: 00498 case Alpha::SEXTW: { 00499 // op: Rc 00500 op = getMachineOpValue(MI, MI.getOperand(0)); 00501 Value |= op & 31U; 00502 // op: Rb 00503 op = getMachineOpValue(MI, MI.getOperand(1)); 00504 Value |= (op & 31U) << 16; 00505 break; 00506 } 00507 case Alpha::CMOVEQ: 00508 case Alpha::CMOVGE: 00509 case Alpha::CMOVGT: 00510 case Alpha::CMOVLBC: 00511 case Alpha::CMOVLBS: 00512 case Alpha::CMOVLE: 00513 case Alpha::CMOVLT: 00514 case Alpha::CMOVNE: { 00515 // op: Rc 00516 op = getMachineOpValue(MI, MI.getOperand(0)); 00517 Value |= op & 31U; 00518 // op: Rb 00519 op = getMachineOpValue(MI, MI.getOperand(1)); 00520 Value |= (op & 31U) << 16; 00521 // op: Ra 00522 op = getMachineOpValue(MI, MI.getOperand(2)); 00523 Value |= (op & 31U) << 21; 00524 break; 00525 } 00526 case Alpha::BR: 00527 case Alpha::BSR: { 00528 // op: disp 00529 op = getMachineOpValue(MI, MI.getOperand(0)); 00530 Value |= op & 2097151U; 00531 break; 00532 } 00533 default: 00534 std::cerr << "Not supported instr: " << MI << "\n"; 00535 abort(); 00536 } 00537 return Value; 00538 } 00539