LLVM API Documentation
ARMInstrInfo() | llvm::ARMInstrInfo | |
commuteInstruction(MachineInstr *MI) const | llvm::TargetInstrInfo | [virtual] |
convertToThreeAddress(MachineInstr *TA) const | llvm::TargetInstrInfo | [inline, virtual] |
get(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
getImplicitDefs(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
getImplicitUses(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
getName(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
getNumOpcodes() const | llvm::TargetInstrInfo | [inline] |
getNumOperands(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
getPointerRegClass() const | llvm::TargetInstrInfo | [inline, virtual] |
getRegisterInfo() const | llvm::ARMInstrInfo | [inline, virtual] |
getSchedClass(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
hasDelaySlot(unsigned Opcode) const | llvm::TargetInstrInfo | [inline] |
hasVariableOperands(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
INLINEASM enum value | llvm::TargetInstrInfo | |
insertGoto(MachineBasicBlock &MBB, MachineBasicBlock &TMBB) const | llvm::TargetInstrInfo | [inline, virtual] |
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const | llvm::TargetInstrInfo | [inline, virtual] |
isBarrier(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isBranch(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isCall(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isCommutableInstr(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isLoad(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const | llvm::TargetInstrInfo | [inline, virtual] |
isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const | llvm::ARMInstrInfo | [virtual] |
isReturn(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isStore(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const | llvm::TargetInstrInfo | [inline, virtual] |
isTerminatorInstr(unsigned Opcode) const | llvm::TargetInstrInfo | [inline] |
isTwoAddrInstr(MachineOpCode Opcode) const | llvm::TargetInstrInfo | [inline] |
PHI enum value | llvm::TargetInstrInfo | |
reverseBranchCondition(MachineBasicBlock::iterator MI) const | llvm::TargetInstrInfo | [inline, virtual] |
TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes) | llvm::TargetInstrInfo | |
usesCustomDAGSchedInsertionHook(unsigned Opcode) const | llvm::TargetInstrInfo | [inline] |
~TargetInstrInfo() | llvm::TargetInstrInfo | [virtual] |