LLVM API Documentation
00001 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the PowerPC implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "PPCInstrInfo.h" 00015 #include "PPCGenInstrInfo.inc" 00016 #include "PPCTargetMachine.h" 00017 #include "llvm/CodeGen/MachineInstrBuilder.h" 00018 #include <iostream> 00019 using namespace llvm; 00020 00021 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 00022 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm), 00023 RI(*TM.getSubtargetImpl()) {} 00024 00025 /// getPointerRegClass - Return the register class to use to hold pointers. 00026 /// This is used for addressing modes. 00027 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const { 00028 if (TM.getSubtargetImpl()->isPPC64()) 00029 return &PPC::G8RCRegClass; 00030 else 00031 return &PPC::GPRCRegClass; 00032 } 00033 00034 00035 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 00036 unsigned& sourceReg, 00037 unsigned& destReg) const { 00038 MachineOpCode oc = MI.getOpcode(); 00039 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || 00040 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 00041 assert(MI.getNumOperands() == 3 && 00042 MI.getOperand(0).isRegister() && 00043 MI.getOperand(1).isRegister() && 00044 MI.getOperand(2).isRegister() && 00045 "invalid PPC OR instruction!"); 00046 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 00047 sourceReg = MI.getOperand(1).getReg(); 00048 destReg = MI.getOperand(0).getReg(); 00049 return true; 00050 } 00051 } else if (oc == PPC::ADDI) { // addi r1, r2, 0 00052 assert(MI.getNumOperands() == 3 && 00053 MI.getOperand(0).isRegister() && 00054 MI.getOperand(2).isImmediate() && 00055 "invalid PPC ADDI instruction!"); 00056 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { 00057 sourceReg = MI.getOperand(1).getReg(); 00058 destReg = MI.getOperand(0).getReg(); 00059 return true; 00060 } 00061 } else if (oc == PPC::ORI) { // ori r1, r2, 0 00062 assert(MI.getNumOperands() == 3 && 00063 MI.getOperand(0).isRegister() && 00064 MI.getOperand(1).isRegister() && 00065 MI.getOperand(2).isImmediate() && 00066 "invalid PPC ORI instruction!"); 00067 if (MI.getOperand(2).getImmedValue()==0) { 00068 sourceReg = MI.getOperand(1).getReg(); 00069 destReg = MI.getOperand(0).getReg(); 00070 return true; 00071 } 00072 } else if (oc == PPC::FMRS || oc == PPC::FMRD || 00073 oc == PPC::FMRSD) { // fmr r1, r2 00074 assert(MI.getNumOperands() == 2 && 00075 MI.getOperand(0).isRegister() && 00076 MI.getOperand(1).isRegister() && 00077 "invalid PPC FMR instruction"); 00078 sourceReg = MI.getOperand(1).getReg(); 00079 destReg = MI.getOperand(0).getReg(); 00080 return true; 00081 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 00082 assert(MI.getNumOperands() == 2 && 00083 MI.getOperand(0).isRegister() && 00084 MI.getOperand(1).isRegister() && 00085 "invalid PPC MCRF instruction"); 00086 sourceReg = MI.getOperand(1).getReg(); 00087 destReg = MI.getOperand(0).getReg(); 00088 return true; 00089 } 00090 return false; 00091 } 00092 00093 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 00094 int &FrameIndex) const { 00095 switch (MI->getOpcode()) { 00096 default: break; 00097 case PPC::LD: 00098 case PPC::LWZ: 00099 case PPC::LFS: 00100 case PPC::LFD: 00101 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 00102 MI->getOperand(2).isFrameIndex()) { 00103 FrameIndex = MI->getOperand(2).getFrameIndex(); 00104 return MI->getOperand(0).getReg(); 00105 } 00106 break; 00107 } 00108 return 0; 00109 } 00110 00111 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 00112 int &FrameIndex) const { 00113 switch (MI->getOpcode()) { 00114 default: break; 00115 case PPC::STD: 00116 case PPC::STW: 00117 case PPC::STFS: 00118 case PPC::STFD: 00119 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 00120 MI->getOperand(2).isFrameIndex()) { 00121 FrameIndex = MI->getOperand(2).getFrameIndex(); 00122 return MI->getOperand(0).getReg(); 00123 } 00124 break; 00125 } 00126 return 0; 00127 } 00128 00129 // commuteInstruction - We can commute rlwimi instructions, but only if the 00130 // rotate amt is zero. We also have to munge the immediates a bit. 00131 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { 00132 // Normal instructions can be commuted the obvious way. 00133 if (MI->getOpcode() != PPC::RLWIMI) 00134 return TargetInstrInfo::commuteInstruction(MI); 00135 00136 // Cannot commute if it has a non-zero rotate count. 00137 if (MI->getOperand(3).getImmedValue() != 0) 00138 return 0; 00139 00140 // If we have a zero rotate count, we have: 00141 // M = mask(MB,ME) 00142 // Op0 = (Op1 & ~M) | (Op2 & M) 00143 // Change this to: 00144 // M = mask((ME+1)&31, (MB-1)&31) 00145 // Op0 = (Op2 & ~M) | (Op1 & M) 00146 00147 // Swap op1/op2 00148 unsigned Reg1 = MI->getOperand(1).getReg(); 00149 unsigned Reg2 = MI->getOperand(2).getReg(); 00150 MI->getOperand(2).setReg(Reg1); 00151 MI->getOperand(1).setReg(Reg2); 00152 00153 // Swap the mask around. 00154 unsigned MB = MI->getOperand(4).getImmedValue(); 00155 unsigned ME = MI->getOperand(5).getImmedValue(); 00156 MI->getOperand(4).setImmedValue((ME+1) & 31); 00157 MI->getOperand(5).setImmedValue((MB-1) & 31); 00158 return MI; 00159 } 00160 00161 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 00162 MachineBasicBlock::iterator MI) const { 00163 BuildMI(MBB, MI, PPC::NOP, 0); 00164 }