LLVM API Documentation
00001 //===-- X86IntelAsmPrinter.h - Convert X86 LLVM code to Intel assembly ----===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // Intel assembly code printer class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef X86INTELASMPRINTER_H 00015 #define X86INTELASMPRINTER_H 00016 00017 #include "X86AsmPrinter.h" 00018 #include "llvm/CodeGen/ValueTypes.h" 00019 #include "llvm/Target/MRegisterInfo.h" 00020 00021 namespace llvm { 00022 00023 struct X86IntelAsmPrinter : public X86SharedAsmPrinter { 00024 X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM); 00025 00026 virtual const char *getPassName() const { 00027 return "X86 Intel-Style Assembly Printer"; 00028 } 00029 00030 /// printInstruction - This method is automatically generated by tablegen 00031 /// from the instruction set description. This method returns true if the 00032 /// machine instruction was sufficiently described to print it, otherwise it 00033 /// returns false. 00034 bool printInstruction(const MachineInstr *MI); 00035 00036 // This method is used by the tablegen'erated instruction printer. 00037 void printOperand(const MachineInstr *MI, unsigned OpNo, 00038 const char *Modifier = 0) { 00039 const MachineOperand &MO = MI->getOperand(OpNo); 00040 if (MO.isRegister()) { 00041 assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??"); 00042 O << TM.getRegisterInfo()->get(MO.getReg()).Name; 00043 } else { 00044 printOp(MO, Modifier); 00045 } 00046 } 00047 00048 void printi8mem(const MachineInstr *MI, unsigned OpNo) { 00049 O << "BYTE PTR "; 00050 printMemReference(MI, OpNo); 00051 } 00052 void printi16mem(const MachineInstr *MI, unsigned OpNo) { 00053 O << "WORD PTR "; 00054 printMemReference(MI, OpNo); 00055 } 00056 void printi32mem(const MachineInstr *MI, unsigned OpNo) { 00057 O << "DWORD PTR "; 00058 printMemReference(MI, OpNo); 00059 } 00060 void printi64mem(const MachineInstr *MI, unsigned OpNo) { 00061 O << "QWORD PTR "; 00062 printMemReference(MI, OpNo); 00063 } 00064 void printi128mem(const MachineInstr *MI, unsigned OpNo) { 00065 O << "XMMWORD PTR "; 00066 printMemReference(MI, OpNo); 00067 } 00068 void printf32mem(const MachineInstr *MI, unsigned OpNo) { 00069 O << "DWORD PTR "; 00070 printMemReference(MI, OpNo); 00071 } 00072 void printf64mem(const MachineInstr *MI, unsigned OpNo) { 00073 O << "QWORD PTR "; 00074 printMemReference(MI, OpNo); 00075 } 00076 void printf128mem(const MachineInstr *MI, unsigned OpNo) { 00077 O << "XMMWORD PTR "; 00078 printMemReference(MI, OpNo); 00079 } 00080 00081 bool printAsmMRegister(const MachineOperand &MO, const char Mode); 00082 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 00083 unsigned AsmVariant, const char *ExtraCode); 00084 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, 00085 unsigned AsmVariant, const char *ExtraCode); 00086 void printMachineInstruction(const MachineInstr *MI); 00087 void printOp(const MachineOperand &MO, const char *Modifier = 0); 00088 void printSSECC(const MachineInstr *MI, unsigned Op); 00089 void printMemReference(const MachineInstr *MI, unsigned Op); 00090 void printPICLabel(const MachineInstr *MI, unsigned Op); 00091 bool runOnMachineFunction(MachineFunction &F); 00092 bool doInitialization(Module &M); 00093 bool doFinalization(Module &M); 00094 00095 virtual void EmitString(const ConstantArray *CVA) const; 00096 }; 00097 00098 } // end namespace llvm 00099 00100 #endif