LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // CRRC Register Class... 00013 static const unsigned CRRC[] = { 00014 PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4, 00015 }; 00016 00017 // F4RC Register Class... 00018 static const unsigned F4RC[] = { 00019 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 00020 }; 00021 00022 // F8RC Register Class... 00023 static const unsigned F8RC[] = { 00024 PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 00025 }; 00026 00027 // G8RC Register Class... 00028 static const unsigned G8RC[] = { 00029 PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X31, PPC::X0, PPC::X1, 00030 }; 00031 00032 // GPRC Register Class... 00033 static const unsigned GPRC[] = { 00034 PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::LR, 00035 }; 00036 00037 // VRRC Register Class... 00038 static const unsigned VRRC[] = { 00039 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 00040 }; 00041 00042 // CRRCVTs Register Class Value Types... 00043 static const MVT::ValueType CRRCVTs[] = { 00044 MVT::i32, MVT::Other 00045 }; 00046 00047 // F4RCVTs Register Class Value Types... 00048 static const MVT::ValueType F4RCVTs[] = { 00049 MVT::f32, MVT::Other 00050 }; 00051 00052 // F8RCVTs Register Class Value Types... 00053 static const MVT::ValueType F8RCVTs[] = { 00054 MVT::f64, MVT::Other 00055 }; 00056 00057 // G8RCVTs Register Class Value Types... 00058 static const MVT::ValueType G8RCVTs[] = { 00059 MVT::i64, MVT::Other 00060 }; 00061 00062 // GPRCVTs Register Class Value Types... 00063 static const MVT::ValueType GPRCVTs[] = { 00064 MVT::i32, MVT::Other 00065 }; 00066 00067 // VRRCVTs Register Class Value Types... 00068 static const MVT::ValueType VRRCVTs[] = { 00069 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::Other 00070 }; 00071 00072 } // end anonymous namespace 00073 00074 namespace PPC { // Register class instances 00075 CRRCClass CRRCRegClass; 00076 F4RCClass F4RCRegClass; 00077 F8RCClass F8RCRegClass; 00078 G8RCClass G8RCRegClass; 00079 GPRCClass GPRCRegClass; 00080 VRRCClass VRRCRegClass; 00081 00082 // CRRC Register Class sub-classes... 00083 static const TargetRegisterClass* const CRRCSubclasses [] = { 00084 NULL 00085 }; 00086 00087 // F4RC Register Class sub-classes... 00088 static const TargetRegisterClass* const F4RCSubclasses [] = { 00089 NULL 00090 }; 00091 00092 // F8RC Register Class sub-classes... 00093 static const TargetRegisterClass* const F8RCSubclasses [] = { 00094 NULL 00095 }; 00096 00097 // G8RC Register Class sub-classes... 00098 static const TargetRegisterClass* const G8RCSubclasses [] = { 00099 NULL 00100 }; 00101 00102 // GPRC Register Class sub-classes... 00103 static const TargetRegisterClass* const GPRCSubclasses [] = { 00104 NULL 00105 }; 00106 00107 // VRRC Register Class sub-classes... 00108 static const TargetRegisterClass* const VRRCSubclasses [] = { 00109 NULL 00110 }; 00111 00112 // CRRC Register Class super-classes... 00113 static const TargetRegisterClass* const CRRCSuperclasses [] = { 00114 NULL 00115 }; 00116 00117 // F4RC Register Class super-classes... 00118 static const TargetRegisterClass* const F4RCSuperclasses [] = { 00119 NULL 00120 }; 00121 00122 // F8RC Register Class super-classes... 00123 static const TargetRegisterClass* const F8RCSuperclasses [] = { 00124 NULL 00125 }; 00126 00127 // G8RC Register Class super-classes... 00128 static const TargetRegisterClass* const G8RCSuperclasses [] = { 00129 NULL 00130 }; 00131 00132 // GPRC Register Class super-classes... 00133 static const TargetRegisterClass* const GPRCSuperclasses [] = { 00134 NULL 00135 }; 00136 00137 // VRRC Register Class super-classes... 00138 static const TargetRegisterClass* const VRRCSuperclasses [] = { 00139 NULL 00140 }; 00141 00142 00143 CRRCClass::CRRCClass() : TargetRegisterClass(CRRCRegClassID, CRRCVTs, CRRCSubclasses, CRRCSuperclasses, 4, 4, CRRC, CRRC + 8) {} 00144 00145 F4RCClass::F4RCClass() : TargetRegisterClass(F4RCRegClassID, F4RCVTs, F4RCSubclasses, F4RCSuperclasses, 4, 4, F4RC, F4RC + 32) {} 00146 00147 F8RCClass::F8RCClass() : TargetRegisterClass(F8RCRegClassID, F8RCVTs, F8RCSubclasses, F8RCSuperclasses, 8, 8, F8RC, F8RC + 32) {} 00148 00149 G8RCClass::iterator 00150 G8RCClass::allocation_order_begin(MachineFunction &MF) const { 00151 return begin(); 00152 } 00153 G8RCClass::iterator 00154 G8RCClass::allocation_order_end(MachineFunction &MF) const { 00155 if (hasFP(MF)) 00156 return end()-3; 00157 else 00158 return end()-2; 00159 } 00160 00161 G8RCClass::G8RCClass() : TargetRegisterClass(G8RCRegClassID, G8RCVTs, G8RCSubclasses, G8RCSuperclasses, 8, 8, G8RC, G8RC + 32) {} 00162 00163 GPRCClass::iterator 00164 GPRCClass::allocation_order_begin(MachineFunction &MF) const { 00165 return begin(); 00166 } 00167 GPRCClass::iterator 00168 GPRCClass::allocation_order_end(MachineFunction &MF) const { 00169 if (hasFP(MF)) 00170 return end()-4; // don't allocate R31, R0, R1, LR 00171 else 00172 return end()-3; // don't allocate R0, R1, LR 00173 } 00174 00175 GPRCClass::GPRCClass() : TargetRegisterClass(GPRCRegClassID, GPRCVTs, GPRCSubclasses, GPRCSuperclasses, 4, 4, GPRC, GPRC + 33) {} 00176 00177 VRRCClass::VRRCClass() : TargetRegisterClass(VRRCRegClassID, VRRCVTs, VRRCSubclasses, VRRCSuperclasses, 16, 16, VRRC, VRRC + 32) {} 00178 } 00179 00180 namespace { 00181 const TargetRegisterClass* const RegisterClasses[] = { 00182 &PPC::CRRCRegClass, 00183 &PPC::F4RCRegClass, 00184 &PPC::F8RCRegClass, 00185 &PPC::G8RCRegClass, 00186 &PPC::GPRCRegClass, 00187 &PPC::VRRCRegClass, 00188 }; 00189 00190 00191 // Register Alias Sets... 00192 const unsigned Empty_AliasSet[] = { 0 }; 00193 const unsigned R0_AliasSet[] = { PPC::X0, 0 }; 00194 const unsigned R1_AliasSet[] = { PPC::X1, 0 }; 00195 const unsigned R2_AliasSet[] = { PPC::X2, 0 }; 00196 const unsigned R3_AliasSet[] = { PPC::X3, 0 }; 00197 const unsigned R4_AliasSet[] = { PPC::X4, 0 }; 00198 const unsigned R5_AliasSet[] = { PPC::X5, 0 }; 00199 const unsigned R6_AliasSet[] = { PPC::X6, 0 }; 00200 const unsigned R7_AliasSet[] = { PPC::X7, 0 }; 00201 const unsigned R8_AliasSet[] = { PPC::X8, 0 }; 00202 const unsigned R9_AliasSet[] = { PPC::X9, 0 }; 00203 const unsigned R10_AliasSet[] = { PPC::X10, 0 }; 00204 const unsigned R11_AliasSet[] = { PPC::X11, 0 }; 00205 const unsigned R12_AliasSet[] = { PPC::X12, 0 }; 00206 const unsigned R13_AliasSet[] = { PPC::X13, 0 }; 00207 const unsigned R14_AliasSet[] = { PPC::X14, 0 }; 00208 const unsigned R15_AliasSet[] = { PPC::X15, 0 }; 00209 const unsigned R16_AliasSet[] = { PPC::X16, 0 }; 00210 const unsigned R17_AliasSet[] = { PPC::X17, 0 }; 00211 const unsigned R18_AliasSet[] = { PPC::X18, 0 }; 00212 const unsigned R19_AliasSet[] = { PPC::X19, 0 }; 00213 const unsigned R20_AliasSet[] = { PPC::X20, 0 }; 00214 const unsigned R21_AliasSet[] = { PPC::X21, 0 }; 00215 const unsigned R22_AliasSet[] = { PPC::X22, 0 }; 00216 const unsigned R23_AliasSet[] = { PPC::X23, 0 }; 00217 const unsigned R24_AliasSet[] = { PPC::X24, 0 }; 00218 const unsigned R25_AliasSet[] = { PPC::X25, 0 }; 00219 const unsigned R26_AliasSet[] = { PPC::X26, 0 }; 00220 const unsigned R27_AliasSet[] = { PPC::X27, 0 }; 00221 const unsigned R28_AliasSet[] = { PPC::X28, 0 }; 00222 const unsigned R29_AliasSet[] = { PPC::X29, 0 }; 00223 const unsigned R30_AliasSet[] = { PPC::X30, 0 }; 00224 const unsigned R31_AliasSet[] = { PPC::X31, 0 }; 00225 const unsigned X0_AliasSet[] = { PPC::R0, 0 }; 00226 const unsigned X1_AliasSet[] = { PPC::R1, 0 }; 00227 const unsigned X2_AliasSet[] = { PPC::R2, 0 }; 00228 const unsigned X3_AliasSet[] = { PPC::R3, 0 }; 00229 const unsigned X4_AliasSet[] = { PPC::R4, 0 }; 00230 const unsigned X5_AliasSet[] = { PPC::R5, 0 }; 00231 const unsigned X6_AliasSet[] = { PPC::R6, 0 }; 00232 const unsigned X7_AliasSet[] = { PPC::R7, 0 }; 00233 const unsigned X8_AliasSet[] = { PPC::R8, 0 }; 00234 const unsigned X9_AliasSet[] = { PPC::R9, 0 }; 00235 const unsigned X10_AliasSet[] = { PPC::R10, 0 }; 00236 const unsigned X11_AliasSet[] = { PPC::R11, 0 }; 00237 const unsigned X12_AliasSet[] = { PPC::R12, 0 }; 00238 const unsigned X13_AliasSet[] = { PPC::R13, 0 }; 00239 const unsigned X14_AliasSet[] = { PPC::R14, 0 }; 00240 const unsigned X15_AliasSet[] = { PPC::R15, 0 }; 00241 const unsigned X16_AliasSet[] = { PPC::R16, 0 }; 00242 const unsigned X17_AliasSet[] = { PPC::R17, 0 }; 00243 const unsigned X18_AliasSet[] = { PPC::R18, 0 }; 00244 const unsigned X19_AliasSet[] = { PPC::R19, 0 }; 00245 const unsigned X20_AliasSet[] = { PPC::R20, 0 }; 00246 const unsigned X21_AliasSet[] = { PPC::R21, 0 }; 00247 const unsigned X22_AliasSet[] = { PPC::R22, 0 }; 00248 const unsigned X23_AliasSet[] = { PPC::R23, 0 }; 00249 const unsigned X24_AliasSet[] = { PPC::R24, 0 }; 00250 const unsigned X25_AliasSet[] = { PPC::R25, 0 }; 00251 const unsigned X26_AliasSet[] = { PPC::R26, 0 }; 00252 const unsigned X27_AliasSet[] = { PPC::R27, 0 }; 00253 const unsigned X28_AliasSet[] = { PPC::R28, 0 }; 00254 const unsigned X29_AliasSet[] = { PPC::R29, 0 }; 00255 const unsigned X30_AliasSet[] = { PPC::R30, 0 }; 00256 const unsigned X31_AliasSet[] = { PPC::R31, 0 }; 00257 00258 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00259 { "NOREG", 0 }, 00260 { "cr0", Empty_AliasSet }, 00261 { "cr1", Empty_AliasSet }, 00262 { "cr2", Empty_AliasSet }, 00263 { "cr3", Empty_AliasSet }, 00264 { "cr4", Empty_AliasSet }, 00265 { "cr5", Empty_AliasSet }, 00266 { "cr6", Empty_AliasSet }, 00267 { "cr7", Empty_AliasSet }, 00268 { "ctr", Empty_AliasSet }, 00269 { "f0", Empty_AliasSet }, 00270 { "f1", Empty_AliasSet }, 00271 { "f10", Empty_AliasSet }, 00272 { "f11", Empty_AliasSet }, 00273 { "f12", Empty_AliasSet }, 00274 { "f13", Empty_AliasSet }, 00275 { "f14", Empty_AliasSet }, 00276 { "f15", Empty_AliasSet }, 00277 { "f16", Empty_AliasSet }, 00278 { "f17", Empty_AliasSet }, 00279 { "f18", Empty_AliasSet }, 00280 { "f19", Empty_AliasSet }, 00281 { "f2", Empty_AliasSet }, 00282 { "f20", Empty_AliasSet }, 00283 { "f21", Empty_AliasSet }, 00284 { "f22", Empty_AliasSet }, 00285 { "f23", Empty_AliasSet }, 00286 { "f24", Empty_AliasSet }, 00287 { "f25", Empty_AliasSet }, 00288 { "f26", Empty_AliasSet }, 00289 { "f27", Empty_AliasSet }, 00290 { "f28", Empty_AliasSet }, 00291 { "f29", Empty_AliasSet }, 00292 { "f3", Empty_AliasSet }, 00293 { "f30", Empty_AliasSet }, 00294 { "f31", Empty_AliasSet }, 00295 { "f4", Empty_AliasSet }, 00296 { "f5", Empty_AliasSet }, 00297 { "f6", Empty_AliasSet }, 00298 { "f7", Empty_AliasSet }, 00299 { "f8", Empty_AliasSet }, 00300 { "f9", Empty_AliasSet }, 00301 { "lr", Empty_AliasSet }, 00302 { "r0", R0_AliasSet }, 00303 { "r1", R1_AliasSet }, 00304 { "r10", R10_AliasSet }, 00305 { "r11", R11_AliasSet }, 00306 { "r12", R12_AliasSet }, 00307 { "r13", R13_AliasSet }, 00308 { "r14", R14_AliasSet }, 00309 { "r15", R15_AliasSet }, 00310 { "r16", R16_AliasSet }, 00311 { "r17", R17_AliasSet }, 00312 { "r18", R18_AliasSet }, 00313 { "r19", R19_AliasSet }, 00314 { "r2", R2_AliasSet }, 00315 { "r20", R20_AliasSet }, 00316 { "r21", R21_AliasSet }, 00317 { "r22", R22_AliasSet }, 00318 { "r23", R23_AliasSet }, 00319 { "r24", R24_AliasSet }, 00320 { "r25", R25_AliasSet }, 00321 { "r26", R26_AliasSet }, 00322 { "r27", R27_AliasSet }, 00323 { "r28", R28_AliasSet }, 00324 { "r29", R29_AliasSet }, 00325 { "r3", R3_AliasSet }, 00326 { "r30", R30_AliasSet }, 00327 { "r31", R31_AliasSet }, 00328 { "r4", R4_AliasSet }, 00329 { "r5", R5_AliasSet }, 00330 { "r6", R6_AliasSet }, 00331 { "r7", R7_AliasSet }, 00332 { "r8", R8_AliasSet }, 00333 { "r9", R9_AliasSet }, 00334 { "v0", Empty_AliasSet }, 00335 { "v1", Empty_AliasSet }, 00336 { "v10", Empty_AliasSet }, 00337 { "v11", Empty_AliasSet }, 00338 { "v12", Empty_AliasSet }, 00339 { "v13", Empty_AliasSet }, 00340 { "v14", Empty_AliasSet }, 00341 { "v15", Empty_AliasSet }, 00342 { "v16", Empty_AliasSet }, 00343 { "v17", Empty_AliasSet }, 00344 { "v18", Empty_AliasSet }, 00345 { "v19", Empty_AliasSet }, 00346 { "v2", Empty_AliasSet }, 00347 { "v20", Empty_AliasSet }, 00348 { "v21", Empty_AliasSet }, 00349 { "v22", Empty_AliasSet }, 00350 { "v23", Empty_AliasSet }, 00351 { "v24", Empty_AliasSet }, 00352 { "v25", Empty_AliasSet }, 00353 { "v26", Empty_AliasSet }, 00354 { "v27", Empty_AliasSet }, 00355 { "v28", Empty_AliasSet }, 00356 { "v29", Empty_AliasSet }, 00357 { "v3", Empty_AliasSet }, 00358 { "v30", Empty_AliasSet }, 00359 { "v31", Empty_AliasSet }, 00360 { "v4", Empty_AliasSet }, 00361 { "v5", Empty_AliasSet }, 00362 { "v6", Empty_AliasSet }, 00363 { "v7", Empty_AliasSet }, 00364 { "v8", Empty_AliasSet }, 00365 { "v9", Empty_AliasSet }, 00366 { "VRsave", Empty_AliasSet }, 00367 { "r0", X0_AliasSet }, 00368 { "r1", X1_AliasSet }, 00369 { "r10", X10_AliasSet }, 00370 { "r11", X11_AliasSet }, 00371 { "r12", X12_AliasSet }, 00372 { "r13", X13_AliasSet }, 00373 { "r14", X14_AliasSet }, 00374 { "r15", X15_AliasSet }, 00375 { "r16", X16_AliasSet }, 00376 { "r17", X17_AliasSet }, 00377 { "r18", X18_AliasSet }, 00378 { "r19", X19_AliasSet }, 00379 { "r2", X2_AliasSet }, 00380 { "r20", X20_AliasSet }, 00381 { "r21", X21_AliasSet }, 00382 { "r22", X22_AliasSet }, 00383 { "r23", X23_AliasSet }, 00384 { "r24", X24_AliasSet }, 00385 { "r25", X25_AliasSet }, 00386 { "r26", X26_AliasSet }, 00387 { "r27", X27_AliasSet }, 00388 { "r28", X28_AliasSet }, 00389 { "r29", X29_AliasSet }, 00390 { "r3", X3_AliasSet }, 00391 { "r30", X30_AliasSet }, 00392 { "r31", X31_AliasSet }, 00393 { "r4", X4_AliasSet }, 00394 { "r5", X5_AliasSet }, 00395 { "r6", X6_AliasSet }, 00396 { "r7", X7_AliasSet }, 00397 { "r8", X8_AliasSet }, 00398 { "r9", X9_AliasSet }, 00399 }; 00400 } 00401 00402 PPCGenRegisterInfo::PPCGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00403 : MRegisterInfo(RegisterDescriptors, 140, RegisterClasses, RegisterClasses+6, 00404 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00405 00406 int PPCGenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00407 static const int DwarfRegNums[] = { -1, // NoRegister 00408 68, 69, 70, 71, 72, 73, 74, 75, 66, 32, 33, 42, 43, 44, 45, 46, 00409 47, 48, 49, 50, 51, 34, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 00410 35, 62, 63, 36, 37, 38, 39, 40, 41, 65, 0, 1, 10, 11, 12, 13, 00411 14, 15, 16, 17, 18, 19, 2, 20, 21, 22, 23, 24, 25, 26, 27, 28, 00412 29, 3, 30, 31, 4, 5, 6, 7, 8, 9, 77, 78, 87, 88, 89, 90, 00413 91, 92, 93, 94, 95, 96, 79, 97, 98, 99, 100, 101, 102, 103, 104, 105, 00414 106, 80, 107, 108, 81, 82, 83, 84, 85, 86, 107, 0, 1, 10, 11, 12, 00415 13, 14, 15, 16, 17, 18, 19, 2, 20, 21, 22, 23, 24, 25, 26, 27, 00416 28, 29, 3, 30, 31, 4, 5, 6, 7, 8, 9 00417 }; 00418 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00419 "RegNum exceeds number of registers"); 00420 return DwarfRegNums[RegNum]; 00421 } 00422 00423 } // End llvm namespace