LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned ImplicitList1[] = { SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, 0 }; 00012 static const unsigned ImplicitList2[] = { SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, 0 }; 00013 00014 static const TargetOperandInfo OperandInfo2[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00015 static const TargetOperandInfo OperandInfo3[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, }; 00016 static const TargetOperandInfo OperandInfo4[] = { { 0, 0 }, }; 00017 static const TargetOperandInfo OperandInfo5[] = { { 0, 0 }, { 0, 0 }, }; 00018 static const TargetOperandInfo OperandInfo6[] = { { SP::DFPRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, }; 00019 static const TargetOperandInfo OperandInfo7[] = { { SP::FPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, }; 00020 static const TargetOperandInfo OperandInfo8[] = { { SP::DFPRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, }; 00021 static const TargetOperandInfo OperandInfo9[] = { { SP::FPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, }; 00022 static const TargetOperandInfo OperandInfo10[] = { { SP::FPRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, }; 00023 static const TargetOperandInfo OperandInfo11[] = { { SP::DFPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, }; 00024 static const TargetOperandInfo OperandInfo12[] = { { SP::DFPRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, { 0, 0 }, }; 00025 static const TargetOperandInfo OperandInfo13[] = { { SP::FPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, { 0, 0 }, }; 00026 static const TargetOperandInfo OperandInfo14[] = { { SP::DFPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, }; 00027 static const TargetOperandInfo OperandInfo15[] = { { SP::DFPRegsRegClassID, 0 }, }; 00028 static const TargetOperandInfo OperandInfo16[] = { { SP::FPRegsRegClassID, 0 }, }; 00029 static const TargetOperandInfo OperandInfo17[] = { { SP::IntRegsRegClassID, 0 }, }; 00030 static const TargetOperandInfo OperandInfo18[] = { { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00031 static const TargetOperandInfo OperandInfo19[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, }; 00032 static const TargetOperandInfo OperandInfo20[] = { { SP::DFPRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00033 static const TargetOperandInfo OperandInfo21[] = { { SP::DFPRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, }; 00034 static const TargetOperandInfo OperandInfo22[] = { { SP::FPRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00035 static const TargetOperandInfo OperandInfo23[] = { { SP::FPRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, }; 00036 static const TargetOperandInfo OperandInfo24[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00037 static const TargetOperandInfo OperandInfo25[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00038 static const TargetOperandInfo OperandInfo26[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00039 static const TargetOperandInfo OperandInfo27[] = { { SP::IntRegsRegClassID, 0 }, { 0, 0 }, }; 00040 static const TargetOperandInfo OperandInfo28[] = { { SP::IntRegsRegClassID, 0 }, { 0, 0 }, { SP::IntRegsRegClassID, 0 }, }; 00041 static const TargetOperandInfo OperandInfo29[] = { { SP::IntRegsRegClassID, 0 }, { 0, 0 }, { SP::DFPRegsRegClassID, 0 }, }; 00042 static const TargetOperandInfo OperandInfo30[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { SP::DFPRegsRegClassID, 0 }, }; 00043 static const TargetOperandInfo OperandInfo31[] = { { SP::IntRegsRegClassID, 0 }, { 0, 0 }, { SP::FPRegsRegClassID, 0 }, }; 00044 static const TargetOperandInfo OperandInfo32[] = { { SP::IntRegsRegClassID, 0 }, { SP::IntRegsRegClassID, 0 }, { SP::FPRegsRegClassID, 0 }, }; 00045 00046 static const TargetInstrDescriptor SparcInsts[] = { 00047 { "PHI", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #0 = PHI 00048 { "INLINEASM", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #1 = INLINEASM 00049 { "ADDCCri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #2 = ADDCCri 00050 { "ADDCCrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #3 = ADDCCrr 00051 { "ADDXri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #4 = ADDXri 00052 { "ADDXrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #5 = ADDXrr 00053 { "ADDri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #6 = ADDri 00054 { "ADDrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #7 = ADDrr 00055 { "ADJCALLSTACKDOWN", 1, 0, 0, 0, NULL, NULL, OperandInfo4 }, // Inst #8 = ADJCALLSTACKDOWN 00056 { "ADJCALLSTACKUP", 1, 0, 0, 0, NULL, NULL, OperandInfo4 }, // Inst #9 = ADJCALLSTACKUP 00057 { "ANDNri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #10 = ANDNri 00058 { "ANDNrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #11 = ANDNrr 00059 { "ANDri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #12 = ANDri 00060 { "ANDrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #13 = ANDrr 00061 { "BA", 1, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo4 }, // Inst #14 = BA 00062 { "BCOND", 2, 0, 0|M_BRANCH_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo5 }, // Inst #15 = BCOND 00063 { "CALL", 1, 0, 0|M_DELAY_SLOT_FLAG|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo4 }, // Inst #16 = CALL 00064 { "FABSD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #17 = FABSD 00065 { "FABSS", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #18 = FABSS 00066 { "FADDD", 3, 0, 0, 0, NULL, NULL, OperandInfo8 }, // Inst #19 = FADDD 00067 { "FADDS", 3, 0, 0, 0, NULL, NULL, OperandInfo9 }, // Inst #20 = FADDS 00068 { "FBCOND", 2, 0, 0|M_BRANCH_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo5 }, // Inst #21 = FBCOND 00069 { "FCMPD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #22 = FCMPD 00070 { "FCMPS", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #23 = FCMPS 00071 { "FDIVD", 3, 0, 0, 0, NULL, NULL, OperandInfo8 }, // Inst #24 = FDIVD 00072 { "FDIVS", 3, 0, 0, 0, NULL, NULL, OperandInfo9 }, // Inst #25 = FDIVS 00073 { "FDTOI", 2, 0, 0, 0, NULL, NULL, OperandInfo10 }, // Inst #26 = FDTOI 00074 { "FDTOS", 2, 0, 0, 0, NULL, NULL, OperandInfo10 }, // Inst #27 = FDTOS 00075 { "FITOD", 2, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #28 = FITOD 00076 { "FITOS", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #29 = FITOS 00077 { "FMOVD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #30 = FMOVD 00078 { "FMOVD_FCC", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo12 }, // Inst #31 = FMOVD_FCC 00079 { "FMOVD_ICC", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo12 }, // Inst #32 = FMOVD_ICC 00080 { "FMOVS", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #33 = FMOVS 00081 { "FMOVS_FCC", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo13 }, // Inst #34 = FMOVS_FCC 00082 { "FMOVS_ICC", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo13 }, // Inst #35 = FMOVS_ICC 00083 { "FMULD", 3, 0, 0, 0, NULL, NULL, OperandInfo8 }, // Inst #36 = FMULD 00084 { "FMULS", 3, 0, 0, 0, NULL, NULL, OperandInfo9 }, // Inst #37 = FMULS 00085 { "FNEGD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #38 = FNEGD 00086 { "FNEGS", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #39 = FNEGS 00087 { "FSMULD", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #40 = FSMULD 00088 { "FSQRTD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #41 = FSQRTD 00089 { "FSQRTS", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #42 = FSQRTS 00090 { "FSTOD", 2, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #43 = FSTOD 00091 { "FSTOI", 2, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #44 = FSTOI 00092 { "FSUBD", 3, 0, 0, 0, NULL, NULL, OperandInfo8 }, // Inst #45 = FSUBD 00093 { "FSUBS", 3, 0, 0, 0, NULL, NULL, OperandInfo9 }, // Inst #46 = FSUBS 00094 { "FpABSD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #47 = FpABSD 00095 { "FpMOVD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #48 = FpMOVD 00096 { "FpNEGD", 2, 0, 0, 0, NULL, NULL, OperandInfo6 }, // Inst #49 = FpNEGD 00097 { "IMPLICIT_DEF_DFP", 1, 0, 0, 0, NULL, NULL, OperandInfo15 }, // Inst #50 = IMPLICIT_DEF_DFP 00098 { "IMPLICIT_DEF_FP", 1, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #51 = IMPLICIT_DEF_FP 00099 { "IMPLICIT_DEF_Int", 1, 0, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #52 = IMPLICIT_DEF_Int 00100 { "JMPLri", 2, 0, 0|M_DELAY_SLOT_FLAG|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo18 }, // Inst #53 = JMPLri 00101 { "JMPLrr", 2, 0, 0|M_DELAY_SLOT_FLAG|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo19 }, // Inst #54 = JMPLrr 00102 { "LDDFri", 3, 0, 0, 0, NULL, NULL, OperandInfo20 }, // Inst #55 = LDDFri 00103 { "LDDFrr", 3, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #56 = LDDFrr 00104 { "LDFri", 3, 0, 0, 0, NULL, NULL, OperandInfo22 }, // Inst #57 = LDFri 00105 { "LDFrr", 3, 0, 0, 0, NULL, NULL, OperandInfo23 }, // Inst #58 = LDFrr 00106 { "LDSBri", 3, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #59 = LDSBri 00107 { "LDSBrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #60 = LDSBrr 00108 { "LDSHri", 3, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #61 = LDSHri 00109 { "LDSHrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #62 = LDSHrr 00110 { "LDUBri", 3, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #63 = LDUBri 00111 { "LDUBrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #64 = LDUBrr 00112 { "LDUHri", 3, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #65 = LDUHri 00113 { "LDUHrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #66 = LDUHrr 00114 { "LDri", 3, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #67 = LDri 00115 { "LDrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #68 = LDrr 00116 { "LEA_ADDri", 3, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #69 = LEA_ADDri 00117 { "MOVFCCri", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo25 }, // Inst #70 = MOVFCCri 00118 { "MOVFCCrr", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo26 }, // Inst #71 = MOVFCCrr 00119 { "MOVICCri", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo25 }, // Inst #72 = MOVICCri 00120 { "MOVICCrr", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo26 }, // Inst #73 = MOVICCrr 00121 { "NOP", 0, 0, 0, 0, NULL, NULL, 0 }, // Inst #74 = NOP 00122 { "ORNri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #75 = ORNri 00123 { "ORNrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #76 = ORNrr 00124 { "ORri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #77 = ORri 00125 { "ORrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #78 = ORrr 00126 { "POPCrr", 2, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #79 = POPCrr 00127 { "RDY", 1, 0, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #80 = RDY 00128 { "RESTOREri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #81 = RESTOREri 00129 { "RESTORErr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #82 = RESTORErr 00130 { "RETL", 0, 0, 0|M_RET_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, 0 }, // Inst #83 = RETL 00131 { "SAVEri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #84 = SAVEri 00132 { "SAVErr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #85 = SAVErr 00133 { "SDIVri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #86 = SDIVri 00134 { "SDIVrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #87 = SDIVrr 00135 { "SELECT_CC_DFP_FCC", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo12 }, // Inst #88 = SELECT_CC_DFP_FCC 00136 { "SELECT_CC_DFP_ICC", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo12 }, // Inst #89 = SELECT_CC_DFP_ICC 00137 { "SELECT_CC_FP_FCC", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo13 }, // Inst #90 = SELECT_CC_FP_FCC 00138 { "SELECT_CC_FP_ICC", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo13 }, // Inst #91 = SELECT_CC_FP_ICC 00139 { "SELECT_CC_Int_FCC", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo26 }, // Inst #92 = SELECT_CC_Int_FCC 00140 { "SELECT_CC_Int_ICC", 4, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, NULL, NULL, OperandInfo26 }, // Inst #93 = SELECT_CC_Int_ICC 00141 { "SETHIi", 2, 0, 0, 0, NULL, NULL, OperandInfo27 }, // Inst #94 = SETHIi 00142 { "SLLri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #95 = SLLri 00143 { "SLLrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #96 = SLLrr 00144 { "SMULri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #97 = SMULri 00145 { "SMULrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #98 = SMULrr 00146 { "SRAri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #99 = SRAri 00147 { "SRArr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #100 = SRArr 00148 { "SRLri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #101 = SRLri 00149 { "SRLrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #102 = SRLrr 00150 { "STBri", 3, 0, 0, 0, NULL, NULL, OperandInfo28 }, // Inst #103 = STBri 00151 { "STBrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #104 = STBrr 00152 { "STDFri", 3, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo29 }, // Inst #105 = STDFri 00153 { "STDFrr", 3, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo30 }, // Inst #106 = STDFrr 00154 { "STFri", 3, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo31 }, // Inst #107 = STFri 00155 { "STFrr", 3, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo32 }, // Inst #108 = STFrr 00156 { "STHri", 3, 0, 0, 0, NULL, NULL, OperandInfo28 }, // Inst #109 = STHri 00157 { "STHrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #110 = STHrr 00158 { "STri", 3, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo28 }, // Inst #111 = STri 00159 { "STrr", 3, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo3 }, // Inst #112 = STrr 00160 { "SUBCCri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #113 = SUBCCri 00161 { "SUBCCrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #114 = SUBCCrr 00162 { "SUBXCCrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #115 = SUBXCCrr 00163 { "SUBXri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #116 = SUBXri 00164 { "SUBXrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #117 = SUBXrr 00165 { "SUBri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #118 = SUBri 00166 { "SUBrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #119 = SUBrr 00167 { "UDIVri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #120 = UDIVri 00168 { "UDIVrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #121 = UDIVrr 00169 { "UMULri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #122 = UMULri 00170 { "UMULrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #123 = UMULrr 00171 { "WRYri", 2, 0, 0, 0, NULL, NULL, OperandInfo27 }, // Inst #124 = WRYri 00172 { "WRYrr", 2, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #125 = WRYrr 00173 { "XNORri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #126 = XNORri 00174 { "XNORrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #127 = XNORrr 00175 { "XORri", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #128 = XORri 00176 { "XORrr", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #129 = XORrr 00177 }; 00178 } // End llvm namespace