LLVM API Documentation

PPCRegisterInfo.cpp

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00001 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the PowerPC implementation of the MRegisterInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #define DEBUG_TYPE "reginfo"
00015 #include "PPC.h"
00016 #include "PPCInstrBuilder.h"
00017 #include "PPCRegisterInfo.h"
00018 #include "PPCSubtarget.h"
00019 #include "llvm/Constants.h"
00020 #include "llvm/Type.h"
00021 #include "llvm/CodeGen/ValueTypes.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineDebugInfo.h"
00024 #include "llvm/CodeGen/MachineFunction.h"
00025 #include "llvm/CodeGen/MachineFrameInfo.h"
00026 #include "llvm/CodeGen/MachineLocation.h"
00027 #include "llvm/CodeGen/SelectionDAGNodes.h"
00028 #include "llvm/Target/TargetFrameInfo.h"
00029 #include "llvm/Target/TargetInstrInfo.h"
00030 #include "llvm/Target/TargetMachine.h"
00031 #include "llvm/Target/TargetOptions.h"
00032 #include "llvm/Support/CommandLine.h"
00033 #include "llvm/Support/Debug.h"
00034 #include "llvm/Support/MathExtras.h"
00035 #include "llvm/ADT/STLExtras.h"
00036 #include <cstdlib>
00037 #include <iostream>
00038 using namespace llvm;
00039 
00040 /// getRegisterNumbering - Given the enum value for some register, e.g.
00041 /// PPC::F14, return the number that it corresponds to (e.g. 14).
00042 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
00043   using namespace PPC;
00044   switch (RegEnum) {
00045   case R0 :  case X0 :  case F0 :  case V0 : case CR0:  return  0;
00046   case R1 :  case X1 :  case F1 :  case V1 : case CR1:  return  1;
00047   case R2 :  case X2 :  case F2 :  case V2 : case CR2:  return  2;
00048   case R3 :  case X3 :  case F3 :  case V3 : case CR3:  return  3;
00049   case R4 :  case X4 :  case F4 :  case V4 : case CR4:  return  4;
00050   case R5 :  case X5 :  case F5 :  case V5 : case CR5:  return  5;
00051   case R6 :  case X6 :  case F6 :  case V6 : case CR6:  return  6;
00052   case R7 :  case X7 :  case F7 :  case V7 : case CR7:  return  7;
00053   case R8 :  case X8 :  case F8 :  case V8 : return  8;
00054   case R9 :  case X9 :  case F9 :  case V9 : return  9;
00055   case R10:  case X10:  case F10:  case V10: return 10;
00056   case R11:  case X11:  case F11:  case V11: return 11;
00057   case R12:  case X12:  case F12:  case V12: return 12;
00058   case R13:  case X13:  case F13:  case V13: return 13;
00059   case R14:  case X14:  case F14:  case V14: return 14;
00060   case R15:  case X15:  case F15:  case V15: return 15;
00061   case R16:  case X16:  case F16:  case V16: return 16;
00062   case R17:  case X17:  case F17:  case V17: return 17;
00063   case R18:  case X18:  case F18:  case V18: return 18;
00064   case R19:  case X19:  case F19:  case V19: return 19;
00065   case R20:  case X20:  case F20:  case V20: return 20;
00066   case R21:  case X21:  case F21:  case V21: return 21;
00067   case R22:  case X22:  case F22:  case V22: return 22;
00068   case R23:  case X23:  case F23:  case V23: return 23;
00069   case R24:  case X24:  case F24:  case V24: return 24;
00070   case R25:  case X25:  case F25:  case V25: return 25;
00071   case R26:  case X26:  case F26:  case V26: return 26;
00072   case R27:  case X27:  case F27:  case V27: return 27;
00073   case R28:  case X28:  case F28:  case V28: return 28;
00074   case R29:  case X29:  case F29:  case V29: return 29;
00075   case R30:  case X30:  case F30:  case V30: return 30;
00076   case R31:  case X31:  case F31:  case V31: return 31;
00077   default:
00078     std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
00079     abort();
00080   }
00081 }
00082 
00083 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
00084   : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
00085     Subtarget(ST) {
00086   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
00087   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
00088   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
00089   ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
00090   ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
00091   ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
00092   ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
00093   ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
00094 }
00095 
00096 void
00097 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
00098                                      MachineBasicBlock::iterator MI,
00099                                      unsigned SrcReg, int FrameIdx,
00100                                      const TargetRegisterClass *RC) const {
00101   if (SrcReg == PPC::LR) {
00102     // FIXME: this spills LR immediately to memory in one step.  To do this, we
00103     // use R11, which we know cannot be used in the prolog/epilog.  This is a
00104     // hack.
00105     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
00106     addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
00107   } else if (RC == PPC::CRRCRegisterClass) {
00108     // FIXME: We use R0 here, because it isn't available for RA.
00109     // We need to store the CR in the low 4-bits of the saved value.  First,
00110     // issue a MFCR to save all of the CRBits.
00111     BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
00112     
00113     // If the saved register wasn't CR0, shift the bits left so that they are in
00114     // CR0's slot.
00115     if (SrcReg != PPC::CR0) {
00116       unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
00117       // rlwinm r0, r0, ShiftBits, 0, 31.
00118       BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
00119         .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
00120     }
00121     
00122     addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
00123   } else if (RC == PPC::GPRCRegisterClass) {
00124     addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
00125   } else if (RC == PPC::G8RCRegisterClass) {
00126     addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
00127   } else if (RC == PPC::F8RCRegisterClass) {
00128     addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
00129   } else if (RC == PPC::F4RCRegisterClass) {
00130     addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
00131   } else if (RC == PPC::VRRCRegisterClass) {
00132     // We don't have indexed addressing for vector loads.  Emit:
00133     // R11 = ADDI FI#
00134     // Dest = LVX R0, R11
00135     // 
00136     // FIXME: We use R0 here, because it isn't available for RA.
00137     addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
00138     BuildMI(MBB, MI, PPC::STVX, 3)
00139       .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
00140   } else {
00141     assert(0 && "Unknown regclass!");
00142     abort();
00143   }
00144 }
00145 
00146 void
00147 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
00148                                         MachineBasicBlock::iterator MI,
00149                                         unsigned DestReg, int FrameIdx,
00150                                         const TargetRegisterClass *RC) const {
00151   if (DestReg == PPC::LR) {
00152     addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
00153     BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
00154   } else if (RC == PPC::CRRCRegisterClass) {
00155     // FIXME: We use R0 here, because it isn't available for RA.
00156     addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
00157     
00158     // If the reloaded register isn't CR0, shift the bits right so that they are
00159     // in the right CR's slot.
00160     if (DestReg != PPC::CR0) {
00161       unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
00162       // rlwinm r11, r11, 32-ShiftBits, 0, 31.
00163       BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
00164         .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
00165     }
00166     
00167     BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
00168   } else if (RC == PPC::GPRCRegisterClass) {
00169     addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
00170   } else if (RC == PPC::G8RCRegisterClass) {
00171     addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
00172   } else if (RC == PPC::F8RCRegisterClass) {
00173     addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
00174   } else if (RC == PPC::F4RCRegisterClass) {
00175     addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
00176   } else if (RC == PPC::VRRCRegisterClass) {
00177     // We don't have indexed addressing for vector loads.  Emit:
00178     // R11 = ADDI FI#
00179     // Dest = LVX R0, R11
00180     // 
00181     // FIXME: We use R0 here, because it isn't available for RA.
00182     addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
00183     BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
00184   } else {
00185     assert(0 && "Unknown regclass!");
00186     abort();
00187   }
00188 }
00189 
00190 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
00191                                    MachineBasicBlock::iterator MI,
00192                                    unsigned DestReg, unsigned SrcReg,
00193                                    const TargetRegisterClass *RC) const {
00194   if (RC == PPC::GPRCRegisterClass) {
00195     BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
00196   } else if (RC == PPC::G8RCRegisterClass) {
00197     BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
00198   } else if (RC == PPC::F4RCRegisterClass) {
00199     BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
00200   } else if (RC == PPC::F8RCRegisterClass) {
00201     BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
00202   } else if (RC == PPC::CRRCRegisterClass) {
00203     BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
00204   } else if (RC == PPC::VRRCRegisterClass) {
00205     BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
00206   } else {
00207     std::cerr << "Attempt to copy register that is not GPR or FPR";
00208     abort();
00209   }
00210 }
00211 
00212 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
00213   // 32-bit Darwin calling convention. 
00214   static const unsigned Darwin32_CalleeSaveRegs[] = {
00215     PPC::R1 , PPC::R13, PPC::R14, PPC::R15,
00216     PPC::R16, PPC::R17, PPC::R18, PPC::R19,
00217     PPC::R20, PPC::R21, PPC::R22, PPC::R23,
00218     PPC::R24, PPC::R25, PPC::R26, PPC::R27,
00219     PPC::R28, PPC::R29, PPC::R30, PPC::R31,
00220 
00221     PPC::F14, PPC::F15, PPC::F16, PPC::F17,
00222     PPC::F18, PPC::F19, PPC::F20, PPC::F21,
00223     PPC::F22, PPC::F23, PPC::F24, PPC::F25,
00224     PPC::F26, PPC::F27, PPC::F28, PPC::F29,
00225     PPC::F30, PPC::F31,
00226     
00227     PPC::CR2, PPC::CR3, PPC::CR4,
00228     PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00229     PPC::V24, PPC::V25, PPC::V26, PPC::V27,
00230     PPC::V28, PPC::V29, PPC::V30, PPC::V31,
00231     
00232     PPC::LR,  0
00233   };
00234   // 64-bit Darwin calling convention. 
00235   static const unsigned Darwin64_CalleeSaveRegs[] = {
00236     PPC::X1 , PPC::X13, PPC::X14, PPC::X15,
00237     PPC::X16, PPC::X17, PPC::X18, PPC::X19,
00238     PPC::X20, PPC::X21, PPC::X22, PPC::X23,
00239     PPC::X24, PPC::X25, PPC::X26, PPC::X27,
00240     PPC::X28, PPC::X29, PPC::X30, PPC::X31,
00241     
00242     PPC::F14, PPC::F15, PPC::F16, PPC::F17,
00243     PPC::F18, PPC::F19, PPC::F20, PPC::F21,
00244     PPC::F22, PPC::F23, PPC::F24, PPC::F25,
00245     PPC::F26, PPC::F27, PPC::F28, PPC::F29,
00246     PPC::F30, PPC::F31,
00247     
00248     PPC::CR2, PPC::CR3, PPC::CR4,
00249     PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00250     PPC::V24, PPC::V25, PPC::V26, PPC::V27,
00251     PPC::V28, PPC::V29, PPC::V30, PPC::V31,
00252     
00253     PPC::LR,  0
00254   };
00255   
00256   return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
00257                                Darwin32_CalleeSaveRegs;
00258 }
00259 
00260 const TargetRegisterClass* const*
00261 PPCRegisterInfo::getCalleeSaveRegClasses() const {
00262   // 32-bit Darwin calling convention. 
00263   static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
00264     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
00265     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
00266     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
00267     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
00268     &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
00269 
00270     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00271     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00272     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00273     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00274     &PPC::F8RCRegClass,&PPC::F8RCRegClass,
00275     
00276     &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
00277     
00278     &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
00279     &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
00280     &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
00281     
00282     &PPC::GPRCRegClass, 0
00283   };
00284   
00285   // 64-bit Darwin calling convention. 
00286   static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
00287     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
00288     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
00289     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
00290     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
00291     &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
00292     
00293     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00294     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00295     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00296     &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
00297     &PPC::F8RCRegClass,&PPC::F8RCRegClass,
00298     
00299     &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
00300     
00301     &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
00302     &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
00303     &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
00304     
00305     &PPC::GPRCRegClass, 0
00306   };
00307  
00308   return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
00309                                Darwin32_CalleeSaveRegClasses;
00310 }
00311 
00312 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
00313 /// copy instructions, turning them into load/store instructions.
00314 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
00315                                                  unsigned OpNum,
00316                                                  int FrameIndex) const {
00317   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
00318   // it takes more than one instruction to store it.
00319   unsigned Opc = MI->getOpcode();
00320   
00321   if ((Opc == PPC::OR &&
00322        MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
00323     if (OpNum == 0) {  // move -> store
00324       unsigned InReg = MI->getOperand(1).getReg();
00325       return addFrameReference(BuildMI(PPC::STW,
00326                                        3).addReg(InReg), FrameIndex);
00327     } else {           // move -> load
00328       unsigned OutReg = MI->getOperand(0).getReg();
00329       return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
00330     }
00331   } else if ((Opc == PPC::OR8 &&
00332               MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
00333     if (OpNum == 0) {  // move -> store
00334       unsigned InReg = MI->getOperand(1).getReg();
00335       return addFrameReference(BuildMI(PPC::STD,
00336                                        3).addReg(InReg), FrameIndex);
00337     } else {           // move -> load
00338       unsigned OutReg = MI->getOperand(0).getReg();
00339       return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
00340     }
00341   } else if (Opc == PPC::FMRD) {
00342     if (OpNum == 0) {  // move -> store
00343       unsigned InReg = MI->getOperand(1).getReg();
00344       return addFrameReference(BuildMI(PPC::STFD,
00345                                        3).addReg(InReg), FrameIndex);
00346     } else {           // move -> load
00347       unsigned OutReg = MI->getOperand(0).getReg();
00348       return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
00349     }
00350   } else if (Opc == PPC::FMRS) {
00351     if (OpNum == 0) {  // move -> store
00352       unsigned InReg = MI->getOperand(1).getReg();
00353       return addFrameReference(BuildMI(PPC::STFS,
00354                                        3).addReg(InReg), FrameIndex);
00355     } else {           // move -> load
00356       unsigned OutReg = MI->getOperand(0).getReg();
00357       return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
00358     }
00359   }
00360   return 0;
00361 }
00362 
00363 //===----------------------------------------------------------------------===//
00364 // Stack Frame Processing methods
00365 //===----------------------------------------------------------------------===//
00366 
00367 // hasFP - Return true if the specified function should have a dedicated frame
00368 // pointer register.  This is true if the function has variable sized allocas or
00369 // if frame pointer elimination is disabled.
00370 //
00371 static bool hasFP(const MachineFunction &MF) {
00372   const MachineFrameInfo *MFI = MF.getFrameInfo();
00373   unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
00374 
00375   // If frame pointers are forced, or if there are variable sized stack objects,
00376   // use a frame pointer.
00377   // 
00378   return NoFramePointerElim || MFI->hasVarSizedObjects();
00379 }
00380 
00381 void PPCRegisterInfo::
00382 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
00383                               MachineBasicBlock::iterator I) const {
00384   if (hasFP(MF)) {
00385     // If we have a frame pointer, convert as follows:
00386     // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
00387     // ADJCALLSTACKUP   -> addi, r1, r1, amount
00388     MachineInstr *Old = I;
00389     unsigned Amount = Old->getOperand(0).getImmedValue();
00390     if (Amount != 0) {
00391       // We need to keep the stack aligned properly.  To do this, we round the
00392       // amount of space needed for the outgoing arguments up to the next
00393       // alignment boundary.
00394       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
00395       Amount = (Amount+Align-1)/Align*Align;
00396 
00397       // Replace the pseudo instruction with a new instruction...
00398       if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
00399         BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount);
00400       } else {
00401         assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
00402         BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount);
00403       }
00404     }
00405   }
00406   MBB.erase(I);
00407 }
00408 
00409 void
00410 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
00411   unsigned i = 0;
00412   MachineInstr &MI = *II;
00413   MachineBasicBlock &MBB = *MI.getParent();
00414   MachineFunction &MF = *MBB.getParent();
00415 
00416   while (!MI.getOperand(i).isFrameIndex()) {
00417     ++i;
00418     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
00419   }
00420 
00421   int FrameIndex = MI.getOperand(i).getFrameIndex();
00422 
00423   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
00424   MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
00425 
00426   // Take into account whether it's an add or mem instruction
00427   unsigned OffIdx = (i == 2) ? 1 : 2;
00428 
00429   // Figure out if the offset in the instruction is shifted right two bits. This
00430   // is true for instructions like "STD", which the machine implicitly adds two
00431   // low zeros to.
00432   bool isIXAddr = false;
00433   switch (MI.getOpcode()) {
00434   case PPC::LWA:
00435   case PPC::LD:
00436   case PPC::STD:
00437   case PPC::STD_32:
00438     isIXAddr = true;
00439     break;
00440   }
00441   
00442   
00443   // Now add the frame object offset to the offset from r1.
00444   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
00445   
00446   if (!isIXAddr)
00447     Offset += MI.getOperand(OffIdx).getImmedValue();
00448   else
00449     Offset += MI.getOperand(OffIdx).getImmedValue() << 2;
00450 
00451   // If we're not using a Frame Pointer that has been set to the value of the
00452   // SP before having the stack size subtracted from it, then add the stack size
00453   // to Offset to get the correct offset.
00454   Offset += MF.getFrameInfo()->getStackSize();
00455 
00456   if (Offset > 32767 || Offset < -32768) {
00457     // Insert a set of r0 with the full offset value before the ld, st, or add
00458     MachineBasicBlock *MBB = MI.getParent();
00459     BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
00460     BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
00461     
00462     // convert into indexed form of the instruction
00463     // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
00464     // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
00465     assert(ImmToIdxMap.count(MI.getOpcode()) &&
00466            "No indexed form of load or store available!");
00467     unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
00468     MI.setOpcode(NewOpcode);
00469     MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
00470     MI.getOperand(2).ChangeToRegister(PPC::R0);
00471   } else {
00472     if (isIXAddr) {
00473       assert((Offset & 3) == 0 && "Invalid frame offset!");
00474       Offset >>= 2;    // The actual encoded value has the low two bits zero.
00475     }
00476     MI.getOperand(OffIdx).ChangeToImmediate(Offset);
00477   }
00478 }
00479 
00480 /// VRRegNo - Map from a numbered VR register to its enum value.
00481 ///
00482 static const unsigned short VRRegNo[] = {
00483  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
00484  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
00485  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00486  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
00487 };
00488 
00489 /// RemoveVRSaveCode - We have found that this function does not need any code
00490 /// to manipulate the VRSAVE register, even though it uses vector registers.
00491 /// This can happen when the only registers used are known to be live in or out
00492 /// of the function.  Remove all of the VRSAVE related code from the function.
00493 static void RemoveVRSaveCode(MachineInstr *MI) {
00494   MachineBasicBlock *Entry = MI->getParent();
00495   MachineFunction *MF = Entry->getParent();
00496 
00497   // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
00498   MachineBasicBlock::iterator MBBI = MI;
00499   ++MBBI;
00500   assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
00501   MBBI->eraseFromParent();
00502   
00503   bool RemovedAllMTVRSAVEs = true;
00504   // See if we can find and remove the MTVRSAVE instruction from all of the
00505   // epilog blocks.
00506   const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
00507   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
00508     // If last instruction is a return instruction, add an epilogue
00509     if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
00510       bool FoundIt = false;
00511       for (MBBI = I->end(); MBBI != I->begin(); ) {
00512         --MBBI;
00513         if (MBBI->getOpcode() == PPC::MTVRSAVE) {
00514           MBBI->eraseFromParent();  // remove it.
00515           FoundIt = true;
00516           break;
00517         }
00518       }
00519       RemovedAllMTVRSAVEs &= FoundIt;
00520     }
00521   }
00522 
00523   // If we found and removed all MTVRSAVE instructions, remove the read of
00524   // VRSAVE as well.
00525   if (RemovedAllMTVRSAVEs) {
00526     MBBI = MI;
00527     assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
00528     --MBBI;
00529     assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
00530     MBBI->eraseFromParent();
00531   }
00532   
00533   // Finally, nuke the UPDATE_VRSAVE.
00534   MI->eraseFromParent();
00535 }
00536 
00537 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
00538 // instruction selector.  Based on the vector registers that have been used,
00539 // transform this into the appropriate ORI instruction.
00540 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
00541   unsigned UsedRegMask = 0;
00542   for (unsigned i = 0; i != 32; ++i)
00543     if (UsedRegs[VRRegNo[i]])
00544       UsedRegMask |= 1 << (31-i);
00545   
00546   // Live in and live out values already must be in the mask, so don't bother
00547   // marking them.
00548   MachineFunction *MF = MI->getParent()->getParent();
00549   for (MachineFunction::livein_iterator I = 
00550        MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
00551     unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
00552     if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
00553       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
00554   }
00555   for (MachineFunction::liveout_iterator I = 
00556        MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
00557     unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
00558     if (VRRegNo[RegNo] == *I)              // If this really is a vector reg.
00559       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
00560   }
00561   
00562   unsigned SrcReg = MI->getOperand(1).getReg();
00563   unsigned DstReg = MI->getOperand(0).getReg();
00564   // If no registers are used, turn this into a copy.
00565   if (UsedRegMask == 0) {
00566     // Remove all VRSAVE code.
00567     RemoveVRSaveCode(MI);
00568     return;
00569   } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
00570     BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
00571         .addReg(SrcReg).addImm(UsedRegMask);
00572   } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
00573     BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
00574         .addReg(SrcReg).addImm(UsedRegMask >> 16);
00575   } else {
00576     BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
00577        .addReg(SrcReg).addImm(UsedRegMask >> 16);
00578     BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
00579       .addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
00580   }
00581   
00582   // Remove the old UPDATE_VRSAVE instruction.
00583   MI->eraseFromParent();
00584 }
00585 
00586 
00587 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
00588   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
00589   MachineBasicBlock::iterator MBBI = MBB.begin();
00590   MachineFrameInfo *MFI = MF.getFrameInfo();
00591   MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
00592   
00593   // Do we have a frame pointer for this function?
00594   bool HasFP = hasFP(MF);
00595 
00596   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
00597   // process it.
00598   for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
00599     if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
00600       HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
00601       break;
00602     }
00603   }
00604   
00605   // Move MBBI back to the beginning of the function.
00606   MBBI = MBB.begin();
00607   
00608   // Get the number of bytes to allocate from the FrameInfo
00609   unsigned NumBytes = MFI->getStackSize();
00610   
00611   // Get the alignments provided by the target, and the maximum alignment
00612   // (if any) of the fixed frame objects.
00613   unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
00614   unsigned MaxAlign = MFI->getMaxAlignment();
00615 
00616   // If we have calls, we cannot use the red zone to store callee save registers
00617   // and we must set up a stack frame, so calculate the necessary size here.
00618   if (MFI->hasCalls()) {
00619     // We reserve argument space for call sites in the function immediately on
00620     // entry to the current function.  This eliminates the need for add/sub
00621     // brackets around call sites.
00622     NumBytes += MFI->getMaxCallFrameSize();
00623   }
00624 
00625   // If we are a leaf function, and use up to 224 bytes of stack space,
00626   // and don't have a frame pointer, then we do not need to adjust the stack
00627   // pointer (we fit in the Red Zone).
00628   if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
00629                           MaxAlign <= TargetAlign)) {
00630     MFI->setStackSize(0);
00631     return;
00632   }
00633 
00634   // Add the size of R1 to  NumBytes size for the store of R1 to the bottom
00635   // of the stack and round the size to a multiple of the alignment.
00636   unsigned Align = std::max(TargetAlign, MaxAlign);
00637   unsigned GPRSize = 4;
00638   unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
00639   NumBytes = (NumBytes+Size+Align-1)/Align*Align;
00640 
00641   // Update frame info to pretend that this is part of the stack...
00642   MFI->setStackSize(NumBytes);
00643   int NegNumbytes = -NumBytes;
00644 
00645   // Adjust stack pointer: r1 -= numbytes.
00646   // If there is a preferred stack alignment, align R1 now
00647   if (MaxAlign > TargetAlign) {
00648     assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
00649     assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!");
00650     BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
00651       .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
00652     BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
00653       .addImm(0-NumBytes);
00654     BuildMI(MBB, MBBI, PPC::STWUX, 3)
00655       .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
00656   } else if (NumBytes <= 32768) {
00657     BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes)
00658       .addReg(PPC::R1);
00659   } else {
00660     BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16);
00661     BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
00662       .addImm(NegNumbytes & 0xFFFF);
00663     BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
00664       .addReg(PPC::R0);
00665   }
00666   
00667   if (DebugInfo && DebugInfo->hasInfo()) {
00668     std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
00669     unsigned LabelID = DebugInfo->NextLabelID();
00670     
00671     // Show update of SP.
00672     MachineLocation Dst(MachineLocation::VirtualFP);
00673     MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
00674     Moves.push_back(new MachineMove(LabelID, Dst, Src));
00675 
00676     BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
00677   }
00678   
00679   // If there is a frame pointer, copy R1 (SP) into R31 (FP)
00680   if (HasFP) {
00681     BuildMI(MBB, MBBI, PPC::STW, 3)
00682       .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1);
00683     BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
00684   }
00685 }
00686 
00687 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
00688                                    MachineBasicBlock &MBB) const {
00689   MachineBasicBlock::iterator MBBI = prior(MBB.end());
00690   assert(MBBI->getOpcode() == PPC::BLR &&
00691          "Can only insert epilog into returning blocks");
00692 
00693   // Get alignment info so we know how to restore r1
00694   const MachineFrameInfo *MFI = MF.getFrameInfo();
00695   unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
00696 
00697   // Get the number of bytes allocated from the FrameInfo.
00698   unsigned NumBytes = MFI->getStackSize();
00699   unsigned GPRSize = 4; 
00700 
00701   if (NumBytes != 0) {
00702     // If this function has a frame pointer, load the saved stack pointer from
00703     // its stack slot.
00704     if (hasFP(MF)) {
00705       BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
00706           .addImm(GPRSize).addReg(PPC::R31);
00707     }
00708     
00709     // The loaded (or persistent) stack pointer value is offseted by the 'stwu'
00710     // on entry to the function.  Add this offset back now.
00711     if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
00712       BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
00713           .addReg(PPC::R1).addImm(NumBytes);
00714     } else {
00715       BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
00716     }
00717   }
00718 }
00719 
00720 unsigned PPCRegisterInfo::getRARegister() const {
00721   return PPC::LR;
00722 }
00723 
00724 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
00725   return hasFP(MF) ? PPC::R31 : PPC::R1;
00726 }
00727 
00728 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
00729                                                                          const {
00730   // Initial state is the frame pointer is R1.
00731   MachineLocation Dst(MachineLocation::VirtualFP);
00732   MachineLocation Src(PPC::R1, 0);
00733   Moves.push_back(new MachineMove(0, Dst, Src));
00734 }
00735 
00736 #include "PPCGenRegisterInfo.inc"
00737