LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned ImplicitList1[] = { IA64::out0, IA64::out1, IA64::out2, IA64::out3, IA64::out4, IA64::out5, IA64::out6, IA64::out7, 0 }; 00012 static const unsigned ImplicitList2[] = { IA64::r2, IA64::r3, IA64::r8, IA64::r9, IA64::r10, IA64::r11, IA64::r14, IA64::r15, IA64::r16, IA64::r17, IA64::r18, IA64::r19, IA64::r20, IA64::r21, IA64::r22, IA64::r23, IA64::r24, IA64::r25, IA64::r26, IA64::r27, IA64::r28, IA64::r29, IA64::r30, IA64::r31, IA64::p6, IA64::p7, IA64::p8, IA64::p9, IA64::p10, IA64::p11, IA64::p12, IA64::p13, IA64::p14, IA64::p15, IA64::F6, IA64::F7, IA64::F8, IA64::F9, IA64::F10, IA64::F11, IA64::F12, IA64::F13, IA64::F14, IA64::F15, IA64::F32, IA64::F33, IA64::F34, IA64::F35, IA64::F36, IA64::F37, IA64::F38, IA64::F39, IA64::F40, IA64::F41, IA64::F42, IA64::F43, IA64::F44, IA64::F45, IA64::F46, IA64::F47, IA64::F48, IA64::F49, IA64::F50, IA64::F51, IA64::F52, IA64::F53, IA64::F54, IA64::F55, IA64::F56, IA64::F57, IA64::F58, IA64::F59, IA64::F60, IA64::F61, IA64::F62, IA64::F63, IA64::F64, IA64::F65, IA64::F66, IA64::F67, IA64::F68, IA64::F69, IA64::F70, IA64::F71, IA64::F72, IA64::F73, IA64::F74, IA64::F75, IA64::F76, IA64::F77, IA64::F78, IA64::F79, IA64::F80, IA64::F81, IA64::F82, IA64::F83, IA64::F84, IA64::F85, IA64::F86, IA64::F87, IA64::F88, IA64::F89, IA64::F90, IA64::F91, IA64::F92, IA64::F93, IA64::F94, IA64::F95, IA64::F96, IA64::F97, IA64::F98, IA64::F99, IA64::F100, IA64::F101, IA64::F102, IA64::F103, IA64::F104, IA64::F105, IA64::F106, IA64::F107, IA64::F108, IA64::F109, IA64::F110, IA64::F111, IA64::F112, IA64::F113, IA64::F114, IA64::F115, IA64::F116, IA64::F117, IA64::F118, IA64::F119, IA64::F120, IA64::F121, IA64::F122, IA64::F123, IA64::F124, IA64::F125, IA64::F126, IA64::F127, IA64::out0, IA64::out1, IA64::out2, IA64::out3, IA64::out4, IA64::out5, IA64::out6, IA64::out7, 0 }; 00013 00014 static const TargetOperandInfo OperandInfo2[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, }; 00015 static const TargetOperandInfo OperandInfo3[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { 0, 0 }, }; 00016 static const TargetOperandInfo OperandInfo4[] = { { IA64::GRRegClassID, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, }; 00017 static const TargetOperandInfo OperandInfo5[] = { { IA64::PRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, }; 00018 static const TargetOperandInfo OperandInfo6[] = { { 0, 0 }, }; 00019 static const TargetOperandInfo OperandInfo7[] = { { IA64::GRRegClassID, 0 }, }; 00020 static const TargetOperandInfo OperandInfo8[] = { { IA64::PRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, }; 00021 static const TargetOperandInfo OperandInfo9[] = { { IA64::PRRegClassID, 0 }, { 0, 0 }, }; 00022 static const TargetOperandInfo OperandInfo10[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { 0, 0 }, { IA64::PRRegClassID, 0 }, }; 00023 static const TargetOperandInfo OperandInfo11[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00024 static const TargetOperandInfo OperandInfo12[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00025 static const TargetOperandInfo OperandInfo13[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00026 static const TargetOperandInfo OperandInfo14[] = { { IA64::PRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, }; 00027 static const TargetOperandInfo OperandInfo15[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { 0, 0 }, { 0, 0 }, }; 00028 static const TargetOperandInfo OperandInfo16[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, }; 00029 static const TargetOperandInfo OperandInfo17[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, }; 00030 static const TargetOperandInfo OperandInfo18[] = { { IA64::PRRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, }; 00031 static const TargetOperandInfo OperandInfo19[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, }; 00032 static const TargetOperandInfo OperandInfo20[] = { { IA64::FPRegClassID, 0 }, { IA64::PRRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, }; 00033 static const TargetOperandInfo OperandInfo21[] = { { IA64::GRRegClassID, 0 }, { IA64::FPRegClassID, 0 }, }; 00034 static const TargetOperandInfo OperandInfo22[] = { { IA64::FPRegClassID, 0 }, }; 00035 static const TargetOperandInfo OperandInfo23[] = { { IA64::PRRegClassID, 0 }, }; 00036 static const TargetOperandInfo OperandInfo24[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, }; 00037 static const TargetOperandInfo OperandInfo25[] = { { IA64::FPRegClassID, 0 }, { IA64::GRRegClassID, 0 }, }; 00038 static const TargetOperandInfo OperandInfo26[] = { { IA64::GRRegClassID, 0 }, { 0, 0 }, }; 00039 static const TargetOperandInfo OperandInfo27[] = { { IA64::PRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00040 static const TargetOperandInfo OperandInfo28[] = { { IA64::PRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00041 static const TargetOperandInfo OperandInfo29[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00042 static const TargetOperandInfo OperandInfo30[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00043 static const TargetOperandInfo OperandInfo31[] = { { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { 0, 0 }, { IA64::GRRegClassID, 0 }, }; 00044 static const TargetOperandInfo OperandInfo32[] = { { IA64::GRRegClassID, 0 }, { 0, 0 }, { IA64::GRRegClassID, 0 }, }; 00045 static const TargetOperandInfo OperandInfo33[] = { { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::FPRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00046 static const TargetOperandInfo OperandInfo34[] = { { IA64::PRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::GRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00047 static const TargetOperandInfo OperandInfo35[] = { { IA64::PRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00048 static const TargetOperandInfo OperandInfo36[] = { { IA64::PRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, { 0, 0 }, { IA64::GRRegClassID, 0 }, { IA64::PRRegClassID, 0 }, }; 00049 00050 static const TargetInstrDescriptor IA64Insts[] = { 00051 { "PHI", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #0 = PHI 00052 { "INLINEASM", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #1 = INLINEASM 00053 { "ADD", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #2 = ADD 00054 { "ADD1", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #3 = ADD1 00055 { "ADDIMM14", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #4 = ADDIMM14 00056 { "ADDIMM22", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #5 = ADDIMM22 00057 { "ADDL_EA", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #6 = ADDL_EA 00058 { "ADDL_GA", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #7 = ADDL_GA 00059 { "ADDS", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #8 = ADDS 00060 { "ADJUSTCALLSTACKDOWN", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #9 = ADJUSTCALLSTACKDOWN 00061 { "ADJUSTCALLSTACKUP", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #10 = ADJUSTCALLSTACKUP 00062 { "ALLOC", 5, 0, 0, 0, NULL, NULL, OperandInfo4 }, // Inst #11 = ALLOC 00063 { "AND", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #12 = AND 00064 { "ANDCM", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #13 = ANDCM 00065 { "BCMPEQ", 4, 0, 0, 0, NULL, NULL, OperandInfo5 }, // Inst #14 = BCMPEQ 00066 { "BRCALL", 1, 0, 0|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo6 }, // Inst #15 = BRCALL 00067 { "BRCALL_INDIRECT", 1, 0, 0|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo7 }, // Inst #16 = BRCALL_INDIRECT 00068 { "BRCALL_IPREL_ES", 1, 0, 0|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo6 }, // Inst #17 = BRCALL_IPREL_ES 00069 { "BRCALL_IPREL_GA", 1, 0, 0|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo6 }, // Inst #18 = BRCALL_IPREL_GA 00070 { "BRCOND_CALL", 2, 0, 0|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo8 }, // Inst #19 = BRCOND_CALL 00071 { "BRCOND_NOTCALL", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo8 }, // Inst #20 = BRCOND_NOTCALL 00072 { "BRLCOND_CALL", 2, 0, 0|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo9 }, // Inst #21 = BRLCOND_CALL 00073 { "BRLCOND_NOTCALL", 2, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo9 }, // Inst #22 = BRLCOND_NOTCALL 00074 { "BRL_NOTCALL", 1, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, OperandInfo6 }, // Inst #23 = BRL_NOTCALL 00075 { "CADDIMM22", 4, 0, 0, 0, NULL, NULL, OperandInfo10 }, // Inst #24 = CADDIMM22 00076 { "CFMADS0", 5, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #25 = CFMADS0 00077 { "CFMADS1", 5, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #26 = CFMADS1 00078 { "CFMAS1", 5, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #27 = CFMAS1 00079 { "CFMOV", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo12 }, // Inst #28 = CFMOV 00080 { "CFNMADS1", 5, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #29 = CFNMADS1 00081 { "CFNMAS1", 5, 0, 0, 0, NULL, NULL, OperandInfo11 }, // Inst #30 = CFNMAS1 00082 { "CMOV", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo13 }, // Inst #31 = CMOV 00083 { "CMPEQ", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #32 = CMPEQ 00084 { "CMPGE", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #33 = CMPGE 00085 { "CMPGEU", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #34 = CMPGEU 00086 { "CMPGT", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #35 = CMPGT 00087 { "CMPGTU", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #36 = CMPGTU 00088 { "CMPLE", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #37 = CMPLE 00089 { "CMPLEU", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #38 = CMPLEU 00090 { "CMPLT", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #39 = CMPLT 00091 { "CMPLTU", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #40 = CMPLTU 00092 { "CMPNE", 3, 0, 0, 0, NULL, NULL, OperandInfo14 }, // Inst #41 = CMPNE 00093 { "DEPZ", 4, 0, 0, 0, NULL, NULL, OperandInfo15 }, // Inst #42 = DEPZ 00094 { "EXTRU", 4, 0, 0, 0, NULL, NULL, OperandInfo15 }, // Inst #43 = EXTRU 00095 { "FABS", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #44 = FABS 00096 { "FADD", 3, 0, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #45 = FADD 00097 { "FADDS", 3, 0, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #46 = FADDS 00098 { "FCMPEQ", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #47 = FCMPEQ 00099 { "FCMPGE", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #48 = FCMPGE 00100 { "FCMPGEU", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #49 = FCMPGEU 00101 { "FCMPGT", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #50 = FCMPGT 00102 { "FCMPGTU", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #51 = FCMPGTU 00103 { "FCMPLE", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #52 = FCMPLE 00104 { "FCMPLEU", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #53 = FCMPLEU 00105 { "FCMPLT", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #54 = FCMPLT 00106 { "FCMPLTU", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #55 = FCMPLTU 00107 { "FCMPNE", 3, 0, 0, 0, NULL, NULL, OperandInfo18 }, // Inst #56 = FCMPNE 00108 { "FCVTFX", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #57 = FCVTFX 00109 { "FCVTFXTRUNC", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #58 = FCVTFXTRUNC 00110 { "FCVTFXTRUNCS1", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #59 = FCVTFXTRUNCS1 00111 { "FCVTFXU", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #60 = FCVTFXU 00112 { "FCVTFXUTRUNC", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #61 = FCVTFXUTRUNC 00113 { "FCVTFXUTRUNCS1", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #62 = FCVTFXUTRUNCS1 00114 { "FCVTXF", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #63 = FCVTXF 00115 { "FCVTXUF", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #64 = FCVTXUF 00116 { "FCVTXUFS1", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #65 = FCVTXUFS1 00117 { "FILL_ALL_PREDICATES_FROM_GR", 1, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #66 = FILL_ALL_PREDICATES_FROM_GR 00118 { "FMA", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #67 = FMA 00119 { "FMOV", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #68 = FMOV 00120 { "FMPY", 3, 0, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #69 = FMPY 00121 { "FMS", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #70 = FMS 00122 { "FNEG", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #71 = FNEG 00123 { "FNEGABS", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #72 = FNEGABS 00124 { "FNMA", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #73 = FNMA 00125 { "FNORMD", 2, 0, 0, 0, NULL, NULL, OperandInfo16 }, // Inst #74 = FNORMD 00126 { "FRCPAS0", 4, 0, 0, 0, NULL, NULL, OperandInfo20 }, // Inst #75 = FRCPAS0 00127 { "FRCPAS1", 4, 0, 0, 0, NULL, NULL, OperandInfo20 }, // Inst #76 = FRCPAS1 00128 { "FSUB", 3, 0, 0, 0, NULL, NULL, OperandInfo17 }, // Inst #77 = FSUB 00129 { "GETFD", 2, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #78 = GETFD 00130 { "GETFSIG", 2, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #79 = GETFSIG 00131 { "GETFSIGD", 2, 0, 0, 0, NULL, NULL, OperandInfo21 }, // Inst #80 = GETFSIGD 00132 { "IDEF", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #81 = IDEF 00133 { "IDEF_FP_D", 1, 0, 0, 0, NULL, NULL, OperandInfo22 }, // Inst #82 = IDEF_FP_D 00134 { "IDEF_GR_D", 1, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #83 = IDEF_GR_D 00135 { "IDEF_PR_D", 1, 0, 0, 0, NULL, NULL, OperandInfo23 }, // Inst #84 = IDEF_PR_D 00136 { "IUSE", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #85 = IUSE 00137 { "LD1", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #86 = LD1 00138 { "LD2", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #87 = LD2 00139 { "LD4", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #88 = LD4 00140 { "LD8", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #89 = LD8 00141 { "LDF4", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo25 }, // Inst #90 = LDF4 00142 { "LDF8", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo25 }, // Inst #91 = LDF8 00143 { "LDF_FILL", 2, 0, 0|M_LOAD_FLAG, 0, NULL, NULL, OperandInfo25 }, // Inst #92 = LDF_FILL 00144 { "MIX1L", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #93 = MIX1L 00145 { "MIX1R", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #94 = MIX1R 00146 { "MIX2L", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #95 = MIX2L 00147 { "MIX2R", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #96 = MIX2R 00148 { "MIX4L", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #97 = MIX4L 00149 { "MIX4R", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #98 = MIX4R 00150 { "MOV", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #99 = MOV 00151 { "MOVL", 2, 0, 0, 0, NULL, NULL, OperandInfo26 }, // Inst #100 = MOVL 00152 { "MOVLIMM64", 2, 0, 0, 0, NULL, NULL, OperandInfo26 }, // Inst #101 = MOVLIMM64 00153 { "MOVSIMM14", 2, 0, 0, 0, NULL, NULL, OperandInfo26 }, // Inst #102 = MOVSIMM14 00154 { "MOVSIMM22", 2, 0, 0, 0, NULL, NULL, OperandInfo26 }, // Inst #103 = MOVSIMM22 00155 { "OR", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #104 = OR 00156 { "PCMPEQOR", 4, 0, 0, 0, NULL, NULL, OperandInfo27 }, // Inst #105 = PCMPEQOR 00157 { "PCMPEQUNC", 4, 0, 0, 0, NULL, NULL, OperandInfo27 }, // Inst #106 = PCMPEQUNC 00158 { "PCMPEQUNCR0R0", 2, 0, 0, 0, NULL, NULL, OperandInfo28 }, // Inst #107 = PCMPEQUNCR0R0 00159 { "PCMPNE", 4, 0, 0, 0, NULL, NULL, OperandInfo27 }, // Inst #108 = PCMPNE 00160 { "PFMOV", 3, 0, 0, 0, NULL, NULL, OperandInfo29 }, // Inst #109 = PFMOV 00161 { "PMOV", 3, 0, 0, 0, NULL, NULL, OperandInfo30 }, // Inst #110 = PMOV 00162 { "POPCNT", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #111 = POPCNT 00163 { "PSEUDO_ALLOC", 1, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #112 = PSEUDO_ALLOC 00164 { "RET", 0, 0, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0, NULL, NULL, 0 }, // Inst #113 = RET 00165 { "SETFD", 2, 0, 0, 0, NULL, NULL, OperandInfo25 }, // Inst #114 = SETFD 00166 { "SETFSIG", 2, 0, 0, 0, NULL, NULL, OperandInfo25 }, // Inst #115 = SETFSIG 00167 { "SETFSIGD", 2, 0, 0, 0, NULL, NULL, OperandInfo25 }, // Inst #116 = SETFSIGD 00168 { "SHL", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #117 = SHL 00169 { "SHLADD", 4, 0, 0, 0, NULL, NULL, OperandInfo31 }, // Inst #118 = SHLADD 00170 { "SHLI", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #119 = SHLI 00171 { "SHRS", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #120 = SHRS 00172 { "SHRSI", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #121 = SHRSI 00173 { "SHRU", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #122 = SHRU 00174 { "SHRUI", 3, 0, 0, 0, NULL, NULL, OperandInfo3 }, // Inst #123 = SHRUI 00175 { "SPILL_ALL_PREDICATES_TO_GR", 1, 0, 0, 0, NULL, NULL, OperandInfo7 }, // Inst #124 = SPILL_ALL_PREDICATES_TO_GR 00176 { "ST1", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #125 = ST1 00177 { "ST2", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #126 = ST2 00178 { "ST4", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #127 = ST4 00179 { "ST8", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo24 }, // Inst #128 = ST8 00180 { "STF4", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo21 }, // Inst #129 = STF4 00181 { "STF8", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo21 }, // Inst #130 = STF8 00182 { "STF_SPILL", 2, 0, 0|M_STORE_FLAG, 0, NULL, NULL, OperandInfo21 }, // Inst #131 = STF_SPILL 00183 { "STOP", 0, 0, 0|M_VARIABLE_OPS, 0, NULL, NULL, 0 }, // Inst #132 = STOP 00184 { "SUB", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #133 = SUB 00185 { "SUB1", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #134 = SUB1 00186 { "SUBIMM8", 3, 0, 0, 0, NULL, NULL, OperandInfo32 }, // Inst #135 = SUBIMM8 00187 { "SXT1", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #136 = SXT1 00188 { "SXT2", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #137 = SXT2 00189 { "SXT4", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #138 = SXT4 00190 { "TCFMADS0", 6, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo33 }, // Inst #139 = TCFMADS0 00191 { "TCFMAS1", 6, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo33 }, // Inst #140 = TCFMAS1 00192 { "TCMPNE", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo5 }, // Inst #141 = TCMPNE 00193 { "TPCADDIMM22", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo10 }, // Inst #142 = TPCADDIMM22 00194 { "TPCADDS", 4, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo10 }, // Inst #143 = TPCADDS 00195 { "TPCMPEQ", 5, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo34 }, // Inst #144 = TPCMPEQ 00196 { "TPCMPEQOR", 5, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo34 }, // Inst #145 = TPCMPEQOR 00197 { "TPCMPEQR0R0", 3, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo35 }, // Inst #146 = TPCMPEQR0R0 00198 { "TPCMPIMM8NE", 5, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo36 }, // Inst #147 = TPCMPIMM8NE 00199 { "TPCMPNE", 5, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo34 }, // Inst #148 = TPCMPNE 00200 { "TPCMPNER0R0", 3, 0, 0|M_2_ADDR_FLAG, 0, NULL, NULL, OperandInfo35 }, // Inst #149 = TPCMPNER0R0 00201 { "XMAHD", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #150 = XMAHD 00202 { "XMAHUD", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #151 = XMAHUD 00203 { "XMAL", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #152 = XMAL 00204 { "XMALD", 4, 0, 0, 0, NULL, NULL, OperandInfo19 }, // Inst #153 = XMALD 00205 { "XOR", 3, 0, 0, 0, NULL, NULL, OperandInfo2 }, // Inst #154 = XOR 00206 { "ZXT1", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #155 = ZXT1 00207 { "ZXT2", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #156 = ZXT2 00208 { "ZXT4", 2, 0, 0, 0, NULL, NULL, OperandInfo24 }, // Inst #157 = ZXT4 00209 { "pOR", 4, 0, 0, 0, NULL, NULL, OperandInfo13 }, // Inst #158 = pOR 00210 }; 00211 } // End llvm namespace