LLVM API Documentation
#include <PPCISelLowering.h>
Inheritance diagram for llvm::PPCTargetLowering:
Public Member Functions | |
PPCTargetLowering (TargetMachine &TM) | |
virtual const char * | getTargetNodeName (unsigned Opcode) const |
virtual SDOperand | LowerOperation (SDOperand Op, SelectionDAG &DAG) |
virtual SDOperand | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const |
virtual void | computeMaskedBitsForTargetNode (const SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const |
virtual MachineBasicBlock * | InsertAtEndOfBasicBlock (MachineInstr *MI, MachineBasicBlock *MBB) |
ConstraintType | getConstraintType (char ConstraintLetter) const |
std::vector< unsigned > | getRegClassForInlineAsmConstraint (const std::string &Constraint, MVT::ValueType VT) const |
bool | isOperandValidForConstraint (SDOperand Op, char ConstraintLetter) |
virtual bool | isLegalAddressImmediate (int64_t V) const |
Definition at line 168 of file PPCISelLowering.h.
PPCTargetLowering::PPCTargetLowering | ( | TargetMachine & | TM | ) |
Definition at line 31 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::AddPromotedToType(), llvm::TargetLowering::addRegisterClass(), llvm::ISD::AND, llvm::ISD::BIT_CONVERT, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::computeRegisterProperties(), llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::Custom, llvm::ISD::DEBUG_LABEL, llvm::ISD::DEBUG_LOC, llvm::ISD::DYNAMIC_STACKALLOC, llvm::TargetLowering::Expand, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::ISD::FSQRT, llvm::TargetMachine::getSubtarget(), llvm::ISD::GlobalAddress, llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm::TargetLowering::Legal, llvm::ISD::LOAD, llvm::ISD::LOCATION, llvm::ISD::MEMCPY, llvm::ISD::MEMMOVE, llvm::ISD::MEMSET, llvm::ISD::MUL, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLowering::Promote, llvm::ISD::RET, llvm::ISD::ROTR, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLowering::setOperationAction(), llvm::TargetLowering::setPow2DivIsCheap(), llvm::TargetLowering::setSetCCIsExpensive(), llvm::TargetLowering::setSetCCResultContents(), llvm::TargetLowering::setSetCCResultType(), llvm::TargetLowering::setShiftAmountType(), llvm::TargetLowering::setStackPointerRegisterToSaveRestore(), llvm::TargetLowering::setTargetDAGCombine(), llvm::TargetLowering::setUseUnderscoreSetJmpLongJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCSTORE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, and llvm::TargetLowering::ZeroOrOneSetCCResult.
const char * PPCTargetLowering::getTargetNodeName | ( | unsigned | Opcode | ) | const [virtual] |
getTargetNodeName() - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 274 of file PPCISelLowering.cpp.
References llvm::PPCISD::BCTRL, llvm::PPCISD::CALL, llvm::PPCISD::COND_BRANCH, llvm::PPCISD::EXTSW_32, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::PPCISD::FSEL, llvm::PPCISD::GlobalBaseReg, llvm::PPCISD::Hi, llvm::PPCISD::LBRX, llvm::PPCISD::Lo, llvm::PPCISD::MFCR, llvm::PPCISD::MTCTR, llvm::PPCISD::RET_FLAG, llvm::PPCISD::SHL, llvm::PPCISD::SRA, llvm::PPCISD::SRL, llvm::PPCISD::STBRX, llvm::PPCISD::STD_32, llvm::PPCISD::STFIWX, llvm::PPCISD::VCMP, llvm::PPCISD::VCMPo, llvm::PPCISD::VMADDFP, llvm::PPCISD::VNMSUBFP, and llvm::PPCISD::VPERM.
SDOperand PPCTargetLowering::LowerOperation | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [virtual] |
LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 2193 of file PPCISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::CALL, llvm::ISD::ConstantPool, DAG, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_TO_SINT, llvm::TargetLowering::getPointerTy(), llvm::ISD::GlobalAddress, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, LowerBUILD_VECTOR(), LowerCALL(), LowerConstantPool(), LowerFORMAL_ARGUMENTS(), LowerFP_TO_SINT(), LowerGlobalAddress(), LowerINTRINSIC_WO_CHAIN(), LowerJumpTable(), LowerMUL(), LowerRET(), LowerSCALAR_TO_VECTOR(), LowerSELECT_CC(), LowerSETCC(), LowerSHL(), LowerSINT_TO_FP(), LowerSRA(), LowerSRL(), LowerVASTART(), LowerVECTOR_SHUFFLE(), llvm::ISD::MUL, Op, llvm::ISD::RET, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::VASTART, and llvm::ISD::VECTOR_SHUFFLE.
SDOperand PPCTargetLowering::PerformDAGCombine | ( | SDNode * | N, | |
DAGCombinerInfo & | DCI | |||
) | const [virtual] |
Definition at line 2297 of file PPCISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::BR, llvm::ISD::BR_CC, llvm::ISD::BSWAP, llvm::PPCISD::COND_BRANCH, DAG, E, llvm::MVT::f32, llvm::MVT::f64, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::MVT::Flag, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, getAltivecCompareInfo(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::User::getNumOperands(), llvm::SDOperand::getOpcode(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::SDOperand::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::TargetMachine::getSubtarget(), llvm::TargetLowering::getTargetMachine(), llvm::SDOperand::getValue(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::Value::getValueType(), llvm::SDOperand::getValueType(), llvm::SDOperand::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::PPCISD::LBRX, llvm::SPII::Load, llvm::ISD::LOAD, llvm::PPCISD::MFCR, Ops, llvm::MVT::Other, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SINT_TO_FP, llvm::PPCISD::STBRX, llvm::PPCISD::STFIWX, llvm::ISD::STORE, TM, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), User, llvm::SDOperand::Val, Val, llvm::PPCISD::VCMP, and llvm::PPCISD::VCMPo.
void PPCTargetLowering::computeMaskedBitsForTargetNode | ( | const SDOperand | Op, | |
uint64_t | Mask, | |||
uint64_t & | KnownZero, | |||
uint64_t & | KnownOne, | |||
unsigned | Depth = 0 | |||
) | const [virtual] |
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 2524 of file PPCISelLowering.cpp.
References llvm::MVT::i16, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::PPCISD::LBRX, Op, llvm::Intrinsic::ppc_altivec_vcmpbfp_p, llvm::Intrinsic::ppc_altivec_vcmpeqfp_p, llvm::Intrinsic::ppc_altivec_vcmpequb_p, llvm::Intrinsic::ppc_altivec_vcmpequh_p, llvm::Intrinsic::ppc_altivec_vcmpequw_p, llvm::Intrinsic::ppc_altivec_vcmpgefp_p, llvm::Intrinsic::ppc_altivec_vcmpgtfp_p, llvm::Intrinsic::ppc_altivec_vcmpgtsb_p, llvm::Intrinsic::ppc_altivec_vcmpgtsh_p, llvm::Intrinsic::ppc_altivec_vcmpgtsw_p, llvm::Intrinsic::ppc_altivec_vcmpgtub_p, llvm::Intrinsic::ppc_altivec_vcmpgtuh_p, llvm::Intrinsic::ppc_altivec_vcmpgtuw_p, and U.
MachineBasicBlock * PPCTargetLowering::InsertAtEndOfBasicBlock | ( | MachineInstr * | MI, | |
MachineBasicBlock * | MBB | |||
) | [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 2230 of file PPCISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), BB, llvm::BuildMI(), F, llvm::MachineOperand::getImmedValue(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::BasicBlock::getParent(), llvm::MachineOperand::getReg(), MI, and PHI.
PPCTargetLowering::ConstraintType PPCTargetLowering::getConstraintType | ( | char | ConstraintLetter | ) | const [virtual] |
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 2566 of file PPCISelLowering.cpp.
References llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().
std::vector< unsigned > PPCTargetLowering::getRegClassForInlineAsmConstraint | ( | const std::string & | Constraint, | |
MVT::ValueType | VT | |||
) | const [virtual] |
getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.
Reimplemented from llvm::TargetLowering.
Definition at line 2581 of file PPCISelLowering.cpp.
bool PPCTargetLowering::isOperandValidForConstraint | ( | SDOperand | Op, | |
char | ConstraintLetter | |||
) | [virtual] |
isOperandValidForConstraint - Return true if the specified SDOperand is valid for the specified target constraint letter.
Reimplemented from llvm::TargetLowering.
Definition at line 2638 of file PPCISelLowering.cpp.
References llvm::TargetLowering::isOperandValidForConstraint(), llvm::isPowerOf2_32(), and Op.
bool PPCTargetLowering::isLegalAddressImmediate | ( | int64_t | V | ) | const [virtual] |
isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode.
Reimplemented from llvm::TargetLowering.
Definition at line 2679 of file PPCISelLowering.cpp.