LLVM API Documentation

X86InstrInfo.cpp

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00001 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "X86InstrInfo.h"
00015 #include "X86.h"
00016 #include "X86GenInstrInfo.inc"
00017 #include "X86InstrBuilder.h"
00018 #include "X86Subtarget.h"
00019 #include "X86TargetMachine.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 using namespace llvm;
00022 
00023 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
00024   : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
00025     TM(tm) {
00026 }
00027 
00028 
00029 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
00030                                unsigned& sourceReg,
00031                                unsigned& destReg) const {
00032   MachineOpCode oc = MI.getOpcode();
00033   if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
00034       oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
00035       oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
00036       oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
00037       oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
00038       oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
00039       oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
00040       oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
00041       oc == X86::MOVPDI2DIrr) {
00042       assert(MI.getNumOperands() == 2 &&
00043              MI.getOperand(0).isRegister() &&
00044              MI.getOperand(1).isRegister() &&
00045              "invalid register-register move instruction");
00046       sourceReg = MI.getOperand(1).getReg();
00047       destReg = MI.getOperand(0).getReg();
00048       return true;
00049   }
00050   return false;
00051 }
00052 
00053 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
00054                                            int &FrameIndex) const {
00055   switch (MI->getOpcode()) {
00056   default: break;
00057   case X86::MOV8rm:
00058   case X86::MOV16rm:
00059   case X86::MOV16_rm:
00060   case X86::MOV32rm:
00061   case X86::MOV32_rm:
00062   case X86::FpLD64m:
00063   case X86::MOVSSrm:
00064   case X86::MOVSDrm:
00065   case X86::MOVAPSrm:
00066   case X86::MOVAPDrm:
00067     if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
00068         MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
00069         MI->getOperand(2).getImmedValue() == 1 &&
00070         MI->getOperand(3).getReg() == 0 &&
00071         MI->getOperand(4).getImmedValue() == 0) {
00072       FrameIndex = MI->getOperand(1).getFrameIndex();
00073       return MI->getOperand(0).getReg();
00074     }
00075     break;
00076   }
00077   return 0;
00078 }
00079 
00080 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
00081                                           int &FrameIndex) const {
00082   switch (MI->getOpcode()) {
00083   default: break;
00084   case X86::MOV8mr:
00085   case X86::MOV16mr:
00086   case X86::MOV16_mr:
00087   case X86::MOV32mr:
00088   case X86::MOV32_mr:
00089   case X86::FpSTP64m:
00090   case X86::MOVSSmr:
00091   case X86::MOVSDmr:
00092   case X86::MOVAPSmr:
00093   case X86::MOVAPDmr:
00094     if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
00095         MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
00096         MI->getOperand(1).getImmedValue() == 1 &&
00097         MI->getOperand(2).getReg() == 0 &&
00098         MI->getOperand(3).getImmedValue() == 0) {
00099       FrameIndex = MI->getOperand(0).getFrameIndex();
00100       return MI->getOperand(4).getReg();
00101     }
00102     break;
00103   }
00104   return 0;
00105 }
00106 
00107 
00108 /// convertToThreeAddress - This method must be implemented by targets that
00109 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
00110 /// may be able to convert a two-address instruction into a true
00111 /// three-address instruction on demand.  This allows the X86 target (for
00112 /// example) to convert ADD and SHL instructions into LEA instructions if they
00113 /// would require register copies due to two-addressness.
00114 ///
00115 /// This method returns a null pointer if the transformation cannot be
00116 /// performed, otherwise it returns the new instruction.
00117 ///
00118 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
00119   // All instructions input are two-addr instructions.  Get the known operands.
00120   unsigned Dest = MI->getOperand(0).getReg();
00121   unsigned Src = MI->getOperand(1).getReg();
00122 
00123   switch (MI->getOpcode()) {
00124   default: break;
00125   case X86::SHUFPSrri: {
00126     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
00127     const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
00128     unsigned A = MI->getOperand(0).getReg();
00129     unsigned B = MI->getOperand(1).getReg();
00130     unsigned C = MI->getOperand(2).getReg();
00131     unsigned M = MI->getOperand(3).getImmedValue();
00132     if (!Subtarget->hasSSE2() || B != C) return 0;
00133     return BuildMI(X86::PSHUFDri, 2, A).addReg(B).addImm(M);
00134   }
00135   }
00136 
00137   // FIXME: None of these instructions are promotable to LEAs without
00138   // additional information.  In particular, LEA doesn't set the flags that
00139   // add and inc do.  :(
00140   return 0;
00141 
00142   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
00143   // we have subtarget support, enable the 16-bit LEA generation here.
00144   bool DisableLEA16 = true;
00145 
00146   switch (MI->getOpcode()) {
00147   case X86::INC32r:
00148     assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
00149     return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
00150   case X86::INC16r:
00151     if (DisableLEA16) return 0;
00152     assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
00153     return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
00154   case X86::DEC32r:
00155     assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
00156     return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
00157   case X86::DEC16r:
00158     if (DisableLEA16) return 0;
00159     assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
00160     return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
00161   case X86::ADD32rr:
00162     assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
00163     return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
00164                      MI->getOperand(2).getReg());
00165   case X86::ADD16rr:
00166     if (DisableLEA16) return 0;
00167     assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
00168     return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
00169                      MI->getOperand(2).getReg());
00170   case X86::ADD32ri:
00171   case X86::ADD32ri8:
00172     assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
00173     if (MI->getOperand(2).isImmediate())
00174       return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
00175                           MI->getOperand(2).getImmedValue());
00176     return 0;
00177   case X86::ADD16ri:
00178   case X86::ADD16ri8:
00179     if (DisableLEA16) return 0;
00180     assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
00181     if (MI->getOperand(2).isImmediate())
00182       return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
00183                           MI->getOperand(2).getImmedValue());
00184     break;
00185 
00186   case X86::SHL16ri:
00187     if (DisableLEA16) return 0;
00188   case X86::SHL32ri:
00189     assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
00190            "Unknown shl instruction!");
00191     unsigned ShAmt = MI->getOperand(2).getImmedValue();
00192     if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
00193       X86AddressMode AM;
00194       AM.Scale = 1 << ShAmt;
00195       AM.IndexReg = Src;
00196       unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
00197       return addFullAddress(BuildMI(Opc, 5, Dest), AM);
00198     }
00199     break;
00200   }
00201 
00202   return 0;
00203 }
00204 
00205 /// commuteInstruction - We have a few instructions that must be hacked on to
00206 /// commute them.
00207 ///
00208 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
00209   switch (MI->getOpcode()) {
00210   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
00211   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
00212   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
00213   case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
00214     unsigned Opc;
00215     unsigned Size;
00216     switch (MI->getOpcode()) {
00217     default: assert(0 && "Unreachable!");
00218     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
00219     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
00220     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
00221     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
00222     }
00223     unsigned Amt = MI->getOperand(3).getImmedValue();
00224     unsigned A = MI->getOperand(0).getReg();
00225     unsigned B = MI->getOperand(1).getReg();
00226     unsigned C = MI->getOperand(2).getReg();
00227     return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
00228   }
00229   default:
00230     return TargetInstrInfo::commuteInstruction(MI);
00231   }
00232 }
00233 
00234 
00235 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
00236                               MachineBasicBlock& TMBB) const {
00237   BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
00238 }
00239 
00240 MachineBasicBlock::iterator
00241 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
00242   unsigned Opcode = MI->getOpcode();
00243   assert(isBranch(Opcode) && "MachineInstr must be a branch");
00244   unsigned ROpcode;
00245   switch (Opcode) {
00246   default: assert(0 && "Cannot reverse unconditional branches!");
00247   case X86::JB:  ROpcode = X86::JAE; break;
00248   case X86::JAE: ROpcode = X86::JB;  break;
00249   case X86::JE:  ROpcode = X86::JNE; break;
00250   case X86::JNE: ROpcode = X86::JE;  break;
00251   case X86::JBE: ROpcode = X86::JA;  break;
00252   case X86::JA:  ROpcode = X86::JBE; break;
00253   case X86::JS:  ROpcode = X86::JNS; break;
00254   case X86::JNS: ROpcode = X86::JS;  break;
00255   case X86::JP:  ROpcode = X86::JNP; break;
00256   case X86::JNP: ROpcode = X86::JP;  break;
00257   case X86::JL:  ROpcode = X86::JGE; break;
00258   case X86::JGE: ROpcode = X86::JL;  break;
00259   case X86::JLE: ROpcode = X86::JG;  break;
00260   case X86::JG:  ROpcode = X86::JLE; break;
00261   }
00262   MachineBasicBlock* MBB = MI->getParent();
00263   MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
00264   return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
00265 }
00266