LLVM API Documentation
00001 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the SelectionDAG::Legalize method. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "llvm/CodeGen/SelectionDAG.h" 00015 #include "llvm/CodeGen/MachineFunction.h" 00016 #include "llvm/CodeGen/MachineFrameInfo.h" 00017 #include "llvm/Target/TargetLowering.h" 00018 #include "llvm/Target/TargetData.h" 00019 #include "llvm/Target/TargetOptions.h" 00020 #include "llvm/CallingConv.h" 00021 #include "llvm/Constants.h" 00022 #include "llvm/Support/MathExtras.h" 00023 #include "llvm/Support/CommandLine.h" 00024 #include "llvm/Support/Visibility.h" 00025 #include <iostream> 00026 #include <map> 00027 using namespace llvm; 00028 00029 #ifndef NDEBUG 00030 static cl::opt<bool> 00031 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 00032 cl::desc("Pop up a window to show dags before legalize")); 00033 #else 00034 static const bool ViewLegalizeDAGs = 0; 00035 #endif 00036 00037 //===----------------------------------------------------------------------===// 00038 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 00039 /// hacks on it until the target machine can handle it. This involves 00040 /// eliminating value sizes the machine cannot handle (promoting small sizes to 00041 /// large sizes or splitting up large values into small values) as well as 00042 /// eliminating operations the machine cannot handle. 00043 /// 00044 /// This code also does a small amount of optimization and recognition of idioms 00045 /// as part of its processing. For example, if a target does not support a 00046 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 00047 /// will attempt merge setcc and brc instructions into brcc's. 00048 /// 00049 namespace { 00050 class VISIBILITY_HIDDEN SelectionDAGLegalize { 00051 TargetLowering &TLI; 00052 SelectionDAG &DAG; 00053 00054 // Libcall insertion helpers. 00055 00056 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 00057 /// legalized. We use this to ensure that calls are properly serialized 00058 /// against each other, including inserted libcalls. 00059 SDOperand LastCALLSEQ_END; 00060 00061 /// IsLegalizingCall - This member is used *only* for purposes of providing 00062 /// helpful assertions that a libcall isn't created while another call is 00063 /// being legalized (which could lead to non-serialized call sequences). 00064 bool IsLegalizingCall; 00065 00066 enum LegalizeAction { 00067 Legal, // The target natively supports this operation. 00068 Promote, // This operation should be executed in a larger type. 00069 Expand // Try to expand this to other ops, otherwise use a libcall. 00070 }; 00071 00072 /// ValueTypeActions - This is a bitvector that contains two bits for each 00073 /// value type, where the two bits correspond to the LegalizeAction enum. 00074 /// This can be queried with "getTypeAction(VT)". 00075 TargetLowering::ValueTypeActionImpl ValueTypeActions; 00076 00077 /// LegalizedNodes - For nodes that are of legal width, and that have more 00078 /// than one use, this map indicates what regularized operand to use. This 00079 /// allows us to avoid legalizing the same thing more than once. 00080 std::map<SDOperand, SDOperand> LegalizedNodes; 00081 00082 /// PromotedNodes - For nodes that are below legal width, and that have more 00083 /// than one use, this map indicates what promoted value to use. This allows 00084 /// us to avoid promoting the same thing more than once. 00085 std::map<SDOperand, SDOperand> PromotedNodes; 00086 00087 /// ExpandedNodes - For nodes that need to be expanded this map indicates 00088 /// which which operands are the expanded version of the input. This allows 00089 /// us to avoid expanding the same node more than once. 00090 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 00091 00092 /// SplitNodes - For vector nodes that need to be split, this map indicates 00093 /// which which operands are the split version of the input. This allows us 00094 /// to avoid splitting the same node more than once. 00095 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 00096 00097 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 00098 /// concrete packed types, this contains the mapping of ones we have already 00099 /// processed to the result. 00100 std::map<SDOperand, SDOperand> PackedNodes; 00101 00102 void AddLegalizedOperand(SDOperand From, SDOperand To) { 00103 LegalizedNodes.insert(std::make_pair(From, To)); 00104 // If someone requests legalization of the new node, return itself. 00105 if (From != To) 00106 LegalizedNodes.insert(std::make_pair(To, To)); 00107 } 00108 void AddPromotedOperand(SDOperand From, SDOperand To) { 00109 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 00110 assert(isNew && "Got into the map somehow?"); 00111 // If someone requests legalization of the new node, return itself. 00112 LegalizedNodes.insert(std::make_pair(To, To)); 00113 } 00114 00115 public: 00116 00117 SelectionDAGLegalize(SelectionDAG &DAG); 00118 00119 /// getTypeAction - Return how we should legalize values of this type, either 00120 /// it is already legal or we need to expand it into multiple registers of 00121 /// smaller integer type, or we need to promote it to a larger type. 00122 LegalizeAction getTypeAction(MVT::ValueType VT) const { 00123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 00124 } 00125 00126 /// isTypeLegal - Return true if this type is legal on this target. 00127 /// 00128 bool isTypeLegal(MVT::ValueType VT) const { 00129 return getTypeAction(VT) == Legal; 00130 } 00131 00132 void LegalizeDAG(); 00133 00134 private: 00135 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 00136 /// appropriate for its type. 00137 void HandleOp(SDOperand Op); 00138 00139 /// LegalizeOp - We know that the specified value has a legal type. 00140 /// Recursively ensure that the operands have legal types, then return the 00141 /// result. 00142 SDOperand LegalizeOp(SDOperand O); 00143 00144 /// PromoteOp - Given an operation that produces a value in an invalid type, 00145 /// promote it to compute the value into a larger type. The produced value 00146 /// will have the correct bits for the low portion of the register, but no 00147 /// guarantee is made about the top bits: it may be zero, sign-extended, or 00148 /// garbage. 00149 SDOperand PromoteOp(SDOperand O); 00150 00151 /// ExpandOp - Expand the specified SDOperand into its two component pieces 00152 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 00153 /// the LegalizeNodes map is filled in for any results that are not expanded, 00154 /// the ExpandedNodes map is filled in for any results that are expanded, and 00155 /// the Lo/Hi values are returned. This applies to integer types and Vector 00156 /// types. 00157 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 00158 00159 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 00160 /// two smaller values of MVT::Vector type. 00161 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 00162 00163 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 00164 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 00165 /// this is called, we know that PackedVT is the right type for the result and 00166 /// we know that this type is legal for the target. 00167 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 00168 00169 /// isShuffleLegal - Return true if a vector shuffle is legal with the 00170 /// specified mask and type. Targets can specify exactly which masks they 00171 /// support and the code generator is tasked with not creating illegal masks. 00172 /// 00173 /// Note that this will also return true for shuffles that are promoted to a 00174 /// different type. 00175 /// 00176 /// If this is a legal shuffle, this method returns the (possibly promoted) 00177 /// build_vector Mask. If it's not a legal shuffle, it returns null. 00178 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 00179 00180 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 00181 std::set<SDNode*> &NodesLeadingTo); 00182 00183 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 00184 00185 SDOperand CreateStackTemporary(MVT::ValueType VT); 00186 00187 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 00188 SDOperand &Hi); 00189 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 00190 SDOperand Source); 00191 00192 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 00193 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 00194 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 00195 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 00196 SDOperand LegalOp, 00197 MVT::ValueType DestVT); 00198 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 00199 bool isSigned); 00200 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 00201 bool isSigned); 00202 00203 SDOperand ExpandBSWAP(SDOperand Op); 00204 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 00205 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 00206 SDOperand &Lo, SDOperand &Hi); 00207 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 00208 SDOperand &Lo, SDOperand &Hi); 00209 00210 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 00211 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 00212 00213 SDOperand getIntPtrConstant(uint64_t Val) { 00214 return DAG.getConstant(Val, TLI.getPointerTy()); 00215 } 00216 }; 00217 } 00218 00219 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 00220 /// specified mask and type. Targets can specify exactly which masks they 00221 /// support and the code generator is tasked with not creating illegal masks. 00222 /// 00223 /// Note that this will also return true for shuffles that are promoted to a 00224 /// different type. 00225 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 00226 SDOperand Mask) const { 00227 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 00228 default: return 0; 00229 case TargetLowering::Legal: 00230 case TargetLowering::Custom: 00231 break; 00232 case TargetLowering::Promote: { 00233 // If this is promoted to a different type, convert the shuffle mask and 00234 // ask if it is legal in the promoted type! 00235 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 00236 00237 // If we changed # elements, change the shuffle mask. 00238 unsigned NumEltsGrowth = 00239 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 00240 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 00241 if (NumEltsGrowth > 1) { 00242 // Renumber the elements. 00243 std::vector<SDOperand> Ops; 00244 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 00245 SDOperand InOp = Mask.getOperand(i); 00246 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 00247 if (InOp.getOpcode() == ISD::UNDEF) 00248 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 00249 else { 00250 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 00251 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 00252 } 00253 } 00254 } 00255 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops); 00256 } 00257 VT = NVT; 00258 break; 00259 } 00260 } 00261 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 00262 } 00263 00264 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the 00265 /// specified vector opcode. 00266 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 00267 switch (VecOp) { 00268 default: assert(0 && "Don't know how to scalarize this opcode!"); 00269 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 00270 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 00271 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 00272 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 00273 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 00274 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 00275 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 00276 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 00277 } 00278 } 00279 00280 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 00281 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 00282 ValueTypeActions(TLI.getValueTypeActions()) { 00283 assert(MVT::LAST_VALUETYPE <= 32 && 00284 "Too many value types for ValueTypeActions to hold!"); 00285 } 00286 00287 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has 00288 /// not been visited yet and if all of its operands have already been visited. 00289 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 00290 std::map<SDNode*, unsigned> &Visited) { 00291 if (++Visited[N] != N->getNumOperands()) 00292 return; // Haven't visited all operands yet 00293 00294 Order.push_back(N); 00295 00296 if (N->hasOneUse()) { // Tail recurse in common case. 00297 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 00298 return; 00299 } 00300 00301 // Now that we have N in, add anything that uses it if all of their operands 00302 // are now done. 00303 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 00304 ComputeTopDownOrdering(*UI, Order, Visited); 00305 } 00306 00307 00308 void SelectionDAGLegalize::LegalizeDAG() { 00309 LastCALLSEQ_END = DAG.getEntryNode(); 00310 IsLegalizingCall = false; 00311 00312 // The legalize process is inherently a bottom-up recursive process (users 00313 // legalize their uses before themselves). Given infinite stack space, we 00314 // could just start legalizing on the root and traverse the whole graph. In 00315 // practice however, this causes us to run out of stack space on large basic 00316 // blocks. To avoid this problem, compute an ordering of the nodes where each 00317 // node is only legalized after all of its operands are legalized. 00318 std::map<SDNode*, unsigned> Visited; 00319 std::vector<SDNode*> Order; 00320 00321 // Compute ordering from all of the leaves in the graphs, those (like the 00322 // entry node) that have no operands. 00323 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 00324 E = DAG.allnodes_end(); I != E; ++I) { 00325 if (I->getNumOperands() == 0) { 00326 Visited[I] = 0 - 1U; 00327 ComputeTopDownOrdering(I, Order, Visited); 00328 } 00329 } 00330 00331 assert(Order.size() == Visited.size() && 00332 Order.size() == 00333 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 00334 "Error: DAG is cyclic!"); 00335 Visited.clear(); 00336 00337 for (unsigned i = 0, e = Order.size(); i != e; ++i) 00338 HandleOp(SDOperand(Order[i], 0)); 00339 00340 // Finally, it's possible the root changed. Get the new root. 00341 SDOperand OldRoot = DAG.getRoot(); 00342 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 00343 DAG.setRoot(LegalizedNodes[OldRoot]); 00344 00345 ExpandedNodes.clear(); 00346 LegalizedNodes.clear(); 00347 PromotedNodes.clear(); 00348 SplitNodes.clear(); 00349 PackedNodes.clear(); 00350 00351 // Remove dead nodes now. 00352 DAG.RemoveDeadNodes(OldRoot.Val); 00353 } 00354 00355 00356 /// FindCallEndFromCallStart - Given a chained node that is part of a call 00357 /// sequence, find the CALLSEQ_END node that terminates the call sequence. 00358 static SDNode *FindCallEndFromCallStart(SDNode *Node) { 00359 if (Node->getOpcode() == ISD::CALLSEQ_END) 00360 return Node; 00361 if (Node->use_empty()) 00362 return 0; // No CallSeqEnd 00363 00364 // The chain is usually at the end. 00365 SDOperand TheChain(Node, Node->getNumValues()-1); 00366 if (TheChain.getValueType() != MVT::Other) { 00367 // Sometimes it's at the beginning. 00368 TheChain = SDOperand(Node, 0); 00369 if (TheChain.getValueType() != MVT::Other) { 00370 // Otherwise, hunt for it. 00371 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 00372 if (Node->getValueType(i) == MVT::Other) { 00373 TheChain = SDOperand(Node, i); 00374 break; 00375 } 00376 00377 // Otherwise, we walked into a node without a chain. 00378 if (TheChain.getValueType() != MVT::Other) 00379 return 0; 00380 } 00381 } 00382 00383 for (SDNode::use_iterator UI = Node->use_begin(), 00384 E = Node->use_end(); UI != E; ++UI) { 00385 00386 // Make sure to only follow users of our token chain. 00387 SDNode *User = *UI; 00388 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 00389 if (User->getOperand(i) == TheChain) 00390 if (SDNode *Result = FindCallEndFromCallStart(User)) 00391 return Result; 00392 } 00393 return 0; 00394 } 00395 00396 /// FindCallStartFromCallEnd - Given a chained node that is part of a call 00397 /// sequence, find the CALLSEQ_START node that initiates the call sequence. 00398 static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 00399 assert(Node && "Didn't find callseq_start for a call??"); 00400 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 00401 00402 assert(Node->getOperand(0).getValueType() == MVT::Other && 00403 "Node doesn't have a token chain argument!"); 00404 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 00405 } 00406 00407 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 00408 /// see if any uses can reach Dest. If no dest operands can get to dest, 00409 /// legalize them, legalize ourself, and return false, otherwise, return true. 00410 /// 00411 /// Keep track of the nodes we fine that actually do lead to Dest in 00412 /// NodesLeadingTo. This avoids retraversing them exponential number of times. 00413 /// 00414 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 00415 std::set<SDNode*> &NodesLeadingTo) { 00416 if (N == Dest) return true; // N certainly leads to Dest :) 00417 00418 // If we've already processed this node and it does lead to Dest, there is no 00419 // need to reprocess it. 00420 if (NodesLeadingTo.count(N)) return true; 00421 00422 // If the first result of this node has been already legalized, then it cannot 00423 // reach N. 00424 switch (getTypeAction(N->getValueType(0))) { 00425 case Legal: 00426 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 00427 break; 00428 case Promote: 00429 if (PromotedNodes.count(SDOperand(N, 0))) return false; 00430 break; 00431 case Expand: 00432 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 00433 break; 00434 } 00435 00436 // Okay, this node has not already been legalized. Check and legalize all 00437 // operands. If none lead to Dest, then we can legalize this node. 00438 bool OperandsLeadToDest = false; 00439 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 00440 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 00441 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 00442 00443 if (OperandsLeadToDest) { 00444 NodesLeadingTo.insert(N); 00445 return true; 00446 } 00447 00448 // Okay, this node looks safe, legalize it and return false. 00449 HandleOp(SDOperand(N, 0)); 00450 return false; 00451 } 00452 00453 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 00454 /// appropriate for its type. 00455 void SelectionDAGLegalize::HandleOp(SDOperand Op) { 00456 switch (getTypeAction(Op.getValueType())) { 00457 default: assert(0 && "Bad type action!"); 00458 case Legal: LegalizeOp(Op); break; 00459 case Promote: PromoteOp(Op); break; 00460 case Expand: 00461 if (Op.getValueType() != MVT::Vector) { 00462 SDOperand X, Y; 00463 ExpandOp(Op, X, Y); 00464 } else { 00465 SDNode *N = Op.Val; 00466 unsigned NumOps = N->getNumOperands(); 00467 unsigned NumElements = 00468 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 00469 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 00470 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 00471 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 00472 // In the common case, this is a legal vector type, convert it to the 00473 // packed operation and type now. 00474 PackVectorOp(Op, PackedVT); 00475 } else if (NumElements == 1) { 00476 // Otherwise, if this is a single element vector, convert it to a 00477 // scalar operation. 00478 PackVectorOp(Op, EVT); 00479 } else { 00480 // Otherwise, this is a multiple element vector that isn't supported. 00481 // Split it in half and legalize both parts. 00482 SDOperand X, Y; 00483 SplitVectorOp(Op, X, Y); 00484 } 00485 } 00486 break; 00487 } 00488 } 00489 00490 00491 /// LegalizeOp - We know that the specified value has a legal type. 00492 /// Recursively ensure that the operands have legal types, then return the 00493 /// result. 00494 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 00495 assert(isTypeLegal(Op.getValueType()) && 00496 "Caller should expand or promote operands that are not legal!"); 00497 SDNode *Node = Op.Val; 00498 00499 // If this operation defines any values that cannot be represented in a 00500 // register on this target, make sure to expand or promote them. 00501 if (Node->getNumValues() > 1) { 00502 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 00503 if (getTypeAction(Node->getValueType(i)) != Legal) { 00504 HandleOp(Op.getValue(i)); 00505 assert(LegalizedNodes.count(Op) && 00506 "Handling didn't add legal operands!"); 00507 return LegalizedNodes[Op]; 00508 } 00509 } 00510 00511 // Note that LegalizeOp may be reentered even from single-use nodes, which 00512 // means that we always must cache transformed nodes. 00513 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 00514 if (I != LegalizedNodes.end()) return I->second; 00515 00516 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 00517 SDOperand Result = Op; 00518 bool isCustom = false; 00519 00520 switch (Node->getOpcode()) { 00521 case ISD::FrameIndex: 00522 case ISD::EntryToken: 00523 case ISD::Register: 00524 case ISD::BasicBlock: 00525 case ISD::TargetFrameIndex: 00526 case ISD::TargetJumpTable: 00527 case ISD::TargetConstant: 00528 case ISD::TargetConstantFP: 00529 case ISD::TargetConstantPool: 00530 case ISD::TargetGlobalAddress: 00531 case ISD::TargetExternalSymbol: 00532 case ISD::VALUETYPE: 00533 case ISD::SRCVALUE: 00534 case ISD::STRING: 00535 case ISD::CONDCODE: 00536 // Primitives must all be legal. 00537 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 00538 "This must be legal!"); 00539 break; 00540 default: 00541 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 00542 // If this is a target node, legalize it by legalizing the operands then 00543 // passing it through. 00544 std::vector<SDOperand> Ops; 00545 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 00546 Ops.push_back(LegalizeOp(Node->getOperand(i))); 00547 00548 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops); 00549 00550 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 00551 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 00552 return Result.getValue(Op.ResNo); 00553 } 00554 // Otherwise this is an unhandled builtin node. splat. 00555 #ifndef NDEBUG 00556 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 00557 #endif 00558 assert(0 && "Do not know how to legalize this operator!"); 00559 abort(); 00560 case ISD::GlobalAddress: 00561 case ISD::ExternalSymbol: 00562 case ISD::ConstantPool: 00563 case ISD::JumpTable: // Nothing to do. 00564 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 00565 default: assert(0 && "This action is not supported yet!"); 00566 case TargetLowering::Custom: 00567 Tmp1 = TLI.LowerOperation(Op, DAG); 00568 if (Tmp1.Val) Result = Tmp1; 00569 // FALLTHROUGH if the target doesn't want to lower this op after all. 00570 case TargetLowering::Legal: 00571 break; 00572 } 00573 break; 00574 case ISD::AssertSext: 00575 case ISD::AssertZext: 00576 Tmp1 = LegalizeOp(Node->getOperand(0)); 00577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 00578 break; 00579 case ISD::MERGE_VALUES: 00580 // Legalize eliminates MERGE_VALUES nodes. 00581 Result = Node->getOperand(Op.ResNo); 00582 break; 00583 case ISD::CopyFromReg: 00584 Tmp1 = LegalizeOp(Node->getOperand(0)); 00585 Result = Op.getValue(0); 00586 if (Node->getNumValues() == 2) { 00587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 00588 } else { 00589 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 00590 if (Node->getNumOperands() == 3) { 00591 Tmp2 = LegalizeOp(Node->getOperand(2)); 00592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 00593 } else { 00594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 00595 } 00596 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 00597 } 00598 // Since CopyFromReg produces two values, make sure to remember that we 00599 // legalized both of them. 00600 AddLegalizedOperand(Op.getValue(0), Result); 00601 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 00602 return Result.getValue(Op.ResNo); 00603 case ISD::UNDEF: { 00604 MVT::ValueType VT = Op.getValueType(); 00605 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 00606 default: assert(0 && "This action is not supported yet!"); 00607 case TargetLowering::Expand: 00608 if (MVT::isInteger(VT)) 00609 Result = DAG.getConstant(0, VT); 00610 else if (MVT::isFloatingPoint(VT)) 00611 Result = DAG.getConstantFP(0, VT); 00612 else 00613 assert(0 && "Unknown value type!"); 00614 break; 00615 case TargetLowering::Legal: 00616 break; 00617 } 00618 break; 00619 } 00620 00621 case ISD::INTRINSIC_W_CHAIN: 00622 case ISD::INTRINSIC_WO_CHAIN: 00623 case ISD::INTRINSIC_VOID: { 00624 std::vector<SDOperand> Ops; 00625 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 00626 Ops.push_back(LegalizeOp(Node->getOperand(i))); 00627 Result = DAG.UpdateNodeOperands(Result, Ops); 00628 00629 // Allow the target to custom lower its intrinsics if it wants to. 00630 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 00631 TargetLowering::Custom) { 00632 Tmp3 = TLI.LowerOperation(Result, DAG); 00633 if (Tmp3.Val) Result = Tmp3; 00634 } 00635 00636 if (Result.Val->getNumValues() == 1) break; 00637 00638 // Must have return value and chain result. 00639 assert(Result.Val->getNumValues() == 2 && 00640 "Cannot return more than two values!"); 00641 00642 // Since loads produce two values, make sure to remember that we 00643 // legalized both of them. 00644 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 00645 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 00646 return Result.getValue(Op.ResNo); 00647 } 00648 00649 case ISD::LOCATION: 00650 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 00651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 00652 00653 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 00654 case TargetLowering::Promote: 00655 default: assert(0 && "This action is not supported yet!"); 00656 case TargetLowering::Expand: { 00657 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 00658 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 00659 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 00660 00661 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 00662 const std::string &FName = 00663 cast<StringSDNode>(Node->getOperand(3))->getValue(); 00664 const std::string &DirName = 00665 cast<StringSDNode>(Node->getOperand(4))->getValue(); 00666 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 00667 00668 std::vector<SDOperand> Ops; 00669 Ops.push_back(Tmp1); // chain 00670 SDOperand LineOp = Node->getOperand(1); 00671 SDOperand ColOp = Node->getOperand(2); 00672 00673 if (useDEBUG_LOC) { 00674 Ops.push_back(LineOp); // line # 00675 Ops.push_back(ColOp); // col # 00676 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 00677 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 00678 } else { 00679 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 00680 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 00681 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 00682 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 00683 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 00684 } 00685 } else { 00686 Result = Tmp1; // chain 00687 } 00688 break; 00689 } 00690 case TargetLowering::Legal: 00691 if (Tmp1 != Node->getOperand(0) || 00692 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 00693 std::vector<SDOperand> Ops; 00694 Ops.push_back(Tmp1); 00695 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 00696 Ops.push_back(Node->getOperand(1)); // line # must be legal. 00697 Ops.push_back(Node->getOperand(2)); // col # must be legal. 00698 } else { 00699 // Otherwise promote them. 00700 Ops.push_back(PromoteOp(Node->getOperand(1))); 00701 Ops.push_back(PromoteOp(Node->getOperand(2))); 00702 } 00703 Ops.push_back(Node->getOperand(3)); // filename must be legal. 00704 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 00705 Result = DAG.UpdateNodeOperands(Result, Ops); 00706 } 00707 break; 00708 } 00709 break; 00710 00711 case ISD::DEBUG_LOC: 00712 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 00713 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 00714 default: assert(0 && "This action is not supported yet!"); 00715 case TargetLowering::Legal: 00716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 00717 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 00718 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 00719 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 00720 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 00721 break; 00722 } 00723 break; 00724 00725 case ISD::DEBUG_LABEL: 00726 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 00727 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 00728 default: assert(0 && "This action is not supported yet!"); 00729 case TargetLowering::Legal: 00730 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 00731 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 00732 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 00733 break; 00734 } 00735 break; 00736 00737 case ISD::Constant: 00738 // We know we don't need to expand constants here, constants only have one 00739 // value and we check that it is fine above. 00740 00741 // FIXME: Maybe we should handle things like targets that don't support full 00742 // 32-bit immediates? 00743 break; 00744 case ISD::ConstantFP: { 00745 // Spill FP immediates to the constant pool if the target cannot directly 00746 // codegen them. Targets often have some immediate values that can be 00747 // efficiently generated into an FP register without a load. We explicitly 00748 // leave these constants as ConstantFP nodes for the target to deal with. 00749 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 00750 00751 // Check to see if this FP immediate is already legal. 00752 bool isLegal = false; 00753 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 00754 E = TLI.legal_fpimm_end(); I != E; ++I) 00755 if (CFP->isExactlyValue(*I)) { 00756 isLegal = true; 00757 break; 00758 } 00759 00760 // If this is a legal constant, turn it into a TargetConstantFP node. 00761 if (isLegal) { 00762 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 00763 break; 00764 } 00765 00766 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 00767 default: assert(0 && "This action is not supported yet!"); 00768 case TargetLowering::Custom: 00769 Tmp3 = TLI.LowerOperation(Result, DAG); 00770 if (Tmp3.Val) { 00771 Result = Tmp3; 00772 break; 00773 } 00774 // FALLTHROUGH 00775 case TargetLowering::Expand: 00776 // Otherwise we need to spill the constant to memory. 00777 bool Extend = false; 00778 00779 // If a FP immediate is precise when represented as a float and if the 00780 // target can do an extending load from float to double, we put it into 00781 // the constant pool as a float, even if it's is statically typed as a 00782 // double. 00783 MVT::ValueType VT = CFP->getValueType(0); 00784 bool isDouble = VT == MVT::f64; 00785 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 00786 Type::FloatTy, CFP->getValue()); 00787 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 00788 // Only do this if the target has a native EXTLOAD instruction from 00789 // f32. 00790 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 00791 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 00792 VT = MVT::f32; 00793 Extend = true; 00794 } 00795 00796 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 00797 if (Extend) { 00798 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 00799 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 00800 } else { 00801 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 00802 DAG.getSrcValue(NULL)); 00803 } 00804 } 00805 break; 00806 } 00807 case ISD::TokenFactor: 00808 if (Node->getNumOperands() == 2) { 00809 Tmp1 = LegalizeOp(Node->getOperand(0)); 00810 Tmp2 = LegalizeOp(Node->getOperand(1)); 00811 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 00812 } else if (Node->getNumOperands() == 3) { 00813 Tmp1 = LegalizeOp(Node->getOperand(0)); 00814 Tmp2 = LegalizeOp(Node->getOperand(1)); 00815 Tmp3 = LegalizeOp(Node->getOperand(2)); 00816 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 00817 } else { 00818 std::vector<SDOperand> Ops; 00819 // Legalize the operands. 00820 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 00821 Ops.push_back(LegalizeOp(Node->getOperand(i))); 00822 Result = DAG.UpdateNodeOperands(Result, Ops); 00823 } 00824 break; 00825 00826 case ISD::FORMAL_ARGUMENTS: 00827 case ISD::CALL: 00828 // The only option for this is to custom lower it. 00829 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 00830 assert(Tmp3.Val && "Target didn't custom lower this node!"); 00831 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 00832 "Lowering call/formal_arguments produced unexpected # results!"); 00833 00834 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 00835 // remember that we legalized all of them, so it doesn't get relegalized. 00836 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 00837 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 00838 if (Op.ResNo == i) 00839 Tmp2 = Tmp1; 00840 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 00841 } 00842 return Tmp2; 00843 00844 case ISD::BUILD_VECTOR: 00845 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 00846 default: assert(0 && "This action is not supported yet!"); 00847 case TargetLowering::Custom: 00848 Tmp3 = TLI.LowerOperation(Result, DAG); 00849 if (Tmp3.Val) { 00850 Result = Tmp3; 00851 break; 00852 } 00853 // FALLTHROUGH 00854 case TargetLowering::Expand: 00855 Result = ExpandBUILD_VECTOR(Result.Val); 00856 break; 00857 } 00858 break; 00859 case ISD::INSERT_VECTOR_ELT: 00860 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 00861 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 00862 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 00863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 00864 00865 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 00866 Node->getValueType(0))) { 00867 default: assert(0 && "This action is not supported yet!"); 00868 case TargetLowering::Legal: 00869 break; 00870 case TargetLowering::Custom: 00871 Tmp3 = TLI.LowerOperation(Result, DAG); 00872 if (Tmp3.Val) { 00873 Result = Tmp3; 00874 break; 00875 } 00876 // FALLTHROUGH 00877 case TargetLowering::Expand: { 00878 // If the insert index is a constant, codegen this as a scalar_to_vector, 00879 // then a shuffle that inserts it into the right position in the vector. 00880 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 00881 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 00882 Tmp1.getValueType(), Tmp2); 00883 00884 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 00885 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 00886 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 00887 00888 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 00889 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 00890 // the RHS. 00891 std::vector<SDOperand> ShufOps; 00892 for (unsigned i = 0; i != NumElts; ++i) { 00893 if (i != InsertPos->getValue()) 00894 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 00895 else 00896 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 00897 } 00898 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps); 00899 00900 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 00901 Tmp1, ScVec, ShufMask); 00902 Result = LegalizeOp(Result); 00903 break; 00904 } 00905 00906 // If the target doesn't support this, we have to spill the input vector 00907 // to a temporary stack slot, update the element, then reload it. This is 00908 // badness. We could also load the value into a vector register (either 00909 // with a "move to register" or "extload into register" instruction, then 00910 // permute it into place, if the idx is a constant and if the idx is 00911 // supported by the target. 00912 MVT::ValueType VT = Tmp1.getValueType(); 00913 MVT::ValueType EltVT = Tmp2.getValueType(); 00914 MVT::ValueType IdxVT = Tmp3.getValueType(); 00915 MVT::ValueType PtrVT = TLI.getPointerTy(); 00916 SDOperand StackPtr = CreateStackTemporary(VT); 00917 // Store the vector. 00918 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 00919 Tmp1, StackPtr, DAG.getSrcValue(NULL)); 00920 00921 // Truncate or zero extend offset to target pointer type. 00922 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 00923 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 00924 // Add the offset to the index. 00925 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 00926 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 00927 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 00928 // Store the scalar value. 00929 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch, 00930 Tmp2, StackPtr2, DAG.getSrcValue(NULL)); 00931 // Load the updated vector. 00932 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL)); 00933 break; 00934 } 00935 } 00936 break; 00937 case ISD::SCALAR_TO_VECTOR: 00938 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 00939 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 00940 break; 00941 } 00942 00943 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 00944 Result = DAG.UpdateNodeOperands(Result, Tmp1); 00945 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 00946 Node->getValueType(0))) { 00947 default: assert(0 && "This action is not supported yet!"); 00948 case TargetLowering::Legal: 00949 break; 00950 case TargetLowering::Custom: 00951 Tmp3 = TLI.LowerOperation(Result, DAG); 00952 if (Tmp3.Val) { 00953 Result = Tmp3; 00954 break; 00955 } 00956 // FALLTHROUGH 00957 case TargetLowering::Expand: 00958 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 00959 break; 00960 } 00961 break; 00962 case ISD::VECTOR_SHUFFLE: 00963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 00964 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 00965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 00966 00967 // Allow targets to custom lower the SHUFFLEs they support. 00968 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 00969 default: assert(0 && "Unknown operation action!"); 00970 case TargetLowering::Legal: 00971 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 00972 "vector shuffle should not be created if not legal!"); 00973 break; 00974 case TargetLowering::Custom: 00975 Tmp3 = TLI.LowerOperation(Result, DAG); 00976 if (Tmp3.Val) { 00977 Result = Tmp3; 00978 break; 00979 } 00980 // FALLTHROUGH 00981 case TargetLowering::Expand: { 00982 MVT::ValueType VT = Node->getValueType(0); 00983 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 00984 MVT::ValueType PtrVT = TLI.getPointerTy(); 00985 SDOperand Mask = Node->getOperand(2); 00986 unsigned NumElems = Mask.getNumOperands(); 00987 std::vector<SDOperand> Ops; 00988 for (unsigned i = 0; i != NumElems; ++i) { 00989 SDOperand Arg = Mask.getOperand(i); 00990 if (Arg.getOpcode() == ISD::UNDEF) { 00991 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 00992 } else { 00993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 00994 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 00995 if (Idx < NumElems) 00996 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 00997 DAG.getConstant(Idx, PtrVT))); 00998 else 00999 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 01000 DAG.getConstant(Idx - NumElems, PtrVT))); 01001 } 01002 } 01003 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 01004 break; 01005 } 01006 case TargetLowering::Promote: { 01007 // Change base type to a different vector type. 01008 MVT::ValueType OVT = Node->getValueType(0); 01009 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 01010 01011 // Cast the two input vectors. 01012 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 01013 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 01014 01015 // Convert the shuffle mask to the right # elements. 01016 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 01017 assert(Tmp3.Val && "Shuffle not legal?"); 01018 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 01019 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 01020 break; 01021 } 01022 } 01023 break; 01024 01025 case ISD::EXTRACT_VECTOR_ELT: 01026 Tmp1 = LegalizeOp(Node->getOperand(0)); 01027 Tmp2 = LegalizeOp(Node->getOperand(1)); 01028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 01029 01030 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 01031 Tmp1.getValueType())) { 01032 default: assert(0 && "This action is not supported yet!"); 01033 case TargetLowering::Legal: 01034 break; 01035 case TargetLowering::Custom: 01036 Tmp3 = TLI.LowerOperation(Result, DAG); 01037 if (Tmp3.Val) { 01038 Result = Tmp3; 01039 break; 01040 } 01041 // FALLTHROUGH 01042 case TargetLowering::Expand: 01043 Result = ExpandEXTRACT_VECTOR_ELT(Result); 01044 break; 01045 } 01046 break; 01047 01048 case ISD::VEXTRACT_VECTOR_ELT: 01049 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 01050 break; 01051 01052 case ISD::CALLSEQ_START: { 01053 SDNode *CallEnd = FindCallEndFromCallStart(Node); 01054 01055 // Recursively Legalize all of the inputs of the call end that do not lead 01056 // to this call start. This ensures that any libcalls that need be inserted 01057 // are inserted *before* the CALLSEQ_START. 01058 {std::set<SDNode*> NodesLeadingTo; 01059 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 01060 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 01061 NodesLeadingTo); 01062 } 01063 01064 // Now that we legalized all of the inputs (which may have inserted 01065 // libcalls) create the new CALLSEQ_START node. 01066 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01067 01068 // Merge in the last call, to ensure that this call start after the last 01069 // call ended. 01070 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 01071 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 01072 Tmp1 = LegalizeOp(Tmp1); 01073 } 01074 01075 // Do not try to legalize the target-specific arguments (#1+). 01076 if (Tmp1 != Node->getOperand(0)) { 01077 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 01078 Ops[0] = Tmp1; 01079 Result = DAG.UpdateNodeOperands(Result, Ops); 01080 } 01081 01082 // Remember that the CALLSEQ_START is legalized. 01083 AddLegalizedOperand(Op.getValue(0), Result); 01084 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 01085 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 01086 01087 // Now that the callseq_start and all of the non-call nodes above this call 01088 // sequence have been legalized, legalize the call itself. During this 01089 // process, no libcalls can/will be inserted, guaranteeing that no calls 01090 // can overlap. 01091 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 01092 SDOperand InCallSEQ = LastCALLSEQ_END; 01093 // Note that we are selecting this call! 01094 LastCALLSEQ_END = SDOperand(CallEnd, 0); 01095 IsLegalizingCall = true; 01096 01097 // Legalize the call, starting from the CALLSEQ_END. 01098 LegalizeOp(LastCALLSEQ_END); 01099 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 01100 return Result; 01101 } 01102 case ISD::CALLSEQ_END: 01103 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 01104 // will cause this node to be legalized as well as handling libcalls right. 01105 if (LastCALLSEQ_END.Val != Node) { 01106 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 01107 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 01108 assert(I != LegalizedNodes.end() && 01109 "Legalizing the call start should have legalized this node!"); 01110 return I->second; 01111 } 01112 01113 // Otherwise, the call start has been legalized and everything is going 01114 // according to plan. Just legalize ourselves normally here. 01115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01116 // Do not try to legalize the target-specific arguments (#1+), except for 01117 // an optional flag input. 01118 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 01119 if (Tmp1 != Node->getOperand(0)) { 01120 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 01121 Ops[0] = Tmp1; 01122 Result = DAG.UpdateNodeOperands(Result, Ops); 01123 } 01124 } else { 01125 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 01126 if (Tmp1 != Node->getOperand(0) || 01127 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 01128 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 01129 Ops[0] = Tmp1; 01130 Ops.back() = Tmp2; 01131 Result = DAG.UpdateNodeOperands(Result, Ops); 01132 } 01133 } 01134 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 01135 // This finishes up call legalization. 01136 IsLegalizingCall = false; 01137 01138 // If the CALLSEQ_END node has a flag, remember that we legalized it. 01139 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 01140 if (Node->getNumValues() == 2) 01141 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 01142 return Result.getValue(Op.ResNo); 01143 case ISD::DYNAMIC_STACKALLOC: { 01144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01145 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 01146 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 01147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 01148 01149 Tmp1 = Result.getValue(0); 01150 Tmp2 = Result.getValue(1); 01151 switch (TLI.getOperationAction(Node->getOpcode(), 01152 Node->getValueType(0))) { 01153 default: assert(0 && "This action is not supported yet!"); 01154 case TargetLowering::Expand: { 01155 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 01156 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 01157 " not tell us which reg is the stack pointer!"); 01158 SDOperand Chain = Tmp1.getOperand(0); 01159 SDOperand Size = Tmp2.getOperand(1); 01160 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 01161 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 01162 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 01163 Tmp1 = LegalizeOp(Tmp1); 01164 Tmp2 = LegalizeOp(Tmp2); 01165 break; 01166 } 01167 case TargetLowering::Custom: 01168 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 01169 if (Tmp3.Val) { 01170 Tmp1 = LegalizeOp(Tmp3); 01171 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 01172 } 01173 break; 01174 case TargetLowering::Legal: 01175 break; 01176 } 01177 // Since this op produce two values, make sure to remember that we 01178 // legalized both of them. 01179 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 01180 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 01181 return Op.ResNo ? Tmp2 : Tmp1; 01182 } 01183 case ISD::INLINEASM: { 01184 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 01185 bool Changed = false; 01186 // Legalize all of the operands of the inline asm, in case they are nodes 01187 // that need to be expanded or something. Note we skip the asm string and 01188 // all of the TargetConstant flags. 01189 SDOperand Op = LegalizeOp(Ops[0]); 01190 Changed = Op != Ops[0]; 01191 Ops[0] = Op; 01192 01193 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 01194 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 01195 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 01196 for (++i; NumVals; ++i, --NumVals) { 01197 SDOperand Op = LegalizeOp(Ops[i]); 01198 if (Op != Ops[i]) { 01199 Changed = true; 01200 Ops[i] = Op; 01201 } 01202 } 01203 } 01204 01205 if (HasInFlag) { 01206 Op = LegalizeOp(Ops.back()); 01207 Changed |= Op != Ops.back(); 01208 Ops.back() = Op; 01209 } 01210 01211 if (Changed) 01212 Result = DAG.UpdateNodeOperands(Result, Ops); 01213 01214 // INLINE asm returns a chain and flag, make sure to add both to the map. 01215 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 01216 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 01217 return Result.getValue(Op.ResNo); 01218 } 01219 case ISD::BR: 01220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01221 // Ensure that libcalls are emitted before a branch. 01222 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 01223 Tmp1 = LegalizeOp(Tmp1); 01224 LastCALLSEQ_END = DAG.getEntryNode(); 01225 01226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 01227 break; 01228 case ISD::BRIND: 01229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01230 // Ensure that libcalls are emitted before a branch. 01231 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 01232 Tmp1 = LegalizeOp(Tmp1); 01233 LastCALLSEQ_END = DAG.getEntryNode(); 01234 01235 switch (getTypeAction(Node->getOperand(1).getValueType())) { 01236 default: assert(0 && "Indirect target must be legal type (pointer)!"); 01237 case Legal: 01238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 01239 break; 01240 } 01241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 01242 break; 01243 case ISD::BRCOND: 01244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01245 // Ensure that libcalls are emitted before a return. 01246 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 01247 Tmp1 = LegalizeOp(Tmp1); 01248 LastCALLSEQ_END = DAG.getEntryNode(); 01249 01250 switch (getTypeAction(Node->getOperand(1).getValueType())) { 01251 case Expand: assert(0 && "It's impossible to expand bools"); 01252 case Legal: 01253 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 01254 break; 01255 case Promote: 01256 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 01257 break; 01258 } 01259 01260 // Basic block destination (Op#2) is always legal. 01261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 01262 01263 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 01264 default: assert(0 && "This action is not supported yet!"); 01265 case TargetLowering::Legal: break; 01266 case TargetLowering::Custom: 01267 Tmp1 = TLI.LowerOperation(Result, DAG); 01268 if (Tmp1.Val) Result = Tmp1; 01269 break; 01270 case TargetLowering::Expand: 01271 // Expand brcond's setcc into its constituent parts and create a BR_CC 01272 // Node. 01273 if (Tmp2.getOpcode() == ISD::SETCC) { 01274 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 01275 Tmp2.getOperand(0), Tmp2.getOperand(1), 01276 Node->getOperand(2)); 01277 } else { 01278 // Make sure the condition is either zero or one. It may have been 01279 // promoted from something else. 01280 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType()); 01281 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1)) 01282 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 01283 01284 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 01285 DAG.getCondCode(ISD::SETNE), Tmp2, 01286 DAG.getConstant(0, Tmp2.getValueType()), 01287 Node->getOperand(2)); 01288 } 01289 break; 01290 } 01291 break; 01292 case ISD::BR_CC: 01293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01294 // Ensure that libcalls are emitted before a branch. 01295 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 01296 Tmp1 = LegalizeOp(Tmp1); 01297 LastCALLSEQ_END = DAG.getEntryNode(); 01298 01299 Tmp2 = Node->getOperand(2); // LHS 01300 Tmp3 = Node->getOperand(3); // RHS 01301 Tmp4 = Node->getOperand(1); // CC 01302 01303 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 01304 01305 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 01306 // the LHS is a legal SETCC itself. In this case, we need to compare 01307 // the result against zero to select between true and false values. 01308 if (Tmp3.Val == 0) { 01309 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 01310 Tmp4 = DAG.getCondCode(ISD::SETNE); 01311 } 01312 01313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 01314 Node->getOperand(4)); 01315 01316 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 01317 default: assert(0 && "Unexpected action for BR_CC!"); 01318 case TargetLowering::Legal: break; 01319 case TargetLowering::Custom: 01320 Tmp4 = TLI.LowerOperation(Result, DAG); 01321 if (Tmp4.Val) Result = Tmp4; 01322 break; 01323 } 01324 break; 01325 case ISD::LOAD: { 01326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 01328 01329 MVT::ValueType VT = Node->getValueType(0); 01330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 01331 Tmp3 = Result.getValue(0); 01332 Tmp4 = Result.getValue(1); 01333 01334 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 01335 default: assert(0 && "This action is not supported yet!"); 01336 case TargetLowering::Legal: break; 01337 case TargetLowering::Custom: 01338 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 01339 if (Tmp1.Val) { 01340 Tmp3 = LegalizeOp(Tmp1); 01341 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 01342 } 01343 break; 01344 case TargetLowering::Promote: { 01345 // Only promote a load of vector type to another. 01346 assert(MVT::isVector(VT) && "Cannot promote this load!"); 01347 // Change base type to a different vector type. 01348 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 01349 01350 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2)); 01351 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 01352 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 01353 break; 01354 } 01355 } 01356 // Since loads produce two values, make sure to remember that we 01357 // legalized both of them. 01358 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 01359 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 01360 return Op.ResNo ? Tmp4 : Tmp3; 01361 } 01362 case ISD::EXTLOAD: 01363 case ISD::SEXTLOAD: 01364 case ISD::ZEXTLOAD: { 01365 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01366 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 01367 01368 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 01369 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 01370 default: assert(0 && "This action is not supported yet!"); 01371 case TargetLowering::Promote: 01372 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 01373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 01374 DAG.getValueType(MVT::i8)); 01375 Tmp1 = Result.getValue(0); 01376 Tmp2 = Result.getValue(1); 01377 break; 01378 case TargetLowering::Custom: 01379 isCustom = true; 01380 // FALLTHROUGH 01381 case TargetLowering::Legal: 01382 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 01383 Node->getOperand(3)); 01384 Tmp1 = Result.getValue(0); 01385 Tmp2 = Result.getValue(1); 01386 01387 if (isCustom) { 01388 Tmp3 = TLI.LowerOperation(Tmp3, DAG); 01389 if (Tmp3.Val) { 01390 Tmp1 = LegalizeOp(Tmp3); 01391 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 01392 } 01393 } 01394 break; 01395 case TargetLowering::Expand: 01396 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 01397 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 01398 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 01399 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 01400 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 01401 Tmp2 = LegalizeOp(Load.getValue(1)); 01402 break; 01403 } 01404 assert(Node->getOpcode() != ISD::EXTLOAD && 01405 "EXTLOAD should always be supported!"); 01406 // Turn the unsupported load into an EXTLOAD followed by an explicit 01407 // zero/sign extend inreg. 01408 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 01409 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 01410 SDOperand ValRes; 01411 if (Node->getOpcode() == ISD::SEXTLOAD) 01412 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 01413 Result, DAG.getValueType(SrcVT)); 01414 else 01415 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 01416 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 01417 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 01418 break; 01419 } 01420 // Since loads produce two values, make sure to remember that we legalized 01421 // both of them. 01422 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 01423 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 01424 return Op.ResNo ? Tmp2 : Tmp1; 01425 } 01426 case ISD::EXTRACT_ELEMENT: { 01427 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 01428 switch (getTypeAction(OpTy)) { 01429 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 01430 case Legal: 01431 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 01432 // 1 -> Hi 01433 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 01434 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 01435 TLI.getShiftAmountTy())); 01436 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 01437 } else { 01438 // 0 -> Lo 01439 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 01440 Node->getOperand(0)); 01441 } 01442 break; 01443 case Expand: 01444 // Get both the low and high parts. 01445 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 01446 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 01447 Result = Tmp2; // 1 -> Hi 01448 else 01449 Result = Tmp1; // 0 -> Lo 01450 break; 01451 } 01452 break; 01453 } 01454 01455 case ISD::CopyToReg: 01456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01457 01458 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 01459 "Register type must be legal!"); 01460 // Legalize the incoming value (must be a legal type). 01461 Tmp2 = LegalizeOp(Node->getOperand(2)); 01462 if (Node->getNumValues() == 1) { 01463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 01464 } else { 01465 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 01466 if (Node->getNumOperands() == 4) { 01467 Tmp3 = LegalizeOp(Node->getOperand(3)); 01468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 01469 Tmp3); 01470 } else { 01471 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 01472 } 01473 01474 // Since this produces two values, make sure to remember that we legalized 01475 // both of them. 01476 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 01477 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 01478 return Result; 01479 } 01480 break; 01481 01482 case ISD::RET: 01483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01484 01485 // Ensure that libcalls are emitted before a return. 01486 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 01487 Tmp1 = LegalizeOp(Tmp1); 01488 LastCALLSEQ_END = DAG.getEntryNode(); 01489 01490 switch (Node->getNumOperands()) { 01491 case 3: // ret val 01492 Tmp2 = Node->getOperand(1); 01493 Tmp3 = Node->getOperand(2); // Signness 01494 switch (getTypeAction(Tmp2.getValueType())) { 01495 case Legal: 01496 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 01497 break; 01498 case Expand: 01499 if (Tmp2.getValueType() != MVT::Vector) { 01500 SDOperand Lo, Hi; 01501 ExpandOp(Tmp2, Lo, Hi); 01502 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 01503 } else { 01504 SDNode *InVal = Tmp2.Val; 01505 unsigned NumElems = 01506 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 01507 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 01508 01509 // Figure out if there is a Packed type corresponding to this Vector 01510 // type. If so, convert to the packed type. 01511 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 01512 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 01513 // Turn this into a return of the packed type. 01514 Tmp2 = PackVectorOp(Tmp2, TVT); 01515 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 01516 } else if (NumElems == 1) { 01517 // Turn this into a return of the scalar type. 01518 Tmp2 = PackVectorOp(Tmp2, EVT); 01519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 01520 01521 // FIXME: Returns of gcc generic vectors smaller than a legal type 01522 // should be returned in integer registers! 01523 01524 // The scalarized value type may not be legal, e.g. it might require 01525 // promotion or expansion. Relegalize the return. 01526 Result = LegalizeOp(Result); 01527 } else { 01528 // FIXME: Returns of gcc generic vectors larger than a legal vector 01529 // type should be returned by reference! 01530 SDOperand Lo, Hi; 01531 SplitVectorOp(Tmp2, Lo, Hi); 01532 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); 01533 Result = LegalizeOp(Result); 01534 } 01535 } 01536 break; 01537 case Promote: 01538 Tmp2 = PromoteOp(Node->getOperand(1)); 01539 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 01540 Result = LegalizeOp(Result); 01541 break; 01542 } 01543 break; 01544 case 1: // ret void 01545 Result = DAG.UpdateNodeOperands(Result, Tmp1); 01546 break; 01547 default: { // ret <values> 01548 std::vector<SDOperand> NewValues; 01549 NewValues.push_back(Tmp1); 01550 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 01551 switch (getTypeAction(Node->getOperand(i).getValueType())) { 01552 case Legal: 01553 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 01554 NewValues.push_back(Node->getOperand(i+1)); 01555 break; 01556 case Expand: { 01557 SDOperand Lo, Hi; 01558 assert(Node->getOperand(i).getValueType() != MVT::Vector && 01559 "FIXME: TODO: implement returning non-legal vector types!"); 01560 ExpandOp(Node->getOperand(i), Lo, Hi); 01561 NewValues.push_back(Lo); 01562 NewValues.push_back(Node->getOperand(i+1)); 01563 NewValues.push_back(Hi); 01564 NewValues.push_back(Node->getOperand(i+1)); 01565 break; 01566 } 01567 case Promote: 01568 assert(0 && "Can't promote multiple return value yet!"); 01569 } 01570 01571 if (NewValues.size() == Node->getNumOperands()) 01572 Result = DAG.UpdateNodeOperands(Result, NewValues); 01573 else 01574 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 01575 break; 01576 } 01577 } 01578 01579 if (Result.getOpcode() == ISD::RET) { 01580 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 01581 default: assert(0 && "This action is not supported yet!"); 01582 case TargetLowering::Legal: break; 01583 case TargetLowering::Custom: 01584 Tmp1 = TLI.LowerOperation(Result, DAG); 01585 if (Tmp1.Val) Result = Tmp1; 01586 break; 01587 } 01588 } 01589 break; 01590 case ISD::STORE: { 01591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01592 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 01593 01594 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 01595 // FIXME: We shouldn't do this for TargetConstantFP's. 01596 // FIXME: move this to the DAG Combiner! 01597 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 01598 if (CFP->getValueType(0) == MVT::f32) { 01599 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 01600 } else { 01601 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 01602 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 01603 } 01604 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 01605 Node->getOperand(3)); 01606 break; 01607 } 01608 01609 switch (getTypeAction(Node->getOperand(1).getValueType())) { 01610 case Legal: { 01611 Tmp3 = LegalizeOp(Node->getOperand(1)); 01612 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 01613 Node->getOperand(3)); 01614 01615 MVT::ValueType VT = Tmp3.getValueType(); 01616 switch (TLI.getOperationAction(ISD::STORE, VT)) { 01617 default: assert(0 && "This action is not supported yet!"); 01618 case TargetLowering::Legal: break; 01619 case TargetLowering::Custom: 01620 Tmp1 = TLI.LowerOperation(Result, DAG); 01621 if (Tmp1.Val) Result = Tmp1; 01622 break; 01623 case TargetLowering::Promote: 01624 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 01625 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 01626 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 01627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 01628 Node->getOperand(3)); 01629 break; 01630 } 01631 break; 01632 } 01633 case Promote: 01634 // Truncate the value and store the result. 01635 Tmp3 = PromoteOp(Node->getOperand(1)); 01636 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 01637 Node->getOperand(3), 01638 DAG.getValueType(Node->getOperand(1).getValueType())); 01639 break; 01640 01641 case Expand: 01642 unsigned IncrementSize = 0; 01643 SDOperand Lo, Hi; 01644 01645 // If this is a vector type, then we have to calculate the increment as 01646 // the product of the element size in bytes, and the number of elements 01647 // in the high half of the vector. 01648 if (Node->getOperand(1).getValueType() == MVT::Vector) { 01649 SDNode *InVal = Node->getOperand(1).Val; 01650 unsigned NumElems = 01651 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 01652 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 01653 01654 // Figure out if there is a Packed type corresponding to this Vector 01655 // type. If so, convert to the packed type. 01656 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 01657 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 01658 // Turn this into a normal store of the packed type. 01659 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 01660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 01661 Node->getOperand(3)); 01662 Result = LegalizeOp(Result); 01663 break; 01664 } else if (NumElems == 1) { 01665 // Turn this into a normal store of the scalar type. 01666 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 01667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 01668 Node->getOperand(3)); 01669 // The scalarized value type may not be legal, e.g. it might require 01670 // promotion or expansion. Relegalize the scalar store. 01671 Result = LegalizeOp(Result); 01672 break; 01673 } else { 01674 SplitVectorOp(Node->getOperand(1), Lo, Hi); 01675 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 01676 } 01677 } else { 01678 ExpandOp(Node->getOperand(1), Lo, Hi); 01679 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 01680 01681 if (!TLI.isLittleEndian()) 01682 std::swap(Lo, Hi); 01683 } 01684 01685 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 01686 Node->getOperand(3)); 01687 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 01688 getIntPtrConstant(IncrementSize)); 01689 assert(isTypeLegal(Tmp2.getValueType()) && 01690 "Pointers must be legal!"); 01691 // FIXME: This sets the srcvalue of both halves to be the same, which is 01692 // wrong. 01693 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 01694 Node->getOperand(3)); 01695 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 01696 break; 01697 } 01698 break; 01699 } 01700 case ISD::PCMARKER: 01701 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01702 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 01703 break; 01704 case ISD::STACKSAVE: 01705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01706 Result = DAG.UpdateNodeOperands(Result, Tmp1); 01707 Tmp1 = Result.getValue(0); 01708 Tmp2 = Result.getValue(1); 01709 01710 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 01711 default: assert(0 && "This action is not supported yet!"); 01712 case TargetLowering::Legal: break; 01713 case TargetLowering::Custom: 01714 Tmp3 = TLI.LowerOperation(Result, DAG); 01715 if (Tmp3.Val) { 01716 Tmp1 = LegalizeOp(Tmp3); 01717 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 01718 } 01719 break; 01720 case TargetLowering::Expand: 01721 // Expand to CopyFromReg if the target set 01722 // StackPointerRegisterToSaveRestore. 01723 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 01724 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 01725 Node->getValueType(0)); 01726 Tmp2 = Tmp1.getValue(1); 01727 } else { 01728 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 01729 Tmp2 = Node->getOperand(0); 01730 } 01731 break; 01732 } 01733 01734 // Since stacksave produce two values, make sure to remember that we 01735 // legalized both of them. 01736 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 01737 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 01738 return Op.ResNo ? Tmp2 : Tmp1; 01739 01740 case ISD::STACKRESTORE: 01741 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 01743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 01744 01745 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 01746 default: assert(0 && "This action is not supported yet!"); 01747 case TargetLowering::Legal: break; 01748 case TargetLowering::Custom: 01749 Tmp1 = TLI.LowerOperation(Result, DAG); 01750 if (Tmp1.Val) Result = Tmp1; 01751 break; 01752 case TargetLowering::Expand: 01753 // Expand to CopyToReg if the target set 01754 // StackPointerRegisterToSaveRestore. 01755 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 01756 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 01757 } else { 01758 Result = Tmp1; 01759 } 01760 break; 01761 } 01762 break; 01763 01764 case ISD::READCYCLECOUNTER: 01765 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 01766 Result = DAG.UpdateNodeOperands(Result, Tmp1); 01767 01768 // Since rdcc produce two values, make sure to remember that we legalized 01769 // both of them. 01770 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 01771 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 01772 return Result; 01773 01774 case ISD::TRUNCSTORE: { 01775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 01776 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 01777 01778 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 01779 "Cannot handle illegal TRUNCSTORE yet!"); 01780 Tmp2 = LegalizeOp(Node->getOperand(1)); 01781 01782 // The only promote case we handle is TRUNCSTORE:i1 X into 01783 // -> TRUNCSTORE:i8 (and X, 1) 01784 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 01785 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 01786 TargetLowering::Promote) { 01787 // Promote the bool to a mask then store. 01788 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 01789 DAG.getConstant(1, Tmp2.getValueType())); 01790 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 01791 Node->getOperand(3), DAG.getValueType(MVT::i8)); 01792 01793 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 01794 Tmp3 != Node->getOperand(2)) { 01795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 01796 Node->getOperand(3), Node->getOperand(4)); 01797 } 01798 01799 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 01800 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 01801 default: assert(0 && "This action is not supported yet!"); 01802 case TargetLowering::Legal: break; 01803 case TargetLowering::Custom: 01804 Tmp1 = TLI.LowerOperation(Result, DAG); 01805 if (Tmp1.Val) Result = Tmp1; 01806 break; 01807 } 01808 break; 01809 } 01810 case ISD::SELECT: 01811 switch (getTypeAction(Node->getOperand(0).getValueType())) { 01812 case Expand: assert(0 && "It's impossible to expand bools"); 01813 case Legal: 01814 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 01815 break; 01816 case Promote: 01817 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 01818 break; 01819 } 01820 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 01821 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 01822 01823 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 01824 01825 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 01826 default: assert(0 && "This action is not supported yet!"); 01827 case TargetLowering::Legal: break; 01828 case TargetLowering::Custom: { 01829 Tmp1 = TLI.LowerOperation(Result, DAG); 01830 if (Tmp1.Val) Result = Tmp1; 01831 break; 01832 } 01833 case TargetLowering::Expand: 01834 if (Tmp1.getOpcode() == ISD::SETCC) { 01835 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 01836 Tmp2, Tmp3, 01837 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 01838 } else { 01839 // Make sure the condition is either zero or one. It may have been 01840 // promoted from something else. 01841 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType()); 01842 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1)) 01843 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 01844 Result = DAG.getSelectCC(Tmp1, 01845 DAG.getConstant(0, Tmp1.getValueType()), 01846 Tmp2, Tmp3, ISD::SETNE); 01847 } 01848 break; 01849 case TargetLowering::Promote: { 01850 MVT::ValueType NVT = 01851 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 01852 unsigned ExtOp, TruncOp; 01853 if (MVT::isVector(Tmp2.getValueType())) { 01854 ExtOp = ISD::BIT_CONVERT; 01855 TruncOp = ISD::BIT_CONVERT; 01856 } else if (MVT::isInteger(Tmp2.getValueType())) { 01857 ExtOp = ISD::ANY_EXTEND; 01858 TruncOp = ISD::TRUNCATE; 01859 } else { 01860 ExtOp = ISD::FP_EXTEND; 01861 TruncOp = ISD::FP_ROUND; 01862 } 01863 // Promote each of the values to the new type. 01864 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 01865 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 01866 // Perform the larger operation, then round down. 01867 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 01868 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 01869 break; 01870 } 01871 } 01872 break; 01873 case ISD::SELECT_CC: { 01874 Tmp1 = Node->getOperand(0); // LHS 01875 Tmp2 = Node->getOperand(1); // RHS 01876 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 01877 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 01878 SDOperand CC = Node->getOperand(4); 01879 01880 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 01881 01882 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 01883 // the LHS is a legal SETCC itself. In this case, we need to compare 01884 // the result against zero to select between true and false values. 01885 if (Tmp2.Val == 0) { 01886 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 01887 CC = DAG.getCondCode(ISD::SETNE); 01888 } 01889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 01890 01891 // Everything is legal, see if we should expand this op or something. 01892 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 01893 default: assert(0 && "This action is not supported yet!"); 01894 case TargetLowering::Legal: break; 01895 case TargetLowering::Custom: 01896 Tmp1 = TLI.LowerOperation(Result, DAG); 01897 if (Tmp1.Val) Result = Tmp1; 01898 break; 01899 } 01900 break; 01901 } 01902 case ISD::SETCC: 01903 Tmp1 = Node->getOperand(0); 01904 Tmp2 = Node->getOperand(1); 01905 Tmp3 = Node->getOperand(2); 01906 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 01907 01908 // If we had to Expand the SetCC operands into a SELECT node, then it may 01909 // not always be possible to return a true LHS & RHS. In this case, just 01910 // return the value we legalized, returned in the LHS 01911 if (Tmp2.Val == 0) { 01912 Result = Tmp1; 01913 break; 01914 } 01915 01916 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 01917 default: assert(0 && "Cannot handle this action for SETCC yet!"); 01918 case TargetLowering::Custom: 01919 isCustom = true; 01920 // FALLTHROUGH. 01921 case TargetLowering::Legal: 01922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 01923 if (isCustom) { 01924 Tmp3 = TLI.LowerOperation(Result, DAG); 01925 if (Tmp3.Val) Result = Tmp3; 01926 } 01927 break; 01928 case TargetLowering::Promote: { 01929 // First step, figure out the appropriate operation to use. 01930 // Allow SETCC to not be supported for all legal data types 01931 // Mostly this targets FP 01932 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 01933 MVT::ValueType OldVT = NewInTy; 01934 01935 // Scan for the appropriate larger type to use. 01936 while (1) { 01937 NewInTy = (MVT::ValueType)(NewInTy+1); 01938 01939 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 01940 "Fell off of the edge of the integer world"); 01941 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 01942 "Fell off of the edge of the floating point world"); 01943 01944 // If the target supports SETCC of this type, use it. 01945 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 01946 break; 01947 } 01948 if (MVT::isInteger(NewInTy)) 01949 assert(0 && "Cannot promote Legal Integer SETCC yet"); 01950 else { 01951 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 01952 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 01953 } 01954 Tmp1 = LegalizeOp(Tmp1); 01955 Tmp2 = LegalizeOp(Tmp2); 01956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 01957 Result = LegalizeOp(Result); 01958 break; 01959 } 01960 case TargetLowering::Expand: 01961 // Expand a setcc node into a select_cc of the same condition, lhs, and 01962 // rhs that selects between const 1 (true) and const 0 (false). 01963 MVT::ValueType VT = Node->getValueType(0); 01964 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 01965 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 01966 Node->getOperand(2)); 01967 break; 01968 } 01969 break; 01970 case ISD::MEMSET: 01971 case ISD::MEMCPY: 01972 case ISD::MEMMOVE: { 01973 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 01974 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 01975 01976 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 01977 switch (getTypeAction(Node->getOperand(2).getValueType())) { 01978 case Expand: assert(0 && "Cannot expand a byte!"); 01979 case Legal: 01980 Tmp3 = LegalizeOp(Node->getOperand(2)); 01981 break; 01982 case Promote: 01983 Tmp3 = PromoteOp(Node->getOperand(2)); 01984 break; 01985 } 01986 } else { 01987 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 01988 } 01989 01990 SDOperand Tmp4; 01991 switch (getTypeAction(Node->getOperand(3).getValueType())) { 01992 case Expand: { 01993 // Length is too big, just take the lo-part of the length. 01994 SDOperand HiPart; 01995 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 01996 break; 01997 } 01998 case Legal: 01999 Tmp4 = LegalizeOp(Node->getOperand(3)); 02000 break; 02001 case Promote: 02002 Tmp4 = PromoteOp(Node->getOperand(3)); 02003 break; 02004 } 02005 02006 SDOperand Tmp5; 02007 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 02008 case Expand: assert(0 && "Cannot expand this yet!"); 02009 case Legal: 02010 Tmp5 = LegalizeOp(Node->getOperand(4)); 02011 break; 02012 case Promote: 02013 Tmp5 = PromoteOp(Node->getOperand(4)); 02014 break; 02015 } 02016 02017 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 02018 default: assert(0 && "This action not implemented for this operation!"); 02019 case TargetLowering::Custom: 02020 isCustom = true; 02021 // FALLTHROUGH 02022 case TargetLowering::Legal: 02023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 02024 if (isCustom) { 02025 Tmp1 = TLI.LowerOperation(Result, DAG); 02026 if (Tmp1.Val) Result = Tmp1; 02027 } 02028 break; 02029 case TargetLowering::Expand: { 02030 // Otherwise, the target does not support this operation. Lower the 02031 // operation to an explicit libcall as appropriate. 02032 MVT::ValueType IntPtr = TLI.getPointerTy(); 02033 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 02034 std::vector<std::pair<SDOperand, const Type*> > Args; 02035 02036 const char *FnName = 0; 02037 if (Node->getOpcode() == ISD::MEMSET) { 02038 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 02039 // Extend the (previously legalized) ubyte argument to be an int value 02040 // for the call. 02041 if (Tmp3.getValueType() > MVT::i32) 02042 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 02043 else 02044 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 02045 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 02046 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 02047 02048 FnName = "memset"; 02049 } else if (Node->getOpcode() == ISD::MEMCPY || 02050 Node->getOpcode() == ISD::MEMMOVE) { 02051 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 02052 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 02053 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 02054 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 02055 } else { 02056 assert(0 && "Unknown op!"); 02057 } 02058 02059 std::pair<SDOperand,SDOperand> CallResult = 02060 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 02061 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 02062 Result = CallResult.second; 02063 break; 02064 } 02065 } 02066 break; 02067 } 02068 02069 case ISD::SHL_PARTS: 02070 case ISD::SRA_PARTS: 02071 case ISD::SRL_PARTS: { 02072 std::vector<SDOperand> Ops; 02073 bool Changed = false; 02074 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 02075 Ops.push_back(LegalizeOp(Node->getOperand(i))); 02076 Changed |= Ops.back() != Node->getOperand(i); 02077 } 02078 if (Changed) 02079 Result = DAG.UpdateNodeOperands(Result, Ops); 02080 02081 switch (TLI.getOperationAction(Node->getOpcode(), 02082 Node->getValueType(0))) { 02083 default: assert(0 && "This action is not supported yet!"); 02084 case TargetLowering::Legal: break; 02085 case TargetLowering::Custom: 02086 Tmp1 = TLI.LowerOperation(Result, DAG); 02087 if (Tmp1.Val) { 02088 SDOperand Tmp2, RetVal(0, 0); 02089 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 02090 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 02091 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 02092 if (i == Op.ResNo) 02093 RetVal = Tmp2; 02094 } 02095 assert(RetVal.Val && "Illegal result number"); 02096 return RetVal; 02097 } 02098 break; 02099 } 02100 02101 // Since these produce multiple values, make sure to remember that we 02102 // legalized all of them. 02103 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 02104 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 02105 return Result.getValue(Op.ResNo); 02106 } 02107 02108 // Binary operators 02109 case ISD::ADD: 02110 case ISD::SUB: 02111 case ISD::MUL: 02112 case ISD::MULHS: 02113 case ISD::MULHU: 02114 case ISD::UDIV: 02115 case ISD::SDIV: 02116 case ISD::AND: 02117 case ISD::OR: 02118 case ISD::XOR: 02119 case ISD::SHL: 02120 case ISD::SRL: 02121 case ISD::SRA: 02122 case ISD::FADD: 02123 case ISD::FSUB: 02124 case ISD::FMUL: 02125 case ISD::FDIV: 02126 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 02127 switch (getTypeAction(Node->getOperand(1).getValueType())) { 02128 case Expand: assert(0 && "Not possible"); 02129 case Legal: 02130 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 02131 break; 02132 case Promote: 02133 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 02134 break; 02135 } 02136 02137 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 02138 02139 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 02140 default: assert(0 && "BinOp legalize operation not supported"); 02141 case TargetLowering::Legal: break; 02142 case TargetLowering::Custom: 02143 Tmp1 = TLI.LowerOperation(Result, DAG); 02144 if (Tmp1.Val) Result = Tmp1; 02145 break; 02146 case TargetLowering::Expand: { 02147 assert(MVT::isVector(Node->getValueType(0)) && 02148 "Cannot expand this binary operator!"); 02149 // Expand the operation into a bunch of nasty scalar code. 02150 std::vector<SDOperand> Ops; 02151 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 02152 MVT::ValueType PtrVT = TLI.getPointerTy(); 02153 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 02154 i != e; ++i) { 02155 SDOperand Idx = DAG.getConstant(i, PtrVT); 02156 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 02157 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 02158 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 02159 } 02160 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops); 02161 break; 02162 } 02163 case TargetLowering::Promote: { 02164 switch (Node->getOpcode()) { 02165 default: assert(0 && "Do not know how to promote this BinOp!"); 02166 case ISD::AND: 02167 case ISD::OR: 02168 case ISD::XOR: { 02169 MVT::ValueType OVT = Node->getValueType(0); 02170 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 02171 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 02172 // Bit convert each of the values to the new type. 02173 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 02174 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 02175 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 02176 // Bit convert the result back the original type. 02177 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 02178 break; 02179 } 02180 } 02181 } 02182 } 02183 break; 02184 02185 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 02186 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 02187 switch (getTypeAction(Node->getOperand(1).getValueType())) { 02188 case Expand: assert(0 && "Not possible"); 02189 case Legal: 02190 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 02191 break; 02192 case Promote: 02193 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 02194 break; 02195 } 02196 02197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 02198 02199 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 02200 default: assert(0 && "Operation not supported"); 02201 case TargetLowering::Custom: 02202 Tmp1 = TLI.LowerOperation(Result, DAG); 02203 if (Tmp1.Val) Result = Tmp1; 02204 break; 02205 case TargetLowering::Legal: break; 02206 case TargetLowering::Expand: 02207 // If this target supports fabs/fneg natively, do this efficiently. 02208 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && 02209 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { 02210 // Get the sign bit of the RHS. 02211 MVT::ValueType IVT = 02212 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 02213 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 02214 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 02215 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 02216 // Get the absolute value of the result. 02217 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 02218 // Select between the nabs and abs value based on the sign bit of 02219 // the input. 02220 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 02221 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 02222 AbsVal), 02223 AbsVal); 02224 Result = LegalizeOp(Result); 02225 break; 02226 } 02227 02228 // Otherwise, do bitwise ops! 02229 02230 // copysign -> copysignf/copysign libcall. 02231 const char *FnName; 02232 if (Node->getValueType(0) == MVT::f32) { 02233 FnName = "copysignf"; 02234 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type. 02235 Result = DAG.UpdateNodeOperands(Result, Tmp1, 02236 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2)); 02237 } else { 02238 FnName = "copysign"; 02239 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type. 02240 Result = DAG.UpdateNodeOperands(Result, Tmp1, 02241 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2)); 02242 } 02243 SDOperand Dummy; 02244 Result = ExpandLibCall(FnName, Node, Dummy); 02245 break; 02246 } 02247 break; 02248 02249 case ISD::ADDC: 02250 case ISD::SUBC: 02251 Tmp1 = LegalizeOp(Node->getOperand(0)); 02252 Tmp2 = LegalizeOp(Node->getOperand(1)); 02253 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 02254 // Since this produces two values, make sure to remember that we legalized 02255 // both of them. 02256 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 02257 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 02258 return Result; 02259 02260 case ISD::ADDE: 02261 case ISD::SUBE: 02262 Tmp1 = LegalizeOp(Node->getOperand(0)); 02263 Tmp2 = LegalizeOp(Node->getOperand(1)); 02264 Tmp3 = LegalizeOp(Node->getOperand(2)); 02265 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 02266 // Since this produces two values, make sure to remember that we legalized 02267 // both of them. 02268 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 02269 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 02270 return Result; 02271 02272 case ISD::BUILD_PAIR: { 02273 MVT::ValueType PairTy = Node->getValueType(0); 02274 // TODO: handle the case where the Lo and Hi operands are not of legal type 02275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 02276 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 02277 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 02278 case TargetLowering::Promote: 02279 case TargetLowering::Custom: 02280 assert(0 && "Cannot promote/custom this yet!"); 02281 case TargetLowering::Legal: 02282 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 02283 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 02284 break; 02285 case TargetLowering::Expand: 02286 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 02287 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 02288 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 02289 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 02290 TLI.getShiftAmountTy())); 02291 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 02292 break; 02293 } 02294 break; 02295 } 02296 02297 case ISD::UREM: 02298 case ISD::SREM: 02299 case ISD::FREM: 02300 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 02301 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 02302 02303 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 02304 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 02305 case TargetLowering::Custom: 02306 isCustom = true; 02307 // FALLTHROUGH 02308 case TargetLowering::Legal: 02309 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 02310 if (isCustom) { 02311 Tmp1 = TLI.LowerOperation(Result, DAG); 02312 if (Tmp1.Val) Result = Tmp1; 02313 } 02314 break; 02315 case TargetLowering::Expand: 02316 if (MVT::isInteger(Node->getValueType(0))) { 02317 // X % Y -> X-X/Y*Y 02318 MVT::ValueType VT = Node->getValueType(0); 02319 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 02320 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 02321 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 02322 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 02323 } else { 02324 // Floating point mod -> fmod libcall. 02325 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 02326 SDOperand Dummy; 02327 Result = ExpandLibCall(FnName, Node, Dummy); 02328 } 02329 break; 02330 } 02331 break; 02332 case ISD::VAARG: { 02333 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 02334 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 02335 02336 MVT::ValueType VT = Node->getValueType(0); 02337 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 02338 default: assert(0 && "This action is not supported yet!"); 02339 case TargetLowering::Custom: 02340 isCustom = true; 02341 // FALLTHROUGH 02342 case TargetLowering::Legal: 02343 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 02344 Result = Result.getValue(0); 02345 Tmp1 = Result.getValue(1); 02346 02347 if (isCustom) { 02348 Tmp2 = TLI.LowerOperation(Result, DAG); 02349 if (Tmp2.Val) { 02350 Result = LegalizeOp(Tmp2); 02351 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 02352 } 02353 } 02354 break; 02355 case TargetLowering::Expand: { 02356 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 02357 Node->getOperand(2)); 02358 // Increment the pointer, VAList, to the next vaarg 02359 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 02360 DAG.getConstant(MVT::getSizeInBits(VT)/8, 02361 TLI.getPointerTy())); 02362 // Store the incremented VAList to the legalized pointer 02363 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 02364 Node->getOperand(2)); 02365 // Load the actual argument out of the pointer VAList 02366 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 02367 Tmp1 = LegalizeOp(Result.getValue(1)); 02368 Result = LegalizeOp(Result); 02369 break; 02370 } 02371 } 02372 // Since VAARG produces two values, make sure to remember that we 02373 // legalized both of them. 02374 AddLegalizedOperand(SDOperand(Node, 0), Result); 02375 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 02376 return Op.ResNo ? Tmp1 : Result; 02377 } 02378 02379 case ISD::VACOPY: 02380 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 02381 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 02382 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 02383 02384 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 02385 default: assert(0 && "This action is not supported yet!"); 02386 case TargetLowering::Custom: 02387 isCustom = true; 02388 // FALLTHROUGH 02389 case TargetLowering::Legal: 02390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 02391 Node->getOperand(3), Node->getOperand(4)); 02392 if (isCustom) { 02393 Tmp1 = TLI.LowerOperation(Result, DAG); 02394 if (Tmp1.Val) Result = Tmp1; 02395 } 02396 break; 02397 case TargetLowering::Expand: 02398 // This defaults to loading a pointer from the input and storing it to the 02399 // output, returning the chain. 02400 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 02401 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 02402 Node->getOperand(4)); 02403 break; 02404 } 02405 break; 02406 02407 case ISD::VAEND: 02408 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 02409 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 02410 02411 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 02412 default: assert(0 && "This action is not supported yet!"); 02413 case TargetLowering::Custom: 02414 isCustom = true; 02415 // FALLTHROUGH 02416 case TargetLowering::Legal: 02417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 02418 if (isCustom) { 02419 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 02420 if (Tmp1.Val) Result = Tmp1; 02421 } 02422 break; 02423 case TargetLowering::Expand: 02424 Result = Tmp1; // Default to a no-op, return the chain 02425 break; 02426 } 02427 break; 02428 02429 case ISD::VASTART: 02430 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 02431 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 02432 02433 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 02434 02435 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 02436 default: assert(0 && "This action is not supported yet!"); 02437 case TargetLowering::Legal: break; 02438 case TargetLowering::Custom: 02439 Tmp1 = TLI.LowerOperation(Result, DAG); 02440 if (Tmp1.Val) Result = Tmp1; 02441 break; 02442 } 02443 break; 02444 02445 case ISD::ROTL: 02446 case ISD::ROTR: 02447 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 02448 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 02449 02450 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 02451 "Cannot handle this yet!"); 02452 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 02453 break; 02454 02455 case ISD::BSWAP: 02456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 02457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 02458 case TargetLowering::Custom: 02459 assert(0 && "Cannot custom legalize this yet!"); 02460 case TargetLowering::Legal: 02461 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02462 break; 02463 case TargetLowering::Promote: { 02464 MVT::ValueType OVT = Tmp1.getValueType(); 02465 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 02466 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 02467 02468 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 02469 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 02470 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 02471 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 02472 break; 02473 } 02474 case TargetLowering::Expand: 02475 Result = ExpandBSWAP(Tmp1); 02476 break; 02477 } 02478 break; 02479 02480 case ISD::CTPOP: 02481 case ISD::CTTZ: 02482 case ISD::CTLZ: 02483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 02484 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 02485 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 02486 case TargetLowering::Legal: 02487 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02488 break; 02489 case TargetLowering::Promote: { 02490 MVT::ValueType OVT = Tmp1.getValueType(); 02491 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 02492 02493 // Zero extend the argument. 02494 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 02495 // Perform the larger operation, then subtract if needed. 02496 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 02497 switch (Node->getOpcode()) { 02498 case ISD::CTPOP: 02499 Result = Tmp1; 02500 break; 02501 case ISD::CTTZ: 02502 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 02503 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 02504 DAG.getConstant(getSizeInBits(NVT), NVT), 02505 ISD::SETEQ); 02506 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 02507 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 02508 break; 02509 case ISD::CTLZ: 02510 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 02511 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 02512 DAG.getConstant(getSizeInBits(NVT) - 02513 getSizeInBits(OVT), NVT)); 02514 break; 02515 } 02516 break; 02517 } 02518 case TargetLowering::Expand: 02519 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 02520 break; 02521 } 02522 break; 02523 02524 // Unary operators 02525 case ISD::FABS: 02526 case ISD::FNEG: 02527 case ISD::FSQRT: 02528 case ISD::FSIN: 02529 case ISD::FCOS: 02530 Tmp1 = LegalizeOp(Node->getOperand(0)); 02531 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 02532 case TargetLowering::Promote: 02533 case TargetLowering::Custom: 02534 isCustom = true; 02535 // FALLTHROUGH 02536 case TargetLowering::Legal: 02537 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02538 if (isCustom) { 02539 Tmp1 = TLI.LowerOperation(Result, DAG); 02540 if (Tmp1.Val) Result = Tmp1; 02541 } 02542 break; 02543 case TargetLowering::Expand: 02544 switch (Node->getOpcode()) { 02545 default: assert(0 && "Unreachable!"); 02546 case ISD::FNEG: 02547 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 02548 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 02549 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 02550 break; 02551 case ISD::FABS: { 02552 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 02553 MVT::ValueType VT = Node->getValueType(0); 02554 Tmp2 = DAG.getConstantFP(0.0, VT); 02555 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 02556 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 02557 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 02558 break; 02559 } 02560 case ISD::FSQRT: 02561 case ISD::FSIN: 02562 case ISD::FCOS: { 02563 MVT::ValueType VT = Node->getValueType(0); 02564 const char *FnName = 0; 02565 switch(Node->getOpcode()) { 02566 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 02567 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 02568 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 02569 default: assert(0 && "Unreachable!"); 02570 } 02571 SDOperand Dummy; 02572 Result = ExpandLibCall(FnName, Node, Dummy); 02573 break; 02574 } 02575 } 02576 break; 02577 } 02578 break; 02579 02580 case ISD::BIT_CONVERT: 02581 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 02582 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 02583 } else { 02584 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 02585 Node->getOperand(0).getValueType())) { 02586 default: assert(0 && "Unknown operation action!"); 02587 case TargetLowering::Expand: 02588 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 02589 break; 02590 case TargetLowering::Legal: 02591 Tmp1 = LegalizeOp(Node->getOperand(0)); 02592 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02593 break; 02594 } 02595 } 02596 break; 02597 case ISD::VBIT_CONVERT: { 02598 assert(Op.getOperand(0).getValueType() == MVT::Vector && 02599 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 02600 02601 // The input has to be a vector type, we have to either scalarize it, pack 02602 // it, or convert it based on whether the input vector type is legal. 02603 SDNode *InVal = Node->getOperand(0).Val; 02604 unsigned NumElems = 02605 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 02606 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 02607 02608 // Figure out if there is a Packed type corresponding to this Vector 02609 // type. If so, convert to the packed type. 02610 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 02611 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 02612 // Turn this into a bit convert of the packed input. 02613 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 02614 PackVectorOp(Node->getOperand(0), TVT)); 02615 break; 02616 } else if (NumElems == 1) { 02617 // Turn this into a bit convert of the scalar input. 02618 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 02619 PackVectorOp(Node->getOperand(0), EVT)); 02620 break; 02621 } else { 02622 // FIXME: UNIMP! Store then reload 02623 assert(0 && "Cast from unsupported vector type not implemented yet!"); 02624 } 02625 } 02626 02627 // Conversion operators. The source and destination have different types. 02628 case ISD::SINT_TO_FP: 02629 case ISD::UINT_TO_FP: { 02630 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 02631 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02632 case Legal: 02633 switch (TLI.getOperationAction(Node->getOpcode(), 02634 Node->getOperand(0).getValueType())) { 02635 default: assert(0 && "Unknown operation action!"); 02636 case TargetLowering::Custom: 02637 isCustom = true; 02638 // FALLTHROUGH 02639 case TargetLowering::Legal: 02640 Tmp1 = LegalizeOp(Node->getOperand(0)); 02641 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02642 if (isCustom) { 02643 Tmp1 = TLI.LowerOperation(Result, DAG); 02644 if (Tmp1.Val) Result = Tmp1; 02645 } 02646 break; 02647 case TargetLowering::Expand: 02648 Result = ExpandLegalINT_TO_FP(isSigned, 02649 LegalizeOp(Node->getOperand(0)), 02650 Node->getValueType(0)); 02651 break; 02652 case TargetLowering::Promote: 02653 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 02654 Node->getValueType(0), 02655 isSigned); 02656 break; 02657 } 02658 break; 02659 case Expand: 02660 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 02661 Node->getValueType(0), Node->getOperand(0)); 02662 break; 02663 case Promote: 02664 Tmp1 = PromoteOp(Node->getOperand(0)); 02665 if (isSigned) { 02666 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 02667 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 02668 } else { 02669 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 02670 Node->getOperand(0).getValueType()); 02671 } 02672 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02673 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 02674 break; 02675 } 02676 break; 02677 } 02678 case ISD::TRUNCATE: 02679 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02680 case Legal: 02681 Tmp1 = LegalizeOp(Node->getOperand(0)); 02682 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02683 break; 02684 case Expand: 02685 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 02686 02687 // Since the result is legal, we should just be able to truncate the low 02688 // part of the source. 02689 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 02690 break; 02691 case Promote: 02692 Result = PromoteOp(Node->getOperand(0)); 02693 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 02694 break; 02695 } 02696 break; 02697 02698 case ISD::FP_TO_SINT: 02699 case ISD::FP_TO_UINT: 02700 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02701 case Legal: 02702 Tmp1 = LegalizeOp(Node->getOperand(0)); 02703 02704 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 02705 default: assert(0 && "Unknown operation action!"); 02706 case TargetLowering::Custom: 02707 isCustom = true; 02708 // FALLTHROUGH 02709 case TargetLowering::Legal: 02710 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02711 if (isCustom) { 02712 Tmp1 = TLI.LowerOperation(Result, DAG); 02713 if (Tmp1.Val) Result = Tmp1; 02714 } 02715 break; 02716 case TargetLowering::Promote: 02717 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 02718 Node->getOpcode() == ISD::FP_TO_SINT); 02719 break; 02720 case TargetLowering::Expand: 02721 if (Node->getOpcode() == ISD::FP_TO_UINT) { 02722 SDOperand True, False; 02723 MVT::ValueType VT = Node->getOperand(0).getValueType(); 02724 MVT::ValueType NVT = Node->getValueType(0); 02725 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 02726 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 02727 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 02728 Node->getOperand(0), Tmp2, ISD::SETLT); 02729 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 02730 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 02731 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 02732 Tmp2)); 02733 False = DAG.getNode(ISD::XOR, NVT, False, 02734 DAG.getConstant(1ULL << ShiftAmt, NVT)); 02735 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 02736 break; 02737 } else { 02738 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 02739 } 02740 break; 02741 } 02742 break; 02743 case Expand: 02744 assert(0 && "Shouldn't need to expand other operators here!"); 02745 case Promote: 02746 Tmp1 = PromoteOp(Node->getOperand(0)); 02747 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 02748 Result = LegalizeOp(Result); 02749 break; 02750 } 02751 break; 02752 02753 case ISD::ANY_EXTEND: 02754 case ISD::ZERO_EXTEND: 02755 case ISD::SIGN_EXTEND: 02756 case ISD::FP_EXTEND: 02757 case ISD::FP_ROUND: 02758 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02759 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 02760 case Legal: 02761 Tmp1 = LegalizeOp(Node->getOperand(0)); 02762 Result = DAG.UpdateNodeOperands(Result, Tmp1); 02763 break; 02764 case Promote: 02765 switch (Node->getOpcode()) { 02766 case ISD::ANY_EXTEND: 02767 Tmp1 = PromoteOp(Node->getOperand(0)); 02768 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 02769 break; 02770 case ISD::ZERO_EXTEND: 02771 Result = PromoteOp(Node->getOperand(0)); 02772 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 02773 Result = DAG.getZeroExtendInReg(Result, 02774 Node->getOperand(0).getValueType()); 02775 break; 02776 case ISD::SIGN_EXTEND: 02777 Result = PromoteOp(Node->getOperand(0)); 02778 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 02779 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 02780 Result, 02781 DAG.getValueType(Node->getOperand(0).getValueType())); 02782 break; 02783 case ISD::FP_EXTEND: 02784 Result = PromoteOp(Node->getOperand(0)); 02785 if (Result.getValueType() != Op.getValueType()) 02786 // Dynamically dead while we have only 2 FP types. 02787 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 02788 break; 02789 case ISD::FP_ROUND: 02790 Result = PromoteOp(Node->getOperand(0)); 02791 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 02792 break; 02793 } 02794 } 02795 break; 02796 case ISD::FP_ROUND_INREG: 02797 case ISD::SIGN_EXTEND_INREG: { 02798 Tmp1 = LegalizeOp(Node->getOperand(0)); 02799 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 02800 02801 // If this operation is not supported, convert it to a shl/shr or load/store 02802 // pair. 02803 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 02804 default: assert(0 && "This action not supported for this op yet!"); 02805 case TargetLowering::Legal: 02806 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 02807 break; 02808 case TargetLowering::Expand: 02809 // If this is an integer extend and shifts are supported, do that. 02810 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 02811 // NOTE: we could fall back on load/store here too for targets without 02812 // SAR. However, it is doubtful that any exist. 02813 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 02814 MVT::getSizeInBits(ExtraVT); 02815 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 02816 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 02817 Node->getOperand(0), ShiftCst); 02818 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 02819 Result, ShiftCst); 02820 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 02821 // The only way we can lower this is to turn it into a STORETRUNC, 02822 // EXTLOAD pair, targetting a temporary location (a stack slot). 02823 02824 // NOTE: there is a choice here between constantly creating new stack 02825 // slots and always reusing the same one. We currently always create 02826 // new ones, as reuse may inhibit scheduling. 02827 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 02828 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 02829 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty); 02830 MachineFunction &MF = DAG.getMachineFunction(); 02831 int SSFI = 02832 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 02833 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 02834 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 02835 Node->getOperand(0), StackSlot, 02836 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 02837 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 02838 Result, StackSlot, DAG.getSrcValue(NULL), 02839 ExtraVT); 02840 } else { 02841 assert(0 && "Unknown op"); 02842 } 02843 break; 02844 } 02845 break; 02846 } 02847 } 02848 02849 assert(Result.getValueType() == Op.getValueType() && 02850 "Bad legalization!"); 02851 02852 // Make sure that the generated code is itself legal. 02853 if (Result != Op) 02854 Result = LegalizeOp(Result); 02855 02856 // Note that LegalizeOp may be reentered even from single-use nodes, which 02857 // means that we always must cache transformed nodes. 02858 AddLegalizedOperand(Op, Result); 02859 return Result; 02860 } 02861 02862 /// PromoteOp - Given an operation that produces a value in an invalid type, 02863 /// promote it to compute the value into a larger type. The produced value will 02864 /// have the correct bits for the low portion of the register, but no guarantee 02865 /// is made about the top bits: it may be zero, sign-extended, or garbage. 02866 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 02867 MVT::ValueType VT = Op.getValueType(); 02868 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 02869 assert(getTypeAction(VT) == Promote && 02870 "Caller should expand or legalize operands that are not promotable!"); 02871 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 02872 "Cannot promote to smaller type!"); 02873 02874 SDOperand Tmp1, Tmp2, Tmp3; 02875 SDOperand Result; 02876 SDNode *Node = Op.Val; 02877 02878 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 02879 if (I != PromotedNodes.end()) return I->second; 02880 02881 switch (Node->getOpcode()) { 02882 case ISD::CopyFromReg: 02883 assert(0 && "CopyFromReg must be legal!"); 02884 default: 02885 #ifndef NDEBUG 02886 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 02887 #endif 02888 assert(0 && "Do not know how to promote this operator!"); 02889 abort(); 02890 case ISD::UNDEF: 02891 Result = DAG.getNode(ISD::UNDEF, NVT); 02892 break; 02893 case ISD::Constant: 02894 if (VT != MVT::i1) 02895 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 02896 else 02897 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 02898 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 02899 break; 02900 case ISD::ConstantFP: 02901 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 02902 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 02903 break; 02904 02905 case ISD::SETCC: 02906 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 02907 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 02908 Node->getOperand(1), Node->getOperand(2)); 02909 break; 02910 02911 case ISD::TRUNCATE: 02912 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02913 case Legal: 02914 Result = LegalizeOp(Node->getOperand(0)); 02915 assert(Result.getValueType() >= NVT && 02916 "This truncation doesn't make sense!"); 02917 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 02918 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 02919 break; 02920 case Promote: 02921 // The truncation is not required, because we don't guarantee anything 02922 // about high bits anyway. 02923 Result = PromoteOp(Node->getOperand(0)); 02924 break; 02925 case Expand: 02926 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 02927 // Truncate the low part of the expanded value to the result type 02928 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 02929 } 02930 break; 02931 case ISD::SIGN_EXTEND: 02932 case ISD::ZERO_EXTEND: 02933 case ISD::ANY_EXTEND: 02934 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02935 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 02936 case Legal: 02937 // Input is legal? Just do extend all the way to the larger type. 02938 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 02939 break; 02940 case Promote: 02941 // Promote the reg if it's smaller. 02942 Result = PromoteOp(Node->getOperand(0)); 02943 // The high bits are not guaranteed to be anything. Insert an extend. 02944 if (Node->getOpcode() == ISD::SIGN_EXTEND) 02945 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 02946 DAG.getValueType(Node->getOperand(0).getValueType())); 02947 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 02948 Result = DAG.getZeroExtendInReg(Result, 02949 Node->getOperand(0).getValueType()); 02950 break; 02951 } 02952 break; 02953 case ISD::BIT_CONVERT: 02954 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 02955 Result = PromoteOp(Result); 02956 break; 02957 02958 case ISD::FP_EXTEND: 02959 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 02960 case ISD::FP_ROUND: 02961 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02962 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 02963 case Promote: assert(0 && "Unreachable with 2 FP types!"); 02964 case Legal: 02965 // Input is legal? Do an FP_ROUND_INREG. 02966 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 02967 DAG.getValueType(VT)); 02968 break; 02969 } 02970 break; 02971 02972 case ISD::SINT_TO_FP: 02973 case ISD::UINT_TO_FP: 02974 switch (getTypeAction(Node->getOperand(0).getValueType())) { 02975 case Legal: 02976 // No extra round required here. 02977 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 02978 break; 02979 02980 case Promote: 02981 Result = PromoteOp(Node->getOperand(0)); 02982 if (Node->getOpcode() == ISD::SINT_TO_FP) 02983 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 02984 Result, 02985 DAG.getValueType(Node->getOperand(0).getValueType())); 02986 else 02987 Result = DAG.getZeroExtendInReg(Result, 02988 Node->getOperand(0).getValueType()); 02989 // No extra round required here. 02990 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 02991 break; 02992 case Expand: 02993 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 02994 Node->getOperand(0)); 02995 // Round if we cannot tolerate excess precision. 02996 if (NoExcessFPPrecision) 02997 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 02998 DAG.getValueType(VT)); 02999 break; 03000 } 03001 break; 03002 03003 case ISD::SIGN_EXTEND_INREG: 03004 Result = PromoteOp(Node->getOperand(0)); 03005 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 03006 Node->getOperand(1)); 03007 break; 03008 case ISD::FP_TO_SINT: 03009 case ISD::FP_TO_UINT: 03010 switch (getTypeAction(Node->getOperand(0).getValueType())) { 03011 case Legal: 03012 Tmp1 = Node->getOperand(0); 03013 break; 03014 case Promote: 03015 // The input result is prerounded, so we don't have to do anything 03016 // special. 03017 Tmp1 = PromoteOp(Node->getOperand(0)); 03018 break; 03019 case Expand: 03020 assert(0 && "not implemented"); 03021 } 03022 // If we're promoting a UINT to a larger size, check to see if the new node 03023 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 03024 // we can use that instead. This allows us to generate better code for 03025 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 03026 // legal, such as PowerPC. 03027 if (Node->getOpcode() == ISD::FP_TO_UINT && 03028 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 03029 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 03030 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 03031 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 03032 } else { 03033 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 03034 } 03035 break; 03036 03037 case ISD::FABS: 03038 case ISD::FNEG: 03039 Tmp1 = PromoteOp(Node->getOperand(0)); 03040 assert(Tmp1.getValueType() == NVT); 03041 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 03042 // NOTE: we do not have to do any extra rounding here for 03043 // NoExcessFPPrecision, because we know the input will have the appropriate 03044 // precision, and these operations don't modify precision at all. 03045 break; 03046 03047 case ISD::FSQRT: 03048 case ISD::FSIN: 03049 case ISD::FCOS: 03050 Tmp1 = PromoteOp(Node->getOperand(0)); 03051 assert(Tmp1.getValueType() == NVT); 03052 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 03053 if (NoExcessFPPrecision) 03054 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 03055 DAG.getValueType(VT)); 03056 break; 03057 03058 case ISD::AND: 03059 case ISD::OR: 03060 case ISD::XOR: 03061 case ISD::ADD: 03062 case ISD::SUB: 03063 case ISD::MUL: 03064 // The input may have strange things in the top bits of the registers, but 03065 // these operations don't care. They may have weird bits going out, but 03066 // that too is okay if they are integer operations. 03067 Tmp1 = PromoteOp(Node->getOperand(0)); 03068 Tmp2 = PromoteOp(Node->getOperand(1)); 03069 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 03070 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 03071 break; 03072 case ISD::FADD: 03073 case ISD::FSUB: 03074 case ISD::FMUL: 03075 Tmp1 = PromoteOp(Node->getOperand(0)); 03076 Tmp2 = PromoteOp(Node->getOperand(1)); 03077 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 03078 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 03079 03080 // Floating point operations will give excess precision that we may not be 03081 // able to tolerate. If we DO allow excess precision, just leave it, 03082 // otherwise excise it. 03083 // FIXME: Why would we need to round FP ops more than integer ones? 03084 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 03085 if (NoExcessFPPrecision) 03086 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 03087 DAG.getValueType(VT)); 03088 break; 03089 03090 case ISD::SDIV: 03091 case ISD::SREM: 03092 // These operators require that their input be sign extended. 03093 Tmp1 = PromoteOp(Node->getOperand(0)); 03094 Tmp2 = PromoteOp(Node->getOperand(1)); 03095 if (MVT::isInteger(NVT)) { 03096 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 03097 DAG.getValueType(VT)); 03098 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 03099 DAG.getValueType(VT)); 03100 } 03101 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 03102 03103 // Perform FP_ROUND: this is probably overly pessimistic. 03104 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 03105 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 03106 DAG.getValueType(VT)); 03107 break; 03108 case ISD::FDIV: 03109 case ISD::FREM: 03110 case ISD::FCOPYSIGN: 03111 // These operators require that their input be fp extended. 03112 switch (getTypeAction(Node->getOperand(0).getValueType())) { 03113 case Legal: 03114 Tmp1 = LegalizeOp(Node->getOperand(0)); 03115 break; 03116 case Promote: 03117 Tmp1 = PromoteOp(Node->getOperand(0)); 03118 break; 03119 case Expand: 03120 assert(0 && "not implemented"); 03121 } 03122 switch (getTypeAction(Node->getOperand(1).getValueType())) { 03123 case Legal: 03124 Tmp2 = LegalizeOp(Node->getOperand(1)); 03125 break; 03126 case Promote: 03127 Tmp2 = PromoteOp(Node->getOperand(1)); 03128 break; 03129 case Expand: 03130 assert(0 && "not implemented"); 03131 } 03132 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 03133 03134 // Perform FP_ROUND: this is probably overly pessimistic. 03135 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 03136 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 03137 DAG.getValueType(VT)); 03138 break; 03139 03140 case ISD::UDIV: 03141 case ISD::UREM: 03142 // These operators require that their input be zero extended. 03143 Tmp1 = PromoteOp(Node->getOperand(0)); 03144 Tmp2 = PromoteOp(Node->getOperand(1)); 03145 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 03146 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 03147 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 03148 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 03149 break; 03150 03151 case ISD::SHL: 03152 Tmp1 = PromoteOp(Node->getOperand(0)); 03153 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 03154 break; 03155 case ISD::SRA: 03156 // The input value must be properly sign extended. 03157 Tmp1 = PromoteOp(Node->getOperand(0)); 03158 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 03159 DAG.getValueType(VT)); 03160 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 03161 break; 03162 case ISD::SRL: 03163 // The input value must be properly zero extended. 03164 Tmp1 = PromoteOp(Node->getOperand(0)); 03165 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 03166 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 03167 break; 03168 03169 case ISD::VAARG: 03170 Tmp1 = Node->getOperand(0); // Get the chain. 03171 Tmp2 = Node->getOperand(1); // Get the pointer. 03172 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 03173 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 03174 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 03175 } else { 03176 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 03177 Node->getOperand(2)); 03178 // Increment the pointer, VAList, to the next vaarg 03179 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 03180 DAG.getConstant(MVT::getSizeInBits(VT)/8, 03181 TLI.getPointerTy())); 03182 // Store the incremented VAList to the legalized pointer 03183 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 03184 Node->getOperand(2)); 03185 // Load the actual argument out of the pointer VAList 03186 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, 03187 DAG.getSrcValue(0), VT); 03188 } 03189 // Remember that we legalized the chain. 03190 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 03191 break; 03192 03193 case ISD::LOAD: 03194 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), 03195 Node->getOperand(1), Node->getOperand(2), VT); 03196 // Remember that we legalized the chain. 03197 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 03198 break; 03199 case ISD::SEXTLOAD: 03200 case ISD::ZEXTLOAD: 03201 case ISD::EXTLOAD: 03202 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0), 03203 Node->getOperand(1), Node->getOperand(2), 03204 cast<VTSDNode>(Node->getOperand(3))->getVT()); 03205 // Remember that we legalized the chain. 03206 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 03207 break; 03208 case ISD::SELECT: 03209 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 03210 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 03211 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 03212 break; 03213 case ISD::SELECT_CC: 03214 Tmp2 = PromoteOp(Node->getOperand(2)); // True 03215 Tmp3 = PromoteOp(Node->getOperand(3)); // False 03216 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 03217 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 03218 break; 03219 case ISD::BSWAP: 03220 Tmp1 = Node->getOperand(0); 03221 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 03222 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 03223 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 03224 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 03225 TLI.getShiftAmountTy())); 03226 break; 03227 case ISD::CTPOP: 03228 case ISD::CTTZ: 03229 case ISD::CTLZ: 03230 // Zero extend the argument 03231 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 03232 // Perform the larger operation, then subtract if needed. 03233 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 03234 switch(Node->getOpcode()) { 03235 case ISD::CTPOP: 03236 Result = Tmp1; 03237 break; 03238 case ISD::CTTZ: 03239 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 03240 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 03241 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 03242 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 03243 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 03244 break; 03245 case ISD::CTLZ: 03246 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 03247 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 03248 DAG.getConstant(getSizeInBits(NVT) - 03249 getSizeInBits(VT), NVT)); 03250 break; 03251 } 03252 break; 03253 case ISD::VEXTRACT_VECTOR_ELT: 03254 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 03255 break; 03256 case ISD::EXTRACT_VECTOR_ELT: 03257 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 03258 break; 03259 } 03260 03261 assert(Result.Val && "Didn't set a result!"); 03262 03263 // Make sure the result is itself legal. 03264 Result = LegalizeOp(Result); 03265 03266 // Remember that we promoted this! 03267 AddPromotedOperand(Op, Result); 03268 return Result; 03269 } 03270 03271 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 03272 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 03273 /// on the vector type. The return type of this matches the element type of the 03274 /// vector, which may not be legal for the target. 03275 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 03276 // We know that operand #0 is the Vec vector. If the index is a constant 03277 // or if the invec is a supported hardware type, we can use it. Otherwise, 03278 // lower to a store then an indexed load. 03279 SDOperand Vec = Op.getOperand(0); 03280 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 03281 03282 SDNode *InVal = Vec.Val; 03283 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 03284 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 03285 03286 // Figure out if there is a Packed type corresponding to this Vector 03287 // type. If so, convert to the packed type. 03288 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 03289 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 03290 // Turn this into a packed extract_vector_elt operation. 03291 Vec = PackVectorOp(Vec, TVT); 03292 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 03293 } else if (NumElems == 1) { 03294 // This must be an access of the only element. Return it. 03295 return PackVectorOp(Vec, EVT); 03296 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 03297 SDOperand Lo, Hi; 03298 SplitVectorOp(Vec, Lo, Hi); 03299 if (CIdx->getValue() < NumElems/2) { 03300 Vec = Lo; 03301 } else { 03302 Vec = Hi; 03303 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 03304 } 03305 03306 // It's now an extract from the appropriate high or low part. Recurse. 03307 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 03308 return LowerVEXTRACT_VECTOR_ELT(Op); 03309 } else { 03310 // Variable index case for extract element. 03311 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 03312 assert(0 && "unimp!"); 03313 return SDOperand(); 03314 } 03315 } 03316 03317 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 03318 /// memory traffic. 03319 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 03320 SDOperand Vector = Op.getOperand(0); 03321 SDOperand Idx = Op.getOperand(1); 03322 03323 // If the target doesn't support this, store the value to a temporary 03324 // stack slot, then LOAD the scalar element back out. 03325 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 03326 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 03327 Vector, StackPtr, DAG.getSrcValue(NULL)); 03328 03329 // Add the offset to the index. 03330 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 03331 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 03332 DAG.getConstant(EltSize, Idx.getValueType())); 03333 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 03334 03335 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL)); 03336 } 03337 03338 03339 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 03340 /// with condition CC on the current target. This usually involves legalizing 03341 /// or promoting the arguments. In the case where LHS and RHS must be expanded, 03342 /// there may be no choice but to create a new SetCC node to represent the 03343 /// legalized value of setcc lhs, rhs. In this case, the value is returned in 03344 /// LHS, and the SDOperand returned in RHS has a nil SDNode value. 03345 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 03346 SDOperand &RHS, 03347 SDOperand &CC) { 03348 SDOperand Tmp1, Tmp2, Result; 03349 03350 switch (getTypeAction(LHS.getValueType())) { 03351 case Legal: 03352 Tmp1 = LegalizeOp(LHS); // LHS 03353 Tmp2 = LegalizeOp(RHS); // RHS 03354 break; 03355 case Promote: 03356 Tmp1 = PromoteOp(LHS); // LHS 03357 Tmp2 = PromoteOp(RHS); // RHS 03358 03359 // If this is an FP compare, the operands have already been extended. 03360 if (MVT::isInteger(LHS.getValueType())) { 03361 MVT::ValueType VT = LHS.getValueType(); 03362 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 03363 03364 // Otherwise, we have to insert explicit sign or zero extends. Note 03365 // that we could insert sign extends for ALL conditions, but zero extend 03366 // is cheaper on many machines (an AND instead of two shifts), so prefer 03367 // it. 03368 switch (cast<CondCodeSDNode>(CC)->get()) { 03369 default: assert(0 && "Unknown integer comparison!"); 03370 case ISD::SETEQ: 03371 case ISD::SETNE: 03372 case ISD::SETUGE: 03373 case ISD::SETUGT: 03374 case ISD::SETULE: 03375 case ISD::SETULT: 03376 // ALL of these operations will work if we either sign or zero extend 03377 // the operands (including the unsigned comparisons!). Zero extend is 03378 // usually a simpler/cheaper operation, so prefer it. 03379 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 03380 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 03381 break; 03382 case ISD::SETGE: 03383 case ISD::SETGT: 03384 case ISD::SETLT: 03385 case ISD::SETLE: 03386 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 03387 DAG.getValueType(VT)); 03388 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 03389 DAG.getValueType(VT)); 03390 break; 03391 } 03392 } 03393 break; 03394 case Expand: 03395 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 03396 ExpandOp(LHS, LHSLo, LHSHi); 03397 ExpandOp(RHS, RHSLo, RHSHi); 03398 switch (cast<CondCodeSDNode>(CC)->get()) { 03399 case ISD::SETEQ: 03400 case ISD::SETNE: 03401 if (RHSLo == RHSHi) 03402 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 03403 if (RHSCST->isAllOnesValue()) { 03404 // Comparison to -1. 03405 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 03406 Tmp2 = RHSLo; 03407 break; 03408 } 03409 03410 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 03411 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 03412 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 03413 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 03414 break; 03415 default: 03416 // If this is a comparison of the sign bit, just look at the top part. 03417 // X > -1, x < 0 03418 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 03419 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 03420 CST->getValue() == 0) || // X < 0 03421 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 03422 CST->isAllOnesValue())) { // X > -1 03423 Tmp1 = LHSHi; 03424 Tmp2 = RHSHi; 03425 break; 03426 } 03427 03428 // FIXME: This generated code sucks. 03429 ISD::CondCode LowCC; 03430 switch (cast<CondCodeSDNode>(CC)->get()) { 03431 default: assert(0 && "Unknown integer setcc!"); 03432 case ISD::SETLT: 03433 case ISD::SETULT: LowCC = ISD::SETULT; break; 03434 case ISD::SETGT: 03435 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 03436 case ISD::SETLE: 03437 case ISD::SETULE: LowCC = ISD::SETULE; break; 03438 case ISD::SETGE: 03439 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 03440 } 03441 03442 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 03443 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 03444 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 03445 03446 // NOTE: on targets without efficient SELECT of bools, we can always use 03447 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 03448 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 03449 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 03450 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 03451 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 03452 Result, Tmp1, Tmp2)); 03453 Tmp1 = Result; 03454 Tmp2 = SDOperand(); 03455 } 03456 } 03457 LHS = Tmp1; 03458 RHS = Tmp2; 03459 } 03460 03461 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 03462 /// The resultant code need not be legal. Note that SrcOp is the input operand 03463 /// to the BIT_CONVERT, not the BIT_CONVERT node itself. 03464 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 03465 SDOperand SrcOp) { 03466 // Create the stack frame object. 03467 SDOperand FIPtr = CreateStackTemporary(DestVT); 03468 03469 // Emit a store to the stack slot. 03470 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 03471 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 03472 // Result is a load from the stack slot. 03473 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 03474 } 03475 03476 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 03477 // Create a vector sized/aligned stack slot, store the value to element #0, 03478 // then load the whole vector back out. 03479 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 03480 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 03481 Node->getOperand(0), StackPtr, 03482 DAG.getSrcValue(NULL)); 03483 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL)); 03484 } 03485 03486 03487 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 03488 /// support the operation, but do support the resultant packed vector type. 03489 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 03490 03491 // If the only non-undef value is the low element, turn this into a 03492 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 03493 unsigned NumElems = Node->getNumOperands(); 03494 bool isOnlyLowElement = true; 03495 SDOperand SplatValue = Node->getOperand(0); 03496 std::map<SDOperand, std::vector<unsigned> > Values; 03497 Values[SplatValue].push_back(0); 03498 bool isConstant = true; 03499 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 03500 SplatValue.getOpcode() != ISD::UNDEF) 03501 isConstant = false; 03502 03503 for (unsigned i = 1; i < NumElems; ++i) { 03504 SDOperand V = Node->getOperand(i); 03505 Values[V].push_back(i); 03506 if (V.getOpcode() != ISD::UNDEF) 03507 isOnlyLowElement = false; 03508 if (SplatValue != V) 03509 SplatValue = SDOperand(0,0); 03510 03511 // If this isn't a constant element or an undef, we can't use a constant 03512 // pool load. 03513 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 03514 V.getOpcode() != ISD::UNDEF) 03515 isConstant = false; 03516 } 03517 03518 if (isOnlyLowElement) { 03519 // If the low element is an undef too, then this whole things is an undef. 03520 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 03521 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 03522 // Otherwise, turn this into a scalar_to_vector node. 03523 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 03524 Node->getOperand(0)); 03525 } 03526 03527 // If all elements are constants, create a load from the constant pool. 03528 if (isConstant) { 03529 MVT::ValueType VT = Node->getValueType(0); 03530 const Type *OpNTy = 03531 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 03532 std::vector<Constant*> CV; 03533 for (unsigned i = 0, e = NumElems; i != e; ++i) { 03534 if (ConstantFPSDNode *V = 03535 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 03536 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 03537 } else if (ConstantSDNode *V = 03538 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 03539 CV.push_back(ConstantUInt::get(OpNTy, V->getValue())); 03540 } else { 03541 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 03542 CV.push_back(UndefValue::get(OpNTy)); 03543 } 03544 } 03545 Constant *CP = ConstantPacked::get(CV); 03546 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 03547 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 03548 DAG.getSrcValue(NULL)); 03549 } 03550 03551 if (SplatValue.Val) { // Splat of one value? 03552 // Build the shuffle constant vector: <0, 0, 0, 0> 03553 MVT::ValueType MaskVT = 03554 MVT::getIntVectorWithNumElements(NumElems); 03555 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 03556 std::vector<SDOperand> ZeroVec(NumElems, Zero); 03557 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec); 03558 03559 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 03560 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 03561 // Get the splatted value into the low element of a vector register. 03562 SDOperand LowValVec = 03563 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 03564 03565 // Return shuffle(LowValVec, undef, <0,0,0,0>) 03566 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 03567 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 03568 SplatMask); 03569 } 03570 } 03571 03572 // If there are only two unique elements, we may be able to turn this into a 03573 // vector shuffle. 03574 if (Values.size() == 2) { 03575 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 03576 MVT::ValueType MaskVT = 03577 MVT::getIntVectorWithNumElements(NumElems); 03578 std::vector<SDOperand> MaskVec(NumElems); 03579 unsigned i = 0; 03580 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 03581 E = Values.end(); I != E; ++I) { 03582 for (std::vector<unsigned>::iterator II = I->second.begin(), 03583 EE = I->second.end(); II != EE; ++II) 03584 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 03585 i += NumElems; 03586 } 03587 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); 03588 03589 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 03590 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 03591 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 03592 std::vector<SDOperand> Ops; 03593 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 03594 E = Values.end(); I != E; ++I) { 03595 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 03596 I->first); 03597 Ops.push_back(Op); 03598 } 03599 Ops.push_back(ShuffleMask); 03600 03601 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 03602 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops); 03603 } 03604 } 03605 03606 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 03607 // aligned object on the stack, store each element into it, then load 03608 // the result as a vector. 03609 MVT::ValueType VT = Node->getValueType(0); 03610 // Create the stack frame object. 03611 SDOperand FIPtr = CreateStackTemporary(VT); 03612 03613 // Emit a store of each element to the stack slot. 03614 std::vector<SDOperand> Stores; 03615 unsigned TypeByteSize = 03616 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 03617 unsigned VectorSize = MVT::getSizeInBits(VT)/8; 03618 // Store (in the right endianness) the elements to memory. 03619 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 03620 // Ignore undef elements. 03621 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 03622 03623 unsigned Offset = TypeByteSize*i; 03624 03625 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 03626 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 03627 03628 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 03629 Node->getOperand(i), Idx, 03630 DAG.getSrcValue(NULL))); 03631 } 03632 03633 SDOperand StoreChain; 03634 if (!Stores.empty()) // Not all undef elements? 03635 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 03636 else 03637 StoreChain = DAG.getEntryNode(); 03638 03639 // Result is a load from the stack slot. 03640 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0)); 03641 } 03642 03643 /// CreateStackTemporary - Create a stack temporary, suitable for holding the 03644 /// specified value type. 03645 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 03646 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 03647 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 03648 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 03649 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 03650 } 03651 03652 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 03653 SDOperand Op, SDOperand Amt, 03654 SDOperand &Lo, SDOperand &Hi) { 03655 // Expand the subcomponents. 03656 SDOperand LHSL, LHSH; 03657 ExpandOp(Op, LHSL, LHSH); 03658 03659 std::vector<SDOperand> Ops; 03660 Ops.push_back(LHSL); 03661 Ops.push_back(LHSH); 03662 Ops.push_back(Amt); 03663 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 03664 Lo = DAG.getNode(NodeOp, VTs, Ops); 03665 Hi = Lo.getValue(1); 03666 } 03667 03668 03669 /// ExpandShift - Try to find a clever way to expand this shift operation out to 03670 /// smaller elements. If we can't find a way that is more efficient than a 03671 /// libcall on this target, return false. Otherwise, return true with the 03672 /// low-parts expanded into Lo and Hi. 03673 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 03674 SDOperand &Lo, SDOperand &Hi) { 03675 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 03676 "This is not a shift!"); 03677 03678 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 03679 SDOperand ShAmt = LegalizeOp(Amt); 03680 MVT::ValueType ShTy = ShAmt.getValueType(); 03681 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 03682 unsigned NVTBits = MVT::getSizeInBits(NVT); 03683 03684 // Handle the case when Amt is an immediate. Other cases are currently broken 03685 // and are disabled. 03686 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 03687 unsigned Cst = CN->getValue(); 03688 // Expand the incoming operand to be shifted, so that we have its parts 03689 SDOperand InL, InH; 03690 ExpandOp(Op, InL, InH); 03691 switch(Opc) { 03692 case ISD::SHL: 03693 if (Cst > VTBits) { 03694 Lo = DAG.getConstant(0, NVT); 03695 Hi = DAG.getConstant(0, NVT); 03696 } else if (Cst > NVTBits) { 03697 Lo = DAG.getConstant(0, NVT); 03698 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 03699 } else if (Cst == NVTBits) { 03700 Lo = DAG.getConstant(0, NVT); 03701 Hi = InL; 03702 } else { 03703 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 03704 Hi = DAG.getNode(ISD::OR, NVT, 03705 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 03706 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 03707 } 03708 return true; 03709 case ISD::SRL: 03710 if (Cst > VTBits) { 03711 Lo = DAG.getConstant(0, NVT); 03712 Hi = DAG.getConstant(0, NVT); 03713 } else if (Cst > NVTBits) { 03714 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 03715 Hi = DAG.getConstant(0, NVT); 03716 } else if (Cst == NVTBits) { 03717 Lo = InH; 03718 Hi = DAG.getConstant(0, NVT); 03719 } else { 03720 Lo = DAG.getNode(ISD::OR, NVT, 03721 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 03722 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 03723 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 03724 } 03725 return true; 03726 case ISD::SRA: 03727 if (Cst > VTBits) { 03728 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 03729 DAG.getConstant(NVTBits-1, ShTy)); 03730 } else if (Cst > NVTBits) { 03731 Lo = DAG.getNode(ISD::SRA, NVT, InH, 03732 DAG.getConstant(Cst-NVTBits, ShTy)); 03733 Hi = DAG.getNode(ISD::SRA, NVT, InH, 03734 DAG.getConstant(NVTBits-1, ShTy)); 03735 } else if (Cst == NVTBits) { 03736 Lo = InH; 03737 Hi = DAG.getNode(ISD::SRA, NVT, InH, 03738 DAG.getConstant(NVTBits-1, ShTy)); 03739 } else { 03740 Lo = DAG.getNode(ISD::OR, NVT, 03741 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 03742 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 03743 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 03744 } 03745 return true; 03746 } 03747 } 03748 return false; 03749 } 03750 03751 03752 // ExpandLibCall - Expand a node into a call to a libcall. If the result value 03753 // does not fit into a register, return the lo part and set the hi part to the 03754 // by-reg argument. If it does fit into a single register, return the result 03755 // and leave the Hi part unset. 03756 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 03757 SDOperand &Hi) { 03758 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 03759 // The input chain to this libcall is the entry node of the function. 03760 // Legalizing the call will automatically add the previous call to the 03761 // dependence. 03762 SDOperand InChain = DAG.getEntryNode(); 03763 03764 TargetLowering::ArgListTy Args; 03765 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 03766 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 03767 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 03768 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 03769 } 03770 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 03771 03772 // Splice the libcall in wherever FindInputOutputChains tells us to. 03773 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 03774 std::pair<SDOperand,SDOperand> CallInfo = 03775 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 03776 Callee, Args, DAG); 03777 03778 // Legalize the call sequence, starting with the chain. This will advance 03779 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 03780 // was added by LowerCallTo (guaranteeing proper serialization of calls). 03781 LegalizeOp(CallInfo.second); 03782 SDOperand Result; 03783 switch (getTypeAction(CallInfo.first.getValueType())) { 03784 default: assert(0 && "Unknown thing"); 03785 case Legal: 03786 Result = CallInfo.first; 03787 break; 03788 case Expand: 03789 ExpandOp(CallInfo.first, Result, Hi); 03790 break; 03791 } 03792 return Result; 03793 } 03794 03795 03796 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 03797 /// destination type is legal. 03798 SDOperand SelectionDAGLegalize:: 03799 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 03800 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 03801 assert(getTypeAction(Source.getValueType()) == Expand && 03802 "This is not an expansion!"); 03803 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 03804 03805 if (!isSigned) { 03806 assert(Source.getValueType() == MVT::i64 && 03807 "This only works for 64-bit -> FP"); 03808 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 03809 // incoming integer is set. To handle this, we dynamically test to see if 03810 // it is set, and, if so, add a fudge factor. 03811 SDOperand Lo, Hi; 03812 ExpandOp(Source, Lo, Hi); 03813 03814 // If this is unsigned, and not supported, first perform the conversion to 03815 // signed, then adjust the result if the sign bit is set. 03816 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 03817 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 03818 03819 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 03820 DAG.getConstant(0, Hi.getValueType()), 03821 ISD::SETLT); 03822 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 03823 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 03824 SignSet, Four, Zero); 03825 uint64_t FF = 0x5f800000ULL; 03826 if (TLI.isLittleEndian()) FF <<= 32; 03827 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 03828 03829 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 03830 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 03831 SDOperand FudgeInReg; 03832 if (DestTy == MVT::f32) 03833 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 03834 DAG.getSrcValue(NULL)); 03835 else { 03836 assert(DestTy == MVT::f64 && "Unexpected conversion"); 03837 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 03838 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 03839 } 03840 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 03841 } 03842 03843 // Check to see if the target has a custom way to lower this. If so, use it. 03844 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 03845 default: assert(0 && "This action not implemented for this operation!"); 03846 case TargetLowering::Legal: 03847 case TargetLowering::Expand: 03848 break; // This case is handled below. 03849 case TargetLowering::Custom: { 03850 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 03851 Source), DAG); 03852 if (NV.Val) 03853 return LegalizeOp(NV); 03854 break; // The target decided this was legal after all 03855 } 03856 } 03857 03858 // Expand the source, then glue it back together for the call. We must expand 03859 // the source in case it is shared (this pass of legalize must traverse it). 03860 SDOperand SrcLo, SrcHi; 03861 ExpandOp(Source, SrcLo, SrcHi); 03862 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 03863 03864 const char *FnName = 0; 03865 if (DestTy == MVT::f32) 03866 FnName = "__floatdisf"; 03867 else { 03868 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 03869 FnName = "__floatdidf"; 03870 } 03871 03872 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 03873 SDOperand UnusedHiPart; 03874 return ExpandLibCall(FnName, Source.Val, UnusedHiPart); 03875 } 03876 03877 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 03878 /// INT_TO_FP operation of the specified operand when the target requests that 03879 /// we expand it. At this point, we know that the result and operand types are 03880 /// legal for the target. 03881 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 03882 SDOperand Op0, 03883 MVT::ValueType DestVT) { 03884 if (Op0.getValueType() == MVT::i32) { 03885 // simple 32-bit [signed|unsigned] integer to float/double expansion 03886 03887 // get the stack frame index of a 8 byte buffer 03888 MachineFunction &MF = DAG.getMachineFunction(); 03889 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 03890 // get address of 8 byte buffer 03891 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 03892 // word offset constant for Hi/Lo address computation 03893 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 03894 // set up Hi and Lo (into buffer) address based on endian 03895 SDOperand Hi = StackSlot; 03896 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 03897 if (TLI.isLittleEndian()) 03898 std::swap(Hi, Lo); 03899 03900 // if signed map to unsigned space 03901 SDOperand Op0Mapped; 03902 if (isSigned) { 03903 // constant used to invert sign bit (signed to unsigned mapping) 03904 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 03905 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 03906 } else { 03907 Op0Mapped = Op0; 03908 } 03909 // store the lo of the constructed double - based on integer input 03910 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 03911 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 03912 // initial hi portion of constructed double 03913 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 03914 // store the hi of the constructed double - biased exponent 03915 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 03916 InitialHi, Hi, DAG.getSrcValue(NULL)); 03917 // load the constructed double 03918 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 03919 DAG.getSrcValue(NULL)); 03920 // FP constant to bias correct the final result 03921 SDOperand Bias = DAG.getConstantFP(isSigned ? 03922 BitsToDouble(0x4330000080000000ULL) 03923 : BitsToDouble(0x4330000000000000ULL), 03924 MVT::f64); 03925 // subtract the bias 03926 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 03927 // final result 03928 SDOperand Result; 03929 // handle final rounding 03930 if (DestVT == MVT::f64) { 03931 // do nothing 03932 Result = Sub; 03933 } else { 03934 // if f32 then cast to f32 03935 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 03936 } 03937 return Result; 03938 } 03939 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 03940 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 03941 03942 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 03943 DAG.getConstant(0, Op0.getValueType()), 03944 ISD::SETLT); 03945 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 03946 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 03947 SignSet, Four, Zero); 03948 03949 // If the sign bit of the integer is set, the large number will be treated 03950 // as a negative number. To counteract this, the dynamic code adds an 03951 // offset depending on the data type. 03952 uint64_t FF; 03953 switch (Op0.getValueType()) { 03954 default: assert(0 && "Unsupported integer type!"); 03955 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 03956 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 03957 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 03958 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 03959 } 03960 if (TLI.isLittleEndian()) FF <<= 32; 03961 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 03962 03963 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 03964 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 03965 SDOperand FudgeInReg; 03966 if (DestVT == MVT::f32) 03967 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 03968 DAG.getSrcValue(NULL)); 03969 else { 03970 assert(DestVT == MVT::f64 && "Unexpected conversion"); 03971 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 03972 DAG.getEntryNode(), CPIdx, 03973 DAG.getSrcValue(NULL), MVT::f32)); 03974 } 03975 03976 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 03977 } 03978 03979 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 03980 /// *INT_TO_FP operation of the specified operand when the target requests that 03981 /// we promote it. At this point, we know that the result and operand types are 03982 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 03983 /// operation that takes a larger input. 03984 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 03985 MVT::ValueType DestVT, 03986 bool isSigned) { 03987 // First step, figure out the appropriate *INT_TO_FP operation to use. 03988 MVT::ValueType NewInTy = LegalOp.getValueType(); 03989 03990 unsigned OpToUse = 0; 03991 03992 // Scan for the appropriate larger type to use. 03993 while (1) { 03994 NewInTy = (MVT::ValueType)(NewInTy+1); 03995 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 03996 03997 // If the target supports SINT_TO_FP of this type, use it. 03998 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 03999 default: break; 04000 case TargetLowering::Legal: 04001 if (!TLI.isTypeLegal(NewInTy)) 04002 break; // Can't use this datatype. 04003 // FALL THROUGH. 04004 case TargetLowering::Custom: 04005 OpToUse = ISD::SINT_TO_FP; 04006 break; 04007 } 04008 if (OpToUse) break; 04009 if (isSigned) continue; 04010 04011 // If the target supports UINT_TO_FP of this type, use it. 04012 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 04013 default: break; 04014 case TargetLowering::Legal: 04015 if (!TLI.isTypeLegal(NewInTy)) 04016 break; // Can't use this datatype. 04017 // FALL THROUGH. 04018 case TargetLowering::Custom: 04019 OpToUse = ISD::UINT_TO_FP; 04020 break; 04021 } 04022 if (OpToUse) break; 04023 04024 // Otherwise, try a larger type. 04025 } 04026 04027 // Okay, we found the operation and type to use. Zero extend our input to the 04028 // desired type then run the operation on it. 04029 return DAG.getNode(OpToUse, DestVT, 04030 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 04031 NewInTy, LegalOp)); 04032 } 04033 04034 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 04035 /// FP_TO_*INT operation of the specified operand when the target requests that 04036 /// we promote it. At this point, we know that the result and operand types are 04037 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 04038 /// operation that returns a larger result. 04039 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 04040 MVT::ValueType DestVT, 04041 bool isSigned) { 04042 // First step, figure out the appropriate FP_TO*INT operation to use. 04043 MVT::ValueType NewOutTy = DestVT; 04044 04045 unsigned OpToUse = 0; 04046 04047 // Scan for the appropriate larger type to use. 04048 while (1) { 04049 NewOutTy = (MVT::ValueType)(NewOutTy+1); 04050 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 04051 04052 // If the target supports FP_TO_SINT returning this type, use it. 04053 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 04054 default: break; 04055 case TargetLowering::Legal: 04056 if (!TLI.isTypeLegal(NewOutTy)) 04057 break; // Can't use this datatype. 04058 // FALL THROUGH. 04059 case TargetLowering::Custom: 04060 OpToUse = ISD::FP_TO_SINT; 04061 break; 04062 } 04063 if (OpToUse) break; 04064 04065 // If the target supports FP_TO_UINT of this type, use it. 04066 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 04067 default: break; 04068 case TargetLowering::Legal: 04069 if (!TLI.isTypeLegal(NewOutTy)) 04070 break; // Can't use this datatype. 04071 // FALL THROUGH. 04072 case TargetLowering::Custom: 04073 OpToUse = ISD::FP_TO_UINT; 04074 break; 04075 } 04076 if (OpToUse) break; 04077 04078 // Otherwise, try a larger type. 04079 } 04080 04081 // Okay, we found the operation and type to use. Truncate the result of the 04082 // extended FP_TO_*INT operation to the desired size. 04083 return DAG.getNode(ISD::TRUNCATE, DestVT, 04084 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 04085 } 04086 04087 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 04088 /// 04089 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 04090 MVT::ValueType VT = Op.getValueType(); 04091 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 04092 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 04093 switch (VT) { 04094 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 04095 case MVT::i16: 04096 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 04097 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 04098 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 04099 case MVT::i32: 04100 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 04101 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 04102 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 04103 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 04104 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 04105 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 04106 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 04107 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 04108 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 04109 case MVT::i64: 04110 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 04111 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 04112 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 04113 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 04114 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 04115 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 04116 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 04117 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 04118 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 04119 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 04120 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 04121 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 04122 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 04123 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 04124 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 04125 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 04126 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 04127 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 04128 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 04129 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 04130 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 04131 } 04132 } 04133 04134 /// ExpandBitCount - Expand the specified bitcount instruction into operations. 04135 /// 04136 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 04137 switch (Opc) { 04138 default: assert(0 && "Cannot expand this yet!"); 04139 case ISD::CTPOP: { 04140 static const uint64_t mask[6] = { 04141 0x5555555555555555ULL, 0x3333333333333333ULL, 04142 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 04143 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 04144 }; 04145 MVT::ValueType VT = Op.getValueType(); 04146 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 04147 unsigned len = getSizeInBits(VT); 04148 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 04149 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 04150 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 04151 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 04152 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 04153 DAG.getNode(ISD::AND, VT, 04154 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 04155 } 04156 return Op; 04157 } 04158 case ISD::CTLZ: { 04159 // for now, we do this: 04160 // x = x | (x >> 1); 04161 // x = x | (x >> 2); 04162 // ... 04163 // x = x | (x >>16); 04164 // x = x | (x >>32); // for 64-bit input 04165 // return popcount(~x); 04166 // 04167 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 04168 MVT::ValueType VT = Op.getValueType(); 04169 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 04170 unsigned len = getSizeInBits(VT); 04171 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 04172 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 04173 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 04174 } 04175 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 04176 return DAG.getNode(ISD::CTPOP, VT, Op); 04177 } 04178 case ISD::CTTZ: { 04179 // for now, we use: { return popcount(~x & (x - 1)); } 04180 // unless the target has ctlz but not ctpop, in which case we use: 04181 // { return 32 - nlz(~x & (x-1)); } 04182 // see also http://www.hackersdelight.org/HDcode/ntz.cc 04183 MVT::ValueType VT = Op.getValueType(); 04184 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 04185 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 04186 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 04187 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 04188 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 04189 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 04190 TLI.isOperationLegal(ISD::CTLZ, VT)) 04191 return DAG.getNode(ISD::SUB, VT, 04192 DAG.getConstant(getSizeInBits(VT), VT), 04193 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 04194 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 04195 } 04196 } 04197 } 04198 04199 /// ExpandOp - Expand the specified SDOperand into its two component pieces 04200 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 04201 /// LegalizeNodes map is filled in for any results that are not expanded, the 04202 /// ExpandedNodes map is filled in for any results that are expanded, and the 04203 /// Lo/Hi values are returned. 04204 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 04205 MVT::ValueType VT = Op.getValueType(); 04206 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 04207 SDNode *Node = Op.Val; 04208 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 04209 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 04210 "Cannot expand FP values!"); 04211 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 04212 "Cannot expand to FP value or to larger int value!"); 04213 04214 // See if we already expanded it. 04215 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 04216 = ExpandedNodes.find(Op); 04217 if (I != ExpandedNodes.end()) { 04218 Lo = I->second.first; 04219 Hi = I->second.second; 04220 return; 04221 } 04222 04223 switch (Node->getOpcode()) { 04224 case ISD::CopyFromReg: 04225 assert(0 && "CopyFromReg must be legal!"); 04226 default: 04227 #ifndef NDEBUG 04228 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 04229 #endif 04230 assert(0 && "Do not know how to expand this operator!"); 04231 abort(); 04232 case ISD::UNDEF: 04233 Lo = DAG.getNode(ISD::UNDEF, NVT); 04234 Hi = DAG.getNode(ISD::UNDEF, NVT); 04235 break; 04236 case ISD::Constant: { 04237 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 04238 Lo = DAG.getConstant(Cst, NVT); 04239 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 04240 break; 04241 } 04242 case ISD::BUILD_PAIR: 04243 // Return the operands. 04244 Lo = Node->getOperand(0); 04245 Hi = Node->getOperand(1); 04246 break; 04247 04248 case ISD::SIGN_EXTEND_INREG: 04249 ExpandOp(Node->getOperand(0), Lo, Hi); 04250 // Sign extend the lo-part. 04251 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 04252 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 04253 TLI.getShiftAmountTy())); 04254 // sext_inreg the low part if needed. 04255 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 04256 break; 04257 04258 case ISD::BSWAP: { 04259 ExpandOp(Node->getOperand(0), Lo, Hi); 04260 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 04261 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 04262 Lo = TempLo; 04263 break; 04264 } 04265 04266 case ISD::CTPOP: 04267 ExpandOp(Node->getOperand(0), Lo, Hi); 04268 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 04269 DAG.getNode(ISD::CTPOP, NVT, Lo), 04270 DAG.getNode(ISD::CTPOP, NVT, Hi)); 04271 Hi = DAG.getConstant(0, NVT); 04272 break; 04273 04274 case ISD::CTLZ: { 04275 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 04276 ExpandOp(Node->getOperand(0), Lo, Hi); 04277 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 04278 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 04279 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 04280 ISD::SETNE); 04281 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 04282 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 04283 04284 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 04285 Hi = DAG.getConstant(0, NVT); 04286 break; 04287 } 04288 04289 case ISD::CTTZ: { 04290 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 04291 ExpandOp(Node->getOperand(0), Lo, Hi); 04292 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 04293 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 04294 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 04295 ISD::SETNE); 04296 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 04297 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 04298 04299 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 04300 Hi = DAG.getConstant(0, NVT); 04301 break; 04302 } 04303 04304 case ISD::VAARG: { 04305 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 04306 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 04307 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 04308 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 04309 04310 // Remember that we legalized the chain. 04311 Hi = LegalizeOp(Hi); 04312 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 04313 if (!TLI.isLittleEndian()) 04314 std::swap(Lo, Hi); 04315 break; 04316 } 04317 04318 case ISD::LOAD: { 04319 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 04320 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 04321 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 04322 04323 // Increment the pointer to the other half. 04324 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 04325 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 04326 getIntPtrConstant(IncrementSize)); 04327 // FIXME: This creates a bogus srcvalue! 04328 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 04329 04330 // Build a factor node to remember that this load is independent of the 04331 // other one. 04332 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 04333 Hi.getValue(1)); 04334 04335 // Remember that we legalized the chain. 04336 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 04337 if (!TLI.isLittleEndian()) 04338 std::swap(Lo, Hi); 04339 break; 04340 } 04341 case ISD::AND: 04342 case ISD::OR: 04343 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 04344 SDOperand LL, LH, RL, RH; 04345 ExpandOp(Node->getOperand(0), LL, LH); 04346 ExpandOp(Node->getOperand(1), RL, RH); 04347 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 04348 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 04349 break; 04350 } 04351 case ISD::SELECT: { 04352 SDOperand LL, LH, RL, RH; 04353 ExpandOp(Node->getOperand(1), LL, LH); 04354 ExpandOp(Node->getOperand(2), RL, RH); 04355 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 04356 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 04357 break; 04358 } 04359 case ISD::SELECT_CC: { 04360 SDOperand TL, TH, FL, FH; 04361 ExpandOp(Node->getOperand(2), TL, TH); 04362 ExpandOp(Node->getOperand(3), FL, FH); 04363 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 04364 Node->getOperand(1), TL, FL, Node->getOperand(4)); 04365 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 04366 Node->getOperand(1), TH, FH, Node->getOperand(4)); 04367 break; 04368 } 04369 case ISD::SEXTLOAD: { 04370 SDOperand Chain = Node->getOperand(0); 04371 SDOperand Ptr = Node->getOperand(1); 04372 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 04373 04374 if (EVT == NVT) 04375 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 04376 else 04377 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 04378 EVT); 04379 04380 // Remember that we legalized the chain. 04381 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 04382 04383 // The high part is obtained by SRA'ing all but one of the bits of the lo 04384 // part. 04385 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 04386 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 04387 TLI.getShiftAmountTy())); 04388 break; 04389 } 04390 case ISD::ZEXTLOAD: { 04391 SDOperand Chain = Node->getOperand(0); 04392 SDOperand Ptr = Node->getOperand(1); 04393 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 04394 04395 if (EVT == NVT) 04396 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 04397 else 04398 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 04399 EVT); 04400 04401 // Remember that we legalized the chain. 04402 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 04403 04404 // The high part is just a zero. 04405 Hi = DAG.getConstant(0, NVT); 04406 break; 04407 } 04408 case ISD::EXTLOAD: { 04409 SDOperand Chain = Node->getOperand(0); 04410 SDOperand Ptr = Node->getOperand(1); 04411 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 04412 04413 if (EVT == NVT) 04414 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 04415 else 04416 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 04417 EVT); 04418 04419 // Remember that we legalized the chain. 04420 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 04421 04422 // The high part is undefined. 04423 Hi = DAG.getNode(ISD::UNDEF, NVT); 04424 break; 04425 } 04426 case ISD::ANY_EXTEND: 04427 // The low part is any extension of the input (which degenerates to a copy). 04428 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 04429 // The high part is undefined. 04430 Hi = DAG.getNode(ISD::UNDEF, NVT); 04431 break; 04432 case ISD::SIGN_EXTEND: { 04433 // The low part is just a sign extension of the input (which degenerates to 04434 // a copy). 04435 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 04436 04437 // The high part is obtained by SRA'ing all but one of the bits of the lo 04438 // part. 04439 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 04440 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 04441 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 04442 break; 04443 } 04444 case ISD::ZERO_EXTEND: 04445 // The low part is just a zero extension of the input (which degenerates to 04446 // a copy). 04447 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 04448 04449 // The high part is just a zero. 04450 Hi = DAG.getConstant(0, NVT); 04451 break; 04452 04453 case ISD::BIT_CONVERT: { 04454 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 04455 Node->getOperand(0)); 04456 ExpandOp(Tmp, Lo, Hi); 04457 break; 04458 } 04459 04460 case ISD::READCYCLECOUNTER: 04461 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 04462 TargetLowering::Custom && 04463 "Must custom expand ReadCycleCounter"); 04464 Lo = TLI.LowerOperation(Op, DAG); 04465 assert(Lo.Val && "Node must be custom expanded!"); 04466 Hi = Lo.getValue(1); 04467 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 04468 LegalizeOp(Lo.getValue(2))); 04469 break; 04470 04471 // These operators cannot be expanded directly, emit them as calls to 04472 // library functions. 04473 case ISD::FP_TO_SINT: 04474 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 04475 SDOperand Op; 04476 switch (getTypeAction(Node->getOperand(0).getValueType())) { 04477 case Expand: assert(0 && "cannot expand FP!"); 04478 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 04479 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 04480 } 04481 04482 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 04483 04484 // Now that the custom expander is done, expand the result, which is still 04485 // VT. 04486 if (Op.Val) { 04487 ExpandOp(Op, Lo, Hi); 04488 break; 04489 } 04490 } 04491 04492 if (Node->getOperand(0).getValueType() == MVT::f32) 04493 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 04494 else 04495 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 04496 break; 04497 04498 case ISD::FP_TO_UINT: 04499 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 04500 SDOperand Op; 04501 switch (getTypeAction(Node->getOperand(0).getValueType())) { 04502 case Expand: assert(0 && "cannot expand FP!"); 04503 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 04504 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 04505 } 04506 04507 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 04508 04509 // Now that the custom expander is done, expand the result. 04510 if (Op.Val) { 04511 ExpandOp(Op, Lo, Hi); 04512 break; 04513 } 04514 } 04515 04516 if (Node->getOperand(0).getValueType() == MVT::f32) 04517 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 04518 else 04519 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 04520 break; 04521 04522 case ISD::SHL: { 04523 // If the target wants custom lowering, do so. 04524 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 04525 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 04526 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 04527 Op = TLI.LowerOperation(Op, DAG); 04528 if (Op.Val) { 04529 // Now that the custom expander is done, expand the result, which is 04530 // still VT. 04531 ExpandOp(Op, Lo, Hi); 04532 break; 04533 } 04534 } 04535 04536 // If we can emit an efficient shift operation, do so now. 04537 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 04538 break; 04539 04540 // If this target supports SHL_PARTS, use it. 04541 TargetLowering::LegalizeAction Action = 04542 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 04543 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 04544 Action == TargetLowering::Custom) { 04545 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 04546 break; 04547 } 04548 04549 // Otherwise, emit a libcall. 04550 Lo = ExpandLibCall("__ashldi3", Node, Hi); 04551 break; 04552 } 04553 04554 case ISD::SRA: { 04555 // If the target wants custom lowering, do so. 04556 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 04557 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 04558 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 04559 Op = TLI.LowerOperation(Op, DAG); 04560 if (Op.Val) { 04561 // Now that the custom expander is done, expand the result, which is 04562 // still VT. 04563 ExpandOp(Op, Lo, Hi); 04564 break; 04565 } 04566 } 04567 04568 // If we can emit an efficient shift operation, do so now. 04569 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 04570 break; 04571 04572 // If this target supports SRA_PARTS, use it. 04573 TargetLowering::LegalizeAction Action = 04574 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 04575 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 04576 Action == TargetLowering::Custom) { 04577 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 04578 break; 04579 } 04580 04581 // Otherwise, emit a libcall. 04582 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 04583 break; 04584 } 04585 04586 case ISD::SRL: { 04587 // If the target wants custom lowering, do so. 04588 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 04589 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 04590 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 04591 Op = TLI.LowerOperation(Op, DAG); 04592 if (Op.Val) { 04593 // Now that the custom expander is done, expand the result, which is 04594 // still VT. 04595 ExpandOp(Op, Lo, Hi); 04596 break; 04597 } 04598 } 04599 04600 // If we can emit an efficient shift operation, do so now. 04601 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 04602 break; 04603 04604 // If this target supports SRL_PARTS, use it. 04605 TargetLowering::LegalizeAction Action = 04606 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 04607 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 04608 Action == TargetLowering::Custom) { 04609 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 04610 break; 04611 } 04612 04613 // Otherwise, emit a libcall. 04614 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 04615 break; 04616 } 04617 04618 case ISD::ADD: 04619 case ISD::SUB: { 04620 // If the target wants to custom expand this, let them. 04621 if (TLI.getOperationAction(Node->getOpcode(), VT) == 04622 TargetLowering::Custom) { 04623 Op = TLI.LowerOperation(Op, DAG); 04624 if (Op.Val) { 04625 ExpandOp(Op, Lo, Hi); 04626 break; 04627 } 04628 } 04629 04630 // Expand the subcomponents. 04631 SDOperand LHSL, LHSH, RHSL, RHSH; 04632 ExpandOp(Node->getOperand(0), LHSL, LHSH); 04633 ExpandOp(Node->getOperand(1), RHSL, RHSH); 04634 std::vector<MVT::ValueType> VTs; 04635 std::vector<SDOperand> LoOps, HiOps; 04636 VTs.push_back(LHSL.getValueType()); 04637 VTs.push_back(MVT::Flag); 04638 LoOps.push_back(LHSL); 04639 LoOps.push_back(RHSL); 04640 HiOps.push_back(LHSH); 04641 HiOps.push_back(RHSH); 04642 if (Node->getOpcode() == ISD::ADD) { 04643 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps); 04644 HiOps.push_back(Lo.getValue(1)); 04645 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps); 04646 } else { 04647 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps); 04648 HiOps.push_back(Lo.getValue(1)); 04649 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps); 04650 } 04651 break; 04652 } 04653 case ISD::MUL: { 04654 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 04655 SDOperand LL, LH, RL, RH; 04656 ExpandOp(Node->getOperand(0), LL, LH); 04657 ExpandOp(Node->getOperand(1), RL, RH); 04658 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 04659 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 04660 // extended the sign bit of the low half through the upper half, and if so 04661 // emit a MULHS instead of the alternate sequence that is valid for any 04662 // i64 x i64 multiply. 04663 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 04664 // is RH an extension of the sign bit of RL? 04665 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 04666 RH.getOperand(1).getOpcode() == ISD::Constant && 04667 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 04668 // is LH an extension of the sign bit of LL? 04669 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 04670 LH.getOperand(1).getOpcode() == ISD::Constant && 04671 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 04672 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 04673 } else { 04674 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 04675 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 04676 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 04677 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 04678 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 04679 } 04680 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 04681 } else { 04682 Lo = ExpandLibCall("__muldi3" , Node, Hi); 04683 } 04684 break; 04685 } 04686 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 04687 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 04688 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 04689 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 04690 } 04691 04692 // Make sure the resultant values have been legalized themselves, unless this 04693 // is a type that requires multi-step expansion. 04694 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 04695 Lo = LegalizeOp(Lo); 04696 Hi = LegalizeOp(Hi); 04697 } 04698 04699 // Remember in a map if the values will be reused later. 04700 bool isNew = 04701 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 04702 assert(isNew && "Value already expanded?!?"); 04703 } 04704 04705 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 04706 /// two smaller values of MVT::Vector type. 04707 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 04708 SDOperand &Hi) { 04709 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 04710 SDNode *Node = Op.Val; 04711 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 04712 assert(NumElements > 1 && "Cannot split a single element vector!"); 04713 unsigned NewNumElts = NumElements/2; 04714 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 04715 SDOperand TypeNode = *(Node->op_end()-1); 04716 04717 // See if we already split it. 04718 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 04719 = SplitNodes.find(Op); 04720 if (I != SplitNodes.end()) { 04721 Lo = I->second.first; 04722 Hi = I->second.second; 04723 return; 04724 } 04725 04726 switch (Node->getOpcode()) { 04727 default: 04728 #ifndef NDEBUG 04729 Node->dump(); 04730 #endif 04731 assert(0 && "Unhandled operation in SplitVectorOp!"); 04732 case ISD::VBUILD_VECTOR: { 04733 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts); 04734 LoOps.push_back(NewNumEltsNode); 04735 LoOps.push_back(TypeNode); 04736 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps); 04737 04738 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2); 04739 HiOps.push_back(NewNumEltsNode); 04740 HiOps.push_back(TypeNode); 04741 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps); 04742 break; 04743 } 04744 case ISD::VADD: 04745 case ISD::VSUB: 04746 case ISD::VMUL: 04747 case ISD::VSDIV: 04748 case ISD::VUDIV: 04749 case ISD::VAND: 04750 case ISD::VOR: 04751 case ISD::VXOR: { 04752 SDOperand LL, LH, RL, RH; 04753 SplitVectorOp(Node->getOperand(0), LL, LH); 04754 SplitVectorOp(Node->getOperand(1), RL, RH); 04755 04756 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 04757 NewNumEltsNode, TypeNode); 04758 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 04759 NewNumEltsNode, TypeNode); 04760 break; 04761 } 04762 case ISD::VLOAD: { 04763 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 04764 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 04765 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 04766 04767 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 04768 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 04769 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 04770 getIntPtrConstant(IncrementSize)); 04771 // FIXME: This creates a bogus srcvalue! 04772 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 04773 04774 // Build a factor node to remember that this load is independent of the 04775 // other one. 04776 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 04777 Hi.getValue(1)); 04778 04779 // Remember that we legalized the chain. 04780 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 04781 break; 04782 } 04783 case ISD::VBIT_CONVERT: { 04784 // We know the result is a vector. The input may be either a vector or a 04785 // scalar value. 04786 if (Op.getOperand(0).getValueType() != MVT::Vector) { 04787 // Lower to a store/load. FIXME: this could be improved probably. 04788 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 04789 04790 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 04791 Op.getOperand(0), Ptr, DAG.getSrcValue(0)); 04792 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 04793 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 04794 SplitVectorOp(St, Lo, Hi); 04795 } else { 04796 // If the input is a vector type, we have to either scalarize it, pack it 04797 // or convert it based on whether the input vector type is legal. 04798 SDNode *InVal = Node->getOperand(0).Val; 04799 unsigned NumElems = 04800 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 04801 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 04802 04803 // If the input is from a single element vector, scalarize the vector, 04804 // then treat like a scalar. 04805 if (NumElems == 1) { 04806 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 04807 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 04808 Op.getOperand(1), Op.getOperand(2)); 04809 SplitVectorOp(Scalar, Lo, Hi); 04810 } else { 04811 // Split the input vector. 04812 SplitVectorOp(Op.getOperand(0), Lo, Hi); 04813 04814 // Convert each of the pieces now. 04815 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 04816 NewNumEltsNode, TypeNode); 04817 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 04818 NewNumEltsNode, TypeNode); 04819 } 04820 break; 04821 } 04822 } 04823 } 04824 04825 // Remember in a map if the values will be reused later. 04826 bool isNew = 04827 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 04828 assert(isNew && "Value already expanded?!?"); 04829 } 04830 04831 04832 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 04833 /// equivalent operation that returns a scalar (e.g. F32) or packed value 04834 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 04835 /// type for the result. 04836 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 04837 MVT::ValueType NewVT) { 04838 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 04839 SDNode *Node = Op.Val; 04840 04841 // See if we already packed it. 04842 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 04843 if (I != PackedNodes.end()) return I->second; 04844 04845 SDOperand Result; 04846 switch (Node->getOpcode()) { 04847 default: 04848 #ifndef NDEBUG 04849 Node->dump(); std::cerr << "\n"; 04850 #endif 04851 assert(0 && "Unknown vector operation in PackVectorOp!"); 04852 case ISD::VADD: 04853 case ISD::VSUB: 04854 case ISD::VMUL: 04855 case ISD::VSDIV: 04856 case ISD::VUDIV: 04857 case ISD::VAND: 04858 case ISD::VOR: 04859 case ISD::VXOR: 04860 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 04861 NewVT, 04862 PackVectorOp(Node->getOperand(0), NewVT), 04863 PackVectorOp(Node->getOperand(1), NewVT)); 04864 break; 04865 case ISD::VLOAD: { 04866 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 04867 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 04868 04869 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2)); 04870 04871 // Remember that we legalized the chain. 04872 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 04873 break; 04874 } 04875 case ISD::VBUILD_VECTOR: 04876 if (Node->getOperand(0).getValueType() == NewVT) { 04877 // Returning a scalar? 04878 Result = Node->getOperand(0); 04879 } else { 04880 // Returning a BUILD_VECTOR? 04881 04882 // If all elements of the build_vector are undefs, return an undef. 04883 bool AllUndef = true; 04884 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 04885 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 04886 AllUndef = false; 04887 break; 04888 } 04889 if (AllUndef) { 04890 Result = DAG.getNode(ISD::UNDEF, NewVT); 04891 } else { 04892 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2); 04893 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops); 04894 } 04895 } 04896 break; 04897 case ISD::VINSERT_VECTOR_ELT: 04898 if (!MVT::isVector(NewVT)) { 04899 // Returning a scalar? Must be the inserted element. 04900 Result = Node->getOperand(1); 04901 } else { 04902 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 04903 PackVectorOp(Node->getOperand(0), NewVT), 04904 Node->getOperand(1), Node->getOperand(2)); 04905 } 04906 break; 04907 case ISD::VVECTOR_SHUFFLE: 04908 if (!MVT::isVector(NewVT)) { 04909 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 04910 SDOperand EltNum = Node->getOperand(2).getOperand(0); 04911 if (cast<ConstantSDNode>(EltNum)->getValue()) 04912 Result = PackVectorOp(Node->getOperand(1), NewVT); 04913 else 04914 Result = PackVectorOp(Node->getOperand(0), NewVT); 04915 } else { 04916 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 04917 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 04918 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 04919 Node->getOperand(2).Val->op_end()-2); 04920 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 04921 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx); 04922 04923 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 04924 PackVectorOp(Node->getOperand(0), NewVT), 04925 PackVectorOp(Node->getOperand(1), NewVT), BV); 04926 } 04927 break; 04928 case ISD::VBIT_CONVERT: 04929 if (Op.getOperand(0).getValueType() != MVT::Vector) 04930 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 04931 else { 04932 // If the input is a vector type, we have to either scalarize it, pack it 04933 // or convert it based on whether the input vector type is legal. 04934 SDNode *InVal = Node->getOperand(0).Val; 04935 unsigned NumElems = 04936 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 04937 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 04938 04939 // Figure out if there is a Packed type corresponding to this Vector 04940 // type. If so, convert to the packed type. 04941 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 04942 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 04943 // Turn this into a bit convert of the packed input. 04944 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 04945 PackVectorOp(Node->getOperand(0), TVT)); 04946 break; 04947 } else if (NumElems == 1) { 04948 // Turn this into a bit convert of the scalar input. 04949 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 04950 PackVectorOp(Node->getOperand(0), EVT)); 04951 break; 04952 } else { 04953 // FIXME: UNIMP! 04954 assert(0 && "Cast from unsupported vector type not implemented yet!"); 04955 } 04956 } 04957 break; 04958 case ISD::VSELECT: 04959 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 04960 PackVectorOp(Op.getOperand(1), NewVT), 04961 PackVectorOp(Op.getOperand(2), NewVT)); 04962 break; 04963 } 04964 04965 if (TLI.isTypeLegal(NewVT)) 04966 Result = LegalizeOp(Result); 04967 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 04968 assert(isNew && "Value already packed?"); 04969 return Result; 04970 } 04971 04972 04973 // SelectionDAG::Legalize - This is the entry point for the file. 04974 // 04975 void SelectionDAG::Legalize() { 04976 if (ViewLegalizeDAGs) viewGraph(); 04977 04978 /// run - This is the main entry point to this class. 04979 /// 04980 SelectionDAGLegalize(*this).LegalizeDAG(); 04981 } 04982