LLVM API Documentation
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86MachineFunctionInfo.h"
#include "X86TargetMachine.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Intrinsics.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
Include dependency graph for X86ISelLowering.cpp:
Go to the source code of this file.
Functions | |
static unsigned | AddLiveIn (MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) |
static void | HowToPassCCCArgument (MVT::ValueType ObjectVT, unsigned NumXMMRegs, unsigned &ObjSize, unsigned &ObjXMMRegs) |
static void | HowToPassFastCCArgument (MVT::ValueType ObjectVT, unsigned NumIntRegs, unsigned NumXMMRegs, unsigned &ObjSize, unsigned &ObjIntRegs, unsigned &ObjXMMRegs) |
static unsigned | getCondBrOpcodeForX86CC (unsigned X86CC) |
static bool | translateX86CC (ISD::CondCode SetCCOpcode, bool isFP, unsigned &X86CC, bool &Flip) |
static bool | translateX86CC (SDOperand CC, bool isFP, unsigned &X86CC, bool &Flip) |
static bool | hasFPCMov (unsigned X86CC) |
static bool | DarwinGVRequiresExtraLoad (GlobalValue *GV) |
static bool | isUndefOrInRange (SDOperand Op, unsigned Low, unsigned Hi) |
static bool | isUndefOrEqual (SDOperand Op, unsigned Val) |
static bool | isSHUFPMask (std::vector< SDOperand > &N) |
static bool | isCommutedSHUFP (std::vector< SDOperand > &Ops) |
static bool | isCommutedSHUFP (SDNode *N) |
static bool | isUNPCKLMask (std::vector< SDOperand > &N, bool V2IsSplat=false) |
static bool | isUNPCKHMask (std::vector< SDOperand > &N, bool V2IsSplat=false) |
static bool | isMOVLMask (std::vector< SDOperand > &N) |
static bool | isCommutedMOVL (std::vector< SDOperand > &Ops, bool V2IsSplat=false) |
static bool | isCommutedMOVL (SDNode *N, bool V2IsSplat=false) |
static bool | isSplatMask (SDNode *N) |
static bool | isPSHUFHW_PSHUFLWMask (SDNode *N) |
static SDOperand | CommuteVectorShuffle (SDOperand Op, SelectionDAG &DAG) |
static bool | ShouldXformToMOVHLPS (SDNode *Mask) |
static bool | isScalarLoadToVector (SDNode *N) |
static bool | ShouldXformToMOVLP (SDNode *V1, SDNode *Mask) |
static bool | isSplatVector (SDNode *N) |
static SDOperand | NormalizeMask (SDOperand Mask, SelectionDAG &DAG) |
static SDOperand | getMOVLMask (unsigned NumElems, SelectionDAG &DAG) |
static SDOperand | getUnpacklMask (unsigned NumElems, SelectionDAG &DAG) |
static SDOperand | getUnpackhMask (unsigned NumElems, SelectionDAG &DAG) |
static SDOperand | getZeroVector (MVT::ValueType VT, SelectionDAG &DAG) |
static SDOperand | PromoteSplat (SDOperand Op, SelectionDAG &DAG) |
static bool | isZeroNode (SDOperand Elt) |
static SDOperand | getShuffleVectorZeroOrUndef (SDOperand V2, MVT::ValueType VT, unsigned NumElems, unsigned Idx, bool isZero, SelectionDAG &DAG) |
static SDOperand | LowerBuildVectorv16i8 (SDOperand Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG) |
static SDOperand | LowerBuildVectorv8i16 (SDOperand Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG) |
static SDOperand | getShuffleScalarElt (SDNode *N, unsigned i, SelectionDAG &DAG) |
static bool | isGAPlusOffset (SDNode *N, GlobalValue *&GA, int64_t &Offset) |
static bool | isConsecutiveLoad (SDNode *N, SDNode *Base, int Dist, int Size, MachineFrameInfo *MFI) |
static bool | isBaseAlignment16 (SDNode *Base, MachineFrameInfo *MFI, const X86Subtarget *Subtarget) |
static SDOperand | PerformShuffleCombine (SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) |
Variables | |
static cl::opt< bool > | EnableFastCC ("enable-x86-fastcc", cl::Hidden, cl::desc("Enable fastcc on X86")) |
static unsigned AddLiveIn | ( | MachineFunction & | MF, | |
unsigned | PReg, | |||
TargetRegisterClass * | RC | |||
) | [static] |
AddLiveIn - This helper function adds the specified physical register to the MachineFunction as a live in value. It also creates a corresponding virtual register for it.
Definition at line 372 of file X86ISelLowering.cpp.
References llvm::MachineFunction::addLiveIn(), llvm::SSARegMap::createVirtualRegister(), llvm::MachineFunction::getSSARegMap(), MF, and RC.
static SDOperand CommuteVectorShuffle | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [static] |
CommuteVectorShuffle - Swap vector_shuffle operandsas well as values in ther permute mask.
Definition at line 1942 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), llvm::SDOperand::getOperand(), llvm::SDOperand::getValueType(), llvm::MVT::getVectorBaseType(), Op, llvm::ISD::UNDEF, Val, and llvm::ISD::VECTOR_SHUFFLE.
static bool DarwinGVRequiresExtraLoad | ( | GlobalValue * | GV | ) | [static] |
DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra load. For Darwin, external and weak symbols are indirect, loading the value at address GV rather then the value of GV itself. This means that the GlobalAddress must be in the base or index register of the address, not the GV offset field.
Definition at line 1405 of file X86ISelLowering.cpp.
References GV, llvm::GlobalValue::hasLinkOnceLinkage(), llvm::GlobalValue::hasNotBeenReadFromBytecode(), llvm::GlobalValue::hasWeakLinkage(), and llvm::GlobalValue::isExternal().
Referenced by llvm::X86TargetLowering::isLegalAddressImmediate().
static unsigned getCondBrOpcodeForX86CC | ( | unsigned | X86CC | ) | [static] |
getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode which corresponds to the condition code.
Definition at line 1299 of file X86ISelLowering.cpp.
References llvm::X86ISD::COND_A, llvm::X86ISD::COND_AE, llvm::X86ISD::COND_B, llvm::X86ISD::COND_BE, llvm::X86ISD::COND_E, llvm::X86ISD::COND_G, llvm::X86ISD::COND_GE, llvm::X86ISD::COND_L, llvm::X86ISD::COND_LE, llvm::X86ISD::COND_NE, llvm::X86ISD::COND_NO, llvm::X86ISD::COND_NP, llvm::X86ISD::COND_NS, llvm::X86ISD::COND_O, llvm::X86ISD::COND_P, and llvm::X86ISD::COND_S.
Referenced by llvm::X86TargetLowering::InsertAtEndOfBasicBlock().
static SDOperand getMOVLMask | ( | unsigned | NumElems, | |
SelectionDAG & | DAG | |||
) | [static] |
getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd operation of specified width.
Definition at line 2058 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), and llvm::MVT::getVectorBaseType().
static SDOperand getShuffleScalarElt | ( | SDNode * | N, | |
unsigned | i, | |||
SelectionDAG & | DAG | |||
) | [static] |
getShuffleScalarElt - Returns the scalar element that will make up the ith element of the result of the vector shuffle.
Definition at line 3981 of file X86ISelLowering.cpp.
References DAG, llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), llvm::SDOperand::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::getVectorBaseType(), llvm::ISD::SCALAR_TO_VECTOR, V, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by PerformShuffleCombine().
static SDOperand getShuffleVectorZeroOrUndef | ( | SDOperand | V2, | |
MVT::ValueType | VT, | |||
unsigned | NumElems, | |||
unsigned | Idx, | |||
bool | isZero, | |||
SelectionDAG & | DAG | |||
) | [static] |
getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified vector and zero or undef vector.
Definition at line 2140 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorBaseType(), getZeroVector(), llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.
static SDOperand getUnpackhMask | ( | unsigned | NumElems, | |
SelectionDAG & | DAG | |||
) | [static] |
getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation of specified width.
Definition at line 2084 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), and llvm::MVT::getVectorBaseType().
static SDOperand getUnpacklMask | ( | unsigned | NumElems, | |
SelectionDAG & | DAG | |||
) | [static] |
getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation of specified width.
Definition at line 2071 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), and llvm::MVT::getVectorBaseType().
Referenced by PromoteSplat().
static SDOperand getZeroVector | ( | MVT::ValueType | VT, | |
SelectionDAG & | DAG | |||
) | [static] |
getZeroVector - Returns a vector of specified type with all zero elements.
Definition at line 2098 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorBaseType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFloatingPoint(), and llvm::MVT::isVector().
Referenced by getShuffleVectorZeroOrUndef(), LowerBuildVectorv16i8(), LowerBuildVectorv8i16(), and PromoteSplat().
static bool hasFPCMov | ( | unsigned | X86CC | ) | [static] |
hasFPCMov - is there a floating point cmov for the specific X86 condition code. Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Definition at line 1384 of file X86ISelLowering.cpp.
References llvm::X86ISD::COND_A, llvm::X86ISD::COND_AE, llvm::X86ISD::COND_B, llvm::X86ISD::COND_BE, llvm::X86ISD::COND_E, llvm::X86ISD::COND_NE, llvm::X86ISD::COND_NP, and llvm::X86ISD::COND_P.
static void HowToPassCCCArgument | ( | MVT::ValueType | ObjectVT, | |
unsigned | NumXMMRegs, | |||
unsigned & | ObjSize, | |||
unsigned & | ObjXMMRegs | |||
) | [static] |
HowToPassCCCArgument - Returns how an formal argument of the specified type should be passed. If it is through stack, returns the size of the stack slot; if it is through XMM register, returns the number of XMM registers are needed.
Definition at line 385 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.
static void HowToPassFastCCArgument | ( | MVT::ValueType | ObjectVT, | |
unsigned | NumIntRegs, | |||
unsigned | NumXMMRegs, | |||
unsigned & | ObjSize, | |||
unsigned & | ObjIntRegs, | |||
unsigned & | ObjXMMRegs | |||
) | [static] |
HowToPassFastCCArgument - Returns how an formal argument of the specified type should be passed. If it is through stack, returns the size of the stack slot; if it is through integer or XMM register, returns the number of integer or XMM registers are needed.
Definition at line 773 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, FASTCC_NUM_INT_ARGS_INREGS, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.
static bool isBaseAlignment16 | ( | SDNode * | Base, | |
MachineFrameInfo * | MFI, | |||
const X86Subtarget * | Subtarget | |||
) | [static] |
Definition at line 4059 of file X86ISelLowering.cpp.
References Base, llvm::ISD::FrameIndex, llvm::GlobalValue::getAlignment(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), GV, isGAPlusOffset(), and Subtarget.
Referenced by PerformShuffleCombine().
static bool isCommutedMOVL | ( | SDNode * | N, | |
bool | V2IsSplat = false | |||
) | [static] |
Definition at line 1738 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getOpcode(), isCommutedMOVL(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), and Ops.
static bool isCommutedMOVL | ( | std::vector< SDOperand > & | Ops, | |
bool | V2IsSplat = false | |||
) | [static] |
isCommutedMOVL - Returns true if the shuffle mask is except the reverse of what x86 movss want. X86 movs requires the lowest element to be lowest element of vector 2 and the other elements to come from vector 1 in order.
Definition at line 1716 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by isCommutedMOVL(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
static bool isCommutedSHUFP | ( | SDNode * | N | ) | [static] |
Definition at line 1540 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getOpcode(), isCommutedSHUFP(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), and Ops.
static bool isCommutedSHUFP | ( | std::vector< SDOperand > & | Ops | ) | [static] |
isCommutedSHUFP - Returns true if the shuffle mask is except the reverse of what x86 shuffles want. x86 shuffles requires the lower half elements to come from vector 1 (which would equal the dest.) and the upper half to come from vector 2.
Definition at line 1526 of file X86ISelLowering.cpp.
References isUndefOrInRange().
Referenced by isCommutedSHUFP(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
static bool isConsecutiveLoad | ( | SDNode * | N, | |
SDNode * | Base, | |||
int | Dist, | |||
int | Size, | |||
MachineFrameInfo * | MFI | |||
) | [static] |
isConsecutiveLoad - Returns true if N is loading from an address of Base + Dist * Size.
Definition at line 4029 of file X86ISelLowering.cpp.
References Base, llvm::ISD::FrameIndex, llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDOperand::getOpcode(), llvm::SDNode::getOperand(), isGAPlusOffset(), and llvm::SDOperand::Val.
Referenced by PerformShuffleCombine().
static bool isGAPlusOffset | ( | SDNode * | N, | |
GlobalValue *& | GA, | |||
int64_t & | Offset | |||
) | [static] |
isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + an offset.
Definition at line 4001 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), V, llvm::SDOperand::Val, and llvm::X86ISD::Wrapper.
Referenced by isBaseAlignment16(), and isConsecutiveLoad().
static bool isMOVLMask | ( | std::vector< SDOperand > & | N | ) | [static] |
isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSS, MOVSD, and MOVD, i.e. setting the lowest element.
Definition at line 1690 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by llvm::X86::isMOVLMask(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
static bool isPSHUFHW_PSHUFLWMask | ( | SDNode * | N | ) | [static] |
isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand specifies a 8 element shuffle that can be broken into a pair of PSHUFHW and PSHUFLW.
Definition at line 1911 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::UNDEF, and Val.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
static bool isScalarLoadToVector | ( | SDNode * | N | ) | [inline, static] |
isScalarLoadToVector - Returns true if the node is a scalar load that is promoted to a vector.
Definition at line 1989 of file X86ISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::LOAD, llvm::ISD::SCALAR_TO_VECTOR, and llvm::SDOperand::Val.
Referenced by ShouldXformToMOVLP().
static bool isSHUFPMask | ( | std::vector< SDOperand > & | N | ) | [static] |
isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to SHUFP*.
Definition at line 1501 of file X86ISelLowering.cpp.
References isUndefOrInRange().
Referenced by llvm::X86::isSHUFPMask(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
static bool isSplatMask | ( | SDNode * | N | ) | [static] |
isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element.
Definition at line 1808 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::UNDEF, and llvm::SDOperand::Val.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), and llvm::X86::isSplatMask().
static bool isSplatVector | ( | SDNode * | N | ) | [static] |
isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are all the same.
Definition at line 2020 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().
static bool isUndefOrEqual | ( | SDOperand | Op, | |
unsigned | Val | |||
) | [static] |
isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value equal to the specified value.
Definition at line 1422 of file X86ISelLowering.cpp.
References Op, and llvm::ISD::UNDEF.
Referenced by isCommutedMOVL(), llvm::X86::isMOVHLPSMask(), llvm::X86::isMOVHPMask(), isMOVLMask(), llvm::X86::isMOVLPMask(), llvm::X86::isPSHUFLWMask(), isUNPCKHMask(), llvm::X86::isUNPCKL_v_undef_Mask(), isUNPCKLMask(), ShouldXformToMOVHLPS(), and ShouldXformToMOVLP().
static bool isUndefOrInRange | ( | SDOperand | Op, | |
unsigned | Low, | |||
unsigned | Hi | |||
) | [static] |
isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value falls within the specified range (L, H].
Definition at line 1412 of file X86ISelLowering.cpp.
References Op, llvm::ISD::UNDEF, and Val.
Referenced by isCommutedSHUFP(), llvm::X86::isPSHUFLWMask(), and isSHUFPMask().
static bool isUNPCKHMask | ( | std::vector< SDOperand > & | N, | |
bool | V2IsSplat = false | |||
) | [static] |
isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKH.
Definition at line 1636 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), and llvm::X86::isUNPCKHMask().
static bool isUNPCKLMask | ( | std::vector< SDOperand > & | N, | |
bool | V2IsSplat = false | |||
) | [static] |
isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKL.
Definition at line 1606 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), and llvm::X86::isUNPCKLMask().
static bool isZeroNode | ( | SDOperand | Elt | ) | [inline, static] |
isZeroNode - Returns true if Elt is a constant zero or a floating point constant +0.0.
Definition at line 2131 of file X86ISelLowering.cpp.
static SDOperand LowerBuildVectorv16i8 | ( | SDOperand | Op, | |
unsigned | NonZeros, | |||
unsigned | NumNonZero, | |||
unsigned | NumZero, | |||
SelectionDAG & | DAG | |||
) | [static] |
LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
Definition at line 2155 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, Op, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::UNDEF, V, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::ISD::ZERO_EXTEND.
static SDOperand LowerBuildVectorv8i16 | ( | SDOperand | Op, | |
unsigned | NonZeros, | |||
unsigned | NumNonZero, | |||
unsigned | NumZero, | |||
SelectionDAG & | DAG | |||
) | [static] |
LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
Definition at line 2199 of file X86ISelLowering.cpp.
References DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, Op, llvm::ISD::UNDEF, V, and llvm::MVT::v8i16.
static SDOperand NormalizeMask | ( | SDOperand | Mask, | |
SelectionDAG & | DAG | |||
) | [static] |
NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements that point to V2 points to its first element.
Definition at line 2033 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, Changed, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), llvm::SDOperand::getOpcode(), llvm::SDOperand::getOperand(), llvm::SDOperand::getValueType(), llvm::ISD::UNDEF, and Val.
static SDOperand PerformShuffleCombine | ( | SDNode * | N, | |
SelectionDAG & | DAG, | |||
const X86Subtarget * | Subtarget | |||
) | [static] |
PerformShuffleCombine - Combine a vector_shuffle that is equal to build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are consecutive, non-overlapping, and in the right order.
Definition at line 4083 of file X86ISelLowering.cpp.
References Base, llvm::ISD::BIT_CONVERT, DAG, llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), llvm::SDOperand::getOpcode(), llvm::SDOperand::getOperand(), llvm::SDNode::getOperand(), getShuffleScalarElt(), llvm::MVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::getVectorBaseType(), isBaseAlignment16(), isConsecutiveLoad(), llvm::ISD::LOAD, llvm::X86ISD::LOAD_UA, MF, Subtarget, llvm::MVT::v4f32, and llvm::SDOperand::Val.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
static SDOperand PromoteSplat | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [static] |
PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
Definition at line 2110 of file X86ISelLowering.cpp.
References llvm::ISD::BIT_CONVERT, DAG, llvm::MVT::getIntVectorWithNumElements(), llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), getUnpacklMask(), getZeroVector(), Op, llvm::ISD::UNDEF, llvm::MVT::v4i32, and llvm::ISD::VECTOR_SHUFFLE.
static bool ShouldXformToMOVHLPS | ( | SDNode * | Mask | ) | [static] |
ShouldXformToMOVHLPS - Return true if the node should be transformed to match movhlps. The lower half elements should come from upper half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order).
Definition at line 1974 of file X86ISelLowering.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), and isUndefOrEqual().
ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to match movlp{s|d}. The lower half elements should come from lower half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order). And since V1 will become the source of the MOVLP, it must be either a vector load or a scalar load to vector.
Definition at line 2002 of file X86ISelLowering.cpp.
References llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), isScalarLoadToVector(), isUndefOrEqual(), and llvm::ISD::LOAD.
static bool translateX86CC | ( | SDOperand | CC, | |
bool | isFP, | |||
unsigned & | X86CC, | |||
bool & | Flip | |||
) | [static] |
static bool translateX86CC | ( | ISD::CondCode | SetCCOpcode, | |
bool | isFP, | |||
unsigned & | X86CC, | |||
bool & | Flip | |||
) | [static] |
translateX86CC - do a one to one translation of a ISD::CondCode to the X86 specific condition code. It returns a false if it cannot do a direct translation. X86CC is the translated CondCode. Flip is set to true if the the order of comparison operands should be flipped.
Definition at line 1325 of file X86ISelLowering.cpp.
References llvm::X86ISD::COND_A, llvm::X86ISD::COND_AE, llvm::X86ISD::COND_B, llvm::X86ISD::COND_BE, llvm::X86ISD::COND_E, llvm::X86ISD::COND_G, llvm::X86ISD::COND_GE, llvm::X86ISD::COND_INVALID, llvm::X86ISD::COND_L, llvm::X86ISD::COND_LE, llvm::X86ISD::COND_NE, llvm::X86ISD::COND_NP, llvm::X86ISD::COND_P, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.
Referenced by translateX86CC().
cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, cl::desc("Enable fastcc on X86")) [static] |