LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // FP Register Class... 00013 static const unsigned FP[] = { 00014 IA64::F6, IA64::F7, IA64::F8, IA64::F9, IA64::F10, IA64::F11, IA64::F12, IA64::F13, IA64::F14, IA64::F15, IA64::F32, IA64::F33, IA64::F34, IA64::F35, IA64::F36, IA64::F37, IA64::F38, IA64::F39, IA64::F40, IA64::F41, IA64::F42, IA64::F43, IA64::F44, IA64::F45, IA64::F46, IA64::F47, IA64::F48, IA64::F49, IA64::F50, IA64::F51, IA64::F52, IA64::F53, IA64::F54, IA64::F55, IA64::F56, IA64::F57, IA64::F58, IA64::F59, IA64::F60, IA64::F61, IA64::F62, IA64::F63, IA64::F64, IA64::F65, IA64::F66, IA64::F67, IA64::F68, IA64::F69, IA64::F70, IA64::F71, IA64::F72, IA64::F73, IA64::F74, IA64::F75, IA64::F76, IA64::F77, IA64::F78, IA64::F79, IA64::F80, IA64::F81, IA64::F82, IA64::F83, IA64::F84, IA64::F85, IA64::F86, IA64::F87, IA64::F88, IA64::F89, IA64::F90, IA64::F91, IA64::F92, IA64::F93, IA64::F94, IA64::F95, IA64::F96, IA64::F97, IA64::F98, IA64::F99, IA64::F100, IA64::F101, IA64::F102, IA64::F103, IA64::F104, IA64::F105, IA64::F106, IA64::F107, IA64::F108, IA64::F109, IA64::F110, IA64::F111, IA64::F112, IA64::F113, IA64::F114, IA64::F115, IA64::F116, IA64::F117, IA64::F118, IA64::F119, IA64::F120, IA64::F121, IA64::F122, IA64::F123, IA64::F124, IA64::F125, IA64::F126, IA64::F127, IA64::F0, IA64::F1, 00015 }; 00016 00017 // GR Register Class... 00018 static const unsigned GR[] = { 00019 IA64::out7, IA64::out6, IA64::out5, IA64::out4, IA64::out3, IA64::out2, IA64::out1, IA64::out0, IA64::r3, IA64::r8, IA64::r9, IA64::r10, IA64::r11, IA64::r14, IA64::r15, IA64::r16, IA64::r17, IA64::r18, IA64::r19, IA64::r20, IA64::r21, IA64::r23, IA64::r24, IA64::r25, IA64::r26, IA64::r27, IA64::r28, IA64::r29, IA64::r30, IA64::r31, IA64::r32, IA64::r33, IA64::r34, IA64::r35, IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41, IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47, IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53, IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59, IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65, IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71, IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77, IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83, IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89, IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95, IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101, IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107, IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113, IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119, IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125, IA64::r126, IA64::r127, IA64::r0, IA64::r1, IA64::r2, IA64::r5, IA64::r12, IA64::r13, IA64::r22, IA64::rp, 00020 }; 00021 00022 // PR Register Class... 00023 static const unsigned PR[] = { 00024 IA64::p6, IA64::p7, IA64::p8, IA64::p9, IA64::p10, IA64::p11, IA64::p12, IA64::p13, IA64::p14, IA64::p15, 00025 }; 00026 00027 // FPVTs Register Class Value Types... 00028 static const MVT::ValueType FPVTs[] = { 00029 MVT::f64, MVT::Other 00030 }; 00031 00032 // GRVTs Register Class Value Types... 00033 static const MVT::ValueType GRVTs[] = { 00034 MVT::i64, MVT::Other 00035 }; 00036 00037 // PRVTs Register Class Value Types... 00038 static const MVT::ValueType PRVTs[] = { 00039 MVT::i1, MVT::Other 00040 }; 00041 00042 } // end anonymous namespace 00043 00044 namespace IA64 { // Register class instances 00045 FPClass FPRegClass; 00046 GRClass GRRegClass; 00047 PRClass PRRegClass; 00048 00049 // FP Register Class sub-classes... 00050 static const TargetRegisterClass* const FPSubclasses [] = { 00051 NULL 00052 }; 00053 00054 // GR Register Class sub-classes... 00055 static const TargetRegisterClass* const GRSubclasses [] = { 00056 NULL 00057 }; 00058 00059 // PR Register Class sub-classes... 00060 static const TargetRegisterClass* const PRSubclasses [] = { 00061 NULL 00062 }; 00063 00064 // FP Register Class super-classes... 00065 static const TargetRegisterClass* const FPSuperclasses [] = { 00066 NULL 00067 }; 00068 00069 // GR Register Class super-classes... 00070 static const TargetRegisterClass* const GRSuperclasses [] = { 00071 NULL 00072 }; 00073 00074 // PR Register Class super-classes... 00075 static const TargetRegisterClass* const PRSuperclasses [] = { 00076 NULL 00077 }; 00078 00079 00080 FPClass::iterator 00081 FPClass::allocation_order_begin(MachineFunction &MF) const { 00082 return begin(); // we don't hide any FP regs from the start 00083 } 00084 00085 FPClass::iterator 00086 FPClass::allocation_order_end(MachineFunction &MF) const { 00087 return end()-2; // we hide regs F0, F1 from the end 00088 } 00089 00090 FPClass::FPClass() : TargetRegisterClass(FPRegClassID, FPVTs, FPSubclasses, FPSuperclasses, 16, 16, FP, FP + 108) {} 00091 00092 GRClass::iterator 00093 GRClass::allocation_order_begin(MachineFunction &MF) const { 00094 // hide the 8 out? registers appropriately: 00095 return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed)); 00096 } 00097 00098 GRClass::iterator 00099 GRClass::allocation_order_end(MachineFunction &MF) const { 00100 int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc 00101 00102 // we also can't allocate registers for use as locals if they're 00103 // already required as 'out' registers 00104 numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; 00105 00106 return end()-numReservedRegs; // hide registers appropriately 00107 } 00108 00109 GRClass::GRClass() : TargetRegisterClass(GRRegClassID, GRVTs, GRSubclasses, GRSuperclasses, 8, 8, GR, GR + 134) {} 00110 00111 PRClass::PRClass() : TargetRegisterClass(PRRegClassID, PRVTs, PRSubclasses, PRSuperclasses, 8, 8, PR, PR + 10) {} 00112 } 00113 00114 namespace { 00115 const TargetRegisterClass* const RegisterClasses[] = { 00116 &IA64::FPRegClass, 00117 &IA64::GRRegClass, 00118 &IA64::PRRegClass, 00119 }; 00120 const unsigned Empty_AliasSet[] = { 0 }; 00121 00122 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00123 { "NOREG", 0 }, 00124 { "ar.pfs", Empty_AliasSet }, 00125 { "b6", Empty_AliasSet }, 00126 { "f0", Empty_AliasSet }, 00127 { "f1", Empty_AliasSet }, 00128 { "f10", Empty_AliasSet }, 00129 { "f100", Empty_AliasSet }, 00130 { "f101", Empty_AliasSet }, 00131 { "f102", Empty_AliasSet }, 00132 { "f103", Empty_AliasSet }, 00133 { "f104", Empty_AliasSet }, 00134 { "f105", Empty_AliasSet }, 00135 { "f106", Empty_AliasSet }, 00136 { "f107", Empty_AliasSet }, 00137 { "f108", Empty_AliasSet }, 00138 { "f109", Empty_AliasSet }, 00139 { "f11", Empty_AliasSet }, 00140 { "f110", Empty_AliasSet }, 00141 { "f111", Empty_AliasSet }, 00142 { "f112", Empty_AliasSet }, 00143 { "f113", Empty_AliasSet }, 00144 { "f114", Empty_AliasSet }, 00145 { "f115", Empty_AliasSet }, 00146 { "f116", Empty_AliasSet }, 00147 { "f117", Empty_AliasSet }, 00148 { "f118", Empty_AliasSet }, 00149 { "f119", Empty_AliasSet }, 00150 { "f12", Empty_AliasSet }, 00151 { "f120", Empty_AliasSet }, 00152 { "f121", Empty_AliasSet }, 00153 { "f122", Empty_AliasSet }, 00154 { "f123", Empty_AliasSet }, 00155 { "f124", Empty_AliasSet }, 00156 { "f125", Empty_AliasSet }, 00157 { "f126", Empty_AliasSet }, 00158 { "f127", Empty_AliasSet }, 00159 { "f13", Empty_AliasSet }, 00160 { "f14", Empty_AliasSet }, 00161 { "f15", Empty_AliasSet }, 00162 { "f16", Empty_AliasSet }, 00163 { "f17", Empty_AliasSet }, 00164 { "f18", Empty_AliasSet }, 00165 { "f19", Empty_AliasSet }, 00166 { "f2", Empty_AliasSet }, 00167 { "f20", Empty_AliasSet }, 00168 { "f21", Empty_AliasSet }, 00169 { "f22", Empty_AliasSet }, 00170 { "f23", Empty_AliasSet }, 00171 { "f24", Empty_AliasSet }, 00172 { "f25", Empty_AliasSet }, 00173 { "f26", Empty_AliasSet }, 00174 { "f27", Empty_AliasSet }, 00175 { "f28", Empty_AliasSet }, 00176 { "f29", Empty_AliasSet }, 00177 { "f3", Empty_AliasSet }, 00178 { "f30", Empty_AliasSet }, 00179 { "f31", Empty_AliasSet }, 00180 { "f32", Empty_AliasSet }, 00181 { "f33", Empty_AliasSet }, 00182 { "f34", Empty_AliasSet }, 00183 { "f35", Empty_AliasSet }, 00184 { "f36", Empty_AliasSet }, 00185 { "f37", Empty_AliasSet }, 00186 { "f38", Empty_AliasSet }, 00187 { "f39", Empty_AliasSet }, 00188 { "f4", Empty_AliasSet }, 00189 { "f40", Empty_AliasSet }, 00190 { "f41", Empty_AliasSet }, 00191 { "f42", Empty_AliasSet }, 00192 { "f43", Empty_AliasSet }, 00193 { "f44", Empty_AliasSet }, 00194 { "f45", Empty_AliasSet }, 00195 { "f46", Empty_AliasSet }, 00196 { "f47", Empty_AliasSet }, 00197 { "f48", Empty_AliasSet }, 00198 { "f49", Empty_AliasSet }, 00199 { "f5", Empty_AliasSet }, 00200 { "f50", Empty_AliasSet }, 00201 { "f51", Empty_AliasSet }, 00202 { "f52", Empty_AliasSet }, 00203 { "f53", Empty_AliasSet }, 00204 { "f54", Empty_AliasSet }, 00205 { "f55", Empty_AliasSet }, 00206 { "f56", Empty_AliasSet }, 00207 { "f57", Empty_AliasSet }, 00208 { "f58", Empty_AliasSet }, 00209 { "f59", Empty_AliasSet }, 00210 { "f6", Empty_AliasSet }, 00211 { "f60", Empty_AliasSet }, 00212 { "f61", Empty_AliasSet }, 00213 { "f62", Empty_AliasSet }, 00214 { "f63", Empty_AliasSet }, 00215 { "f64", Empty_AliasSet }, 00216 { "f65", Empty_AliasSet }, 00217 { "f66", Empty_AliasSet }, 00218 { "f67", Empty_AliasSet }, 00219 { "f68", Empty_AliasSet }, 00220 { "f69", Empty_AliasSet }, 00221 { "f7", Empty_AliasSet }, 00222 { "f70", Empty_AliasSet }, 00223 { "f71", Empty_AliasSet }, 00224 { "f72", Empty_AliasSet }, 00225 { "f73", Empty_AliasSet }, 00226 { "f74", Empty_AliasSet }, 00227 { "f75", Empty_AliasSet }, 00228 { "f76", Empty_AliasSet }, 00229 { "f77", Empty_AliasSet }, 00230 { "f78", Empty_AliasSet }, 00231 { "f79", Empty_AliasSet }, 00232 { "f8", Empty_AliasSet }, 00233 { "f80", Empty_AliasSet }, 00234 { "f81", Empty_AliasSet }, 00235 { "f82", Empty_AliasSet }, 00236 { "f83", Empty_AliasSet }, 00237 { "f84", Empty_AliasSet }, 00238 { "f85", Empty_AliasSet }, 00239 { "f86", Empty_AliasSet }, 00240 { "f87", Empty_AliasSet }, 00241 { "f88", Empty_AliasSet }, 00242 { "f89", Empty_AliasSet }, 00243 { "f9", Empty_AliasSet }, 00244 { "f90", Empty_AliasSet }, 00245 { "f91", Empty_AliasSet }, 00246 { "f92", Empty_AliasSet }, 00247 { "f93", Empty_AliasSet }, 00248 { "f94", Empty_AliasSet }, 00249 { "f95", Empty_AliasSet }, 00250 { "f96", Empty_AliasSet }, 00251 { "f97", Empty_AliasSet }, 00252 { "f98", Empty_AliasSet }, 00253 { "f99", Empty_AliasSet }, 00254 { "out0", Empty_AliasSet }, 00255 { "out1", Empty_AliasSet }, 00256 { "out2", Empty_AliasSet }, 00257 { "out3", Empty_AliasSet }, 00258 { "out4", Empty_AliasSet }, 00259 { "out5", Empty_AliasSet }, 00260 { "out6", Empty_AliasSet }, 00261 { "out7", Empty_AliasSet }, 00262 { "p0", Empty_AliasSet }, 00263 { "p1", Empty_AliasSet }, 00264 { "p10", Empty_AliasSet }, 00265 { "p11", Empty_AliasSet }, 00266 { "p12", Empty_AliasSet }, 00267 { "p13", Empty_AliasSet }, 00268 { "p14", Empty_AliasSet }, 00269 { "p15", Empty_AliasSet }, 00270 { "p16", Empty_AliasSet }, 00271 { "p17", Empty_AliasSet }, 00272 { "p18", Empty_AliasSet }, 00273 { "p19", Empty_AliasSet }, 00274 { "p2", Empty_AliasSet }, 00275 { "p20", Empty_AliasSet }, 00276 { "p21", Empty_AliasSet }, 00277 { "p22", Empty_AliasSet }, 00278 { "p23", Empty_AliasSet }, 00279 { "p24", Empty_AliasSet }, 00280 { "p25", Empty_AliasSet }, 00281 { "p26", Empty_AliasSet }, 00282 { "p27", Empty_AliasSet }, 00283 { "p28", Empty_AliasSet }, 00284 { "p29", Empty_AliasSet }, 00285 { "p3", Empty_AliasSet }, 00286 { "p30", Empty_AliasSet }, 00287 { "p31", Empty_AliasSet }, 00288 { "p32", Empty_AliasSet }, 00289 { "p33", Empty_AliasSet }, 00290 { "p34", Empty_AliasSet }, 00291 { "p35", Empty_AliasSet }, 00292 { "p36", Empty_AliasSet }, 00293 { "p37", Empty_AliasSet }, 00294 { "p38", Empty_AliasSet }, 00295 { "p39", Empty_AliasSet }, 00296 { "p4", Empty_AliasSet }, 00297 { "p40", Empty_AliasSet }, 00298 { "p41", Empty_AliasSet }, 00299 { "p42", Empty_AliasSet }, 00300 { "p43", Empty_AliasSet }, 00301 { "p44", Empty_AliasSet }, 00302 { "p45", Empty_AliasSet }, 00303 { "p46", Empty_AliasSet }, 00304 { "p47", Empty_AliasSet }, 00305 { "p48", Empty_AliasSet }, 00306 { "p49", Empty_AliasSet }, 00307 { "p5", Empty_AliasSet }, 00308 { "p50", Empty_AliasSet }, 00309 { "p51", Empty_AliasSet }, 00310 { "p52", Empty_AliasSet }, 00311 { "p53", Empty_AliasSet }, 00312 { "p54", Empty_AliasSet }, 00313 { "p55", Empty_AliasSet }, 00314 { "p56", Empty_AliasSet }, 00315 { "p57", Empty_AliasSet }, 00316 { "p58", Empty_AliasSet }, 00317 { "p59", Empty_AliasSet }, 00318 { "p6", Empty_AliasSet }, 00319 { "p60", Empty_AliasSet }, 00320 { "p61", Empty_AliasSet }, 00321 { "p62", Empty_AliasSet }, 00322 { "p63", Empty_AliasSet }, 00323 { "p7", Empty_AliasSet }, 00324 { "p8", Empty_AliasSet }, 00325 { "p9", Empty_AliasSet }, 00326 { "r0", Empty_AliasSet }, 00327 { "r1", Empty_AliasSet }, 00328 { "r10", Empty_AliasSet }, 00329 { "r100", Empty_AliasSet }, 00330 { "r101", Empty_AliasSet }, 00331 { "r102", Empty_AliasSet }, 00332 { "r103", Empty_AliasSet }, 00333 { "r104", Empty_AliasSet }, 00334 { "r105", Empty_AliasSet }, 00335 { "r106", Empty_AliasSet }, 00336 { "r107", Empty_AliasSet }, 00337 { "r108", Empty_AliasSet }, 00338 { "r109", Empty_AliasSet }, 00339 { "r11", Empty_AliasSet }, 00340 { "r110", Empty_AliasSet }, 00341 { "r111", Empty_AliasSet }, 00342 { "r112", Empty_AliasSet }, 00343 { "r113", Empty_AliasSet }, 00344 { "r114", Empty_AliasSet }, 00345 { "r115", Empty_AliasSet }, 00346 { "r116", Empty_AliasSet }, 00347 { "r117", Empty_AliasSet }, 00348 { "r118", Empty_AliasSet }, 00349 { "r119", Empty_AliasSet }, 00350 { "r12", Empty_AliasSet }, 00351 { "r120", Empty_AliasSet }, 00352 { "r121", Empty_AliasSet }, 00353 { "r122", Empty_AliasSet }, 00354 { "r123", Empty_AliasSet }, 00355 { "r124", Empty_AliasSet }, 00356 { "r125", Empty_AliasSet }, 00357 { "r126", Empty_AliasSet }, 00358 { "r127", Empty_AliasSet }, 00359 { "r13", Empty_AliasSet }, 00360 { "r14", Empty_AliasSet }, 00361 { "r15", Empty_AliasSet }, 00362 { "r16", Empty_AliasSet }, 00363 { "r17", Empty_AliasSet }, 00364 { "r18", Empty_AliasSet }, 00365 { "r19", Empty_AliasSet }, 00366 { "r2", Empty_AliasSet }, 00367 { "r20", Empty_AliasSet }, 00368 { "r21", Empty_AliasSet }, 00369 { "r22", Empty_AliasSet }, 00370 { "r23", Empty_AliasSet }, 00371 { "r24", Empty_AliasSet }, 00372 { "r25", Empty_AliasSet }, 00373 { "r26", Empty_AliasSet }, 00374 { "r27", Empty_AliasSet }, 00375 { "r28", Empty_AliasSet }, 00376 { "r29", Empty_AliasSet }, 00377 { "r3", Empty_AliasSet }, 00378 { "r30", Empty_AliasSet }, 00379 { "r31", Empty_AliasSet }, 00380 { "r32", Empty_AliasSet }, 00381 { "r33", Empty_AliasSet }, 00382 { "r34", Empty_AliasSet }, 00383 { "r35", Empty_AliasSet }, 00384 { "r36", Empty_AliasSet }, 00385 { "r37", Empty_AliasSet }, 00386 { "r38", Empty_AliasSet }, 00387 { "r39", Empty_AliasSet }, 00388 { "r4", Empty_AliasSet }, 00389 { "r40", Empty_AliasSet }, 00390 { "r41", Empty_AliasSet }, 00391 { "r42", Empty_AliasSet }, 00392 { "r43", Empty_AliasSet }, 00393 { "r44", Empty_AliasSet }, 00394 { "r45", Empty_AliasSet }, 00395 { "r46", Empty_AliasSet }, 00396 { "r47", Empty_AliasSet }, 00397 { "r48", Empty_AliasSet }, 00398 { "r49", Empty_AliasSet }, 00399 { "r5", Empty_AliasSet }, 00400 { "r50", Empty_AliasSet }, 00401 { "r51", Empty_AliasSet }, 00402 { "r52", Empty_AliasSet }, 00403 { "r53", Empty_AliasSet }, 00404 { "r54", Empty_AliasSet }, 00405 { "r55", Empty_AliasSet }, 00406 { "r56", Empty_AliasSet }, 00407 { "r57", Empty_AliasSet }, 00408 { "r58", Empty_AliasSet }, 00409 { "r59", Empty_AliasSet }, 00410 { "r6", Empty_AliasSet }, 00411 { "r60", Empty_AliasSet }, 00412 { "r61", Empty_AliasSet }, 00413 { "r62", Empty_AliasSet }, 00414 { "r63", Empty_AliasSet }, 00415 { "r64", Empty_AliasSet }, 00416 { "r65", Empty_AliasSet }, 00417 { "r66", Empty_AliasSet }, 00418 { "r67", Empty_AliasSet }, 00419 { "r68", Empty_AliasSet }, 00420 { "r69", Empty_AliasSet }, 00421 { "r7", Empty_AliasSet }, 00422 { "r70", Empty_AliasSet }, 00423 { "r71", Empty_AliasSet }, 00424 { "r72", Empty_AliasSet }, 00425 { "r73", Empty_AliasSet }, 00426 { "r74", Empty_AliasSet }, 00427 { "r75", Empty_AliasSet }, 00428 { "r76", Empty_AliasSet }, 00429 { "r77", Empty_AliasSet }, 00430 { "r78", Empty_AliasSet }, 00431 { "r79", Empty_AliasSet }, 00432 { "r8", Empty_AliasSet }, 00433 { "r80", Empty_AliasSet }, 00434 { "r81", Empty_AliasSet }, 00435 { "r82", Empty_AliasSet }, 00436 { "r83", Empty_AliasSet }, 00437 { "r84", Empty_AliasSet }, 00438 { "r85", Empty_AliasSet }, 00439 { "r86", Empty_AliasSet }, 00440 { "r87", Empty_AliasSet }, 00441 { "r88", Empty_AliasSet }, 00442 { "r89", Empty_AliasSet }, 00443 { "r9", Empty_AliasSet }, 00444 { "r90", Empty_AliasSet }, 00445 { "r91", Empty_AliasSet }, 00446 { "r92", Empty_AliasSet }, 00447 { "r93", Empty_AliasSet }, 00448 { "r94", Empty_AliasSet }, 00449 { "r95", Empty_AliasSet }, 00450 { "r96", Empty_AliasSet }, 00451 { "r97", Empty_AliasSet }, 00452 { "r98", Empty_AliasSet }, 00453 { "r99", Empty_AliasSet }, 00454 { "rp", Empty_AliasSet }, 00455 }; 00456 } 00457 00458 IA64GenRegisterInfo::IA64GenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00459 : MRegisterInfo(RegisterDescriptors, 332, RegisterClasses, RegisterClasses+3, 00460 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00461 00462 int IA64GenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00463 static const int DwarfRegNums[] = { -1, // NoRegister 00464 331, 326, 128, 129, 138, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 139, 00465 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 140, 248, 249, 250, 251, 252, 00466 253, 254, 255, 141, 142, 143, 144, 145, 146, 147, 130, 148, 149, 150, 151, 152, 00467 153, 154, 155, 156, 157, 131, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 00468 132, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 133, 178, 179, 180, 181, 00469 182, 183, 184, 185, 186, 187, 134, 188, 189, 190, 191, 192, 193, 194, 195, 196, 00470 197, 135, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 136, 208, 209, 210, 00471 211, 212, 213, 214, 215, 216, 217, 137, 218, 219, 220, 221, 222, 223, 224, 225, 00472 226, 227, 120, 121, 122, 123, 124, 125, 126, 127, 256, 257, 266, 267, 268, 269, 00473 270, 271, 272, 273, 274, 275, 258, 276, 277, 278, 279, 280, 281, 282, 283, 284, 00474 285, 259, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 260, 296, 297, 298, 00475 299, 300, 301, 302, 303, 304, 305, 261, 306, 307, 308, 309, 310, 311, 312, 313, 00476 314, 315, 262, 316, 317, 318, 319, 263, 264, 265, 0, 1, 10, 100, 101, 102, 00477 103, 104, 105, 106, 107, 108, 109, 11, 110, 111, 112, 113, 114, 115, 116, 117, 00478 118, 119, 12, 120, 121, 122, 123, 124, 125, 126, 127, 13, 14, 15, 16, 17, 00479 18, 19, 2, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 3, 30, 31, 00480 32, 33, 34, 35, 36, 37, 38, 39, 4, 40, 41, 42, 43, 44, 45, 46, 00481 47, 48, 49, 5, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 6, 60, 00482 61, 62, 63, 64, 65, 66, 67, 68, 69, 7, 70, 71, 72, 73, 74, 75, 00483 76, 77, 78, 79, 8, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 9, 00484 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, -1 00485 }; 00486 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00487 "RegNum exceeds number of registers"); 00488 return DwarfRegNums[RegNum]; 00489 } 00490 00491 } // End llvm namespace