LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Assembly Writer Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 /// printInstruction - This method is automatically generated by tablegen 00010 /// from the instruction set description. This method returns true if the 00011 /// machine instruction was sufficiently described to print it, otherwise 00012 /// it returns false. 00013 bool ARMAsmPrinter::printInstruction(const MachineInstr *MI) { 00014 static const unsigned OpInfo[] = { 00015 0U, // PHI 00016 0U, // INLINEASM 00017 2147483657U, // ADJCALLSTACKDOWN 00018 2147483676U, // ADJCALLSTACKUP 00019 2684354605U, // addri 00020 2147483698U, // bl 00021 2147483702U, // bx 00022 3355443258U, // ldr 00023 2952790079U, // movri 00024 2952790079U, // movrr 00025 3623878724U, // str 00026 2684354633U, // subri 00027 0U 00028 }; 00029 00030 const char *AsmStrs = 00031 "PHINODE\n\000!ADJCALLSTACKDOWN \000!ADJCALLSTACKUP \000add \000bl \000b" 00032 "x \000ldr \000mov \000str \000sub \000"; 00033 00034 if (MI->getOpcode() == TargetInstrInfo::INLINEASM) { 00035 printInlineAsm(MI); 00036 return true; 00037 } 00038 00039 // Emit the opcode for the instruction. 00040 unsigned Bits = OpInfo[MI->getOpcode()]; 00041 if (Bits == 0) return false; 00042 O << AsmStrs+(Bits & 127); 00043 00044 00045 // Fragment 0 encoded into 1 bits for 2 unique commands. 00046 if ((Bits >> 31) & 1) { 00047 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, addri, bl, bx, ldr, movri, movrr, st... 00048 printOperand(MI, 0); 00049 } else { 00050 return true; 00051 } 00052 00053 00054 // Fragment 1 encoded into 2 bits for 3 unique commands. 00055 switch ((Bits >> 29) & 3) { 00056 default: // unreachable. 00057 case 0: 00058 // ADJCALLSTACKDOWN, ADJCALLSTACKUP, bl, bx 00059 O << "\n"; 00060 return true; 00061 break; 00062 case 1: 00063 // addri, movri, movrr, subri 00064 O << ", "; 00065 printOperand(MI, 1); 00066 break; 00067 case 2: 00068 // ldr, str 00069 O << ", ["; 00070 break; 00071 } 00072 00073 00074 // Fragment 2 encoded into 2 bits for 4 unique commands. 00075 switch ((Bits >> 27) & 3) { 00076 default: // unreachable. 00077 case 0: 00078 // addri, subri 00079 O << ", "; 00080 printOperand(MI, 2); 00081 O << "\n"; 00082 return true; 00083 break; 00084 case 1: 00085 // ldr 00086 printMemRegImm(MI, 1); 00087 O << "]\n"; 00088 return true; 00089 break; 00090 case 2: 00091 // movri, movrr 00092 O << "\n"; 00093 return true; 00094 break; 00095 case 3: 00096 // str 00097 printOperand(MI, 1); 00098 O << "]\n"; 00099 return true; 00100 break; 00101 } 00102 00103 }