LLVM API Documentation
#include <X86ISelLowering.h>
Inheritance diagram for llvm::X86TargetLowering:
Definition at line 268 of file X86ISelLowering.h.
X86TargetLowering::X86TargetLowering | ( | TargetMachine & | TM | ) |
Definition at line 41 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::addLegalAddressScale(), llvm::TargetLowering::addLegalFPImmediate(), llvm::TargetLowering::AddPromotedToType(), llvm::TargetLowering::addRegisterClass(), llvm::TargetLowering::allowUnalignedMemoryAccesses, llvm::ISD::AND, llvm::ISD::BIT_CONVERT, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::computeRegisterProperties(), llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::Custom, llvm::ISD::DEBUG_LABEL, llvm::ISD::DEBUG_LOC, llvm::ISD::DYNAMIC_STACKALLOC, N86::ESP, llvm::TargetLowering::Expand, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FNEG, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::TargetMachine::getSubtarget(), llvm::ISD::GlobalAddress, llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::X86Subtarget::isTargetDarwin(), llvm::ISD::JumpTable, llvm::MVT::LAST_VALUETYPE, llvm::TargetLowering::Legal, llvm::ISD::LOAD, llvm::ISD::LOCATION, llvm::TargetLowering::Mask, llvm::TargetLowering::maxStoresPerMemcpy, llvm::TargetLowering::maxStoresPerMemmove, llvm::TargetLowering::maxStoresPerMemset, llvm::ISD::MEMCPY, llvm::ISD::MEMMOVE, llvm::ISD::MEMSET, llvm::ISD::MUL, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLowering::Promote, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RET, llvm::ISD::SCALAR_TO_VECTOR, llvm::TargetLowering::SchedulingForRegPressure, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLowering::setOperationAction(), llvm::TargetLowering::setSchedulingPreference(), llvm::TargetLowering::setSetCCResultContents(), llvm::TargetLowering::setSetCCResultType(), llvm::TargetLowering::setShiftAmountFlavor(), llvm::TargetLowering::setShiftAmountType(), llvm::TargetLowering::setStackPointerRegisterToSaveRestore(), llvm::TargetLowering::setTargetDAGCombine(), llvm::TargetLowering::setUseUnderscoreSetJmpLongJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::SUB, llvm::ISD::UINT_TO_FP, llvm::ISD::UNDEF, llvm::UnsafeFPMath, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::MVT::Vector, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, and llvm::TargetLowering::ZeroOrOneSetCCResult.
unsigned llvm::X86TargetLowering::getBytesToPopOnReturn | ( | ) | const [inline] |
Definition at line 279 of file X86ISelLowering.h.
unsigned llvm::X86TargetLowering::getBytesCallerReserves | ( | ) | const [inline] |
Definition at line 283 of file X86ISelLowering.h.
SDOperand X86TargetLowering::LowerOperation | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [virtual] |
LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 3694 of file X86ISelLowering.cpp.
References llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CALL, llvm::ISD::ConstantPool, DAG, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FNEG, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_TO_SINT, llvm::ISD::GlobalAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm::ISD::MEMCPY, llvm::ISD::MEMSET, Op, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RET, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, llvm::ISD::VASTART, and llvm::ISD::VECTOR_SHUFFLE.
std::pair< SDOperand, SDOperand > X86TargetLowering::LowerFrameReturnAddress | ( | bool | isFrameAddr, | |
SDOperand | Chain, | |||
unsigned | Depth, | |||
SelectionDAG & | DAG | |||
) | [virtual] |
LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or llvm.frameaddress (depending on the value of the first argument). The return values are the result pointer and the resultant token chain. If not implemented, both of these intrinsics will return null.
Reimplemented from llvm::TargetLowering.
Definition at line 1279 of file X86ISelLowering.cpp.
References DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), getReturnAddressFrameIndex(), llvm::SelectionDAG::getSrcValue(), llvm::MVT::i32, and llvm::ISD::SUB.
SDOperand X86TargetLowering::PerformDAGCombine | ( | SDNode * | N, | |
DAGCombinerInfo & | DCI | |||
) | const [virtual] |
Definition at line 4121 of file X86ISelLowering.cpp.
References DAG, llvm::SDNode::getOpcode(), llvm::TargetLowering::getTargetMachine(), PerformShuffleCombine(), TM, and llvm::ISD::VECTOR_SHUFFLE.
MachineBasicBlock * X86TargetLowering::InsertAtEndOfBasicBlock | ( | MachineInstr * | MI, | |
MachineBasicBlock * | MBB | |||
) | [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 3826 of file X86ISelLowering.cpp.
References llvm::addFrameReference(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::X86AddressMode::Base, llvm::X86AddressMode::BaseType, BB, llvm::BuildMI(), llvm::X86AddressMode::Disp, F, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86AddressMode::FrameIndex, llvm::X86AddressMode::FrameIndexBase, getCondBrOpcodeForX86CC(), llvm::MachineOperand::getImmedValue(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::BasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::X86AddressMode::GV, llvm::X86AddressMode::IndexReg, MI, Op, PHI, llvm::X86AddressMode::Reg, llvm::X86AddressMode::RegBase, and llvm::X86AddressMode::Scale.
const char * X86TargetLowering::getTargetNodeName | ( | unsigned | Opcode | ) | const [virtual] |
getTargetNodeName - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 3727 of file X86ISelLowering.cpp.
References llvm::X86ISD::BRCOND, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86ISD::COMI, llvm::X86ISD::FAND, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FLD, llvm::X86ISD::FP_GET_RESULT, llvm::X86ISD::FP_SET_RESULT, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FST, llvm::X86ISD::FXOR, llvm::X86ISD::GlobalBaseReg, llvm::X86ISD::LOAD_PACK, llvm::X86ISD::LOAD_UA, llvm::X86ISD::PEXTRW, llvm::X86ISD::PINSRW, llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::REP_MOVS, llvm::X86ISD::REP_STOS, llvm::X86ISD::RET_FLAG, llvm::X86ISD::S2VEC, llvm::X86ISD::SETCC, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::X86ISD::TAILCALL, llvm::X86ISD::TEST, llvm::X86ISD::UCOMI, and llvm::X86ISD::Wrapper.
void X86TargetLowering::computeMaskedBitsForTargetNode | ( | const SDOperand | Op, | |
uint64_t | Mask, | |||
uint64_t & | KnownZero, | |||
uint64_t & | KnownOne, | |||
unsigned | Depth = 0 | |||
) | const [virtual] |
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 3957 of file X86ISelLowering.cpp.
References llvm::ISD::BUILTIN_OP_END, llvm::MVT::getIntVTBitMask(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, Op, and llvm::X86ISD::SETCC.
SDOperand X86TargetLowering::getReturnAddressFrameIndex | ( | SelectionDAG & | DAG | ) |
Definition at line 1266 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), DAG, llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::MVT::i32, and MF.
Referenced by LowerFrameReturnAddress().
X86TargetLowering::ConstraintType X86TargetLowering::getConstraintType | ( | char | ConstraintLetter | ) | const [virtual] |
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 4141 of file X86ISelLowering.cpp.
References llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().
std::vector< unsigned > X86TargetLowering::getRegClassForInlineAsmConstraint | ( | const std::string & | Constraint, | |
MVT::ValueType | VT | |||
) | const [virtual] |
getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.
Reimplemented from llvm::TargetLowering.
Definition at line 4157 of file X86ISelLowering.cpp.
References N86::EBP, N86::EBX, N86::ECX, N86::EDI, N86::ESI, N86::ESP, llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i16, llvm::MVT::i64, and llvm::MVT::i8.
bool X86TargetLowering::isLegalAddressImmediate | ( | int64_t | V | ) | const [virtual] |
isLegalAddressImmediate - Return true if the integer value or GlobalValue can be used as the offset of the target addressing mode.
Reimplemented from llvm::TargetLowering.
Definition at line 3768 of file X86ISelLowering.cpp.
bool X86TargetLowering::isLegalAddressImmediate | ( | GlobalValue * | GV | ) | const [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 3773 of file X86ISelLowering.cpp.
References DarwinGVRequiresExtraLoad(), llvm::Reloc::DynamicNoPIC, llvm::TargetMachine::getRelocationModel(), llvm::TargetLowering::getTargetMachine(), GV, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetDarwin(), and llvm::Reloc::Static.
bool X86TargetLowering::isShuffleMaskLegal | ( | SDOperand | Mask, | |
MVT::ValueType | VT | |||
) | const [virtual] |
isShuffleMaskLegal - Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented from llvm::TargetLowering.
Definition at line 3796 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), isPSHUFHW_PSHUFLWMask(), isSplatMask(), isUNPCKHMask(), llvm::X86::isUNPCKL_v_undef_Mask(), isUNPCKLMask(), and llvm::TargetLowering::Mask.
bool X86TargetLowering::isVectorClearMaskLegal | ( | std::vector< SDOperand > & | BVOps, | |
MVT::ValueType | EVT, | |||
SelectionDAG & | DAG | |||
) | const [virtual] |
isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented from llvm::TargetLowering.
Definition at line 3807 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), isCommutedMOVL(), isCommutedSHUFP(), isMOVLMask(), and isSHUFPMask().