LLVM API Documentation
00001 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the TwoAddress instruction pass which is used 00011 // by most register allocators. Two-Address instructions are rewritten 00012 // from: 00013 // 00014 // A = B op C 00015 // 00016 // to: 00017 // 00018 // A = B 00019 // A op= C 00020 // 00021 // Note that if a register allocator chooses to use this pass, that it 00022 // has to be capable of handling the non-SSA nature of these rewritten 00023 // virtual registers. 00024 // 00025 // It is also worth noting that the duplicate operand of the two 00026 // address instruction is removed. 00027 // 00028 //===----------------------------------------------------------------------===// 00029 00030 #define DEBUG_TYPE "twoaddrinstr" 00031 #include "llvm/CodeGen/Passes.h" 00032 #include "llvm/Function.h" 00033 #include "llvm/CodeGen/LiveVariables.h" 00034 #include "llvm/CodeGen/MachineFunctionPass.h" 00035 #include "llvm/CodeGen/MachineInstr.h" 00036 #include "llvm/CodeGen/SSARegMap.h" 00037 #include "llvm/Target/MRegisterInfo.h" 00038 #include "llvm/Target/TargetInstrInfo.h" 00039 #include "llvm/Target/TargetMachine.h" 00040 #include "llvm/Support/Debug.h" 00041 #include "llvm/Support/Visibility.h" 00042 #include "llvm/ADT/Statistic.h" 00043 #include "llvm/ADT/STLExtras.h" 00044 #include <iostream> 00045 using namespace llvm; 00046 00047 namespace { 00048 static Statistic<> NumTwoAddressInstrs("twoaddressinstruction", 00049 "Number of two-address instructions"); 00050 static Statistic<> NumCommuted("twoaddressinstruction", 00051 "Number of instructions commuted to coalesce"); 00052 static Statistic<> NumConvertedTo3Addr("twoaddressinstruction", 00053 "Number of instructions promoted to 3-address"); 00054 00055 struct VISIBILITY_HIDDEN TwoAddressInstructionPass 00056 : public MachineFunctionPass { 00057 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 00058 00059 /// runOnMachineFunction - pass entry point 00060 bool runOnMachineFunction(MachineFunction&); 00061 }; 00062 00063 RegisterPass<TwoAddressInstructionPass> 00064 X("twoaddressinstruction", "Two-Address instruction pass"); 00065 } 00066 00067 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo(); 00068 00069 void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const { 00070 AU.addRequired<LiveVariables>(); 00071 AU.addPreserved<LiveVariables>(); 00072 AU.addPreservedID(PHIEliminationID); 00073 MachineFunctionPass::getAnalysisUsage(AU); 00074 } 00075 00076 /// runOnMachineFunction - Reduce two-address instructions to two 00077 /// operands. 00078 /// 00079 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 00080 DEBUG(std::cerr << "Machine Function\n"); 00081 const TargetMachine &TM = MF.getTarget(); 00082 const MRegisterInfo &MRI = *TM.getRegisterInfo(); 00083 const TargetInstrInfo &TII = *TM.getInstrInfo(); 00084 LiveVariables &LV = getAnalysis<LiveVariables>(); 00085 00086 bool MadeChange = false; 00087 00088 DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n"); 00089 DEBUG(std::cerr << "********** Function: " 00090 << MF.getFunction()->getName() << '\n'); 00091 00092 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 00093 mbbi != mbbe; ++mbbi) { 00094 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 00095 mi != me; ++mi) { 00096 unsigned opcode = mi->getOpcode(); 00097 00098 // ignore if it is not a two-address instruction 00099 if (!TII.isTwoAddrInstr(opcode)) 00100 continue; 00101 00102 ++NumTwoAddressInstrs; 00103 DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM)); 00104 assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() && 00105 mi->getOperand(1).isUse() && "two address instruction invalid"); 00106 00107 // if the two operands are the same we just remove the use 00108 // and mark the def as def&use, otherwise we have to insert a copy. 00109 if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) { 00110 // rewrite: 00111 // a = b op c 00112 // to: 00113 // a = b 00114 // a = a op c 00115 unsigned regA = mi->getOperand(0).getReg(); 00116 unsigned regB = mi->getOperand(1).getReg(); 00117 00118 assert(MRegisterInfo::isVirtualRegister(regA) && 00119 MRegisterInfo::isVirtualRegister(regB) && 00120 "cannot update physical register live information"); 00121 00122 #ifndef NDEBUG 00123 // First, verify that we do not have a use of a in the instruction (a = 00124 // b + a for example) because our transformation will not work. This 00125 // should never occur because we are in SSA form. 00126 for (unsigned i = 1; i != mi->getNumOperands(); ++i) 00127 assert(!mi->getOperand(i).isRegister() || 00128 mi->getOperand(i).getReg() != regA); 00129 #endif 00130 00131 // If this instruction is not the killing user of B, see if we can 00132 // rearrange the code to make it so. Making it the killing user will 00133 // allow us to coalesce A and B together, eliminating the copy we are 00134 // about to insert. 00135 if (!LV.KillsRegister(mi, regB)) { 00136 const TargetInstrDescriptor &TID = TII.get(opcode); 00137 00138 // If this instruction is commutative, check to see if C dies. If so, 00139 // swap the B and C operands. This makes the live ranges of A and C 00140 // joinable. 00141 if (TID.Flags & M_COMMUTABLE) { 00142 assert(mi->getOperand(2).isRegister() && 00143 "Not a proper commutative instruction!"); 00144 unsigned regC = mi->getOperand(2).getReg(); 00145 if (LV.KillsRegister(mi, regC)) { 00146 DEBUG(std::cerr << "2addr: COMMUTING : " << *mi); 00147 MachineInstr *NewMI = TII.commuteInstruction(mi); 00148 if (NewMI == 0) { 00149 DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n"); 00150 } else { 00151 DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI); 00152 // If the instruction changed to commute it, update livevar. 00153 if (NewMI != mi) { 00154 LV.instructionChanged(mi, NewMI); // Update live variables 00155 mbbi->insert(mi, NewMI); // Insert the new inst 00156 mbbi->erase(mi); // Nuke the old inst. 00157 mi = NewMI; 00158 } 00159 00160 ++NumCommuted; 00161 regB = regC; 00162 goto InstructionRearranged; 00163 } 00164 } 00165 } 00166 // If this instruction is potentially convertible to a true 00167 // three-address instruction, 00168 if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR) 00169 if (MachineInstr *New = TII.convertToThreeAddress(mi)) { 00170 DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); 00171 DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New); 00172 LV.instructionChanged(mi, New); // Update live variables 00173 mbbi->insert(mi, New); // Insert the new inst 00174 mbbi->erase(mi); // Nuke the old inst. 00175 mi = New; 00176 ++NumConvertedTo3Addr; 00177 assert(!TII.isTwoAddrInstr(New->getOpcode()) && 00178 "convertToThreeAddress returned a 2-addr instruction??"); 00179 // Done with this instruction. 00180 continue; 00181 } 00182 } 00183 InstructionRearranged: 00184 const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); 00185 MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); 00186 00187 MachineBasicBlock::iterator prevMi = prior(mi); 00188 DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM)); 00189 00190 // Update live variables for regA 00191 LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA); 00192 varInfo.DefInst = prevMi; 00193 00194 // update live variables for regB 00195 if (LV.removeVirtualRegisterKilled(regB, mbbi, mi)) 00196 LV.addVirtualRegisterKilled(regB, prevMi); 00197 00198 if (LV.removeVirtualRegisterDead(regB, mbbi, mi)) 00199 LV.addVirtualRegisterDead(regB, prevMi); 00200 00201 // replace all occurences of regB with regA 00202 for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { 00203 if (mi->getOperand(i).isRegister() && 00204 mi->getOperand(i).getReg() == regB) 00205 mi->getOperand(i).setReg(regA); 00206 } 00207 } 00208 00209 assert(mi->getOperand(0).isDef()); 00210 mi->getOperand(0).setUse(); 00211 mi->RemoveOperand(1); 00212 MadeChange = true; 00213 00214 DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM)); 00215 } 00216 } 00217 00218 return MadeChange; 00219 }