LLVM API Documentation
00001 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by Duraid Madina and is distributed under the 00006 // University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the IA64 implementation of the MRegisterInfo class. This 00011 // file is responsible for the frame pointer elimination optimization on IA64. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #include "IA64.h" 00016 #include "IA64RegisterInfo.h" 00017 #include "IA64InstrBuilder.h" 00018 #include "IA64MachineFunctionInfo.h" 00019 #include "llvm/Constants.h" 00020 #include "llvm/Type.h" 00021 #include "llvm/CodeGen/ValueTypes.h" 00022 #include "llvm/CodeGen/MachineInstrBuilder.h" 00023 #include "llvm/CodeGen/MachineFunction.h" 00024 #include "llvm/CodeGen/MachineFrameInfo.h" 00025 #include "llvm/CodeGen/MachineLocation.h" 00026 #include "llvm/Target/TargetFrameInfo.h" 00027 #include "llvm/Target/TargetMachine.h" 00028 #include "llvm/Target/TargetOptions.h" 00029 #include "llvm/Support/CommandLine.h" 00030 #include "llvm/ADT/STLExtras.h" 00031 #include <iostream> 00032 using namespace llvm; 00033 00034 00035 IA64RegisterInfo::IA64RegisterInfo() 00036 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {} 00037 00038 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 00039 MachineBasicBlock::iterator MI, 00040 unsigned SrcReg, int FrameIdx, 00041 const TargetRegisterClass *RC) const{ 00042 00043 if (RC == IA64::FPRegisterClass) { 00044 BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg); 00045 } else if (RC == IA64::GRRegisterClass) { 00046 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg); 00047 } 00048 else if (RC == IA64::PRRegisterClass) { 00049 /* we use IA64::r2 as a temporary register for doing this hackery. */ 00050 // first we load 0: 00051 BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0); 00052 // then conditionally add 1: 00053 BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2) 00054 .addImm(1).addReg(SrcReg); 00055 // and then store it to the stack 00056 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2); 00057 } else assert(0 && 00058 "sorry, I don't know how to store this sort of reg in the stack\n"); 00059 } 00060 00061 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 00062 MachineBasicBlock::iterator MI, 00063 unsigned DestReg, int FrameIdx, 00064 const TargetRegisterClass *RC)const{ 00065 00066 if (RC == IA64::FPRegisterClass) { 00067 BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx); 00068 } else if (RC == IA64::GRRegisterClass) { 00069 BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx); 00070 } else if (RC == IA64::PRRegisterClass) { 00071 // first we load a byte from the stack into r2, our 'predicate hackery' 00072 // scratch reg 00073 BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx); 00074 // then we compare it to zero. If it _is_ zero, compare-not-equal to 00075 // r0 gives us 0, which is what we want, so that's nice. 00076 BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0); 00077 } else assert(0 && 00078 "sorry, I don't know how to load this sort of reg from the stack\n"); 00079 } 00080 00081 void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 00082 MachineBasicBlock::iterator MI, 00083 unsigned DestReg, unsigned SrcReg, 00084 const TargetRegisterClass *RC) const { 00085 00086 if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode 00087 // (SrcReg) DestReg = cmp.eq.unc(r0, r0) 00088 BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); 00089 else // otherwise, MOV works (for both gen. regs and FP regs) 00090 BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg); 00091 } 00092 00093 const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const { 00094 static const unsigned CalleeSaveRegs[] = { 00095 IA64::r5, 0 00096 }; 00097 return CalleeSaveRegs; 00098 } 00099 00100 const TargetRegisterClass* const* 00101 IA64RegisterInfo::getCalleeSaveRegClasses() const { 00102 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 00103 &IA64::GRRegClass, 0 00104 }; 00105 return CalleeSaveRegClasses; 00106 } 00107 00108 //===----------------------------------------------------------------------===// 00109 // Stack Frame Processing methods 00110 //===----------------------------------------------------------------------===// 00111 00112 // hasFP - Return true if the specified function should have a dedicated frame 00113 // pointer register. This is true if the function has variable sized allocas or 00114 // if frame pointer elimination is disabled. 00115 // 00116 static bool hasFP(MachineFunction &MF) { 00117 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 00118 } 00119 00120 void IA64RegisterInfo:: 00121 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 00122 MachineBasicBlock::iterator I) const { 00123 00124 if (hasFP(MF)) { 00125 // If we have a frame pointer, turn the adjcallstackup instruction into a 00126 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP, 00127 // <amt>' 00128 MachineInstr *Old = I; 00129 unsigned Amount = Old->getOperand(0).getImmedValue(); 00130 if (Amount != 0) { 00131 // We need to keep the stack aligned properly. To do this, we round the 00132 // amount of space needed for the outgoing arguments up to the next 00133 // alignment boundary. 00134 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 00135 Amount = (Amount+Align-1)/Align*Align; 00136 00137 MachineInstr *New; 00138 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { 00139 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12) 00140 .addImm(-Amount); 00141 } else { 00142 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); 00143 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12) 00144 .addImm(Amount); 00145 } 00146 00147 // Replace the pseudo instruction with a new instruction... 00148 MBB.insert(I, New); 00149 } 00150 } 00151 00152 MBB.erase(I); 00153 } 00154 00155 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ 00156 unsigned i = 0; 00157 MachineInstr &MI = *II; 00158 MachineBasicBlock &MBB = *MI.getParent(); 00159 MachineFunction &MF = *MBB.getParent(); 00160 00161 bool FP = hasFP(MF); 00162 00163 while (!MI.getOperand(i).isFrameIndex()) { 00164 ++i; 00165 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 00166 } 00167 00168 int FrameIndex = MI.getOperand(i).getFrameIndex(); 00169 00170 // choose a base register: ( hasFP? framepointer : stack pointer ) 00171 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; 00172 // Add the base register 00173 MI.getOperand(i).ChangeToRegister(BaseRegister); 00174 00175 // Now add the frame object offset to the offset from r1. 00176 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 00177 00178 // If we're not using a Frame Pointer that has been set to the value of the 00179 // SP before having the stack size subtracted from it, then add the stack size 00180 // to Offset to get the correct offset. 00181 Offset += MF.getFrameInfo()->getStackSize(); 00182 00183 // XXX: we use 'r22' as another hack+slash temporary register here :( 00184 if ( Offset <= 8191 && Offset >= -8192) { // smallish offset 00185 //fix up the old: 00186 MI.getOperand(i).ChangeToRegister(IA64::r22); 00187 MI.getOperand(i).setUse(); // mark r22 as being used 00188 // (the bundler wants to know this) 00189 //insert the new 00190 MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22) 00191 .addReg(BaseRegister).addImm(Offset); 00192 MBB.insert(II, nMI); 00193 } else { // it's big 00194 //fix up the old: 00195 MI.getOperand(i).ChangeToRegister(IA64::r22); 00196 MI.getOperand(i).setUse(); // mark r22 as being used 00197 // (the bundler wants to know this) 00198 MachineInstr* nMI; 00199 nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset); 00200 MBB.insert(II, nMI); 00201 nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister) 00202 .addReg(IA64::r22); 00203 MBB.insert(II, nMI); 00204 } 00205 00206 } 00207 00208 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { 00209 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 00210 MachineBasicBlock::iterator MBBI = MBB.begin(); 00211 MachineFrameInfo *MFI = MF.getFrameInfo(); 00212 MachineInstr *MI; 00213 bool FP = hasFP(MF); 00214 00215 // first, we handle the 'alloc' instruction, that should be right up the 00216 // top of any function 00217 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the 00218 // RSE worries about 00219 IA64::r32, IA64::r33, IA64::r34, IA64::r35, 00220 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41, 00221 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47, 00222 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53, 00223 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59, 00224 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65, 00225 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71, 00226 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77, 00227 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83, 00228 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89, 00229 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95, 00230 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101, 00231 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107, 00232 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113, 00233 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119, 00234 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125, 00235 IA64::r126, IA64::r127 }; 00236 00237 unsigned numStackedGPRsUsed=0; 00238 for(int i=0; i<96; i++) { 00239 if(MF.isPhysRegUsed(RegsInOrder[i])) 00240 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int) 00241 } 00242 00243 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; 00244 00245 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB) 00246 unsigned dstRegOfPseudoAlloc; 00247 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) { 00248 assert(MBBI != MBB.end()); 00249 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) { 00250 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg(); 00251 break; 00252 } 00253 } 00254 00255 MI=BuildMI(IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0).\ 00256 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0); 00257 MBB.insert(MBBI, MI); 00258 00259 // Get the number of bytes to allocate from the FrameInfo 00260 unsigned NumBytes = MFI->getStackSize(); 00261 00262 if (MFI->hasCalls() && !FP) { 00263 // We reserve argument space for call sites in the function immediately on 00264 // entry to the current function. This eliminates the need for add/sub 00265 // brackets around call sites. 00266 NumBytes += MFI->getMaxCallFrameSize(); 00267 } 00268 00269 if(FP) 00270 NumBytes += 8; // reserve space for the old FP 00271 00272 // Do we need to allocate space on the stack? 00273 if (NumBytes == 0) 00274 return; 00275 00276 // Add 16 bytes at the bottom of the stack (scratch area) 00277 // and round the size to a multiple of the alignment. 00278 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 00279 unsigned Size = 16 + (FP ? 8 : 0); 00280 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 00281 00282 // Update frame info to pretend that this is part of the stack... 00283 MFI->setStackSize(NumBytes); 00284 00285 // adjust stack pointer: r12 -= numbytes 00286 if (NumBytes <= 8191) { 00287 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes); 00288 MBB.insert(MBBI, MI); 00289 } else { // we use r22 as a scratch register here 00290 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes); 00291 // FIXME: MOVLSI32 expects a _u_32imm 00292 MBB.insert(MBBI, MI); // first load the decrement into r22 00293 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22); 00294 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr) 00295 } 00296 00297 // now if we need to, save the old FP and set the new 00298 if (FP) { 00299 MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5); 00300 MBB.insert(MBBI, MI); 00301 // this must be the last instr in the prolog ? (XXX: why??) 00302 MI = BuildMI(IA64::MOV, 1, IA64::r5).addReg(IA64::r12); 00303 MBB.insert(MBBI, MI); 00304 } 00305 00306 } 00307 00308 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, 00309 MachineBasicBlock &MBB) const { 00310 const MachineFrameInfo *MFI = MF.getFrameInfo(); 00311 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 00312 MachineInstr *MI; 00313 assert(MBBI->getOpcode() == IA64::RET && 00314 "Can only insert epilog into returning blocks"); 00315 00316 bool FP = hasFP(MF); 00317 00318 // Get the number of bytes allocated from the FrameInfo... 00319 unsigned NumBytes = MFI->getStackSize(); 00320 00321 //now if we need to, restore the old FP 00322 if (FP) 00323 { 00324 //copy the FP into the SP (discards allocas) 00325 MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r5); 00326 MBB.insert(MBBI, MI); 00327 //restore the FP 00328 MI=BuildMI(IA64::LD8, 1, IA64::r5).addReg(IA64::r5); 00329 MBB.insert(MBBI, MI); 00330 } 00331 00332 if (NumBytes != 0) 00333 { 00334 if (NumBytes <= 8191) { 00335 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes); 00336 MBB.insert(MBBI, MI); 00337 } else { 00338 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes); 00339 MBB.insert(MBBI, MI); 00340 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22); 00341 MBB.insert(MBBI, MI); 00342 } 00343 } 00344 00345 } 00346 00347 unsigned IA64RegisterInfo::getRARegister() const { 00348 assert(0 && "What is the return address register"); 00349 return 0; 00350 } 00351 00352 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const { 00353 return hasFP(MF) ? IA64::r5 : IA64::r12; 00354 } 00355 00356 #include "IA64GenRegisterInfo.inc" 00357