LLVM API Documentation

X86FloatingPoint.cpp

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00001 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the pass which converts floating point instructions from
00011 // virtual registers into register stack instructions.  This pass uses live
00012 // variable information to indicate where the FPn registers are used and their
00013 // lifetimes.
00014 //
00015 // This pass is hampered by the lack of decent CFG manipulation routines for
00016 // machine code.  In particular, this wants to be able to split critical edges
00017 // as necessary, traverse the machine basic block CFG in depth-first order, and
00018 // allow there to be multiple machine basic blocks for each LLVM basicblock
00019 // (needed for critical edge splitting).
00020 //
00021 // In particular, this pass currently barfs on critical edges.  Because of this,
00022 // it requires the instruction selector to insert FP_REG_KILL instructions on
00023 // the exits of any basic block that has critical edges going from it, or which
00024 // branch to a critical basic block.
00025 //
00026 // FIXME: this is not implemented yet.  The stackifier pass only works on local
00027 // basic blocks.
00028 //
00029 //===----------------------------------------------------------------------===//
00030 
00031 #define DEBUG_TYPE "fp"
00032 #include "X86.h"
00033 #include "X86InstrInfo.h"
00034 #include "llvm/CodeGen/MachineFunctionPass.h"
00035 #include "llvm/CodeGen/MachineInstrBuilder.h"
00036 #include "llvm/CodeGen/LiveVariables.h"
00037 #include "llvm/CodeGen/Passes.h"
00038 #include "llvm/Target/TargetInstrInfo.h"
00039 #include "llvm/Target/TargetMachine.h"
00040 #include "llvm/Support/Debug.h"
00041 #include "llvm/Support/Visibility.h"
00042 #include "llvm/ADT/DepthFirstIterator.h"
00043 #include "llvm/ADT/Statistic.h"
00044 #include "llvm/ADT/STLExtras.h"
00045 #include <algorithm>
00046 #include <iostream>
00047 #include <set>
00048 using namespace llvm;
00049 
00050 namespace {
00051   Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
00052   Statistic<> NumFP  ("x86-codegen", "Number of floating point instructions");
00053 
00054   struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
00055     virtual bool runOnMachineFunction(MachineFunction &MF);
00056 
00057     virtual const char *getPassName() const { return "X86 FP Stackifier"; }
00058 
00059     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
00060       AU.addRequired<LiveVariables>();
00061       MachineFunctionPass::getAnalysisUsage(AU);
00062     }
00063   private:
00064     LiveVariables     *LV;    // Live variable info for current function...
00065     MachineBasicBlock *MBB;   // Current basic block
00066     unsigned Stack[8];        // FP<n> Registers in each stack slot...
00067     unsigned RegMap[8];       // Track which stack slot contains each register
00068     unsigned StackTop;        // The current top of the FP stack.
00069 
00070     void dumpStack() const {
00071       std::cerr << "Stack contents:";
00072       for (unsigned i = 0; i != StackTop; ++i) {
00073         std::cerr << " FP" << Stack[i];
00074         assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
00075       }
00076       std::cerr << "\n";
00077     }
00078   private:
00079     // getSlot - Return the stack slot number a particular register number is
00080     // in...
00081     unsigned getSlot(unsigned RegNo) const {
00082       assert(RegNo < 8 && "Regno out of range!");
00083       return RegMap[RegNo];
00084     }
00085 
00086     // getStackEntry - Return the X86::FP<n> register in register ST(i)
00087     unsigned getStackEntry(unsigned STi) const {
00088       assert(STi < StackTop && "Access past stack top!");
00089       return Stack[StackTop-1-STi];
00090     }
00091 
00092     // getSTReg - Return the X86::ST(i) register which contains the specified
00093     // FP<RegNo> register
00094     unsigned getSTReg(unsigned RegNo) const {
00095       return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
00096     }
00097 
00098     // pushReg - Push the specified FP<n> register onto the stack
00099     void pushReg(unsigned Reg) {
00100       assert(Reg < 8 && "Register number out of range!");
00101       assert(StackTop < 8 && "Stack overflow!");
00102       Stack[StackTop] = Reg;
00103       RegMap[Reg] = StackTop++;
00104     }
00105 
00106     bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
00107     void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
00108       if (!isAtTop(RegNo)) {
00109         unsigned Slot = getSlot(RegNo);
00110         unsigned STReg = getSTReg(RegNo);
00111         unsigned RegOnTop = getStackEntry(0);
00112 
00113         // Swap the slots the regs are in
00114         std::swap(RegMap[RegNo], RegMap[RegOnTop]);
00115 
00116         // Swap stack slot contents
00117         assert(RegMap[RegOnTop] < StackTop);
00118         std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
00119 
00120         // Emit an fxch to update the runtime processors version of the state
00121         BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
00122         NumFXCH++;
00123       }
00124     }
00125 
00126     void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
00127       unsigned STReg = getSTReg(RegNo);
00128       pushReg(AsReg);   // New register on top of stack
00129 
00130       BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
00131     }
00132 
00133     // popStackAfter - Pop the current value off of the top of the FP stack
00134     // after the specified instruction.
00135     void popStackAfter(MachineBasicBlock::iterator &I);
00136 
00137     // freeStackSlotAfter - Free the specified register from the register stack,
00138     // so that it is no longer in a register.  If the register is currently at
00139     // the top of the stack, we just pop the current instruction, otherwise we
00140     // store the current top-of-stack into the specified slot, then pop the top
00141     // of stack.
00142     void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
00143 
00144     bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
00145 
00146     void handleZeroArgFP(MachineBasicBlock::iterator &I);
00147     void handleOneArgFP(MachineBasicBlock::iterator &I);
00148     void handleOneArgFPRW(MachineBasicBlock::iterator &I);
00149     void handleTwoArgFP(MachineBasicBlock::iterator &I);
00150     void handleCompareFP(MachineBasicBlock::iterator &I);
00151     void handleCondMovFP(MachineBasicBlock::iterator &I);
00152     void handleSpecialFP(MachineBasicBlock::iterator &I);
00153   };
00154 }
00155 
00156 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
00157 
00158 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
00159 /// register references into FP stack references.
00160 ///
00161 bool FPS::runOnMachineFunction(MachineFunction &MF) {
00162   // We only need to run this pass if there are any FP registers used in this
00163   // function.  If it is all integer, there is nothing for us to do!
00164   const bool *PhysRegsUsed = MF.getUsedPhysregs();
00165   bool FPIsUsed = false;
00166 
00167   assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
00168   for (unsigned i = 0; i <= 6; ++i)
00169     if (PhysRegsUsed[X86::FP0+i]) {
00170       FPIsUsed = true;
00171       break;
00172     }
00173 
00174   // Early exit.
00175   if (!FPIsUsed) return false;
00176 
00177   LV = &getAnalysis<LiveVariables>();
00178   StackTop = 0;
00179 
00180   // Process the function in depth first order so that we process at least one
00181   // of the predecessors for every reachable block in the function.
00182   std::set<MachineBasicBlock*> Processed;
00183   MachineBasicBlock *Entry = MF.begin();
00184 
00185   bool Changed = false;
00186   for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
00187          I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
00188        I != E; ++I)
00189     Changed |= processBasicBlock(MF, **I);
00190 
00191   return Changed;
00192 }
00193 
00194 /// processBasicBlock - Loop over all of the instructions in the basic block,
00195 /// transforming FP instructions into their stack form.
00196 ///
00197 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
00198   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
00199   bool Changed = false;
00200   MBB = &BB;
00201 
00202   for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
00203     MachineInstr *MI = I;
00204     unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
00205     if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
00206       continue;  // Efficiently ignore non-fp insts!
00207 
00208     MachineInstr *PrevMI = 0;
00209     if (I != BB.begin())
00210         PrevMI = prior(I);
00211 
00212     ++NumFP;  // Keep track of # of pseudo instrs
00213     DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget())));
00214 
00215     // Get dead variables list now because the MI pointer may be deleted as part
00216     // of processing!
00217     LiveVariables::killed_iterator IB, IE;
00218     tie(IB, IE) = LV->dead_range(MI);
00219 
00220     DEBUG(
00221       const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
00222       LiveVariables::killed_iterator I = LV->killed_begin(MI);
00223       LiveVariables::killed_iterator E = LV->killed_end(MI);
00224       if (I != E) {
00225         std::cerr << "Killed Operands:";
00226         for (; I != E; ++I)
00227           std::cerr << " %" << MRI->getName(*I);
00228         std::cerr << "\n";
00229       }
00230     );
00231 
00232     switch (Flags & X86II::FPTypeMask) {
00233     case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
00234     case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
00235     case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
00236     case X86II::TwoArgFP:   handleTwoArgFP(I); break;
00237     case X86II::CompareFP:  handleCompareFP(I); break;
00238     case X86II::CondMovFP:  handleCondMovFP(I); break;
00239     case X86II::SpecialFP:  handleSpecialFP(I); break;
00240     default: assert(0 && "Unknown FP Type!");
00241     }
00242 
00243     // Check to see if any of the values defined by this instruction are dead
00244     // after definition.  If so, pop them.
00245     for (; IB != IE; ++IB) {
00246       unsigned Reg = *IB;
00247       if (Reg >= X86::FP0 && Reg <= X86::FP6) {
00248         DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
00249         freeStackSlotAfter(I, Reg-X86::FP0);
00250       }
00251     }
00252 
00253     // Print out all of the instructions expanded to if -debug
00254     DEBUG(
00255       MachineBasicBlock::iterator PrevI(PrevMI);
00256       if (I == PrevI) {
00257         std::cerr << "Just deleted pseudo instruction\n";
00258       } else {
00259         MachineBasicBlock::iterator Start = I;
00260         // Rewind to first instruction newly inserted.
00261         while (Start != BB.begin() && prior(Start) != PrevI) --Start;
00262         std::cerr << "Inserted instructions:\n\t";
00263         Start->print(std::cerr, &MF.getTarget());
00264         while (++Start != next(I));
00265       }
00266       dumpStack();
00267     );
00268 
00269     Changed = true;
00270   }
00271 
00272   assert(StackTop == 0 && "Stack not empty at end of basic block?");
00273   return Changed;
00274 }
00275 
00276 //===----------------------------------------------------------------------===//
00277 // Efficient Lookup Table Support
00278 //===----------------------------------------------------------------------===//
00279 
00280 namespace {
00281   struct TableEntry {
00282     unsigned from;
00283     unsigned to;
00284     bool operator<(const TableEntry &TE) const { return from < TE.from; }
00285     friend bool operator<(const TableEntry &TE, unsigned V) {
00286       return TE.from < V;
00287     }
00288     friend bool operator<(unsigned V, const TableEntry &TE) {
00289       return V < TE.from;
00290     }
00291   };
00292 }
00293 
00294 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
00295   for (unsigned i = 0; i != NumEntries-1; ++i)
00296     if (!(Table[i] < Table[i+1])) return false;
00297   return true;
00298 }
00299 
00300 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
00301   const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
00302   if (I != Table+N && I->from == Opcode)
00303     return I->to;
00304   return -1;
00305 }
00306 
00307 #define ARRAY_SIZE(TABLE)  \
00308    (sizeof(TABLE)/sizeof(TABLE[0]))
00309 
00310 #ifdef NDEBUG
00311 #define ASSERT_SORTED(TABLE)
00312 #else
00313 #define ASSERT_SORTED(TABLE)                                              \
00314   { static bool TABLE##Checked = false;                                   \
00315     if (!TABLE##Checked) {                                                \
00316        assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) &&                  \
00317               "All lookup tables must be sorted for efficient access!");  \
00318        TABLE##Checked = true;                                             \
00319     }                                                                     \
00320   }
00321 #endif
00322 
00323 //===----------------------------------------------------------------------===//
00324 // Register File -> Register Stack Mapping Methods
00325 //===----------------------------------------------------------------------===//
00326 
00327 // OpcodeTable - Sorted map of register instructions to their stack version.
00328 // The first element is an register file pseudo instruction, the second is the
00329 // concrete X86 instruction which uses the register stack.
00330 //
00331 static const TableEntry OpcodeTable[] = {
00332   { X86::FpABS     , X86::FABS     },
00333   { X86::FpADD32m  , X86::FADD32m  },
00334   { X86::FpADD64m  , X86::FADD64m  },
00335   { X86::FpCHS     , X86::FCHS     },
00336   { X86::FpCMOVB   , X86::FCMOVB   },
00337   { X86::FpCMOVBE  , X86::FCMOVBE  },
00338   { X86::FpCMOVE   , X86::FCMOVE   },
00339   { X86::FpCMOVNB  , X86::FCMOVNB  },
00340   { X86::FpCMOVNBE , X86::FCMOVNBE },
00341   { X86::FpCMOVNE  , X86::FCMOVNE  },
00342   { X86::FpCMOVNP  , X86::FCMOVNP  },
00343   { X86::FpCMOVP   , X86::FCMOVP   },
00344   { X86::FpCOS     , X86::FCOS     },
00345   { X86::FpDIV32m  , X86::FDIV32m  },
00346   { X86::FpDIV64m  , X86::FDIV64m  },
00347   { X86::FpDIVR32m , X86::FDIVR32m },
00348   { X86::FpDIVR64m , X86::FDIVR64m },
00349   { X86::FpIADD16m , X86::FIADD16m },
00350   { X86::FpIADD32m , X86::FIADD32m },
00351   { X86::FpIDIV16m , X86::FIDIV16m },
00352   { X86::FpIDIV32m , X86::FIDIV32m },
00353   { X86::FpIDIVR16m, X86::FIDIVR16m},
00354   { X86::FpIDIVR32m, X86::FIDIVR32m},
00355   { X86::FpILD16m  , X86::FILD16m  },
00356   { X86::FpILD32m  , X86::FILD32m  },
00357   { X86::FpILD64m  , X86::FILD64m  },
00358   { X86::FpIMUL16m , X86::FIMUL16m },
00359   { X86::FpIMUL32m , X86::FIMUL32m },
00360   { X86::FpIST16m  , X86::FIST16m  },
00361   { X86::FpIST32m  , X86::FIST32m  },
00362   { X86::FpIST64m  , X86::FISTP64m },
00363   { X86::FpISTT16m , X86::FISTTP16m},
00364   { X86::FpISTT32m , X86::FISTTP32m},
00365   { X86::FpISTT64m , X86::FISTTP64m},
00366   { X86::FpISUB16m , X86::FISUB16m },
00367   { X86::FpISUB32m , X86::FISUB32m },
00368   { X86::FpISUBR16m, X86::FISUBR16m},
00369   { X86::FpISUBR32m, X86::FISUBR32m},
00370   { X86::FpLD0     , X86::FLD0     },
00371   { X86::FpLD1     , X86::FLD1     },
00372   { X86::FpLD32m   , X86::FLD32m   },
00373   { X86::FpLD64m   , X86::FLD64m   },
00374   { X86::FpMUL32m  , X86::FMUL32m  },
00375   { X86::FpMUL64m  , X86::FMUL64m  },
00376   { X86::FpSIN     , X86::FSIN     },
00377   { X86::FpSQRT    , X86::FSQRT    },
00378   { X86::FpST32m   , X86::FST32m   },
00379   { X86::FpST64m   , X86::FST64m   },
00380   { X86::FpSUB32m  , X86::FSUB32m  },
00381   { X86::FpSUB64m  , X86::FSUB64m  },
00382   { X86::FpSUBR32m , X86::FSUBR32m },
00383   { X86::FpSUBR64m , X86::FSUBR64m },
00384   { X86::FpTST     , X86::FTST     },
00385   { X86::FpUCOMIr  , X86::FUCOMIr  },
00386   { X86::FpUCOMr   , X86::FUCOMr   },
00387 };
00388 
00389 static unsigned getConcreteOpcode(unsigned Opcode) {
00390   ASSERT_SORTED(OpcodeTable);
00391   int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode);
00392   assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
00393   return Opc;
00394 }
00395 
00396 //===----------------------------------------------------------------------===//
00397 // Helper Methods
00398 //===----------------------------------------------------------------------===//
00399 
00400 // PopTable - Sorted map of instructions to their popping version.  The first
00401 // element is an instruction, the second is the version which pops.
00402 //
00403 static const TableEntry PopTable[] = {
00404   { X86::FADDrST0 , X86::FADDPrST0  },
00405 
00406   { X86::FDIVRrST0, X86::FDIVRPrST0 },
00407   { X86::FDIVrST0 , X86::FDIVPrST0  },
00408 
00409   { X86::FIST16m  , X86::FISTP16m   },
00410   { X86::FIST32m  , X86::FISTP32m   },
00411 
00412   { X86::FMULrST0 , X86::FMULPrST0  },
00413 
00414   { X86::FST32m   , X86::FSTP32m    },
00415   { X86::FST64m   , X86::FSTP64m    },
00416   { X86::FSTrr    , X86::FSTPrr     },
00417 
00418   { X86::FSUBRrST0, X86::FSUBRPrST0 },
00419   { X86::FSUBrST0 , X86::FSUBPrST0  },
00420 
00421   { X86::FUCOMIr  , X86::FUCOMIPr   },
00422 
00423   { X86::FUCOMPr  , X86::FUCOMPPr   },
00424   { X86::FUCOMr   , X86::FUCOMPr    },
00425 };
00426 
00427 /// popStackAfter - Pop the current value off of the top of the FP stack after
00428 /// the specified instruction.  This attempts to be sneaky and combine the pop
00429 /// into the instruction itself if possible.  The iterator is left pointing to
00430 /// the last instruction, be it a new pop instruction inserted, or the old
00431 /// instruction if it was modified in place.
00432 ///
00433 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
00434   ASSERT_SORTED(PopTable);
00435   assert(StackTop > 0 && "Cannot pop empty stack!");
00436   RegMap[Stack[--StackTop]] = ~0;     // Update state
00437 
00438   // Check to see if there is a popping version of this instruction...
00439   int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
00440   if (Opcode != -1) {
00441     I->setOpcode(Opcode);
00442     if (Opcode == X86::FUCOMPPr)
00443       I->RemoveOperand(0);
00444 
00445   } else {    // Insert an explicit pop
00446     I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
00447   }
00448 }
00449 
00450 /// freeStackSlotAfter - Free the specified register from the register stack, so
00451 /// that it is no longer in a register.  If the register is currently at the top
00452 /// of the stack, we just pop the current instruction, otherwise we store the
00453 /// current top-of-stack into the specified slot, then pop the top of stack.
00454 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
00455   if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
00456     popStackAfter(I);
00457     return;
00458   }
00459 
00460   // Otherwise, store the top of stack into the dead slot, killing the operand
00461   // without having to add in an explicit xchg then pop.
00462   //
00463   unsigned STReg    = getSTReg(FPRegNo);
00464   unsigned OldSlot  = getSlot(FPRegNo);
00465   unsigned TopReg   = Stack[StackTop-1];
00466   Stack[OldSlot]    = TopReg;
00467   RegMap[TopReg]    = OldSlot;
00468   RegMap[FPRegNo]   = ~0;
00469   Stack[--StackTop] = ~0;
00470   I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
00471 }
00472 
00473 
00474 static unsigned getFPReg(const MachineOperand &MO) {
00475   assert(MO.isRegister() && "Expected an FP register!");
00476   unsigned Reg = MO.getReg();
00477   assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
00478   return Reg - X86::FP0;
00479 }
00480 
00481 
00482 //===----------------------------------------------------------------------===//
00483 // Instruction transformation implementation
00484 //===----------------------------------------------------------------------===//
00485 
00486 /// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
00487 ///
00488 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
00489   MachineInstr *MI = I;
00490   unsigned DestReg = getFPReg(MI->getOperand(0));
00491 
00492   // Change from the pseudo instruction to the concrete instruction.
00493   MI->RemoveOperand(0);   // Remove the explicit ST(0) operand
00494   MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
00495   
00496   // Result gets pushed on the stack.
00497   pushReg(DestReg);
00498 }
00499 
00500 /// handleOneArgFP - fst <mem>, ST(0)
00501 ///
00502 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
00503   MachineInstr *MI = I;
00504   assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
00505          "Can only handle fst* & ftst instructions!");
00506 
00507   // Is this the last use of the source register?
00508   unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
00509   bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
00510 
00511   // FISTP64m is strange because there isn't a non-popping versions.
00512   // If we have one _and_ we don't want to pop the operand, duplicate the value
00513   // on the stack instead of moving it.  This ensure that popping the value is
00514   // always ok.
00515   // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
00516   //
00517   if (!KillsSrc &&
00518       (MI->getOpcode() == X86::FpIST64m ||
00519        MI->getOpcode() == X86::FpISTT16m ||
00520        MI->getOpcode() == X86::FpISTT32m ||
00521        MI->getOpcode() == X86::FpISTT64m)) {
00522     duplicateToTop(Reg, 7 /*temp register*/, I);
00523   } else {
00524     moveToTop(Reg, I);            // Move to the top of the stack...
00525   }
00526   
00527   // Convert from the pseudo instruction to the concrete instruction.
00528   MI->RemoveOperand(MI->getNumOperands()-1);    // Remove explicit ST(0) operand
00529   MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
00530 
00531   if (MI->getOpcode() == X86::FISTP64m ||
00532       MI->getOpcode() == X86::FISTTP16m ||
00533       MI->getOpcode() == X86::FISTTP32m ||
00534       MI->getOpcode() == X86::FISTTP64m) {
00535     assert(StackTop > 0 && "Stack empty??");
00536     --StackTop;
00537   } else if (KillsSrc) { // Last use of operand?
00538     popStackAfter(I);
00539   }
00540 }
00541 
00542 
00543 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
00544 /// replace the value with a newly computed value.  These instructions may have
00545 /// non-fp operands after their FP operands.
00546 ///
00547 ///  Examples:
00548 ///     R1 = fchs R2
00549 ///     R1 = fadd R2, [mem]
00550 ///
00551 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
00552   MachineInstr *MI = I;
00553   assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!");
00554 
00555   // Is this the last use of the source register?
00556   unsigned Reg = getFPReg(MI->getOperand(1));
00557   bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
00558 
00559   if (KillsSrc) {
00560     // If this is the last use of the source register, just make sure it's on
00561     // the top of the stack.
00562     moveToTop(Reg, I);
00563     assert(StackTop > 0 && "Stack cannot be empty!");
00564     --StackTop;
00565     pushReg(getFPReg(MI->getOperand(0)));
00566   } else {
00567     // If this is not the last use of the source register, _copy_ it to the top
00568     // of the stack.
00569     duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
00570   }
00571 
00572   // Change from the pseudo instruction to the concrete instruction.
00573   MI->RemoveOperand(1);   // Drop the source operand.
00574   MI->RemoveOperand(0);   // Drop the destination operand.
00575   MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
00576 }
00577 
00578 
00579 //===----------------------------------------------------------------------===//
00580 // Define tables of various ways to map pseudo instructions
00581 //
00582 
00583 // ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
00584 static const TableEntry ForwardST0Table[] = {
00585   { X86::FpADD  , X86::FADDST0r },
00586   { X86::FpDIV  , X86::FDIVST0r },
00587   { X86::FpMUL  , X86::FMULST0r },
00588   { X86::FpSUB  , X86::FSUBST0r },
00589 };
00590 
00591 // ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
00592 static const TableEntry ReverseST0Table[] = {
00593   { X86::FpADD  , X86::FADDST0r  },   // commutative
00594   { X86::FpDIV  , X86::FDIVRST0r },
00595   { X86::FpMUL  , X86::FMULST0r  },   // commutative
00596   { X86::FpSUB  , X86::FSUBRST0r },
00597 };
00598 
00599 // ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
00600 static const TableEntry ForwardSTiTable[] = {
00601   { X86::FpADD  , X86::FADDrST0  },   // commutative
00602   { X86::FpDIV  , X86::FDIVRrST0 },
00603   { X86::FpMUL  , X86::FMULrST0  },   // commutative
00604   { X86::FpSUB  , X86::FSUBRrST0 },
00605 };
00606 
00607 // ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
00608 static const TableEntry ReverseSTiTable[] = {
00609   { X86::FpADD  , X86::FADDrST0 },
00610   { X86::FpDIV  , X86::FDIVrST0 },
00611   { X86::FpMUL  , X86::FMULrST0 },
00612   { X86::FpSUB  , X86::FSUBrST0 },
00613 };
00614 
00615 
00616 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
00617 /// instructions which need to be simplified and possibly transformed.
00618 ///
00619 /// Result: ST(0) = fsub  ST(0), ST(i)
00620 ///         ST(i) = fsub  ST(0), ST(i)
00621 ///         ST(0) = fsubr ST(0), ST(i)
00622 ///         ST(i) = fsubr ST(0), ST(i)
00623 ///
00624 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
00625   ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
00626   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
00627   MachineInstr *MI = I;
00628 
00629   unsigned NumOperands = MI->getNumOperands();
00630   assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
00631   unsigned Dest = getFPReg(MI->getOperand(0));
00632   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
00633   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
00634   bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
00635   bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
00636 
00637   unsigned TOS = getStackEntry(0);
00638 
00639   // One of our operands must be on the top of the stack.  If neither is yet, we
00640   // need to move one.
00641   if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
00642     // We can choose to move either operand to the top of the stack.  If one of
00643     // the operands is killed by this instruction, we want that one so that we
00644     // can update right on top of the old version.
00645     if (KillsOp0) {
00646       moveToTop(Op0, I);         // Move dead operand to TOS.
00647       TOS = Op0;
00648     } else if (KillsOp1) {
00649       moveToTop(Op1, I);
00650       TOS = Op1;
00651     } else {
00652       // All of the operands are live after this instruction executes, so we
00653       // cannot update on top of any operand.  Because of this, we must
00654       // duplicate one of the stack elements to the top.  It doesn't matter
00655       // which one we pick.
00656       //
00657       duplicateToTop(Op0, Dest, I);
00658       Op0 = TOS = Dest;
00659       KillsOp0 = true;
00660     }
00661   } else if (!KillsOp0 && !KillsOp1) {
00662     // If we DO have one of our operands at the top of the stack, but we don't
00663     // have a dead operand, we must duplicate one of the operands to a new slot
00664     // on the stack.
00665     duplicateToTop(Op0, Dest, I);
00666     Op0 = TOS = Dest;
00667     KillsOp0 = true;
00668   }
00669 
00670   // Now we know that one of our operands is on the top of the stack, and at
00671   // least one of our operands is killed by this instruction.
00672   assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
00673          "Stack conditions not set up right!");
00674 
00675   // We decide which form to use based on what is on the top of the stack, and
00676   // which operand is killed by this instruction.
00677   const TableEntry *InstTable;
00678   bool isForward = TOS == Op0;
00679   bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
00680   if (updateST0) {
00681     if (isForward)
00682       InstTable = ForwardST0Table;
00683     else
00684       InstTable = ReverseST0Table;
00685   } else {
00686     if (isForward)
00687       InstTable = ForwardSTiTable;
00688     else
00689       InstTable = ReverseSTiTable;
00690   }
00691 
00692   int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
00693   assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
00694 
00695   // NotTOS - The register which is not on the top of stack...
00696   unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
00697 
00698   // Replace the old instruction with a new instruction
00699   MBB->remove(I++);
00700   I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
00701 
00702   // If both operands are killed, pop one off of the stack in addition to
00703   // overwriting the other one.
00704   if (KillsOp0 && KillsOp1 && Op0 != Op1) {
00705     assert(!updateST0 && "Should have updated other operand!");
00706     popStackAfter(I);   // Pop the top of stack
00707   }
00708 
00709   // Update stack information so that we know the destination register is now on
00710   // the stack.
00711   unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
00712   assert(UpdatedSlot < StackTop && Dest < 7);
00713   Stack[UpdatedSlot]   = Dest;
00714   RegMap[Dest]         = UpdatedSlot;
00715   delete MI;   // Remove the old instruction
00716 }
00717 
00718 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
00719 /// register arguments and no explicit destinations.
00720 ///
00721 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
00722   ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
00723   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
00724   MachineInstr *MI = I;
00725 
00726   unsigned NumOperands = MI->getNumOperands();
00727   assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
00728   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
00729   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
00730   bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
00731   bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
00732 
00733   // Make sure the first operand is on the top of stack, the other one can be
00734   // anywhere.
00735   moveToTop(Op0, I);
00736 
00737   // Change from the pseudo instruction to the concrete instruction.
00738   MI->getOperand(0).setReg(getSTReg(Op1));
00739   MI->RemoveOperand(1);
00740   MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
00741 
00742   // If any of the operands are killed by this instruction, free them.
00743   if (KillsOp0) freeStackSlotAfter(I, Op0);
00744   if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
00745 }
00746 
00747 /// handleCondMovFP - Handle two address conditional move instructions.  These
00748 /// instructions move a st(i) register to st(0) iff a condition is true.  These
00749 /// instructions require that the first operand is at the top of the stack, but
00750 /// otherwise don't modify the stack at all.
00751 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
00752   MachineInstr *MI = I;
00753 
00754   unsigned Op0 = getFPReg(MI->getOperand(0));
00755   unsigned Op1 = getFPReg(MI->getOperand(1));
00756 
00757   // The first operand *must* be on the top of the stack.
00758   moveToTop(Op0, I);
00759 
00760   // Change the second operand to the stack register that the operand is in.
00761   // Change from the pseudo instruction to the concrete instruction.
00762   MI->RemoveOperand(0);
00763   MI->getOperand(0).setReg(getSTReg(Op1));
00764   MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
00765   
00766   
00767   // If we kill the second operand, make sure to pop it from the stack.
00768   if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
00769     // Get this value off of the register stack.
00770     freeStackSlotAfter(I, Op1);
00771   }
00772 }
00773 
00774 
00775 /// handleSpecialFP - Handle special instructions which behave unlike other
00776 /// floating point instructions.  This is primarily intended for use by pseudo
00777 /// instructions.
00778 ///
00779 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
00780   MachineInstr *MI = I;
00781   switch (MI->getOpcode()) {
00782   default: assert(0 && "Unknown SpecialFP instruction!");
00783   case X86::FpGETRESULT:  // Appears immediately after a call returning FP type!
00784     assert(StackTop == 0 && "Stack should be empty after a call!");
00785     pushReg(getFPReg(MI->getOperand(0)));
00786     break;
00787   case X86::FpSETRESULT:
00788     assert(StackTop == 1 && "Stack should have one element on it to return!");
00789     --StackTop;   // "Forget" we have something on the top of stack!
00790     break;
00791   case X86::FpMOV: {
00792     unsigned SrcReg = getFPReg(MI->getOperand(1));
00793     unsigned DestReg = getFPReg(MI->getOperand(0));
00794 
00795     if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
00796       // If the input operand is killed, we can just change the owner of the
00797       // incoming stack slot into the result.
00798       unsigned Slot = getSlot(SrcReg);
00799       assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
00800       Stack[Slot] = DestReg;
00801       RegMap[DestReg] = Slot;
00802 
00803     } else {
00804       // For FMOV we just duplicate the specified value to a new stack slot.
00805       // This could be made better, but would require substantial changes.
00806       duplicateToTop(SrcReg, DestReg, I);
00807     }
00808     break;
00809   }
00810   }
00811 
00812   I = MBB->erase(I);  // Remove the pseudo instruction
00813   --I;
00814 }