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X86ISelLowering.h

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00001 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Chris Lattner and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the interfaces that X86 uses to lower LLVM code into a
00011 // selection DAG.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #ifndef X86ISELLOWERING_H
00016 #define X86ISELLOWERING_H
00017 
00018 #include "X86Subtarget.h"
00019 #include "llvm/Target/TargetLowering.h"
00020 #include "llvm/CodeGen/SelectionDAG.h"
00021 
00022 namespace llvm {
00023   namespace X86ISD {
00024     // X86 Specific DAG Nodes
00025     enum NodeType {
00026       // Start the numbering where the builtin ops leave off.
00027       FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
00028 
00029       /// SHLD, SHRD - Double shift instructions. These correspond to
00030       /// X86::SHLDxx and X86::SHRDxx instructions.
00031       SHLD,
00032       SHRD,
00033 
00034       /// FAND - Bitwise logical AND of floating point values. This corresponds
00035       /// to X86::ANDPS or X86::ANDPD.
00036       FAND,
00037 
00038       /// FXOR - Bitwise logical XOR of floating point values. This corresponds
00039       /// to X86::XORPS or X86::XORPD.
00040       FXOR,
00041 
00042       /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
00043       /// integer source in memory and FP reg result.  This corresponds to the
00044       /// X86::FILD*m instructions. It has three inputs (token chain, address,
00045       /// and source type) and two outputs (FP value and token chain). FILD_FLAG
00046       /// also produces a flag).
00047       FILD,
00048       FILD_FLAG,
00049 
00050       /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
00051       /// integer destination in memory and a FP reg source.  This corresponds
00052       /// to the X86::FIST*m instructions and the rounding mode change stuff. It
00053       /// has two inputs (token chain and address) and two outputs (int value and
00054       /// token chain).
00055       FP_TO_INT16_IN_MEM,
00056       FP_TO_INT32_IN_MEM,
00057       FP_TO_INT64_IN_MEM,
00058 
00059       /// FLD - This instruction implements an extending load to FP stack slots.
00060       /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
00061       /// operand, ptr to load from, and a ValueType node indicating the type
00062       /// to load to.
00063       FLD,
00064 
00065       /// FST - This instruction implements a truncating store to FP stack
00066       /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
00067       /// chain operand, value to store, address, and a ValueType to store it
00068       /// as.
00069       FST,
00070 
00071       /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
00072       /// which copies from ST(0) to the destination. It takes a chain and writes
00073       /// a RFP result and a chain.
00074       FP_GET_RESULT,
00075 
00076       /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
00077       /// which copies the source operand to ST(0). It takes a chain and writes
00078       /// a chain and a flag.
00079       FP_SET_RESULT,
00080 
00081       /// CALL/TAILCALL - These operations represent an abstract X86 call
00082       /// instruction, which includes a bunch of information.  In particular the
00083       /// operands of these node are:
00084       ///
00085       ///     #0 - The incoming token chain
00086       ///     #1 - The callee
00087       ///     #2 - The number of arg bytes the caller pushes on the stack.
00088       ///     #3 - The number of arg bytes the callee pops off the stack.
00089       ///     #4 - The value to pass in AL/AX/EAX (optional)
00090       ///     #5 - The value to pass in DL/DX/EDX (optional)
00091       ///
00092       /// The result values of these nodes are:
00093       ///
00094       ///     #0 - The outgoing token chain
00095       ///     #1 - The first register result value (optional)
00096       ///     #2 - The second register result value (optional)
00097       ///
00098       /// The CALL vs TAILCALL distinction boils down to whether the callee is
00099       /// known not to modify the caller's stack frame, as is standard with
00100       /// LLVM.
00101       CALL,
00102       TAILCALL,
00103       
00104       /// RDTSC_DAG - This operation implements the lowering for 
00105       /// readcyclecounter
00106       RDTSC_DAG,
00107 
00108       /// X86 compare and logical compare instructions.
00109       CMP, TEST, COMI, UCOMI,
00110 
00111       /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
00112       /// operand produced by a CMP instruction.
00113       SETCC,
00114 
00115       /// X86 conditional moves. Operand 1 and operand 2 are the two values
00116       /// to select from (operand 1 is a R/W operand). Operand 3 is the condition
00117       /// code, and operand 4 is the flag operand produced by a CMP or TEST
00118       /// instruction. It also writes a flag result.
00119       CMOV,
00120 
00121       /// X86 conditional branches. Operand 1 is the chain operand, operand 2
00122       /// is the block to branch if condition is true, operand 3 is the
00123       /// condition code, and operand 4 is the flag operand produced by a CMP
00124       /// or TEST instruction.
00125       BRCOND,
00126 
00127       /// Return with a flag operand. Operand 1 is the chain operand, operand
00128       /// 2 is the number of bytes of stack to pop.
00129       RET_FLAG,
00130 
00131       /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
00132       REP_STOS,
00133 
00134       /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
00135       REP_MOVS,
00136 
00137       /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
00138       /// operands as a normal load.
00139       LOAD_PACK,
00140 
00141       /// GlobalBaseReg - On Darwin, this node represents the result of the popl
00142       /// at function entry, used for PIC code.
00143       GlobalBaseReg,
00144 
00145       /// TCPWrapper - A wrapper node for TargetConstantPool,
00146       /// TargetExternalSymbol, and TargetGlobalAddress.
00147       Wrapper,
00148 
00149       /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
00150       /// have to match the operand type.
00151       S2VEC,
00152 
00153       /// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
00154       /// does not have to match the operand type.
00155       ZEXT_S2VEC,
00156 
00157       /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
00158       /// i32, corresponds to X86::PEXTRW.
00159       PEXTRW,
00160 
00161       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
00162       /// corresponds to X86::PINSRW.
00163       PINSRW,
00164     };
00165 
00166     // X86 specific condition code. These correspond to X86_*_COND in
00167     // X86InstrInfo.td. They must be kept in synch.
00168     enum CondCode {
00169       COND_A  = 0,
00170       COND_AE = 1,
00171       COND_B  = 2,
00172       COND_BE = 3,
00173       COND_E  = 4,
00174       COND_G  = 5,
00175       COND_GE = 6,
00176       COND_L  = 7,
00177       COND_LE = 8,
00178       COND_NE = 9,
00179       COND_NO = 10,
00180       COND_NP = 11,
00181       COND_NS = 12,
00182       COND_O  = 13,
00183       COND_P  = 14,
00184       COND_S  = 15,
00185       COND_INVALID
00186     };
00187   }
00188 
00189  /// Define some predicates that are used for node matching.
00190  namespace X86 {
00191    /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
00192    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
00193    bool isPSHUFDMask(SDNode *N);
00194 
00195    /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
00196    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
00197    bool isPSHUFHWMask(SDNode *N);
00198 
00199    /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
00200    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
00201    bool isPSHUFLWMask(SDNode *N);
00202 
00203    /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
00204    /// specifies a shuffle of elements that is suitable for input to SHUFP*.
00205    bool isSHUFPMask(SDNode *N);
00206 
00207    /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
00208    /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
00209    bool isMOVLHPSMask(SDNode *N);
00210 
00211    /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
00212    /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
00213    bool isMOVHLPSMask(SDNode *N);
00214 
00215    /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
00216    /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
00217    bool isMOVLPMask(SDNode *N);
00218 
00219    /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
00220    /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}.
00221    bool isMOVHPMask(SDNode *N);
00222 
00223    /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
00224    /// specifies a shuffle of elements that is suitable for input to UNPCKL.
00225    bool isUNPCKLMask(SDNode *N);
00226 
00227    /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
00228    /// specifies a shuffle of elements that is suitable for input to UNPCKH.
00229    bool isUNPCKHMask(SDNode *N);
00230 
00231    /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
00232    /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
00233    /// <0, 0, 1, 1>
00234    bool isUNPCKL_v_undef_Mask(SDNode *N);
00235 
00236    /// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand
00237    /// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
00238    bool isMOVSMask(SDNode *N);
00239 
00240    /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
00241    /// specifies a splat of a single element.
00242    bool isSplatMask(SDNode *N);
00243 
00244    /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
00245    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
00246    /// instructions.
00247    unsigned getShuffleSHUFImmediate(SDNode *N);
00248 
00249    /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
00250    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
00251    /// instructions.
00252    unsigned getShufflePSHUFHWImmediate(SDNode *N);
00253 
00254    /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
00255    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
00256    /// instructions.
00257    unsigned getShufflePSHUFLWImmediate(SDNode *N);
00258  }
00259 
00260   //===----------------------------------------------------------------------===//
00261   //  X86TargetLowering - X86 Implementation of the TargetLowering interface
00262   class X86TargetLowering : public TargetLowering {
00263     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
00264     int ReturnAddrIndex;              // FrameIndex for return slot.
00265     int BytesToPopOnReturn;           // Number of arg bytes ret should pop.
00266     int BytesCallerReserves;          // Number of arg bytes caller makes.
00267   public:
00268     X86TargetLowering(TargetMachine &TM);
00269 
00270     // Return the number of bytes that a function should pop when it returns (in
00271     // addition to the space used by the return address).
00272     //
00273     unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
00274 
00275     // Return the number of bytes that the caller reserves for arguments passed
00276     // to this function.
00277     unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
00278  
00279     /// LowerOperation - Provide custom lowering hooks for some operations.
00280     ///
00281     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
00282 
00283     /// LowerArguments - This hook must be implemented to indicate how we should
00284     /// lower the arguments for the specified function, into the specified DAG.
00285     virtual std::vector<SDOperand>
00286     LowerArguments(Function &F, SelectionDAG &DAG);
00287 
00288     /// LowerCallTo - This hook lowers an abstract call to a function into an
00289     /// actual call.
00290     virtual std::pair<SDOperand, SDOperand>
00291     LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
00292                 bool isTailCall, SDOperand Callee, ArgListTy &Args,
00293                 SelectionDAG &DAG);
00294 
00295     virtual std::pair<SDOperand, SDOperand>
00296     LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
00297                             SelectionDAG &DAG);
00298 
00299     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
00300                                                        MachineBasicBlock *MBB);
00301 
00302     /// getTargetNodeName - This method returns the name of a target specific
00303     /// DAG node.
00304     virtual const char *getTargetNodeName(unsigned Opcode) const;
00305 
00306     /// computeMaskedBitsForTargetNode - Determine which of the bits specified 
00307     /// in Mask are known to be either zero or one and return them in the 
00308     /// KnownZero/KnownOne bitsets.
00309     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
00310                                                 uint64_t Mask,
00311                                                 uint64_t &KnownZero, 
00312                                                 uint64_t &KnownOne,
00313                                                 unsigned Depth = 0) const;
00314     
00315     SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
00316 
00317     std::vector<unsigned> 
00318       getRegClassForInlineAsmConstraint(const std::string &Constraint,
00319                                         MVT::ValueType VT) const;
00320 
00321     /// isLegalAddressImmediate - Return true if the integer value or
00322     /// GlobalValue can be used as the offset of the target addressing mode.
00323     virtual bool isLegalAddressImmediate(int64_t V) const;
00324     virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
00325 
00326     /// isShuffleMaskLegal - Targets can use this to indicate that they only
00327     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
00328     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
00329     /// are assumed to be legal.
00330     virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
00331   private:
00332     // C Calling Convention implementation.
00333     std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
00334     std::pair<SDOperand, SDOperand>
00335     LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
00336                    bool isTailCall,
00337                    SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
00338 
00339     // Fast Calling Convention implementation.
00340     std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
00341     std::pair<SDOperand, SDOperand>
00342     LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
00343                       SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
00344 
00345     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
00346     /// make the right decision when generating code for different targets.
00347     const X86Subtarget *Subtarget;
00348 
00349     /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
00350     bool X86ScalarSSE;
00351   };
00352 }
00353 
00354 #endif    // X86ISELLOWERING_H