LLVM API Documentation
00001 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the PowerPC implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "PPCInstrInfo.h" 00015 #include "PPCGenInstrInfo.inc" 00016 #include "PPC.h" 00017 #include "llvm/CodeGen/MachineInstrBuilder.h" 00018 #include <iostream> 00019 using namespace llvm; 00020 00021 PPCInstrInfo::PPCInstrInfo() 00022 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {} 00023 00024 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, 00025 unsigned& sourceReg, 00026 unsigned& destReg) const { 00027 MachineOpCode oc = MI.getOpcode(); 00028 if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR || 00029 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 00030 assert(MI.getNumOperands() == 3 && 00031 MI.getOperand(0).isRegister() && 00032 MI.getOperand(1).isRegister() && 00033 MI.getOperand(2).isRegister() && 00034 "invalid PPC OR instruction!"); 00035 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 00036 sourceReg = MI.getOperand(1).getReg(); 00037 destReg = MI.getOperand(0).getReg(); 00038 return true; 00039 } 00040 } else if (oc == PPC::ADDI) { // addi r1, r2, 0 00041 assert(MI.getNumOperands() == 3 && 00042 MI.getOperand(0).isRegister() && 00043 MI.getOperand(2).isImmediate() && 00044 "invalid PPC ADDI instruction!"); 00045 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) { 00046 sourceReg = MI.getOperand(1).getReg(); 00047 destReg = MI.getOperand(0).getReg(); 00048 return true; 00049 } 00050 } else if (oc == PPC::ORI) { // ori r1, r2, 0 00051 assert(MI.getNumOperands() == 3 && 00052 MI.getOperand(0).isRegister() && 00053 MI.getOperand(1).isRegister() && 00054 MI.getOperand(2).isImmediate() && 00055 "invalid PPC ORI instruction!"); 00056 if (MI.getOperand(2).getImmedValue()==0) { 00057 sourceReg = MI.getOperand(1).getReg(); 00058 destReg = MI.getOperand(0).getReg(); 00059 return true; 00060 } 00061 } else if (oc == PPC::FMRS || oc == PPC::FMRD || 00062 oc == PPC::FMRSD) { // fmr r1, r2 00063 assert(MI.getNumOperands() == 2 && 00064 MI.getOperand(0).isRegister() && 00065 MI.getOperand(1).isRegister() && 00066 "invalid PPC FMR instruction"); 00067 sourceReg = MI.getOperand(1).getReg(); 00068 destReg = MI.getOperand(0).getReg(); 00069 return true; 00070 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 00071 assert(MI.getNumOperands() == 2 && 00072 MI.getOperand(0).isRegister() && 00073 MI.getOperand(1).isRegister() && 00074 "invalid PPC MCRF instruction"); 00075 sourceReg = MI.getOperand(1).getReg(); 00076 destReg = MI.getOperand(0).getReg(); 00077 return true; 00078 } 00079 return false; 00080 } 00081 00082 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 00083 int &FrameIndex) const { 00084 switch (MI->getOpcode()) { 00085 default: break; 00086 case PPC::LD: 00087 case PPC::LWZ: 00088 case PPC::LFS: 00089 case PPC::LFD: 00090 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 00091 MI->getOperand(2).isFrameIndex()) { 00092 FrameIndex = MI->getOperand(2).getFrameIndex(); 00093 return MI->getOperand(0).getReg(); 00094 } 00095 break; 00096 } 00097 return 0; 00098 } 00099 00100 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 00101 int &FrameIndex) const { 00102 switch (MI->getOpcode()) { 00103 default: break; 00104 case PPC::STD: 00105 case PPC::STW: 00106 case PPC::STFS: 00107 case PPC::STFD: 00108 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 00109 MI->getOperand(2).isFrameIndex()) { 00110 FrameIndex = MI->getOperand(2).getFrameIndex(); 00111 return MI->getOperand(0).getReg(); 00112 } 00113 break; 00114 } 00115 return 0; 00116 } 00117 00118 // commuteInstruction - We can commute rlwimi instructions, but only if the 00119 // rotate amt is zero. We also have to munge the immediates a bit. 00120 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { 00121 // Normal instructions can be commuted the obvious way. 00122 if (MI->getOpcode() != PPC::RLWIMI) 00123 return TargetInstrInfo::commuteInstruction(MI); 00124 00125 // Cannot commute if it has a non-zero rotate count. 00126 if (MI->getOperand(3).getImmedValue() != 0) 00127 return 0; 00128 00129 // If we have a zero rotate count, we have: 00130 // M = mask(MB,ME) 00131 // Op0 = (Op1 & ~M) | (Op2 & M) 00132 // Change this to: 00133 // M = mask((ME+1)&31, (MB-1)&31) 00134 // Op0 = (Op2 & ~M) | (Op1 & M) 00135 00136 // Swap op1/op2 00137 unsigned Reg1 = MI->getOperand(1).getReg(); 00138 unsigned Reg2 = MI->getOperand(2).getReg(); 00139 MI->SetMachineOperandReg(2, Reg1); 00140 MI->SetMachineOperandReg(1, Reg2); 00141 00142 // Swap the mask around. 00143 unsigned MB = MI->getOperand(4).getImmedValue(); 00144 unsigned ME = MI->getOperand(5).getImmedValue(); 00145 MI->getOperand(4).setImmedValue((ME+1) & 31); 00146 MI->getOperand(5).setImmedValue((MB-1) & 31); 00147 return MI; 00148 } 00149 00150 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 00151 MachineBasicBlock::iterator MI) const { 00152 BuildMI(MBB, MI, PPC::NOP, 0); 00153 }