LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Machine Code Emitter 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 unsigned PPCCodeEmitter::getBinaryCodeForInstr(MachineInstr &MI) { 00010 unsigned Value = 0; 00011 DEBUG(std::cerr << MI); 00012 switch (MI.getOpcode()) { 00013 case PPC::ADD4: { 00014 DEBUG(std::cerr << "Emitting ADD4\n"); 00015 Value = 2080375316U; 00016 00017 // op0: RT 00018 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00019 op0 &= (1<<5) - 1; 00020 op0 <<= 21; 00021 Value |= op0; 00022 // op1: RA 00023 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00024 op1 &= (1<<5) - 1; 00025 op1 <<= 16; 00026 Value |= op1; 00027 // op2: RB 00028 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00029 op2 &= (1<<5) - 1; 00030 op2 <<= 11; 00031 Value |= op2; 00032 break; 00033 } 00034 case PPC::ADD8: { 00035 DEBUG(std::cerr << "Emitting ADD8\n"); 00036 Value = 2080375316U; 00037 00038 // op0: RT 00039 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00040 op0 &= (1<<5) - 1; 00041 op0 <<= 21; 00042 Value |= op0; 00043 // op1: RA 00044 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00045 op1 &= (1<<5) - 1; 00046 op1 <<= 16; 00047 Value |= op1; 00048 // op2: RB 00049 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00050 op2 &= (1<<5) - 1; 00051 op2 <<= 11; 00052 Value |= op2; 00053 break; 00054 } 00055 case PPC::ADDC: { 00056 DEBUG(std::cerr << "Emitting ADDC\n"); 00057 Value = 2080374804U; 00058 00059 // op0: RT 00060 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00061 op0 &= (1<<5) - 1; 00062 op0 <<= 21; 00063 Value |= op0; 00064 // op1: RA 00065 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00066 op1 &= (1<<5) - 1; 00067 op1 <<= 16; 00068 Value |= op1; 00069 // op2: RB 00070 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00071 op2 &= (1<<5) - 1; 00072 op2 <<= 11; 00073 Value |= op2; 00074 break; 00075 } 00076 case PPC::ADDE: { 00077 DEBUG(std::cerr << "Emitting ADDE\n"); 00078 Value = 2080375060U; 00079 00080 // op0: RT 00081 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00082 op0 &= (1<<5) - 1; 00083 op0 <<= 21; 00084 Value |= op0; 00085 // op1: RA 00086 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00087 op1 &= (1<<5) - 1; 00088 op1 <<= 16; 00089 Value |= op1; 00090 // op2: RB 00091 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00092 op2 &= (1<<5) - 1; 00093 op2 <<= 11; 00094 Value |= op2; 00095 break; 00096 } 00097 case PPC::ADDI: { 00098 DEBUG(std::cerr << "Emitting ADDI\n"); 00099 Value = 939524096U; 00100 00101 // op0: A 00102 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00103 op0 &= (1<<5) - 1; 00104 op0 <<= 21; 00105 Value |= op0; 00106 // op1: B 00107 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00108 op1 &= (1<<5) - 1; 00109 op1 <<= 16; 00110 Value |= op1; 00111 // op2: C 00112 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00113 op2 &= (1<<16) - 1; 00114 Value |= op2; 00115 break; 00116 } 00117 case PPC::ADDIC: { 00118 DEBUG(std::cerr << "Emitting ADDIC\n"); 00119 Value = 805306368U; 00120 00121 // op0: A 00122 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00123 op0 &= (1<<5) - 1; 00124 op0 <<= 21; 00125 Value |= op0; 00126 // op1: B 00127 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00128 op1 &= (1<<5) - 1; 00129 op1 <<= 16; 00130 Value |= op1; 00131 // op2: C 00132 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00133 op2 &= (1<<16) - 1; 00134 Value |= op2; 00135 break; 00136 } 00137 case PPC::ADDICo: { 00138 DEBUG(std::cerr << "Emitting ADDICo\n"); 00139 Value = 872415232U; 00140 00141 // op0: A 00142 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00143 op0 &= (1<<5) - 1; 00144 op0 <<= 21; 00145 Value |= op0; 00146 // op1: B 00147 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00148 op1 &= (1<<5) - 1; 00149 op1 <<= 16; 00150 Value |= op1; 00151 // op2: C 00152 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00153 op2 &= (1<<16) - 1; 00154 Value |= op2; 00155 break; 00156 } 00157 case PPC::ADDIS: { 00158 DEBUG(std::cerr << "Emitting ADDIS\n"); 00159 Value = 1006632960U; 00160 00161 // op0: A 00162 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00163 op0 &= (1<<5) - 1; 00164 op0 <<= 21; 00165 Value |= op0; 00166 // op1: B 00167 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00168 op1 &= (1<<5) - 1; 00169 op1 <<= 16; 00170 Value |= op1; 00171 // op2: C 00172 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00173 op2 &= (1<<16) - 1; 00174 Value |= op2; 00175 break; 00176 } 00177 case PPC::ADDME: { 00178 DEBUG(std::cerr << "Emitting ADDME\n"); 00179 Value = 2080375252U; 00180 00181 // op0: RT 00182 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00183 op0 &= (1<<5) - 1; 00184 op0 <<= 21; 00185 Value |= op0; 00186 // op1: RA 00187 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00188 op1 &= (1<<5) - 1; 00189 op1 <<= 16; 00190 Value |= op1; 00191 break; 00192 } 00193 case PPC::ADDZE: { 00194 DEBUG(std::cerr << "Emitting ADDZE\n"); 00195 Value = 2080375188U; 00196 00197 // op0: RT 00198 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00199 op0 &= (1<<5) - 1; 00200 op0 <<= 21; 00201 Value |= op0; 00202 // op1: RA 00203 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00204 op1 &= (1<<5) - 1; 00205 op1 <<= 16; 00206 Value |= op1; 00207 break; 00208 } 00209 case PPC::ADJCALLSTACKDOWN: { 00210 DEBUG(std::cerr << "Emitting ADJCALLSTACKDOWN\n"); 00211 Value = 0U; 00212 00213 break; 00214 } 00215 case PPC::ADJCALLSTACKUP: { 00216 DEBUG(std::cerr << "Emitting ADJCALLSTACKUP\n"); 00217 Value = 0U; 00218 00219 break; 00220 } 00221 case PPC::AND: { 00222 DEBUG(std::cerr << "Emitting AND\n"); 00223 Value = 2080374840U; 00224 00225 // op0: A 00226 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00227 op0 &= (1<<5) - 1; 00228 op0 <<= 16; 00229 Value |= op0; 00230 // op1: RST 00231 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00232 op1 &= (1<<5) - 1; 00233 op1 <<= 21; 00234 Value |= op1; 00235 // op2: B 00236 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00237 op2 &= (1<<5) - 1; 00238 op2 <<= 11; 00239 Value |= op2; 00240 break; 00241 } 00242 case PPC::ANDC: { 00243 DEBUG(std::cerr << "Emitting ANDC\n"); 00244 Value = 2080374904U; 00245 00246 // op0: A 00247 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00248 op0 &= (1<<5) - 1; 00249 op0 <<= 16; 00250 Value |= op0; 00251 // op1: RST 00252 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00253 op1 &= (1<<5) - 1; 00254 op1 <<= 21; 00255 Value |= op1; 00256 // op2: B 00257 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00258 op2 &= (1<<5) - 1; 00259 op2 <<= 11; 00260 Value |= op2; 00261 break; 00262 } 00263 case PPC::ANDISo: { 00264 DEBUG(std::cerr << "Emitting ANDISo\n"); 00265 Value = 1946157056U; 00266 00267 // op0: B 00268 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00269 op0 &= (1<<5) - 1; 00270 op0 <<= 16; 00271 Value |= op0; 00272 // op1: A 00273 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00274 op1 &= (1<<5) - 1; 00275 op1 <<= 21; 00276 Value |= op1; 00277 // op2: C 00278 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00279 op2 &= (1<<16) - 1; 00280 Value |= op2; 00281 break; 00282 } 00283 case PPC::ANDIo: { 00284 DEBUG(std::cerr << "Emitting ANDIo\n"); 00285 Value = 1879048192U; 00286 00287 // op0: B 00288 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00289 op0 &= (1<<5) - 1; 00290 op0 <<= 16; 00291 Value |= op0; 00292 // op1: A 00293 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00294 op1 &= (1<<5) - 1; 00295 op1 <<= 21; 00296 Value |= op1; 00297 // op2: C 00298 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00299 op2 &= (1<<16) - 1; 00300 Value |= op2; 00301 break; 00302 } 00303 case PPC::ANDo: { 00304 DEBUG(std::cerr << "Emitting ANDo\n"); 00305 Value = 2080374841U; 00306 00307 // op0: A 00308 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00309 op0 &= (1<<5) - 1; 00310 op0 <<= 16; 00311 Value |= op0; 00312 // op1: RST 00313 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00314 op1 &= (1<<5) - 1; 00315 op1 <<= 21; 00316 Value |= op1; 00317 // op2: B 00318 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00319 op2 &= (1<<5) - 1; 00320 op2 <<= 11; 00321 Value |= op2; 00322 break; 00323 } 00324 case PPC::B: { 00325 DEBUG(std::cerr << "Emitting B\n"); 00326 Value = 1207959552U; 00327 00328 // op0: LI 00329 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00330 op0 &= (1<<24) - 1; 00331 op0 <<= 2; 00332 Value |= op0; 00333 break; 00334 } 00335 case PPC::BCTR: { 00336 DEBUG(std::cerr << "Emitting BCTR\n"); 00337 Value = 1317012512U; 00338 00339 break; 00340 } 00341 case PPC::BCTRL: { 00342 DEBUG(std::cerr << "Emitting BCTRL\n"); 00343 Value = 1317012513U; 00344 00345 break; 00346 } 00347 case PPC::BEQ: { 00348 DEBUG(std::cerr << "Emitting BEQ\n"); 00349 Value = 1099038720U; 00350 00351 // op0: CR 00352 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00353 op0 &= (1<<3) - 1; 00354 op0 <<= 18; 00355 Value |= op0; 00356 // op1: BD 00357 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00358 op1 &= (1<<14) - 1; 00359 op1 <<= 2; 00360 Value |= op1; 00361 break; 00362 } 00363 case PPC::BGE: { 00364 DEBUG(std::cerr << "Emitting BGE\n"); 00365 Value = 1082130432U; 00366 00367 // op0: CR 00368 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00369 op0 &= (1<<3) - 1; 00370 op0 <<= 18; 00371 Value |= op0; 00372 // op1: BD 00373 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00374 op1 &= (1<<14) - 1; 00375 op1 <<= 2; 00376 Value |= op1; 00377 break; 00378 } 00379 case PPC::BGT: { 00380 DEBUG(std::cerr << "Emitting BGT\n"); 00381 Value = 1098973184U; 00382 00383 // op0: CR 00384 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00385 op0 &= (1<<3) - 1; 00386 op0 <<= 18; 00387 Value |= op0; 00388 // op1: BD 00389 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00390 op1 &= (1<<14) - 1; 00391 op1 <<= 2; 00392 Value |= op1; 00393 break; 00394 } 00395 case PPC::BL: { 00396 DEBUG(std::cerr << "Emitting BL\n"); 00397 Value = 1207959553U; 00398 00399 // op0: LI 00400 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00401 op0 &= (1<<24) - 1; 00402 op0 <<= 2; 00403 Value |= op0; 00404 break; 00405 } 00406 case PPC::BLA: { 00407 DEBUG(std::cerr << "Emitting BLA\n"); 00408 Value = 1207959555U; 00409 00410 // op0: LI 00411 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00412 op0 &= (1<<24) - 1; 00413 op0 <<= 2; 00414 Value |= op0; 00415 break; 00416 } 00417 case PPC::BLE: { 00418 DEBUG(std::cerr << "Emitting BLE\n"); 00419 Value = 1082195968U; 00420 00421 // op0: CR 00422 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00423 op0 &= (1<<3) - 1; 00424 op0 <<= 18; 00425 Value |= op0; 00426 // op1: BD 00427 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00428 op1 &= (1<<14) - 1; 00429 op1 <<= 2; 00430 Value |= op1; 00431 break; 00432 } 00433 case PPC::BLR: { 00434 DEBUG(std::cerr << "Emitting BLR\n"); 00435 Value = 1317011488U; 00436 00437 break; 00438 } 00439 case PPC::BLT: { 00440 DEBUG(std::cerr << "Emitting BLT\n"); 00441 Value = 1098907648U; 00442 00443 // op0: CR 00444 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00445 op0 &= (1<<3) - 1; 00446 op0 <<= 18; 00447 Value |= op0; 00448 // op1: BD 00449 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00450 op1 &= (1<<14) - 1; 00451 op1 <<= 2; 00452 Value |= op1; 00453 break; 00454 } 00455 case PPC::BNE: { 00456 DEBUG(std::cerr << "Emitting BNE\n"); 00457 Value = 1082261504U; 00458 00459 // op0: CR 00460 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00461 op0 &= (1<<3) - 1; 00462 op0 <<= 18; 00463 Value |= op0; 00464 // op1: BD 00465 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00466 op1 &= (1<<14) - 1; 00467 op1 <<= 2; 00468 Value |= op1; 00469 break; 00470 } 00471 case PPC::BNU: { 00472 DEBUG(std::cerr << "Emitting BNU\n"); 00473 Value = 1082327040U; 00474 00475 // op0: CR 00476 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00477 op0 &= (1<<3) - 1; 00478 op0 <<= 18; 00479 Value |= op0; 00480 // op1: BD 00481 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00482 op1 &= (1<<14) - 1; 00483 op1 <<= 2; 00484 Value |= op1; 00485 break; 00486 } 00487 case PPC::BUN: { 00488 DEBUG(std::cerr << "Emitting BUN\n"); 00489 Value = 1099104256U; 00490 00491 // op0: CR 00492 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00493 op0 &= (1<<3) - 1; 00494 op0 <<= 18; 00495 Value |= op0; 00496 // op1: BD 00497 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00498 op1 &= (1<<14) - 1; 00499 op1 <<= 2; 00500 Value |= op1; 00501 break; 00502 } 00503 case PPC::CMP: { 00504 DEBUG(std::cerr << "Emitting CMP\n"); 00505 Value = 2080374784U; 00506 00507 // op0: BF 00508 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00509 op0 &= (1<<3) - 1; 00510 op0 <<= 23; 00511 Value |= op0; 00512 // op1: L 00513 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00514 op1 &= (1<<1) - 1; 00515 op1 <<= 21; 00516 Value |= op1; 00517 // op2: RA 00518 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00519 op2 &= (1<<5) - 1; 00520 op2 <<= 16; 00521 Value |= op2; 00522 // op3: RB 00523 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00524 op3 &= (1<<5) - 1; 00525 op3 <<= 11; 00526 Value |= op3; 00527 break; 00528 } 00529 case PPC::CMPD: { 00530 DEBUG(std::cerr << "Emitting CMPD\n"); 00531 Value = 2082471936U; 00532 00533 // op0: BF 00534 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00535 op0 &= (1<<3) - 1; 00536 op0 <<= 23; 00537 Value |= op0; 00538 // op1: RA 00539 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00540 op1 &= (1<<5) - 1; 00541 op1 <<= 16; 00542 Value |= op1; 00543 // op2: RB 00544 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00545 op2 &= (1<<5) - 1; 00546 op2 <<= 11; 00547 Value |= op2; 00548 break; 00549 } 00550 case PPC::CMPDI: { 00551 DEBUG(std::cerr << "Emitting CMPDI\n"); 00552 Value = 740294656U; 00553 00554 // op0: BF 00555 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00556 op0 &= (1<<3) - 1; 00557 op0 <<= 23; 00558 Value |= op0; 00559 // op1: RA 00560 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00561 op1 &= (1<<5) - 1; 00562 op1 <<= 16; 00563 Value |= op1; 00564 // op2: I 00565 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00566 op2 &= (1<<16) - 1; 00567 Value |= op2; 00568 break; 00569 } 00570 case PPC::CMPI: { 00571 DEBUG(std::cerr << "Emitting CMPI\n"); 00572 Value = 738197504U; 00573 00574 // op0: BF 00575 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00576 op0 &= (1<<3) - 1; 00577 op0 <<= 23; 00578 Value |= op0; 00579 // op1: L 00580 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00581 op1 &= (1<<1) - 1; 00582 op1 <<= 21; 00583 Value |= op1; 00584 // op2: RA 00585 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00586 op2 &= (1<<5) - 1; 00587 op2 <<= 16; 00588 Value |= op2; 00589 // op3: I 00590 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00591 op3 &= (1<<16) - 1; 00592 Value |= op3; 00593 break; 00594 } 00595 case PPC::CMPL: { 00596 DEBUG(std::cerr << "Emitting CMPL\n"); 00597 Value = 2080374848U; 00598 00599 // op0: BF 00600 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00601 op0 &= (1<<3) - 1; 00602 op0 <<= 23; 00603 Value |= op0; 00604 // op1: L 00605 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00606 op1 &= (1<<1) - 1; 00607 op1 <<= 21; 00608 Value |= op1; 00609 // op2: RA 00610 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00611 op2 &= (1<<5) - 1; 00612 op2 <<= 16; 00613 Value |= op2; 00614 // op3: RB 00615 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00616 op3 &= (1<<5) - 1; 00617 op3 <<= 11; 00618 Value |= op3; 00619 break; 00620 } 00621 case PPC::CMPLD: { 00622 DEBUG(std::cerr << "Emitting CMPLD\n"); 00623 Value = 2082472000U; 00624 00625 // op0: BF 00626 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00627 op0 &= (1<<3) - 1; 00628 op0 <<= 23; 00629 Value |= op0; 00630 // op1: RA 00631 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00632 op1 &= (1<<5) - 1; 00633 op1 <<= 16; 00634 Value |= op1; 00635 // op2: RB 00636 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00637 op2 &= (1<<5) - 1; 00638 op2 <<= 11; 00639 Value |= op2; 00640 break; 00641 } 00642 case PPC::CMPLDI: { 00643 DEBUG(std::cerr << "Emitting CMPLDI\n"); 00644 Value = 673185792U; 00645 00646 // op0: BF 00647 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00648 op0 &= (1<<3) - 1; 00649 op0 <<= 23; 00650 Value |= op0; 00651 // op1: RA 00652 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00653 op1 &= (1<<5) - 1; 00654 op1 <<= 16; 00655 Value |= op1; 00656 // op2: I 00657 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00658 op2 &= (1<<16) - 1; 00659 Value |= op2; 00660 break; 00661 } 00662 case PPC::CMPLI: { 00663 DEBUG(std::cerr << "Emitting CMPLI\n"); 00664 Value = 671088640U; 00665 00666 // op0: BF 00667 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00668 op0 &= (1<<3) - 1; 00669 op0 <<= 23; 00670 Value |= op0; 00671 // op1: L 00672 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00673 op1 &= (1<<1) - 1; 00674 op1 <<= 21; 00675 Value |= op1; 00676 // op2: RA 00677 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00678 op2 &= (1<<5) - 1; 00679 op2 <<= 16; 00680 Value |= op2; 00681 // op3: I 00682 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00683 op3 &= (1<<16) - 1; 00684 Value |= op3; 00685 break; 00686 } 00687 case PPC::CMPLW: { 00688 DEBUG(std::cerr << "Emitting CMPLW\n"); 00689 Value = 2080374848U; 00690 00691 // op0: BF 00692 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00693 op0 &= (1<<3) - 1; 00694 op0 <<= 23; 00695 Value |= op0; 00696 // op1: RA 00697 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00698 op1 &= (1<<5) - 1; 00699 op1 <<= 16; 00700 Value |= op1; 00701 // op2: RB 00702 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00703 op2 &= (1<<5) - 1; 00704 op2 <<= 11; 00705 Value |= op2; 00706 break; 00707 } 00708 case PPC::CMPLWI: { 00709 DEBUG(std::cerr << "Emitting CMPLWI\n"); 00710 Value = 671088640U; 00711 00712 // op0: BF 00713 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00714 op0 &= (1<<3) - 1; 00715 op0 <<= 23; 00716 Value |= op0; 00717 // op1: RA 00718 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00719 op1 &= (1<<5) - 1; 00720 op1 <<= 16; 00721 Value |= op1; 00722 // op2: I 00723 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00724 op2 &= (1<<16) - 1; 00725 Value |= op2; 00726 break; 00727 } 00728 case PPC::CMPW: { 00729 DEBUG(std::cerr << "Emitting CMPW\n"); 00730 Value = 2080374784U; 00731 00732 // op0: BF 00733 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00734 op0 &= (1<<3) - 1; 00735 op0 <<= 23; 00736 Value |= op0; 00737 // op1: RA 00738 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00739 op1 &= (1<<5) - 1; 00740 op1 <<= 16; 00741 Value |= op1; 00742 // op2: RB 00743 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00744 op2 &= (1<<5) - 1; 00745 op2 <<= 11; 00746 Value |= op2; 00747 break; 00748 } 00749 case PPC::CMPWI: { 00750 DEBUG(std::cerr << "Emitting CMPWI\n"); 00751 Value = 738197504U; 00752 00753 // op0: BF 00754 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00755 op0 &= (1<<3) - 1; 00756 op0 <<= 23; 00757 Value |= op0; 00758 // op1: RA 00759 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00760 op1 &= (1<<5) - 1; 00761 op1 <<= 16; 00762 Value |= op1; 00763 // op2: I 00764 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00765 op2 &= (1<<16) - 1; 00766 Value |= op2; 00767 break; 00768 } 00769 case PPC::CNTLZW: { 00770 DEBUG(std::cerr << "Emitting CNTLZW\n"); 00771 Value = 2080374836U; 00772 00773 // op0: A 00774 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00775 op0 &= (1<<5) - 1; 00776 op0 <<= 16; 00777 Value |= op0; 00778 // op1: RST 00779 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00780 op1 &= (1<<5) - 1; 00781 op1 <<= 21; 00782 Value |= op1; 00783 break; 00784 } 00785 case PPC::COND_BRANCH: { 00786 DEBUG(std::cerr << "Emitting COND_BRANCH\n"); 00787 Value = 0U; 00788 00789 break; 00790 } 00791 case PPC::DIVD: { 00792 DEBUG(std::cerr << "Emitting DIVD\n"); 00793 Value = 2080375762U; 00794 00795 // op0: RT 00796 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00797 op0 &= (1<<5) - 1; 00798 op0 <<= 21; 00799 Value |= op0; 00800 // op1: RA 00801 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00802 op1 &= (1<<5) - 1; 00803 op1 <<= 16; 00804 Value |= op1; 00805 // op2: RB 00806 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00807 op2 &= (1<<5) - 1; 00808 op2 <<= 11; 00809 Value |= op2; 00810 break; 00811 } 00812 case PPC::DIVDU: { 00813 DEBUG(std::cerr << "Emitting DIVDU\n"); 00814 Value = 2080375698U; 00815 00816 // op0: RT 00817 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00818 op0 &= (1<<5) - 1; 00819 op0 <<= 21; 00820 Value |= op0; 00821 // op1: RA 00822 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00823 op1 &= (1<<5) - 1; 00824 op1 <<= 16; 00825 Value |= op1; 00826 // op2: RB 00827 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00828 op2 &= (1<<5) - 1; 00829 op2 <<= 11; 00830 Value |= op2; 00831 break; 00832 } 00833 case PPC::DIVW: { 00834 DEBUG(std::cerr << "Emitting DIVW\n"); 00835 Value = 2080375766U; 00836 00837 // op0: RT 00838 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00839 op0 &= (1<<5) - 1; 00840 op0 <<= 21; 00841 Value |= op0; 00842 // op1: RA 00843 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00844 op1 &= (1<<5) - 1; 00845 op1 <<= 16; 00846 Value |= op1; 00847 // op2: RB 00848 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00849 op2 &= (1<<5) - 1; 00850 op2 <<= 11; 00851 Value |= op2; 00852 break; 00853 } 00854 case PPC::DIVWU: { 00855 DEBUG(std::cerr << "Emitting DIVWU\n"); 00856 Value = 2080375702U; 00857 00858 // op0: RT 00859 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00860 op0 &= (1<<5) - 1; 00861 op0 <<= 21; 00862 Value |= op0; 00863 // op1: RA 00864 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00865 op1 &= (1<<5) - 1; 00866 op1 <<= 16; 00867 Value |= op1; 00868 // op2: RB 00869 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00870 op2 &= (1<<5) - 1; 00871 op2 <<= 11; 00872 Value |= op2; 00873 break; 00874 } 00875 case PPC::DSS: { 00876 DEBUG(std::cerr << "Emitting DSS\n"); 00877 Value = 2080376428U; 00878 00879 // op0: T 00880 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00881 op0 &= (1<<1) - 1; 00882 op0 <<= 25; 00883 Value |= op0; 00884 // op1: STRM 00885 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00886 op1 &= (1<<2) - 1; 00887 op1 <<= 21; 00888 Value |= op1; 00889 // op2: A 00890 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00891 op2 &= (1<<5) - 1; 00892 op2 <<= 16; 00893 Value |= op2; 00894 // op3: B 00895 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00896 op3 &= (1<<5) - 1; 00897 op3 <<= 11; 00898 Value |= op3; 00899 break; 00900 } 00901 case PPC::DST: { 00902 DEBUG(std::cerr << "Emitting DST\n"); 00903 Value = 2080375468U; 00904 00905 // op0: T 00906 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00907 op0 &= (1<<1) - 1; 00908 op0 <<= 25; 00909 Value |= op0; 00910 // op1: STRM 00911 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00912 op1 &= (1<<2) - 1; 00913 op1 <<= 21; 00914 Value |= op1; 00915 // op2: A 00916 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00917 op2 &= (1<<5) - 1; 00918 op2 <<= 16; 00919 Value |= op2; 00920 // op3: B 00921 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00922 op3 &= (1<<5) - 1; 00923 op3 <<= 11; 00924 Value |= op3; 00925 break; 00926 } 00927 case PPC::DSTST: { 00928 DEBUG(std::cerr << "Emitting DSTST\n"); 00929 Value = 2080375532U; 00930 00931 // op0: T 00932 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00933 op0 &= (1<<1) - 1; 00934 op0 <<= 25; 00935 Value |= op0; 00936 // op1: STRM 00937 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00938 op1 &= (1<<2) - 1; 00939 op1 <<= 21; 00940 Value |= op1; 00941 // op2: A 00942 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00943 op2 &= (1<<5) - 1; 00944 op2 <<= 16; 00945 Value |= op2; 00946 // op3: B 00947 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 00948 op3 &= (1<<5) - 1; 00949 op3 <<= 11; 00950 Value |= op3; 00951 break; 00952 } 00953 case PPC::DWARF_LABEL: { 00954 DEBUG(std::cerr << "Emitting DWARF_LABEL\n"); 00955 Value = 0U; 00956 00957 break; 00958 } 00959 case PPC::DWARF_LOC: { 00960 DEBUG(std::cerr << "Emitting DWARF_LOC\n"); 00961 Value = 0U; 00962 00963 break; 00964 } 00965 case PPC::EQV: { 00966 DEBUG(std::cerr << "Emitting EQV\n"); 00967 Value = 2080375352U; 00968 00969 // op0: A 00970 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00971 op0 &= (1<<5) - 1; 00972 op0 <<= 16; 00973 Value |= op0; 00974 // op1: RST 00975 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00976 op1 &= (1<<5) - 1; 00977 op1 <<= 21; 00978 Value |= op1; 00979 // op2: B 00980 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00981 op2 &= (1<<5) - 1; 00982 op2 <<= 11; 00983 Value |= op2; 00984 break; 00985 } 00986 case PPC::EXTSB: { 00987 DEBUG(std::cerr << "Emitting EXTSB\n"); 00988 Value = 2080376692U; 00989 00990 // op0: A 00991 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00992 op0 &= (1<<5) - 1; 00993 op0 <<= 16; 00994 Value |= op0; 00995 // op1: RST 00996 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00997 op1 &= (1<<5) - 1; 00998 op1 <<= 21; 00999 Value |= op1; 01000 break; 01001 } 01002 case PPC::EXTSH: { 01003 DEBUG(std::cerr << "Emitting EXTSH\n"); 01004 Value = 2080376628U; 01005 01006 // op0: A 01007 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01008 op0 &= (1<<5) - 1; 01009 op0 <<= 16; 01010 Value |= op0; 01011 // op1: RST 01012 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01013 op1 &= (1<<5) - 1; 01014 op1 <<= 21; 01015 Value |= op1; 01016 break; 01017 } 01018 case PPC::EXTSW: { 01019 DEBUG(std::cerr << "Emitting EXTSW\n"); 01020 Value = 2080376756U; 01021 01022 // op0: A 01023 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01024 op0 &= (1<<5) - 1; 01025 op0 <<= 16; 01026 Value |= op0; 01027 // op1: RST 01028 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01029 op1 &= (1<<5) - 1; 01030 op1 <<= 21; 01031 Value |= op1; 01032 break; 01033 } 01034 case PPC::EXTSW_32: { 01035 DEBUG(std::cerr << "Emitting EXTSW_32\n"); 01036 Value = 2080376756U; 01037 01038 // op0: A 01039 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01040 op0 &= (1<<5) - 1; 01041 op0 <<= 16; 01042 Value |= op0; 01043 // op1: RST 01044 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01045 op1 &= (1<<5) - 1; 01046 op1 <<= 21; 01047 Value |= op1; 01048 break; 01049 } 01050 case PPC::FABSD: { 01051 DEBUG(std::cerr << "Emitting FABSD\n"); 01052 Value = 4227858960U; 01053 01054 // op0: RST 01055 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01056 op0 &= (1<<5) - 1; 01057 op0 <<= 21; 01058 Value |= op0; 01059 // op1: B 01060 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01061 op1 &= (1<<5) - 1; 01062 op1 <<= 11; 01063 Value |= op1; 01064 break; 01065 } 01066 case PPC::FABSS: { 01067 DEBUG(std::cerr << "Emitting FABSS\n"); 01068 Value = 4227858960U; 01069 01070 // op0: RST 01071 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01072 op0 &= (1<<5) - 1; 01073 op0 <<= 21; 01074 Value |= op0; 01075 // op1: B 01076 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01077 op1 &= (1<<5) - 1; 01078 op1 <<= 11; 01079 Value |= op1; 01080 break; 01081 } 01082 case PPC::FADD: { 01083 DEBUG(std::cerr << "Emitting FADD\n"); 01084 Value = 4227858474U; 01085 01086 // op0: FRT 01087 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01088 op0 &= (1<<5) - 1; 01089 op0 <<= 21; 01090 Value |= op0; 01091 // op1: FRA 01092 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01093 op1 &= (1<<5) - 1; 01094 op1 <<= 16; 01095 Value |= op1; 01096 // op2: FRB 01097 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01098 op2 &= (1<<5) - 1; 01099 op2 <<= 11; 01100 Value |= op2; 01101 break; 01102 } 01103 case PPC::FADDS: { 01104 DEBUG(std::cerr << "Emitting FADDS\n"); 01105 Value = 3959423018U; 01106 01107 // op0: FRT 01108 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01109 op0 &= (1<<5) - 1; 01110 op0 <<= 21; 01111 Value |= op0; 01112 // op1: FRA 01113 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01114 op1 &= (1<<5) - 1; 01115 op1 <<= 16; 01116 Value |= op1; 01117 // op2: FRB 01118 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01119 op2 &= (1<<5) - 1; 01120 op2 <<= 11; 01121 Value |= op2; 01122 break; 01123 } 01124 case PPC::FCFID: { 01125 DEBUG(std::cerr << "Emitting FCFID\n"); 01126 Value = 4227860124U; 01127 01128 // op0: RST 01129 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01130 op0 &= (1<<5) - 1; 01131 op0 <<= 21; 01132 Value |= op0; 01133 // op1: B 01134 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01135 op1 &= (1<<5) - 1; 01136 op1 <<= 11; 01137 Value |= op1; 01138 break; 01139 } 01140 case PPC::FCMPUD: { 01141 DEBUG(std::cerr << "Emitting FCMPUD\n"); 01142 Value = 4227858432U; 01143 01144 // op0: BF 01145 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01146 op0 &= (1<<3) - 1; 01147 op0 <<= 23; 01148 Value |= op0; 01149 // op1: FRA 01150 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01151 op1 &= (1<<5) - 1; 01152 op1 <<= 16; 01153 Value |= op1; 01154 // op2: FRB 01155 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01156 op2 &= (1<<5) - 1; 01157 op2 <<= 11; 01158 Value |= op2; 01159 break; 01160 } 01161 case PPC::FCMPUS: { 01162 DEBUG(std::cerr << "Emitting FCMPUS\n"); 01163 Value = 4227858432U; 01164 01165 // op0: BF 01166 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01167 op0 &= (1<<3) - 1; 01168 op0 <<= 23; 01169 Value |= op0; 01170 // op1: FRA 01171 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01172 op1 &= (1<<5) - 1; 01173 op1 <<= 16; 01174 Value |= op1; 01175 // op2: FRB 01176 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01177 op2 &= (1<<5) - 1; 01178 op2 <<= 11; 01179 Value |= op2; 01180 break; 01181 } 01182 case PPC::FCTIDZ: { 01183 DEBUG(std::cerr << "Emitting FCTIDZ\n"); 01184 Value = 4227860062U; 01185 01186 // op0: RST 01187 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01188 op0 &= (1<<5) - 1; 01189 op0 <<= 21; 01190 Value |= op0; 01191 // op1: B 01192 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01193 op1 &= (1<<5) - 1; 01194 op1 <<= 11; 01195 Value |= op1; 01196 break; 01197 } 01198 case PPC::FCTIWZ: { 01199 DEBUG(std::cerr << "Emitting FCTIWZ\n"); 01200 Value = 4227858462U; 01201 01202 // op0: RST 01203 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01204 op0 &= (1<<5) - 1; 01205 op0 <<= 21; 01206 Value |= op0; 01207 // op1: B 01208 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01209 op1 &= (1<<5) - 1; 01210 op1 <<= 11; 01211 Value |= op1; 01212 break; 01213 } 01214 case PPC::FDIV: { 01215 DEBUG(std::cerr << "Emitting FDIV\n"); 01216 Value = 4227858468U; 01217 01218 // op0: FRT 01219 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01220 op0 &= (1<<5) - 1; 01221 op0 <<= 21; 01222 Value |= op0; 01223 // op1: FRA 01224 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01225 op1 &= (1<<5) - 1; 01226 op1 <<= 16; 01227 Value |= op1; 01228 // op2: FRB 01229 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01230 op2 &= (1<<5) - 1; 01231 op2 <<= 11; 01232 Value |= op2; 01233 break; 01234 } 01235 case PPC::FDIVS: { 01236 DEBUG(std::cerr << "Emitting FDIVS\n"); 01237 Value = 3959423012U; 01238 01239 // op0: FRT 01240 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01241 op0 &= (1<<5) - 1; 01242 op0 <<= 21; 01243 Value |= op0; 01244 // op1: FRA 01245 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01246 op1 &= (1<<5) - 1; 01247 op1 <<= 16; 01248 Value |= op1; 01249 // op2: FRB 01250 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01251 op2 &= (1<<5) - 1; 01252 op2 <<= 11; 01253 Value |= op2; 01254 break; 01255 } 01256 case PPC::FMADD: { 01257 DEBUG(std::cerr << "Emitting FMADD\n"); 01258 Value = 4227858490U; 01259 01260 // op0: FRT 01261 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01262 op0 &= (1<<5) - 1; 01263 op0 <<= 21; 01264 Value |= op0; 01265 // op1: FRA 01266 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01267 op1 &= (1<<5) - 1; 01268 op1 <<= 16; 01269 Value |= op1; 01270 // op2: FRC 01271 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01272 op2 &= (1<<5) - 1; 01273 op2 <<= 6; 01274 Value |= op2; 01275 // op3: FRB 01276 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01277 op3 &= (1<<5) - 1; 01278 op3 <<= 11; 01279 Value |= op3; 01280 break; 01281 } 01282 case PPC::FMADDS: { 01283 DEBUG(std::cerr << "Emitting FMADDS\n"); 01284 Value = 3959423034U; 01285 01286 // op0: FRT 01287 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01288 op0 &= (1<<5) - 1; 01289 op0 <<= 21; 01290 Value |= op0; 01291 // op1: FRA 01292 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01293 op1 &= (1<<5) - 1; 01294 op1 <<= 16; 01295 Value |= op1; 01296 // op2: FRC 01297 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01298 op2 &= (1<<5) - 1; 01299 op2 <<= 6; 01300 Value |= op2; 01301 // op3: FRB 01302 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01303 op3 &= (1<<5) - 1; 01304 op3 <<= 11; 01305 Value |= op3; 01306 break; 01307 } 01308 case PPC::FMRD: { 01309 DEBUG(std::cerr << "Emitting FMRD\n"); 01310 Value = 4227858576U; 01311 01312 // op0: RST 01313 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01314 op0 &= (1<<5) - 1; 01315 op0 <<= 21; 01316 Value |= op0; 01317 // op1: B 01318 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01319 op1 &= (1<<5) - 1; 01320 op1 <<= 11; 01321 Value |= op1; 01322 break; 01323 } 01324 case PPC::FMRS: { 01325 DEBUG(std::cerr << "Emitting FMRS\n"); 01326 Value = 4227858576U; 01327 01328 // op0: RST 01329 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01330 op0 &= (1<<5) - 1; 01331 op0 <<= 21; 01332 Value |= op0; 01333 // op1: B 01334 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01335 op1 &= (1<<5) - 1; 01336 op1 <<= 11; 01337 Value |= op1; 01338 break; 01339 } 01340 case PPC::FMRSD: { 01341 DEBUG(std::cerr << "Emitting FMRSD\n"); 01342 Value = 4227858576U; 01343 01344 // op0: RST 01345 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01346 op0 &= (1<<5) - 1; 01347 op0 <<= 21; 01348 Value |= op0; 01349 // op1: B 01350 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01351 op1 &= (1<<5) - 1; 01352 op1 <<= 11; 01353 Value |= op1; 01354 break; 01355 } 01356 case PPC::FMSUB: { 01357 DEBUG(std::cerr << "Emitting FMSUB\n"); 01358 Value = 4227858488U; 01359 01360 // op0: FRT 01361 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01362 op0 &= (1<<5) - 1; 01363 op0 <<= 21; 01364 Value |= op0; 01365 // op1: FRA 01366 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01367 op1 &= (1<<5) - 1; 01368 op1 <<= 16; 01369 Value |= op1; 01370 // op2: FRC 01371 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01372 op2 &= (1<<5) - 1; 01373 op2 <<= 6; 01374 Value |= op2; 01375 // op3: FRB 01376 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01377 op3 &= (1<<5) - 1; 01378 op3 <<= 11; 01379 Value |= op3; 01380 break; 01381 } 01382 case PPC::FMSUBS: { 01383 DEBUG(std::cerr << "Emitting FMSUBS\n"); 01384 Value = 3959423032U; 01385 01386 // op0: FRT 01387 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01388 op0 &= (1<<5) - 1; 01389 op0 <<= 21; 01390 Value |= op0; 01391 // op1: FRA 01392 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01393 op1 &= (1<<5) - 1; 01394 op1 <<= 16; 01395 Value |= op1; 01396 // op2: FRC 01397 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01398 op2 &= (1<<5) - 1; 01399 op2 <<= 6; 01400 Value |= op2; 01401 // op3: FRB 01402 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01403 op3 &= (1<<5) - 1; 01404 op3 <<= 11; 01405 Value |= op3; 01406 break; 01407 } 01408 case PPC::FMUL: { 01409 DEBUG(std::cerr << "Emitting FMUL\n"); 01410 Value = 4227858482U; 01411 01412 // op0: FRT 01413 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01414 op0 &= (1<<5) - 1; 01415 op0 <<= 21; 01416 Value |= op0; 01417 // op1: FRA 01418 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01419 op1 &= (1<<5) - 1; 01420 op1 <<= 16; 01421 Value |= op1; 01422 // op2: FRC 01423 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01424 op2 &= (1<<5) - 1; 01425 op2 <<= 6; 01426 Value |= op2; 01427 break; 01428 } 01429 case PPC::FMULS: { 01430 DEBUG(std::cerr << "Emitting FMULS\n"); 01431 Value = 3959423026U; 01432 01433 // op0: FRT 01434 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01435 op0 &= (1<<5) - 1; 01436 op0 <<= 21; 01437 Value |= op0; 01438 // op1: FRA 01439 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01440 op1 &= (1<<5) - 1; 01441 op1 <<= 16; 01442 Value |= op1; 01443 // op2: FRC 01444 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01445 op2 &= (1<<5) - 1; 01446 op2 <<= 6; 01447 Value |= op2; 01448 break; 01449 } 01450 case PPC::FNABSD: { 01451 DEBUG(std::cerr << "Emitting FNABSD\n"); 01452 Value = 4227858704U; 01453 01454 // op0: RST 01455 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01456 op0 &= (1<<5) - 1; 01457 op0 <<= 21; 01458 Value |= op0; 01459 // op1: B 01460 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01461 op1 &= (1<<5) - 1; 01462 op1 <<= 11; 01463 Value |= op1; 01464 break; 01465 } 01466 case PPC::FNABSS: { 01467 DEBUG(std::cerr << "Emitting FNABSS\n"); 01468 Value = 4227858704U; 01469 01470 // op0: RST 01471 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01472 op0 &= (1<<5) - 1; 01473 op0 <<= 21; 01474 Value |= op0; 01475 // op1: B 01476 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01477 op1 &= (1<<5) - 1; 01478 op1 <<= 11; 01479 Value |= op1; 01480 break; 01481 } 01482 case PPC::FNEGD: { 01483 DEBUG(std::cerr << "Emitting FNEGD\n"); 01484 Value = 4227858512U; 01485 01486 // op0: RST 01487 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01488 op0 &= (1<<5) - 1; 01489 op0 <<= 21; 01490 Value |= op0; 01491 // op1: B 01492 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01493 op1 &= (1<<5) - 1; 01494 op1 <<= 11; 01495 Value |= op1; 01496 break; 01497 } 01498 case PPC::FNEGS: { 01499 DEBUG(std::cerr << "Emitting FNEGS\n"); 01500 Value = 4227858512U; 01501 01502 // op0: RST 01503 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01504 op0 &= (1<<5) - 1; 01505 op0 <<= 21; 01506 Value |= op0; 01507 // op1: B 01508 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01509 op1 &= (1<<5) - 1; 01510 op1 <<= 11; 01511 Value |= op1; 01512 break; 01513 } 01514 case PPC::FNMADD: { 01515 DEBUG(std::cerr << "Emitting FNMADD\n"); 01516 Value = 4227858494U; 01517 01518 // op0: FRT 01519 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01520 op0 &= (1<<5) - 1; 01521 op0 <<= 21; 01522 Value |= op0; 01523 // op1: FRA 01524 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01525 op1 &= (1<<5) - 1; 01526 op1 <<= 16; 01527 Value |= op1; 01528 // op2: FRC 01529 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01530 op2 &= (1<<5) - 1; 01531 op2 <<= 6; 01532 Value |= op2; 01533 // op3: FRB 01534 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01535 op3 &= (1<<5) - 1; 01536 op3 <<= 11; 01537 Value |= op3; 01538 break; 01539 } 01540 case PPC::FNMADDS: { 01541 DEBUG(std::cerr << "Emitting FNMADDS\n"); 01542 Value = 3959423038U; 01543 01544 // op0: FRT 01545 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01546 op0 &= (1<<5) - 1; 01547 op0 <<= 21; 01548 Value |= op0; 01549 // op1: FRA 01550 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01551 op1 &= (1<<5) - 1; 01552 op1 <<= 16; 01553 Value |= op1; 01554 // op2: FRC 01555 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01556 op2 &= (1<<5) - 1; 01557 op2 <<= 6; 01558 Value |= op2; 01559 // op3: FRB 01560 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01561 op3 &= (1<<5) - 1; 01562 op3 <<= 11; 01563 Value |= op3; 01564 break; 01565 } 01566 case PPC::FNMSUB: { 01567 DEBUG(std::cerr << "Emitting FNMSUB\n"); 01568 Value = 4227858492U; 01569 01570 // op0: FRT 01571 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01572 op0 &= (1<<5) - 1; 01573 op0 <<= 21; 01574 Value |= op0; 01575 // op1: FRA 01576 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01577 op1 &= (1<<5) - 1; 01578 op1 <<= 16; 01579 Value |= op1; 01580 // op2: FRC 01581 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01582 op2 &= (1<<5) - 1; 01583 op2 <<= 6; 01584 Value |= op2; 01585 // op3: FRB 01586 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01587 op3 &= (1<<5) - 1; 01588 op3 <<= 11; 01589 Value |= op3; 01590 break; 01591 } 01592 case PPC::FNMSUBS: { 01593 DEBUG(std::cerr << "Emitting FNMSUBS\n"); 01594 Value = 3959423036U; 01595 01596 // op0: FRT 01597 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01598 op0 &= (1<<5) - 1; 01599 op0 <<= 21; 01600 Value |= op0; 01601 // op1: FRA 01602 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01603 op1 &= (1<<5) - 1; 01604 op1 <<= 16; 01605 Value |= op1; 01606 // op2: FRC 01607 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01608 op2 &= (1<<5) - 1; 01609 op2 <<= 6; 01610 Value |= op2; 01611 // op3: FRB 01612 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01613 op3 &= (1<<5) - 1; 01614 op3 <<= 11; 01615 Value |= op3; 01616 break; 01617 } 01618 case PPC::FRSP: { 01619 DEBUG(std::cerr << "Emitting FRSP\n"); 01620 Value = 4227858456U; 01621 01622 // op0: RST 01623 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01624 op0 &= (1<<5) - 1; 01625 op0 <<= 21; 01626 Value |= op0; 01627 // op1: B 01628 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01629 op1 &= (1<<5) - 1; 01630 op1 <<= 11; 01631 Value |= op1; 01632 break; 01633 } 01634 case PPC::FSELD: { 01635 DEBUG(std::cerr << "Emitting FSELD\n"); 01636 Value = 4227858478U; 01637 01638 // op0: FRT 01639 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01640 op0 &= (1<<5) - 1; 01641 op0 <<= 21; 01642 Value |= op0; 01643 // op1: FRA 01644 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01645 op1 &= (1<<5) - 1; 01646 op1 <<= 16; 01647 Value |= op1; 01648 // op2: FRC 01649 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01650 op2 &= (1<<5) - 1; 01651 op2 <<= 6; 01652 Value |= op2; 01653 // op3: FRB 01654 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01655 op3 &= (1<<5) - 1; 01656 op3 <<= 11; 01657 Value |= op3; 01658 break; 01659 } 01660 case PPC::FSELS: { 01661 DEBUG(std::cerr << "Emitting FSELS\n"); 01662 Value = 4227858478U; 01663 01664 // op0: FRT 01665 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01666 op0 &= (1<<5) - 1; 01667 op0 <<= 21; 01668 Value |= op0; 01669 // op1: FRA 01670 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01671 op1 &= (1<<5) - 1; 01672 op1 <<= 16; 01673 Value |= op1; 01674 // op2: FRC 01675 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01676 op2 &= (1<<5) - 1; 01677 op2 <<= 6; 01678 Value |= op2; 01679 // op3: FRB 01680 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 01681 op3 &= (1<<5) - 1; 01682 op3 <<= 11; 01683 Value |= op3; 01684 break; 01685 } 01686 case PPC::FSQRT: { 01687 DEBUG(std::cerr << "Emitting FSQRT\n"); 01688 Value = 4227858476U; 01689 01690 // op0: RST 01691 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01692 op0 &= (1<<5) - 1; 01693 op0 <<= 21; 01694 Value |= op0; 01695 // op1: B 01696 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01697 op1 &= (1<<5) - 1; 01698 op1 <<= 11; 01699 Value |= op1; 01700 break; 01701 } 01702 case PPC::FSQRTS: { 01703 DEBUG(std::cerr << "Emitting FSQRTS\n"); 01704 Value = 3959423020U; 01705 01706 // op0: RST 01707 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01708 op0 &= (1<<5) - 1; 01709 op0 <<= 21; 01710 Value |= op0; 01711 // op1: B 01712 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01713 op1 &= (1<<5) - 1; 01714 op1 <<= 11; 01715 Value |= op1; 01716 break; 01717 } 01718 case PPC::FSUB: { 01719 DEBUG(std::cerr << "Emitting FSUB\n"); 01720 Value = 4227858472U; 01721 01722 // op0: FRT 01723 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01724 op0 &= (1<<5) - 1; 01725 op0 <<= 21; 01726 Value |= op0; 01727 // op1: FRA 01728 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01729 op1 &= (1<<5) - 1; 01730 op1 <<= 16; 01731 Value |= op1; 01732 // op2: FRB 01733 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01734 op2 &= (1<<5) - 1; 01735 op2 <<= 11; 01736 Value |= op2; 01737 break; 01738 } 01739 case PPC::FSUBS: { 01740 DEBUG(std::cerr << "Emitting FSUBS\n"); 01741 Value = 3959423016U; 01742 01743 // op0: FRT 01744 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01745 op0 &= (1<<5) - 1; 01746 op0 <<= 21; 01747 Value |= op0; 01748 // op1: FRA 01749 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01750 op1 &= (1<<5) - 1; 01751 op1 <<= 16; 01752 Value |= op1; 01753 // op2: FRB 01754 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01755 op2 &= (1<<5) - 1; 01756 op2 <<= 11; 01757 Value |= op2; 01758 break; 01759 } 01760 case PPC::IMPLICIT_DEF_F4: { 01761 DEBUG(std::cerr << "Emitting IMPLICIT_DEF_F4\n"); 01762 Value = 0U; 01763 01764 break; 01765 } 01766 case PPC::IMPLICIT_DEF_F8: { 01767 DEBUG(std::cerr << "Emitting IMPLICIT_DEF_F8\n"); 01768 Value = 0U; 01769 01770 break; 01771 } 01772 case PPC::IMPLICIT_DEF_GPR: { 01773 DEBUG(std::cerr << "Emitting IMPLICIT_DEF_GPR\n"); 01774 Value = 0U; 01775 01776 break; 01777 } 01778 case PPC::IMPLICIT_DEF_VRRC: { 01779 DEBUG(std::cerr << "Emitting IMPLICIT_DEF_VRRC\n"); 01780 Value = 0U; 01781 01782 break; 01783 } 01784 case PPC::LA: { 01785 DEBUG(std::cerr << "Emitting LA\n"); 01786 Value = 939524096U; 01787 01788 // op0: A 01789 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01790 op0 &= (1<<5) - 1; 01791 op0 <<= 21; 01792 Value |= op0; 01793 // op1: B 01794 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01795 op1 &= (1<<5) - 1; 01796 op1 <<= 16; 01797 Value |= op1; 01798 // op2: C 01799 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01800 op2 &= (1<<16) - 1; 01801 Value |= op2; 01802 break; 01803 } 01804 case PPC::LBZ: { 01805 DEBUG(std::cerr << "Emitting LBZ\n"); 01806 Value = 2281701376U; 01807 01808 // op0: A 01809 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01810 op0 &= (1<<5) - 1; 01811 op0 <<= 21; 01812 Value |= op0; 01813 // op1: C 01814 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01815 op1 &= (1<<16) - 1; 01816 Value |= op1; 01817 // op2: B 01818 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01819 op2 &= (1<<5) - 1; 01820 op2 <<= 16; 01821 Value |= op2; 01822 break; 01823 } 01824 case PPC::LBZX: { 01825 DEBUG(std::cerr << "Emitting LBZX\n"); 01826 Value = 2080374958U; 01827 01828 // op0: RST 01829 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01830 op0 &= (1<<5) - 1; 01831 op0 <<= 21; 01832 Value |= op0; 01833 // op1: A 01834 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01835 op1 &= (1<<5) - 1; 01836 op1 <<= 16; 01837 Value |= op1; 01838 // op2: B 01839 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01840 op2 &= (1<<5) - 1; 01841 op2 <<= 11; 01842 Value |= op2; 01843 break; 01844 } 01845 case PPC::LD: { 01846 DEBUG(std::cerr << "Emitting LD\n"); 01847 Value = 3892314112U; 01848 01849 // op0: RST 01850 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01851 op0 &= (1<<5) - 1; 01852 op0 <<= 21; 01853 Value |= op0; 01854 // op1: DS 01855 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01856 op1 &= (1<<14) - 1; 01857 op1 <<= 2; 01858 Value |= op1; 01859 // op2: RA 01860 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01861 op2 &= (1<<5) - 1; 01862 op2 <<= 16; 01863 Value |= op2; 01864 break; 01865 } 01866 case PPC::LDX: { 01867 DEBUG(std::cerr << "Emitting LDX\n"); 01868 Value = 2080374826U; 01869 01870 // op0: RST 01871 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01872 op0 &= (1<<5) - 1; 01873 op0 <<= 21; 01874 Value |= op0; 01875 // op1: A 01876 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01877 op1 &= (1<<5) - 1; 01878 op1 <<= 16; 01879 Value |= op1; 01880 // op2: B 01881 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01882 op2 &= (1<<5) - 1; 01883 op2 <<= 11; 01884 Value |= op2; 01885 break; 01886 } 01887 case PPC::LFD: { 01888 DEBUG(std::cerr << "Emitting LFD\n"); 01889 Value = 3355443200U; 01890 01891 // op0: A 01892 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01893 op0 &= (1<<5) - 1; 01894 op0 <<= 21; 01895 Value |= op0; 01896 // op1: C 01897 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01898 op1 &= (1<<16) - 1; 01899 Value |= op1; 01900 // op2: B 01901 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01902 op2 &= (1<<5) - 1; 01903 op2 <<= 16; 01904 Value |= op2; 01905 break; 01906 } 01907 case PPC::LFDX: { 01908 DEBUG(std::cerr << "Emitting LFDX\n"); 01909 Value = 2080375982U; 01910 01911 // op0: RST 01912 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01913 op0 &= (1<<5) - 1; 01914 op0 <<= 21; 01915 Value |= op0; 01916 // op1: A 01917 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01918 op1 &= (1<<5) - 1; 01919 op1 <<= 16; 01920 Value |= op1; 01921 // op2: B 01922 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01923 op2 &= (1<<5) - 1; 01924 op2 <<= 11; 01925 Value |= op2; 01926 break; 01927 } 01928 case PPC::LFS: { 01929 DEBUG(std::cerr << "Emitting LFS\n"); 01930 Value = 3221225472U; 01931 01932 // op0: A 01933 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01934 op0 &= (1<<5) - 1; 01935 op0 <<= 21; 01936 Value |= op0; 01937 // op1: C 01938 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01939 op1 &= (1<<16) - 1; 01940 Value |= op1; 01941 // op2: B 01942 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01943 op2 &= (1<<5) - 1; 01944 op2 <<= 16; 01945 Value |= op2; 01946 break; 01947 } 01948 case PPC::LFSX: { 01949 DEBUG(std::cerr << "Emitting LFSX\n"); 01950 Value = 2080375854U; 01951 01952 // op0: RST 01953 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01954 op0 &= (1<<5) - 1; 01955 op0 <<= 21; 01956 Value |= op0; 01957 // op1: A 01958 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01959 op1 &= (1<<5) - 1; 01960 op1 <<= 16; 01961 Value |= op1; 01962 // op2: B 01963 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01964 op2 &= (1<<5) - 1; 01965 op2 <<= 11; 01966 Value |= op2; 01967 break; 01968 } 01969 case PPC::LHA: { 01970 DEBUG(std::cerr << "Emitting LHA\n"); 01971 Value = 2818572288U; 01972 01973 // op0: A 01974 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01975 op0 &= (1<<5) - 1; 01976 op0 <<= 21; 01977 Value |= op0; 01978 // op1: C 01979 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01980 op1 &= (1<<16) - 1; 01981 Value |= op1; 01982 // op2: B 01983 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01984 op2 &= (1<<5) - 1; 01985 op2 <<= 16; 01986 Value |= op2; 01987 break; 01988 } 01989 case PPC::LHAX: { 01990 DEBUG(std::cerr << "Emitting LHAX\n"); 01991 Value = 2080375470U; 01992 01993 // op0: RST 01994 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01995 op0 &= (1<<5) - 1; 01996 op0 <<= 21; 01997 Value |= op0; 01998 // op1: A 01999 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02000 op1 &= (1<<5) - 1; 02001 op1 <<= 16; 02002 Value |= op1; 02003 // op2: B 02004 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02005 op2 &= (1<<5) - 1; 02006 op2 <<= 11; 02007 Value |= op2; 02008 break; 02009 } 02010 case PPC::LHZ: { 02011 DEBUG(std::cerr << "Emitting LHZ\n"); 02012 Value = 2684354560U; 02013 02014 // op0: A 02015 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02016 op0 &= (1<<5) - 1; 02017 op0 <<= 21; 02018 Value |= op0; 02019 // op1: C 02020 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02021 op1 &= (1<<16) - 1; 02022 Value |= op1; 02023 // op2: B 02024 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02025 op2 &= (1<<5) - 1; 02026 op2 <<= 16; 02027 Value |= op2; 02028 break; 02029 } 02030 case PPC::LHZX: { 02031 DEBUG(std::cerr << "Emitting LHZX\n"); 02032 Value = 2080375342U; 02033 02034 // op0: RST 02035 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02036 op0 &= (1<<5) - 1; 02037 op0 <<= 21; 02038 Value |= op0; 02039 // op1: A 02040 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02041 op1 &= (1<<5) - 1; 02042 op1 <<= 16; 02043 Value |= op1; 02044 // op2: B 02045 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02046 op2 &= (1<<5) - 1; 02047 op2 <<= 11; 02048 Value |= op2; 02049 break; 02050 } 02051 case PPC::LI: { 02052 DEBUG(std::cerr << "Emitting LI\n"); 02053 Value = 939524096U; 02054 02055 // op0: A 02056 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02057 op0 &= (1<<5) - 1; 02058 op0 <<= 21; 02059 Value |= op0; 02060 // op1: B 02061 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02062 op1 &= (1<<16) - 1; 02063 Value |= op1; 02064 break; 02065 } 02066 case PPC::LIS: { 02067 DEBUG(std::cerr << "Emitting LIS\n"); 02068 Value = 1006632960U; 02069 02070 // op0: A 02071 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02072 op0 &= (1<<5) - 1; 02073 op0 <<= 21; 02074 Value |= op0; 02075 // op1: B 02076 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02077 op1 &= (1<<16) - 1; 02078 Value |= op1; 02079 break; 02080 } 02081 case PPC::LVEBX: { 02082 DEBUG(std::cerr << "Emitting LVEBX\n"); 02083 Value = 2080374798U; 02084 02085 // op0: RST 02086 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02087 op0 &= (1<<5) - 1; 02088 op0 <<= 21; 02089 Value |= op0; 02090 // op1: A 02091 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02092 op1 &= (1<<5) - 1; 02093 op1 <<= 16; 02094 Value |= op1; 02095 // op2: B 02096 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02097 op2 &= (1<<5) - 1; 02098 op2 <<= 11; 02099 Value |= op2; 02100 break; 02101 } 02102 case PPC::LVEHX: { 02103 DEBUG(std::cerr << "Emitting LVEHX\n"); 02104 Value = 2080374862U; 02105 02106 // op0: RST 02107 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02108 op0 &= (1<<5) - 1; 02109 op0 <<= 21; 02110 Value |= op0; 02111 // op1: A 02112 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02113 op1 &= (1<<5) - 1; 02114 op1 <<= 16; 02115 Value |= op1; 02116 // op2: B 02117 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02118 op2 &= (1<<5) - 1; 02119 op2 <<= 11; 02120 Value |= op2; 02121 break; 02122 } 02123 case PPC::LVEWX: { 02124 DEBUG(std::cerr << "Emitting LVEWX\n"); 02125 Value = 2080374926U; 02126 02127 // op0: RST 02128 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02129 op0 &= (1<<5) - 1; 02130 op0 <<= 21; 02131 Value |= op0; 02132 // op1: A 02133 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02134 op1 &= (1<<5) - 1; 02135 op1 <<= 16; 02136 Value |= op1; 02137 // op2: B 02138 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02139 op2 &= (1<<5) - 1; 02140 op2 <<= 11; 02141 Value |= op2; 02142 break; 02143 } 02144 case PPC::LVSL: { 02145 DEBUG(std::cerr << "Emitting LVSL\n"); 02146 Value = 2080374796U; 02147 02148 // op0: RST 02149 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02150 op0 &= (1<<5) - 1; 02151 op0 <<= 21; 02152 Value |= op0; 02153 // op1: A 02154 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02155 op1 &= (1<<5) - 1; 02156 op1 <<= 16; 02157 Value |= op1; 02158 // op2: B 02159 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02160 op2 &= (1<<5) - 1; 02161 op2 <<= 11; 02162 Value |= op2; 02163 break; 02164 } 02165 case PPC::LVSR: { 02166 DEBUG(std::cerr << "Emitting LVSR\n"); 02167 Value = 2080374860U; 02168 02169 // op0: RST 02170 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02171 op0 &= (1<<5) - 1; 02172 op0 <<= 21; 02173 Value |= op0; 02174 // op1: A 02175 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02176 op1 &= (1<<5) - 1; 02177 op1 <<= 16; 02178 Value |= op1; 02179 // op2: B 02180 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02181 op2 &= (1<<5) - 1; 02182 op2 <<= 11; 02183 Value |= op2; 02184 break; 02185 } 02186 case PPC::LVX: { 02187 DEBUG(std::cerr << "Emitting LVX\n"); 02188 Value = 2080374990U; 02189 02190 // op0: RST 02191 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02192 op0 &= (1<<5) - 1; 02193 op0 <<= 21; 02194 Value |= op0; 02195 // op1: A 02196 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02197 op1 &= (1<<5) - 1; 02198 op1 <<= 16; 02199 Value |= op1; 02200 // op2: B 02201 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02202 op2 &= (1<<5) - 1; 02203 op2 <<= 11; 02204 Value |= op2; 02205 break; 02206 } 02207 case PPC::LVXL: { 02208 DEBUG(std::cerr << "Emitting LVXL\n"); 02209 Value = 2080375502U; 02210 02211 // op0: RST 02212 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02213 op0 &= (1<<5) - 1; 02214 op0 <<= 21; 02215 Value |= op0; 02216 // op1: A 02217 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02218 op1 &= (1<<5) - 1; 02219 op1 <<= 16; 02220 Value |= op1; 02221 // op2: B 02222 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02223 op2 &= (1<<5) - 1; 02224 op2 <<= 11; 02225 Value |= op2; 02226 break; 02227 } 02228 case PPC::LWA: { 02229 DEBUG(std::cerr << "Emitting LWA\n"); 02230 Value = 3892314114U; 02231 02232 // op0: RST 02233 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02234 op0 &= (1<<5) - 1; 02235 op0 <<= 21; 02236 Value |= op0; 02237 // op1: DS 02238 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02239 op1 &= (1<<14) - 1; 02240 op1 <<= 2; 02241 Value |= op1; 02242 // op2: RA 02243 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02244 op2 &= (1<<5) - 1; 02245 op2 <<= 16; 02246 Value |= op2; 02247 break; 02248 } 02249 case PPC::LWAX: { 02250 DEBUG(std::cerr << "Emitting LWAX\n"); 02251 Value = 2080375466U; 02252 02253 // op0: RST 02254 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02255 op0 &= (1<<5) - 1; 02256 op0 <<= 21; 02257 Value |= op0; 02258 // op1: A 02259 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02260 op1 &= (1<<5) - 1; 02261 op1 <<= 16; 02262 Value |= op1; 02263 // op2: B 02264 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02265 op2 &= (1<<5) - 1; 02266 op2 <<= 11; 02267 Value |= op2; 02268 break; 02269 } 02270 case PPC::LWZ: { 02271 DEBUG(std::cerr << "Emitting LWZ\n"); 02272 Value = 2147483648U; 02273 02274 // op0: A 02275 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02276 op0 &= (1<<5) - 1; 02277 op0 <<= 21; 02278 Value |= op0; 02279 // op1: C 02280 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02281 op1 &= (1<<16) - 1; 02282 Value |= op1; 02283 // op2: B 02284 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02285 op2 &= (1<<5) - 1; 02286 op2 <<= 16; 02287 Value |= op2; 02288 break; 02289 } 02290 case PPC::LWZU: { 02291 DEBUG(std::cerr << "Emitting LWZU\n"); 02292 Value = 2348810240U; 02293 02294 // op0: A 02295 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02296 op0 &= (1<<5) - 1; 02297 op0 <<= 21; 02298 Value |= op0; 02299 // op1: C 02300 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02301 op1 &= (1<<16) - 1; 02302 Value |= op1; 02303 // op2: B 02304 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02305 op2 &= (1<<5) - 1; 02306 op2 <<= 16; 02307 Value |= op2; 02308 break; 02309 } 02310 case PPC::LWZX: { 02311 DEBUG(std::cerr << "Emitting LWZX\n"); 02312 Value = 2080374830U; 02313 02314 // op0: RST 02315 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02316 op0 &= (1<<5) - 1; 02317 op0 <<= 21; 02318 Value |= op0; 02319 // op1: A 02320 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02321 op1 &= (1<<5) - 1; 02322 op1 <<= 16; 02323 Value |= op1; 02324 // op2: B 02325 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02326 op2 &= (1<<5) - 1; 02327 op2 <<= 11; 02328 Value |= op2; 02329 break; 02330 } 02331 case PPC::MCRF: { 02332 DEBUG(std::cerr << "Emitting MCRF\n"); 02333 Value = 1275068416U; 02334 02335 // op0: BF 02336 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02337 op0 &= (1<<3) - 1; 02338 op0 <<= 23; 02339 Value |= op0; 02340 // op1: BFA 02341 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02342 op1 &= (1<<3) - 1; 02343 op1 <<= 18; 02344 Value |= op1; 02345 break; 02346 } 02347 case PPC::MFCR: { 02348 DEBUG(std::cerr << "Emitting MFCR\n"); 02349 Value = 2080374822U; 02350 02351 // op0: RT 02352 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02353 op0 &= (1<<5) - 1; 02354 op0 <<= 21; 02355 Value |= op0; 02356 break; 02357 } 02358 case PPC::MFCTR: { 02359 DEBUG(std::cerr << "Emitting MFCTR\n"); 02360 Value = 2080965286U; 02361 02362 // op0: RT 02363 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02364 op0 &= (1<<5) - 1; 02365 op0 <<= 21; 02366 Value |= op0; 02367 break; 02368 } 02369 case PPC::MFLR: { 02370 DEBUG(std::cerr << "Emitting MFLR\n"); 02371 Value = 2080899750U; 02372 02373 // op0: RT 02374 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02375 op0 &= (1<<5) - 1; 02376 op0 <<= 21; 02377 Value |= op0; 02378 break; 02379 } 02380 case PPC::MFOCRF: { 02381 DEBUG(std::cerr << "Emitting MFOCRF\n"); 02382 Value = 2081423398U; 02383 02384 // op0: ST 02385 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02386 op0 &= (1<<5) - 1; 02387 op0 <<= 21; 02388 Value |= op0; 02389 // op1: FXM 02390 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02391 op1 &= (1<<8) - 1; 02392 op1 <<= 12; 02393 Value |= op1; 02394 break; 02395 } 02396 case PPC::MFVRSAVE: { 02397 DEBUG(std::cerr << "Emitting MFVRSAVE\n"); 02398 Value = 2080391846U; 02399 02400 // op0: RT 02401 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02402 op0 &= (1<<5) - 1; 02403 op0 <<= 21; 02404 Value |= op0; 02405 break; 02406 } 02407 case PPC::MFVSCR: { 02408 DEBUG(std::cerr << "Emitting MFVSCR\n"); 02409 Value = 268436996U; 02410 02411 // op0: VD 02412 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02413 op0 &= (1<<5) - 1; 02414 op0 <<= 21; 02415 Value |= op0; 02416 break; 02417 } 02418 case PPC::MTCRF: { 02419 DEBUG(std::cerr << "Emitting MTCRF\n"); 02420 Value = 2080375072U; 02421 02422 // op0: FXM 02423 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02424 op0 &= (1<<8) - 1; 02425 op0 <<= 12; 02426 Value |= op0; 02427 // op1: ST 02428 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02429 op1 &= (1<<5) - 1; 02430 op1 <<= 21; 02431 Value |= op1; 02432 break; 02433 } 02434 case PPC::MTCTR: { 02435 DEBUG(std::cerr << "Emitting MTCTR\n"); 02436 Value = 2080965542U; 02437 02438 // op0: RT 02439 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02440 op0 &= (1<<5) - 1; 02441 op0 <<= 21; 02442 Value |= op0; 02443 break; 02444 } 02445 case PPC::MTLR: { 02446 DEBUG(std::cerr << "Emitting MTLR\n"); 02447 Value = 2080900006U; 02448 02449 // op0: RT 02450 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02451 op0 &= (1<<5) - 1; 02452 op0 <<= 21; 02453 Value |= op0; 02454 break; 02455 } 02456 case PPC::MTVRSAVE: { 02457 DEBUG(std::cerr << "Emitting MTVRSAVE\n"); 02458 Value = 2080392102U; 02459 02460 // op0: RT 02461 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02462 op0 &= (1<<5) - 1; 02463 op0 <<= 21; 02464 Value |= op0; 02465 break; 02466 } 02467 case PPC::MTVSCR: { 02468 DEBUG(std::cerr << "Emitting MTVSCR\n"); 02469 Value = 268437060U; 02470 02471 // op0: VB 02472 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02473 op0 &= (1<<5) - 1; 02474 op0 <<= 11; 02475 Value |= op0; 02476 break; 02477 } 02478 case PPC::MULHD: { 02479 DEBUG(std::cerr << "Emitting MULHD\n"); 02480 Value = 2080374930U; 02481 02482 // op0: RT 02483 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02484 op0 &= (1<<5) - 1; 02485 op0 <<= 21; 02486 Value |= op0; 02487 // op1: RA 02488 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02489 op1 &= (1<<5) - 1; 02490 op1 <<= 16; 02491 Value |= op1; 02492 // op2: RB 02493 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02494 op2 &= (1<<5) - 1; 02495 op2 <<= 11; 02496 Value |= op2; 02497 break; 02498 } 02499 case PPC::MULHDU: { 02500 DEBUG(std::cerr << "Emitting MULHDU\n"); 02501 Value = 2080374802U; 02502 02503 // op0: RT 02504 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02505 op0 &= (1<<5) - 1; 02506 op0 <<= 21; 02507 Value |= op0; 02508 // op1: RA 02509 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02510 op1 &= (1<<5) - 1; 02511 op1 <<= 16; 02512 Value |= op1; 02513 // op2: RB 02514 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02515 op2 &= (1<<5) - 1; 02516 op2 <<= 11; 02517 Value |= op2; 02518 break; 02519 } 02520 case PPC::MULHW: { 02521 DEBUG(std::cerr << "Emitting MULHW\n"); 02522 Value = 2080374934U; 02523 02524 // op0: RT 02525 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02526 op0 &= (1<<5) - 1; 02527 op0 <<= 21; 02528 Value |= op0; 02529 // op1: RA 02530 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02531 op1 &= (1<<5) - 1; 02532 op1 <<= 16; 02533 Value |= op1; 02534 // op2: RB 02535 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02536 op2 &= (1<<5) - 1; 02537 op2 <<= 11; 02538 Value |= op2; 02539 break; 02540 } 02541 case PPC::MULHWU: { 02542 DEBUG(std::cerr << "Emitting MULHWU\n"); 02543 Value = 2080374806U; 02544 02545 // op0: RT 02546 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02547 op0 &= (1<<5) - 1; 02548 op0 <<= 21; 02549 Value |= op0; 02550 // op1: RA 02551 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02552 op1 &= (1<<5) - 1; 02553 op1 <<= 16; 02554 Value |= op1; 02555 // op2: RB 02556 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02557 op2 &= (1<<5) - 1; 02558 op2 <<= 11; 02559 Value |= op2; 02560 break; 02561 } 02562 case PPC::MULLD: { 02563 DEBUG(std::cerr << "Emitting MULLD\n"); 02564 Value = 2080375250U; 02565 02566 // op0: RT 02567 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02568 op0 &= (1<<5) - 1; 02569 op0 <<= 21; 02570 Value |= op0; 02571 // op1: RA 02572 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02573 op1 &= (1<<5) - 1; 02574 op1 <<= 16; 02575 Value |= op1; 02576 // op2: RB 02577 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02578 op2 &= (1<<5) - 1; 02579 op2 <<= 11; 02580 Value |= op2; 02581 break; 02582 } 02583 case PPC::MULLI: { 02584 DEBUG(std::cerr << "Emitting MULLI\n"); 02585 Value = 469762048U; 02586 02587 // op0: A 02588 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02589 op0 &= (1<<5) - 1; 02590 op0 <<= 21; 02591 Value |= op0; 02592 // op1: B 02593 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02594 op1 &= (1<<5) - 1; 02595 op1 <<= 16; 02596 Value |= op1; 02597 // op2: C 02598 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02599 op2 &= (1<<16) - 1; 02600 Value |= op2; 02601 break; 02602 } 02603 case PPC::MULLW: { 02604 DEBUG(std::cerr << "Emitting MULLW\n"); 02605 Value = 2080375254U; 02606 02607 // op0: RT 02608 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02609 op0 &= (1<<5) - 1; 02610 op0 <<= 21; 02611 Value |= op0; 02612 // op1: RA 02613 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02614 op1 &= (1<<5) - 1; 02615 op1 <<= 16; 02616 Value |= op1; 02617 // op2: RB 02618 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02619 op2 &= (1<<5) - 1; 02620 op2 <<= 11; 02621 Value |= op2; 02622 break; 02623 } 02624 case PPC::MovePCtoLR: { 02625 DEBUG(std::cerr << "Emitting MovePCtoLR\n"); 02626 Value = 0U; 02627 02628 break; 02629 } 02630 case PPC::NAND: { 02631 DEBUG(std::cerr << "Emitting NAND\n"); 02632 Value = 2080375736U; 02633 02634 // op0: A 02635 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02636 op0 &= (1<<5) - 1; 02637 op0 <<= 16; 02638 Value |= op0; 02639 // op1: RST 02640 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02641 op1 &= (1<<5) - 1; 02642 op1 <<= 21; 02643 Value |= op1; 02644 // op2: B 02645 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02646 op2 &= (1<<5) - 1; 02647 op2 <<= 11; 02648 Value |= op2; 02649 break; 02650 } 02651 case PPC::NEG: { 02652 DEBUG(std::cerr << "Emitting NEG\n"); 02653 Value = 2080374992U; 02654 02655 // op0: RT 02656 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02657 op0 &= (1<<5) - 1; 02658 op0 <<= 21; 02659 Value |= op0; 02660 // op1: RA 02661 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02662 op1 &= (1<<5) - 1; 02663 op1 <<= 16; 02664 Value |= op1; 02665 break; 02666 } 02667 case PPC::NOP: { 02668 DEBUG(std::cerr << "Emitting NOP\n"); 02669 Value = 1610612736U; 02670 02671 break; 02672 } 02673 case PPC::NOR: { 02674 DEBUG(std::cerr << "Emitting NOR\n"); 02675 Value = 2080375032U; 02676 02677 // op0: A 02678 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02679 op0 &= (1<<5) - 1; 02680 op0 <<= 16; 02681 Value |= op0; 02682 // op1: RST 02683 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02684 op1 &= (1<<5) - 1; 02685 op1 <<= 21; 02686 Value |= op1; 02687 // op2: B 02688 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02689 op2 &= (1<<5) - 1; 02690 op2 <<= 11; 02691 Value |= op2; 02692 break; 02693 } 02694 case PPC::OR4: { 02695 DEBUG(std::cerr << "Emitting OR4\n"); 02696 Value = 2080375672U; 02697 02698 // op0: A 02699 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02700 op0 &= (1<<5) - 1; 02701 op0 <<= 16; 02702 Value |= op0; 02703 // op1: RST 02704 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02705 op1 &= (1<<5) - 1; 02706 op1 <<= 21; 02707 Value |= op1; 02708 // op2: B 02709 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02710 op2 &= (1<<5) - 1; 02711 op2 <<= 11; 02712 Value |= op2; 02713 break; 02714 } 02715 case PPC::OR4To8: { 02716 DEBUG(std::cerr << "Emitting OR4To8\n"); 02717 Value = 2080375672U; 02718 02719 // op0: A 02720 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02721 op0 &= (1<<5) - 1; 02722 op0 <<= 16; 02723 Value |= op0; 02724 // op1: RST 02725 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02726 op1 &= (1<<5) - 1; 02727 op1 <<= 21; 02728 Value |= op1; 02729 // op2: B 02730 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02731 op2 &= (1<<5) - 1; 02732 op2 <<= 11; 02733 Value |= op2; 02734 break; 02735 } 02736 case PPC::OR8: { 02737 DEBUG(std::cerr << "Emitting OR8\n"); 02738 Value = 2080375672U; 02739 02740 // op0: A 02741 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02742 op0 &= (1<<5) - 1; 02743 op0 <<= 16; 02744 Value |= op0; 02745 // op1: RST 02746 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02747 op1 &= (1<<5) - 1; 02748 op1 <<= 21; 02749 Value |= op1; 02750 // op2: B 02751 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02752 op2 &= (1<<5) - 1; 02753 op2 <<= 11; 02754 Value |= op2; 02755 break; 02756 } 02757 case PPC::OR8To4: { 02758 DEBUG(std::cerr << "Emitting OR8To4\n"); 02759 Value = 2080375672U; 02760 02761 // op0: A 02762 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02763 op0 &= (1<<5) - 1; 02764 op0 <<= 16; 02765 Value |= op0; 02766 // op1: RST 02767 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02768 op1 &= (1<<5) - 1; 02769 op1 <<= 21; 02770 Value |= op1; 02771 // op2: B 02772 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02773 op2 &= (1<<5) - 1; 02774 op2 <<= 11; 02775 Value |= op2; 02776 break; 02777 } 02778 case PPC::ORC: { 02779 DEBUG(std::cerr << "Emitting ORC\n"); 02780 Value = 2080375608U; 02781 02782 // op0: A 02783 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02784 op0 &= (1<<5) - 1; 02785 op0 <<= 16; 02786 Value |= op0; 02787 // op1: RST 02788 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02789 op1 &= (1<<5) - 1; 02790 op1 <<= 21; 02791 Value |= op1; 02792 // op2: B 02793 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02794 op2 &= (1<<5) - 1; 02795 op2 <<= 11; 02796 Value |= op2; 02797 break; 02798 } 02799 case PPC::ORI: { 02800 DEBUG(std::cerr << "Emitting ORI\n"); 02801 Value = 1610612736U; 02802 02803 // op0: B 02804 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02805 op0 &= (1<<5) - 1; 02806 op0 <<= 16; 02807 Value |= op0; 02808 // op1: A 02809 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02810 op1 &= (1<<5) - 1; 02811 op1 <<= 21; 02812 Value |= op1; 02813 // op2: C 02814 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02815 op2 &= (1<<16) - 1; 02816 Value |= op2; 02817 break; 02818 } 02819 case PPC::ORIS: { 02820 DEBUG(std::cerr << "Emitting ORIS\n"); 02821 Value = 1677721600U; 02822 02823 // op0: B 02824 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02825 op0 &= (1<<5) - 1; 02826 op0 <<= 16; 02827 Value |= op0; 02828 // op1: A 02829 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02830 op1 &= (1<<5) - 1; 02831 op1 <<= 21; 02832 Value |= op1; 02833 // op2: C 02834 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02835 op2 &= (1<<16) - 1; 02836 Value |= op2; 02837 break; 02838 } 02839 case PPC::ORo: { 02840 DEBUG(std::cerr << "Emitting ORo\n"); 02841 Value = 2080375673U; 02842 02843 // op0: A 02844 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02845 op0 &= (1<<5) - 1; 02846 op0 <<= 16; 02847 Value |= op0; 02848 // op1: RST 02849 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02850 op1 &= (1<<5) - 1; 02851 op1 <<= 21; 02852 Value |= op1; 02853 // op2: B 02854 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02855 op2 &= (1<<5) - 1; 02856 op2 <<= 11; 02857 Value |= op2; 02858 break; 02859 } 02860 case PPC::RLDICL: { 02861 DEBUG(std::cerr << "Emitting RLDICL\n"); 02862 Value = 2013265920U; 02863 02864 // op0: RS 02865 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02866 op0 &= (1<<5) - 1; 02867 op0 <<= 21; 02868 Value |= op0; 02869 // op1: RA 02870 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02871 op1 &= (1<<5) - 1; 02872 op1 <<= 16; 02873 Value |= op1; 02874 // op2: SH 02875 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02876 // op3: MBE 02877 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 02878 op3 &= (1<<6) - 1; 02879 op3 <<= 5; 02880 Value |= op3; 02881 Value |= getValueBit(op2, 1) << 15; 02882 Value |= getValueBit(op2, 2) << 14; 02883 Value |= getValueBit(op2, 3) << 13; 02884 Value |= getValueBit(op2, 4) << 12; 02885 Value |= getValueBit(op2, 5) << 11; 02886 Value |= getValueBit(op2, 0) << 1; 02887 break; 02888 } 02889 case PPC::RLDICR: { 02890 DEBUG(std::cerr << "Emitting RLDICR\n"); 02891 Value = 2013265924U; 02892 02893 // op0: RS 02894 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02895 op0 &= (1<<5) - 1; 02896 op0 <<= 21; 02897 Value |= op0; 02898 // op1: RA 02899 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02900 op1 &= (1<<5) - 1; 02901 op1 <<= 16; 02902 Value |= op1; 02903 // op2: SH 02904 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02905 // op3: MBE 02906 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 02907 op3 &= (1<<6) - 1; 02908 op3 <<= 5; 02909 Value |= op3; 02910 Value |= getValueBit(op2, 1) << 15; 02911 Value |= getValueBit(op2, 2) << 14; 02912 Value |= getValueBit(op2, 3) << 13; 02913 Value |= getValueBit(op2, 4) << 12; 02914 Value |= getValueBit(op2, 5) << 11; 02915 Value |= getValueBit(op2, 0) << 1; 02916 break; 02917 } 02918 case PPC::RLDIMI: { 02919 DEBUG(std::cerr << "Emitting RLDIMI\n"); 02920 Value = 2013265932U; 02921 02922 // op0: RS 02923 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02924 op0 &= (1<<5) - 1; 02925 op0 <<= 21; 02926 Value |= op0; 02927 // op1: RA 02928 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02929 op1 &= (1<<5) - 1; 02930 op1 <<= 16; 02931 Value |= op1; 02932 // op2: SH 02933 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02934 // op3: MBE 02935 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 02936 op3 &= (1<<6) - 1; 02937 op3 <<= 5; 02938 Value |= op3; 02939 Value |= getValueBit(op2, 1) << 15; 02940 Value |= getValueBit(op2, 2) << 14; 02941 Value |= getValueBit(op2, 3) << 13; 02942 Value |= getValueBit(op2, 4) << 12; 02943 Value |= getValueBit(op2, 5) << 11; 02944 Value |= getValueBit(op2, 0) << 1; 02945 break; 02946 } 02947 case PPC::RLWIMI: { 02948 DEBUG(std::cerr << "Emitting RLWIMI\n"); 02949 Value = 1342177280U; 02950 02951 // op0: RA 02952 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02953 op0 &= (1<<5) - 1; 02954 op0 <<= 16; 02955 Value |= op0; 02956 // op1: RS 02957 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02958 op1 &= (1<<5) - 1; 02959 op1 <<= 21; 02960 Value |= op1; 02961 // op2: RB 02962 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02963 op2 &= (1<<5) - 1; 02964 op2 <<= 11; 02965 Value |= op2; 02966 // op3: MB 02967 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 02968 op3 &= (1<<5) - 1; 02969 op3 <<= 6; 02970 Value |= op3; 02971 // op4: ME 02972 int op4 = getMachineOpValue(MI, MI.getOperand(4)); 02973 op4 &= (1<<5) - 1; 02974 op4 <<= 1; 02975 Value |= op4; 02976 break; 02977 } 02978 case PPC::RLWINM: { 02979 DEBUG(std::cerr << "Emitting RLWINM\n"); 02980 Value = 1409286144U; 02981 02982 // op0: RA 02983 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02984 op0 &= (1<<5) - 1; 02985 op0 <<= 16; 02986 Value |= op0; 02987 // op1: RS 02988 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02989 op1 &= (1<<5) - 1; 02990 op1 <<= 21; 02991 Value |= op1; 02992 // op2: RB 02993 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02994 op2 &= (1<<5) - 1; 02995 op2 <<= 11; 02996 Value |= op2; 02997 // op3: MB 02998 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 02999 op3 &= (1<<5) - 1; 03000 op3 <<= 6; 03001 Value |= op3; 03002 // op4: ME 03003 int op4 = getMachineOpValue(MI, MI.getOperand(4)); 03004 op4 &= (1<<5) - 1; 03005 op4 <<= 1; 03006 Value |= op4; 03007 break; 03008 } 03009 case PPC::RLWINMo: { 03010 DEBUG(std::cerr << "Emitting RLWINMo\n"); 03011 Value = 1409286145U; 03012 03013 // op0: RA 03014 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03015 op0 &= (1<<5) - 1; 03016 op0 <<= 16; 03017 Value |= op0; 03018 // op1: RS 03019 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03020 op1 &= (1<<5) - 1; 03021 op1 <<= 21; 03022 Value |= op1; 03023 // op2: RB 03024 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03025 op2 &= (1<<5) - 1; 03026 op2 <<= 11; 03027 Value |= op2; 03028 // op3: MB 03029 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 03030 op3 &= (1<<5) - 1; 03031 op3 <<= 6; 03032 Value |= op3; 03033 // op4: ME 03034 int op4 = getMachineOpValue(MI, MI.getOperand(4)); 03035 op4 &= (1<<5) - 1; 03036 op4 <<= 1; 03037 Value |= op4; 03038 break; 03039 } 03040 case PPC::RLWNM: { 03041 DEBUG(std::cerr << "Emitting RLWNM\n"); 03042 Value = 1543503872U; 03043 03044 // op0: RA 03045 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03046 op0 &= (1<<5) - 1; 03047 op0 <<= 16; 03048 Value |= op0; 03049 // op1: RS 03050 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03051 op1 &= (1<<5) - 1; 03052 op1 <<= 21; 03053 Value |= op1; 03054 // op2: RB 03055 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03056 op2 &= (1<<5) - 1; 03057 op2 <<= 11; 03058 Value |= op2; 03059 // op3: MB 03060 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 03061 op3 &= (1<<5) - 1; 03062 op3 <<= 6; 03063 Value |= op3; 03064 // op4: ME 03065 int op4 = getMachineOpValue(MI, MI.getOperand(4)); 03066 op4 &= (1<<5) - 1; 03067 op4 <<= 1; 03068 Value |= op4; 03069 break; 03070 } 03071 case PPC::SELECT_CC_F4: { 03072 DEBUG(std::cerr << "Emitting SELECT_CC_F4\n"); 03073 Value = 0U; 03074 03075 break; 03076 } 03077 case PPC::SELECT_CC_F8: { 03078 DEBUG(std::cerr << "Emitting SELECT_CC_F8\n"); 03079 Value = 0U; 03080 03081 break; 03082 } 03083 case PPC::SELECT_CC_Int: { 03084 DEBUG(std::cerr << "Emitting SELECT_CC_Int\n"); 03085 Value = 0U; 03086 03087 break; 03088 } 03089 case PPC::SELECT_CC_VRRC: { 03090 DEBUG(std::cerr << "Emitting SELECT_CC_VRRC\n"); 03091 Value = 0U; 03092 03093 break; 03094 } 03095 case PPC::SLD: { 03096 DEBUG(std::cerr << "Emitting SLD\n"); 03097 Value = 2080374838U; 03098 03099 // op0: A 03100 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03101 op0 &= (1<<5) - 1; 03102 op0 <<= 16; 03103 Value |= op0; 03104 // op1: RST 03105 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03106 op1 &= (1<<5) - 1; 03107 op1 <<= 21; 03108 Value |= op1; 03109 // op2: B 03110 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03111 op2 &= (1<<5) - 1; 03112 op2 <<= 11; 03113 Value |= op2; 03114 break; 03115 } 03116 case PPC::SLW: { 03117 DEBUG(std::cerr << "Emitting SLW\n"); 03118 Value = 2080374832U; 03119 03120 // op0: A 03121 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03122 op0 &= (1<<5) - 1; 03123 op0 <<= 16; 03124 Value |= op0; 03125 // op1: RST 03126 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03127 op1 &= (1<<5) - 1; 03128 op1 <<= 21; 03129 Value |= op1; 03130 // op2: B 03131 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03132 op2 &= (1<<5) - 1; 03133 op2 <<= 11; 03134 Value |= op2; 03135 break; 03136 } 03137 case PPC::SRAD: { 03138 DEBUG(std::cerr << "Emitting SRAD\n"); 03139 Value = 2080376372U; 03140 03141 // op0: A 03142 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03143 op0 &= (1<<5) - 1; 03144 op0 <<= 16; 03145 Value |= op0; 03146 // op1: RST 03147 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03148 op1 &= (1<<5) - 1; 03149 op1 <<= 21; 03150 Value |= op1; 03151 // op2: B 03152 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03153 op2 &= (1<<5) - 1; 03154 op2 <<= 11; 03155 Value |= op2; 03156 break; 03157 } 03158 case PPC::SRADI: { 03159 DEBUG(std::cerr << "Emitting SRADI\n"); 03160 Value = 2080376436U; 03161 03162 // op0: RS 03163 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03164 op0 &= (1<<5) - 1; 03165 op0 <<= 21; 03166 Value |= op0; 03167 // op1: A 03168 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03169 op1 &= (1<<5) - 1; 03170 op1 <<= 16; 03171 Value |= op1; 03172 // op2: SH 03173 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03174 Value |= getValueBit(op2, 1) << 15; 03175 Value |= getValueBit(op2, 2) << 14; 03176 Value |= getValueBit(op2, 3) << 13; 03177 Value |= getValueBit(op2, 4) << 12; 03178 Value |= getValueBit(op2, 5) << 11; 03179 Value |= getValueBit(op2, 0) << 1; 03180 break; 03181 } 03182 case PPC::SRAW: { 03183 DEBUG(std::cerr << "Emitting SRAW\n"); 03184 Value = 2080376368U; 03185 03186 // op0: A 03187 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03188 op0 &= (1<<5) - 1; 03189 op0 <<= 16; 03190 Value |= op0; 03191 // op1: RST 03192 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03193 op1 &= (1<<5) - 1; 03194 op1 <<= 21; 03195 Value |= op1; 03196 // op2: B 03197 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03198 op2 &= (1<<5) - 1; 03199 op2 <<= 11; 03200 Value |= op2; 03201 break; 03202 } 03203 case PPC::SRAWI: { 03204 DEBUG(std::cerr << "Emitting SRAWI\n"); 03205 Value = 2080376432U; 03206 03207 // op0: A 03208 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03209 op0 &= (1<<5) - 1; 03210 op0 <<= 16; 03211 Value |= op0; 03212 // op1: RST 03213 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03214 op1 &= (1<<5) - 1; 03215 op1 <<= 21; 03216 Value |= op1; 03217 // op2: B 03218 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03219 op2 &= (1<<5) - 1; 03220 op2 <<= 11; 03221 Value |= op2; 03222 break; 03223 } 03224 case PPC::SRD: { 03225 DEBUG(std::cerr << "Emitting SRD\n"); 03226 Value = 2080375862U; 03227 03228 // op0: A 03229 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03230 op0 &= (1<<5) - 1; 03231 op0 <<= 16; 03232 Value |= op0; 03233 // op1: RST 03234 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03235 op1 &= (1<<5) - 1; 03236 op1 <<= 21; 03237 Value |= op1; 03238 // op2: B 03239 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03240 op2 &= (1<<5) - 1; 03241 op2 <<= 11; 03242 Value |= op2; 03243 break; 03244 } 03245 case PPC::SRW: { 03246 DEBUG(std::cerr << "Emitting SRW\n"); 03247 Value = 2080375856U; 03248 03249 // op0: A 03250 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03251 op0 &= (1<<5) - 1; 03252 op0 <<= 16; 03253 Value |= op0; 03254 // op1: RST 03255 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03256 op1 &= (1<<5) - 1; 03257 op1 <<= 21; 03258 Value |= op1; 03259 // op2: B 03260 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03261 op2 &= (1<<5) - 1; 03262 op2 <<= 11; 03263 Value |= op2; 03264 break; 03265 } 03266 case PPC::STB: { 03267 DEBUG(std::cerr << "Emitting STB\n"); 03268 Value = 2550136832U; 03269 03270 // op0: A 03271 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03272 op0 &= (1<<5) - 1; 03273 op0 <<= 21; 03274 Value |= op0; 03275 // op1: C 03276 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03277 op1 &= (1<<16) - 1; 03278 Value |= op1; 03279 // op2: B 03280 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03281 op2 &= (1<<5) - 1; 03282 op2 <<= 16; 03283 Value |= op2; 03284 break; 03285 } 03286 case PPC::STBX: { 03287 DEBUG(std::cerr << "Emitting STBX\n"); 03288 Value = 2080375214U; 03289 03290 // op0: RST 03291 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03292 op0 &= (1<<5) - 1; 03293 op0 <<= 21; 03294 Value |= op0; 03295 // op1: A 03296 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03297 op1 &= (1<<5) - 1; 03298 op1 <<= 16; 03299 Value |= op1; 03300 // op2: B 03301 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03302 op2 &= (1<<5) - 1; 03303 op2 <<= 11; 03304 Value |= op2; 03305 break; 03306 } 03307 case PPC::STD: { 03308 DEBUG(std::cerr << "Emitting STD\n"); 03309 Value = 4160749568U; 03310 03311 // op0: RST 03312 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03313 op0 &= (1<<5) - 1; 03314 op0 <<= 21; 03315 Value |= op0; 03316 // op1: DS 03317 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03318 op1 &= (1<<14) - 1; 03319 op1 <<= 2; 03320 Value |= op1; 03321 // op2: RA 03322 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03323 op2 &= (1<<5) - 1; 03324 op2 <<= 16; 03325 Value |= op2; 03326 break; 03327 } 03328 case PPC::STDUX: { 03329 DEBUG(std::cerr << "Emitting STDUX\n"); 03330 Value = 2080375146U; 03331 03332 // op0: RST 03333 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03334 op0 &= (1<<5) - 1; 03335 op0 <<= 21; 03336 Value |= op0; 03337 // op1: A 03338 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03339 op1 &= (1<<5) - 1; 03340 op1 <<= 16; 03341 Value |= op1; 03342 // op2: B 03343 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03344 op2 &= (1<<5) - 1; 03345 op2 <<= 11; 03346 Value |= op2; 03347 break; 03348 } 03349 case PPC::STDX: { 03350 DEBUG(std::cerr << "Emitting STDX\n"); 03351 Value = 2080375082U; 03352 03353 // op0: RST 03354 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03355 op0 &= (1<<5) - 1; 03356 op0 <<= 21; 03357 Value |= op0; 03358 // op1: A 03359 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03360 op1 &= (1<<5) - 1; 03361 op1 <<= 16; 03362 Value |= op1; 03363 // op2: B 03364 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03365 op2 &= (1<<5) - 1; 03366 op2 <<= 11; 03367 Value |= op2; 03368 break; 03369 } 03370 case PPC::STDX_32: { 03371 DEBUG(std::cerr << "Emitting STDX_32\n"); 03372 Value = 2080375082U; 03373 03374 // op0: RST 03375 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03376 op0 &= (1<<5) - 1; 03377 op0 <<= 21; 03378 Value |= op0; 03379 // op1: A 03380 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03381 op1 &= (1<<5) - 1; 03382 op1 <<= 16; 03383 Value |= op1; 03384 // op2: B 03385 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03386 op2 &= (1<<5) - 1; 03387 op2 <<= 11; 03388 Value |= op2; 03389 break; 03390 } 03391 case PPC::STD_32: { 03392 DEBUG(std::cerr << "Emitting STD_32\n"); 03393 Value = 4160749568U; 03394 03395 // op0: RST 03396 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03397 op0 &= (1<<5) - 1; 03398 op0 <<= 21; 03399 Value |= op0; 03400 // op1: DS 03401 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03402 op1 &= (1<<14) - 1; 03403 op1 <<= 2; 03404 Value |= op1; 03405 // op2: RA 03406 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03407 op2 &= (1<<5) - 1; 03408 op2 <<= 16; 03409 Value |= op2; 03410 break; 03411 } 03412 case PPC::STFD: { 03413 DEBUG(std::cerr << "Emitting STFD\n"); 03414 Value = 3623878656U; 03415 03416 // op0: A 03417 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03418 op0 &= (1<<5) - 1; 03419 op0 <<= 21; 03420 Value |= op0; 03421 // op1: C 03422 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03423 op1 &= (1<<16) - 1; 03424 Value |= op1; 03425 // op2: B 03426 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03427 op2 &= (1<<5) - 1; 03428 op2 <<= 16; 03429 Value |= op2; 03430 break; 03431 } 03432 case PPC::STFDX: { 03433 DEBUG(std::cerr << "Emitting STFDX\n"); 03434 Value = 2080376238U; 03435 03436 // op0: RST 03437 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03438 op0 &= (1<<5) - 1; 03439 op0 <<= 21; 03440 Value |= op0; 03441 // op1: A 03442 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03443 op1 &= (1<<5) - 1; 03444 op1 <<= 16; 03445 Value |= op1; 03446 // op2: B 03447 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03448 op2 &= (1<<5) - 1; 03449 op2 <<= 11; 03450 Value |= op2; 03451 break; 03452 } 03453 case PPC::STFIWX: { 03454 DEBUG(std::cerr << "Emitting STFIWX\n"); 03455 Value = 2080376750U; 03456 03457 // op0: RST 03458 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03459 op0 &= (1<<5) - 1; 03460 op0 <<= 21; 03461 Value |= op0; 03462 // op1: A 03463 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03464 op1 &= (1<<5) - 1; 03465 op1 <<= 16; 03466 Value |= op1; 03467 // op2: B 03468 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03469 op2 &= (1<<5) - 1; 03470 op2 <<= 11; 03471 Value |= op2; 03472 break; 03473 } 03474 case PPC::STFS: { 03475 DEBUG(std::cerr << "Emitting STFS\n"); 03476 Value = 3489660928U; 03477 03478 // op0: A 03479 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03480 op0 &= (1<<5) - 1; 03481 op0 <<= 21; 03482 Value |= op0; 03483 // op1: C 03484 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03485 op1 &= (1<<16) - 1; 03486 Value |= op1; 03487 // op2: B 03488 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03489 op2 &= (1<<5) - 1; 03490 op2 <<= 16; 03491 Value |= op2; 03492 break; 03493 } 03494 case PPC::STFSX: { 03495 DEBUG(std::cerr << "Emitting STFSX\n"); 03496 Value = 2080376110U; 03497 03498 // op0: RST 03499 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03500 op0 &= (1<<5) - 1; 03501 op0 <<= 21; 03502 Value |= op0; 03503 // op1: A 03504 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03505 op1 &= (1<<5) - 1; 03506 op1 <<= 16; 03507 Value |= op1; 03508 // op2: B 03509 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03510 op2 &= (1<<5) - 1; 03511 op2 <<= 11; 03512 Value |= op2; 03513 break; 03514 } 03515 case PPC::STH: { 03516 DEBUG(std::cerr << "Emitting STH\n"); 03517 Value = 2952790016U; 03518 03519 // op0: A 03520 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03521 op0 &= (1<<5) - 1; 03522 op0 <<= 21; 03523 Value |= op0; 03524 // op1: C 03525 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03526 op1 &= (1<<16) - 1; 03527 Value |= op1; 03528 // op2: B 03529 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03530 op2 &= (1<<5) - 1; 03531 op2 <<= 16; 03532 Value |= op2; 03533 break; 03534 } 03535 case PPC::STHX: { 03536 DEBUG(std::cerr << "Emitting STHX\n"); 03537 Value = 2080375598U; 03538 03539 // op0: RST 03540 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03541 op0 &= (1<<5) - 1; 03542 op0 <<= 21; 03543 Value |= op0; 03544 // op1: A 03545 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03546 op1 &= (1<<5) - 1; 03547 op1 <<= 16; 03548 Value |= op1; 03549 // op2: B 03550 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03551 op2 &= (1<<5) - 1; 03552 op2 <<= 11; 03553 Value |= op2; 03554 break; 03555 } 03556 case PPC::STVEBX: { 03557 DEBUG(std::cerr << "Emitting STVEBX\n"); 03558 Value = 2080375054U; 03559 03560 // op0: RST 03561 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03562 op0 &= (1<<5) - 1; 03563 op0 <<= 21; 03564 Value |= op0; 03565 // op1: A 03566 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03567 op1 &= (1<<5) - 1; 03568 op1 <<= 16; 03569 Value |= op1; 03570 // op2: B 03571 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03572 op2 &= (1<<5) - 1; 03573 op2 <<= 11; 03574 Value |= op2; 03575 break; 03576 } 03577 case PPC::STVEHX: { 03578 DEBUG(std::cerr << "Emitting STVEHX\n"); 03579 Value = 2080375118U; 03580 03581 // op0: RST 03582 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03583 op0 &= (1<<5) - 1; 03584 op0 <<= 21; 03585 Value |= op0; 03586 // op1: A 03587 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03588 op1 &= (1<<5) - 1; 03589 op1 <<= 16; 03590 Value |= op1; 03591 // op2: B 03592 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03593 op2 &= (1<<5) - 1; 03594 op2 <<= 11; 03595 Value |= op2; 03596 break; 03597 } 03598 case PPC::STVEWX: { 03599 DEBUG(std::cerr << "Emitting STVEWX\n"); 03600 Value = 2080375182U; 03601 03602 // op0: RST 03603 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03604 op0 &= (1<<5) - 1; 03605 op0 <<= 21; 03606 Value |= op0; 03607 // op1: A 03608 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03609 op1 &= (1<<5) - 1; 03610 op1 <<= 16; 03611 Value |= op1; 03612 // op2: B 03613 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03614 op2 &= (1<<5) - 1; 03615 op2 <<= 11; 03616 Value |= op2; 03617 break; 03618 } 03619 case PPC::STVX: { 03620 DEBUG(std::cerr << "Emitting STVX\n"); 03621 Value = 2080375246U; 03622 03623 // op0: RST 03624 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03625 op0 &= (1<<5) - 1; 03626 op0 <<= 21; 03627 Value |= op0; 03628 // op1: A 03629 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03630 op1 &= (1<<5) - 1; 03631 op1 <<= 16; 03632 Value |= op1; 03633 // op2: B 03634 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03635 op2 &= (1<<5) - 1; 03636 op2 <<= 11; 03637 Value |= op2; 03638 break; 03639 } 03640 case PPC::STVXL: { 03641 DEBUG(std::cerr << "Emitting STVXL\n"); 03642 Value = 2080375758U; 03643 03644 // op0: RST 03645 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03646 op0 &= (1<<5) - 1; 03647 op0 <<= 21; 03648 Value |= op0; 03649 // op1: A 03650 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03651 op1 &= (1<<5) - 1; 03652 op1 <<= 16; 03653 Value |= op1; 03654 // op2: B 03655 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03656 op2 &= (1<<5) - 1; 03657 op2 <<= 11; 03658 Value |= op2; 03659 break; 03660 } 03661 case PPC::STW: { 03662 DEBUG(std::cerr << "Emitting STW\n"); 03663 Value = 2415919104U; 03664 03665 // op0: A 03666 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03667 op0 &= (1<<5) - 1; 03668 op0 <<= 21; 03669 Value |= op0; 03670 // op1: C 03671 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03672 op1 &= (1<<16) - 1; 03673 Value |= op1; 03674 // op2: B 03675 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03676 op2 &= (1<<5) - 1; 03677 op2 <<= 16; 03678 Value |= op2; 03679 break; 03680 } 03681 case PPC::STWU: { 03682 DEBUG(std::cerr << "Emitting STWU\n"); 03683 Value = 2483027968U; 03684 03685 // op0: A 03686 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03687 op0 &= (1<<5) - 1; 03688 op0 <<= 21; 03689 Value |= op0; 03690 // op1: C 03691 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03692 op1 &= (1<<16) - 1; 03693 Value |= op1; 03694 // op2: B 03695 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03696 op2 &= (1<<5) - 1; 03697 op2 <<= 16; 03698 Value |= op2; 03699 break; 03700 } 03701 case PPC::STWUX: { 03702 DEBUG(std::cerr << "Emitting STWUX\n"); 03703 Value = 2080375150U; 03704 03705 // op0: RST 03706 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03707 op0 &= (1<<5) - 1; 03708 op0 <<= 21; 03709 Value |= op0; 03710 // op1: A 03711 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03712 op1 &= (1<<5) - 1; 03713 op1 <<= 16; 03714 Value |= op1; 03715 // op2: B 03716 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03717 op2 &= (1<<5) - 1; 03718 op2 <<= 11; 03719 Value |= op2; 03720 break; 03721 } 03722 case PPC::STWX: { 03723 DEBUG(std::cerr << "Emitting STWX\n"); 03724 Value = 2080375086U; 03725 03726 // op0: RST 03727 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03728 op0 &= (1<<5) - 1; 03729 op0 <<= 21; 03730 Value |= op0; 03731 // op1: A 03732 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03733 op1 &= (1<<5) - 1; 03734 op1 <<= 16; 03735 Value |= op1; 03736 // op2: B 03737 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03738 op2 &= (1<<5) - 1; 03739 op2 <<= 11; 03740 Value |= op2; 03741 break; 03742 } 03743 case PPC::SUBF: { 03744 DEBUG(std::cerr << "Emitting SUBF\n"); 03745 Value = 2080374864U; 03746 03747 // op0: RT 03748 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03749 op0 &= (1<<5) - 1; 03750 op0 <<= 21; 03751 Value |= op0; 03752 // op1: RA 03753 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03754 op1 &= (1<<5) - 1; 03755 op1 <<= 16; 03756 Value |= op1; 03757 // op2: RB 03758 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03759 op2 &= (1<<5) - 1; 03760 op2 <<= 11; 03761 Value |= op2; 03762 break; 03763 } 03764 case PPC::SUBFC: { 03765 DEBUG(std::cerr << "Emitting SUBFC\n"); 03766 Value = 2080374800U; 03767 03768 // op0: RT 03769 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03770 op0 &= (1<<5) - 1; 03771 op0 <<= 21; 03772 Value |= op0; 03773 // op1: RA 03774 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03775 op1 &= (1<<5) - 1; 03776 op1 <<= 16; 03777 Value |= op1; 03778 // op2: RB 03779 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03780 op2 &= (1<<5) - 1; 03781 op2 <<= 11; 03782 Value |= op2; 03783 break; 03784 } 03785 case PPC::SUBFE: { 03786 DEBUG(std::cerr << "Emitting SUBFE\n"); 03787 Value = 2080375056U; 03788 03789 // op0: RT 03790 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03791 op0 &= (1<<5) - 1; 03792 op0 <<= 21; 03793 Value |= op0; 03794 // op1: RA 03795 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03796 op1 &= (1<<5) - 1; 03797 op1 <<= 16; 03798 Value |= op1; 03799 // op2: RB 03800 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03801 op2 &= (1<<5) - 1; 03802 op2 <<= 11; 03803 Value |= op2; 03804 break; 03805 } 03806 case PPC::SUBFIC: { 03807 DEBUG(std::cerr << "Emitting SUBFIC\n"); 03808 Value = 536870912U; 03809 03810 // op0: A 03811 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03812 op0 &= (1<<5) - 1; 03813 op0 <<= 21; 03814 Value |= op0; 03815 // op1: B 03816 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03817 op1 &= (1<<5) - 1; 03818 op1 <<= 16; 03819 Value |= op1; 03820 // op2: C 03821 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03822 op2 &= (1<<16) - 1; 03823 Value |= op2; 03824 break; 03825 } 03826 case PPC::SUBFME: { 03827 DEBUG(std::cerr << "Emitting SUBFME\n"); 03828 Value = 2080375248U; 03829 03830 // op0: RT 03831 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03832 op0 &= (1<<5) - 1; 03833 op0 <<= 21; 03834 Value |= op0; 03835 // op1: RA 03836 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03837 op1 &= (1<<5) - 1; 03838 op1 <<= 16; 03839 Value |= op1; 03840 break; 03841 } 03842 case PPC::SUBFZE: { 03843 DEBUG(std::cerr << "Emitting SUBFZE\n"); 03844 Value = 2080375184U; 03845 03846 // op0: RT 03847 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03848 op0 &= (1<<5) - 1; 03849 op0 <<= 21; 03850 Value |= op0; 03851 // op1: RA 03852 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03853 op1 &= (1<<5) - 1; 03854 op1 <<= 16; 03855 Value |= op1; 03856 break; 03857 } 03858 case PPC::UPDATE_VRSAVE: { 03859 DEBUG(std::cerr << "Emitting UPDATE_VRSAVE\n"); 03860 Value = 0U; 03861 03862 break; 03863 } 03864 case PPC::VADDCUW: { 03865 DEBUG(std::cerr << "Emitting VADDCUW\n"); 03866 Value = 268435840U; 03867 03868 // op0: VD 03869 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03870 op0 &= (1<<5) - 1; 03871 op0 <<= 21; 03872 Value |= op0; 03873 // op1: VA 03874 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03875 op1 &= (1<<5) - 1; 03876 op1 <<= 16; 03877 Value |= op1; 03878 // op2: VB 03879 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03880 op2 &= (1<<5) - 1; 03881 op2 <<= 11; 03882 Value |= op2; 03883 break; 03884 } 03885 case PPC::VADDFP: { 03886 DEBUG(std::cerr << "Emitting VADDFP\n"); 03887 Value = 268435466U; 03888 03889 // op0: VD 03890 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03891 op0 &= (1<<5) - 1; 03892 op0 <<= 21; 03893 Value |= op0; 03894 // op1: VA 03895 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03896 op1 &= (1<<5) - 1; 03897 op1 <<= 16; 03898 Value |= op1; 03899 // op2: VB 03900 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03901 op2 &= (1<<5) - 1; 03902 op2 <<= 11; 03903 Value |= op2; 03904 break; 03905 } 03906 case PPC::VADDSBS: { 03907 DEBUG(std::cerr << "Emitting VADDSBS\n"); 03908 Value = 268436224U; 03909 03910 // op0: VD 03911 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03912 op0 &= (1<<5) - 1; 03913 op0 <<= 21; 03914 Value |= op0; 03915 // op1: VA 03916 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03917 op1 &= (1<<5) - 1; 03918 op1 <<= 16; 03919 Value |= op1; 03920 // op2: VB 03921 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03922 op2 &= (1<<5) - 1; 03923 op2 <<= 11; 03924 Value |= op2; 03925 break; 03926 } 03927 case PPC::VADDSHS: { 03928 DEBUG(std::cerr << "Emitting VADDSHS\n"); 03929 Value = 268436288U; 03930 03931 // op0: VD 03932 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03933 op0 &= (1<<5) - 1; 03934 op0 <<= 21; 03935 Value |= op0; 03936 // op1: VA 03937 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03938 op1 &= (1<<5) - 1; 03939 op1 <<= 16; 03940 Value |= op1; 03941 // op2: VB 03942 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03943 op2 &= (1<<5) - 1; 03944 op2 <<= 11; 03945 Value |= op2; 03946 break; 03947 } 03948 case PPC::VADDSWS: { 03949 DEBUG(std::cerr << "Emitting VADDSWS\n"); 03950 Value = 268436352U; 03951 03952 // op0: VD 03953 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03954 op0 &= (1<<5) - 1; 03955 op0 <<= 21; 03956 Value |= op0; 03957 // op1: VA 03958 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03959 op1 &= (1<<5) - 1; 03960 op1 <<= 16; 03961 Value |= op1; 03962 // op2: VB 03963 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03964 op2 &= (1<<5) - 1; 03965 op2 <<= 11; 03966 Value |= op2; 03967 break; 03968 } 03969 case PPC::VADDUBM: { 03970 DEBUG(std::cerr << "Emitting VADDUBM\n"); 03971 Value = 268435456U; 03972 03973 // op0: VD 03974 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03975 op0 &= (1<<5) - 1; 03976 op0 <<= 21; 03977 Value |= op0; 03978 // op1: VA 03979 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03980 op1 &= (1<<5) - 1; 03981 op1 <<= 16; 03982 Value |= op1; 03983 // op2: VB 03984 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03985 op2 &= (1<<5) - 1; 03986 op2 <<= 11; 03987 Value |= op2; 03988 break; 03989 } 03990 case PPC::VADDUBS: { 03991 DEBUG(std::cerr << "Emitting VADDUBS\n"); 03992 Value = 268435968U; 03993 03994 // op0: VD 03995 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03996 op0 &= (1<<5) - 1; 03997 op0 <<= 21; 03998 Value |= op0; 03999 // op1: VA 04000 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04001 op1 &= (1<<5) - 1; 04002 op1 <<= 16; 04003 Value |= op1; 04004 // op2: VB 04005 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04006 op2 &= (1<<5) - 1; 04007 op2 <<= 11; 04008 Value |= op2; 04009 break; 04010 } 04011 case PPC::VADDUHM: { 04012 DEBUG(std::cerr << "Emitting VADDUHM\n"); 04013 Value = 268435520U; 04014 04015 // op0: VD 04016 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04017 op0 &= (1<<5) - 1; 04018 op0 <<= 21; 04019 Value |= op0; 04020 // op1: VA 04021 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04022 op1 &= (1<<5) - 1; 04023 op1 <<= 16; 04024 Value |= op1; 04025 // op2: VB 04026 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04027 op2 &= (1<<5) - 1; 04028 op2 <<= 11; 04029 Value |= op2; 04030 break; 04031 } 04032 case PPC::VADDUHS: { 04033 DEBUG(std::cerr << "Emitting VADDUHS\n"); 04034 Value = 268436032U; 04035 04036 // op0: VD 04037 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04038 op0 &= (1<<5) - 1; 04039 op0 <<= 21; 04040 Value |= op0; 04041 // op1: VA 04042 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04043 op1 &= (1<<5) - 1; 04044 op1 <<= 16; 04045 Value |= op1; 04046 // op2: VB 04047 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04048 op2 &= (1<<5) - 1; 04049 op2 <<= 11; 04050 Value |= op2; 04051 break; 04052 } 04053 case PPC::VADDUWM: { 04054 DEBUG(std::cerr << "Emitting VADDUWM\n"); 04055 Value = 268435584U; 04056 04057 // op0: VD 04058 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04059 op0 &= (1<<5) - 1; 04060 op0 <<= 21; 04061 Value |= op0; 04062 // op1: VA 04063 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04064 op1 &= (1<<5) - 1; 04065 op1 <<= 16; 04066 Value |= op1; 04067 // op2: VB 04068 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04069 op2 &= (1<<5) - 1; 04070 op2 <<= 11; 04071 Value |= op2; 04072 break; 04073 } 04074 case PPC::VADDUWS: { 04075 DEBUG(std::cerr << "Emitting VADDUWS\n"); 04076 Value = 268436096U; 04077 04078 // op0: VD 04079 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04080 op0 &= (1<<5) - 1; 04081 op0 <<= 21; 04082 Value |= op0; 04083 // op1: VA 04084 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04085 op1 &= (1<<5) - 1; 04086 op1 <<= 16; 04087 Value |= op1; 04088 // op2: VB 04089 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04090 op2 &= (1<<5) - 1; 04091 op2 <<= 11; 04092 Value |= op2; 04093 break; 04094 } 04095 case PPC::VAND: { 04096 DEBUG(std::cerr << "Emitting VAND\n"); 04097 Value = 268436484U; 04098 04099 // op0: VD 04100 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04101 op0 &= (1<<5) - 1; 04102 op0 <<= 21; 04103 Value |= op0; 04104 // op1: VA 04105 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04106 op1 &= (1<<5) - 1; 04107 op1 <<= 16; 04108 Value |= op1; 04109 // op2: VB 04110 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04111 op2 &= (1<<5) - 1; 04112 op2 <<= 11; 04113 Value |= op2; 04114 break; 04115 } 04116 case PPC::VANDC: { 04117 DEBUG(std::cerr << "Emitting VANDC\n"); 04118 Value = 268436548U; 04119 04120 // op0: VD 04121 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04122 op0 &= (1<<5) - 1; 04123 op0 <<= 21; 04124 Value |= op0; 04125 // op1: VA 04126 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04127 op1 &= (1<<5) - 1; 04128 op1 <<= 16; 04129 Value |= op1; 04130 // op2: VB 04131 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04132 op2 &= (1<<5) - 1; 04133 op2 <<= 11; 04134 Value |= op2; 04135 break; 04136 } 04137 case PPC::VAVGSB: { 04138 DEBUG(std::cerr << "Emitting VAVGSB\n"); 04139 Value = 268436738U; 04140 04141 // op0: VD 04142 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04143 op0 &= (1<<5) - 1; 04144 op0 <<= 21; 04145 Value |= op0; 04146 // op1: VA 04147 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04148 op1 &= (1<<5) - 1; 04149 op1 <<= 16; 04150 Value |= op1; 04151 // op2: VB 04152 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04153 op2 &= (1<<5) - 1; 04154 op2 <<= 11; 04155 Value |= op2; 04156 break; 04157 } 04158 case PPC::VAVGSH: { 04159 DEBUG(std::cerr << "Emitting VAVGSH\n"); 04160 Value = 268436802U; 04161 04162 // op0: VD 04163 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04164 op0 &= (1<<5) - 1; 04165 op0 <<= 21; 04166 Value |= op0; 04167 // op1: VA 04168 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04169 op1 &= (1<<5) - 1; 04170 op1 <<= 16; 04171 Value |= op1; 04172 // op2: VB 04173 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04174 op2 &= (1<<5) - 1; 04175 op2 <<= 11; 04176 Value |= op2; 04177 break; 04178 } 04179 case PPC::VAVGSW: { 04180 DEBUG(std::cerr << "Emitting VAVGSW\n"); 04181 Value = 268436866U; 04182 04183 // op0: VD 04184 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04185 op0 &= (1<<5) - 1; 04186 op0 <<= 21; 04187 Value |= op0; 04188 // op1: VA 04189 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04190 op1 &= (1<<5) - 1; 04191 op1 <<= 16; 04192 Value |= op1; 04193 // op2: VB 04194 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04195 op2 &= (1<<5) - 1; 04196 op2 <<= 11; 04197 Value |= op2; 04198 break; 04199 } 04200 case PPC::VAVGUB: { 04201 DEBUG(std::cerr << "Emitting VAVGUB\n"); 04202 Value = 268436482U; 04203 04204 // op0: VD 04205 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04206 op0 &= (1<<5) - 1; 04207 op0 <<= 21; 04208 Value |= op0; 04209 // op1: VA 04210 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04211 op1 &= (1<<5) - 1; 04212 op1 <<= 16; 04213 Value |= op1; 04214 // op2: VB 04215 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04216 op2 &= (1<<5) - 1; 04217 op2 <<= 11; 04218 Value |= op2; 04219 break; 04220 } 04221 case PPC::VAVGUH: { 04222 DEBUG(std::cerr << "Emitting VAVGUH\n"); 04223 Value = 268436546U; 04224 04225 // op0: VD 04226 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04227 op0 &= (1<<5) - 1; 04228 op0 <<= 21; 04229 Value |= op0; 04230 // op1: VA 04231 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04232 op1 &= (1<<5) - 1; 04233 op1 <<= 16; 04234 Value |= op1; 04235 // op2: VB 04236 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04237 op2 &= (1<<5) - 1; 04238 op2 <<= 11; 04239 Value |= op2; 04240 break; 04241 } 04242 case PPC::VAVGUW: { 04243 DEBUG(std::cerr << "Emitting VAVGUW\n"); 04244 Value = 268436610U; 04245 04246 // op0: VD 04247 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04248 op0 &= (1<<5) - 1; 04249 op0 <<= 21; 04250 Value |= op0; 04251 // op1: VA 04252 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04253 op1 &= (1<<5) - 1; 04254 op1 <<= 16; 04255 Value |= op1; 04256 // op2: VB 04257 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04258 op2 &= (1<<5) - 1; 04259 op2 <<= 11; 04260 Value |= op2; 04261 break; 04262 } 04263 case PPC::VCFSX: { 04264 DEBUG(std::cerr << "Emitting VCFSX\n"); 04265 Value = 268436298U; 04266 04267 // op0: VD 04268 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04269 op0 &= (1<<5) - 1; 04270 op0 <<= 21; 04271 Value |= op0; 04272 // op1: VA 04273 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04274 op1 &= (1<<5) - 1; 04275 op1 <<= 16; 04276 Value |= op1; 04277 // op2: VB 04278 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04279 op2 &= (1<<5) - 1; 04280 op2 <<= 11; 04281 Value |= op2; 04282 break; 04283 } 04284 case PPC::VCFUX: { 04285 DEBUG(std::cerr << "Emitting VCFUX\n"); 04286 Value = 268436234U; 04287 04288 // op0: VD 04289 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04290 op0 &= (1<<5) - 1; 04291 op0 <<= 21; 04292 Value |= op0; 04293 // op1: VA 04294 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04295 op1 &= (1<<5) - 1; 04296 op1 <<= 16; 04297 Value |= op1; 04298 // op2: VB 04299 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04300 op2 &= (1<<5) - 1; 04301 op2 <<= 11; 04302 Value |= op2; 04303 break; 04304 } 04305 case PPC::VCMPBFP: { 04306 DEBUG(std::cerr << "Emitting VCMPBFP\n"); 04307 Value = 268436422U; 04308 04309 // op0: VD 04310 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04311 op0 &= (1<<5) - 1; 04312 op0 <<= 21; 04313 Value |= op0; 04314 // op1: VA 04315 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04316 op1 &= (1<<5) - 1; 04317 op1 <<= 16; 04318 Value |= op1; 04319 // op2: VB 04320 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04321 op2 &= (1<<5) - 1; 04322 op2 <<= 11; 04323 Value |= op2; 04324 break; 04325 } 04326 case PPC::VCMPBFPo: { 04327 DEBUG(std::cerr << "Emitting VCMPBFPo\n"); 04328 Value = 268437446U; 04329 04330 // op0: VD 04331 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04332 op0 &= (1<<5) - 1; 04333 op0 <<= 21; 04334 Value |= op0; 04335 // op1: VA 04336 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04337 op1 &= (1<<5) - 1; 04338 op1 <<= 16; 04339 Value |= op1; 04340 // op2: VB 04341 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04342 op2 &= (1<<5) - 1; 04343 op2 <<= 11; 04344 Value |= op2; 04345 break; 04346 } 04347 case PPC::VCMPEQFP: { 04348 DEBUG(std::cerr << "Emitting VCMPEQFP\n"); 04349 Value = 268435654U; 04350 04351 // op0: VD 04352 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04353 op0 &= (1<<5) - 1; 04354 op0 <<= 21; 04355 Value |= op0; 04356 // op1: VA 04357 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04358 op1 &= (1<<5) - 1; 04359 op1 <<= 16; 04360 Value |= op1; 04361 // op2: VB 04362 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04363 op2 &= (1<<5) - 1; 04364 op2 <<= 11; 04365 Value |= op2; 04366 break; 04367 } 04368 case PPC::VCMPEQFPo: { 04369 DEBUG(std::cerr << "Emitting VCMPEQFPo\n"); 04370 Value = 268436678U; 04371 04372 // op0: VD 04373 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04374 op0 &= (1<<5) - 1; 04375 op0 <<= 21; 04376 Value |= op0; 04377 // op1: VA 04378 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04379 op1 &= (1<<5) - 1; 04380 op1 <<= 16; 04381 Value |= op1; 04382 // op2: VB 04383 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04384 op2 &= (1<<5) - 1; 04385 op2 <<= 11; 04386 Value |= op2; 04387 break; 04388 } 04389 case PPC::VCMPEQUB: { 04390 DEBUG(std::cerr << "Emitting VCMPEQUB\n"); 04391 Value = 268435462U; 04392 04393 // op0: VD 04394 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04395 op0 &= (1<<5) - 1; 04396 op0 <<= 21; 04397 Value |= op0; 04398 // op1: VA 04399 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04400 op1 &= (1<<5) - 1; 04401 op1 <<= 16; 04402 Value |= op1; 04403 // op2: VB 04404 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04405 op2 &= (1<<5) - 1; 04406 op2 <<= 11; 04407 Value |= op2; 04408 break; 04409 } 04410 case PPC::VCMPEQUBo: { 04411 DEBUG(std::cerr << "Emitting VCMPEQUBo\n"); 04412 Value = 268436486U; 04413 04414 // op0: VD 04415 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04416 op0 &= (1<<5) - 1; 04417 op0 <<= 21; 04418 Value |= op0; 04419 // op1: VA 04420 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04421 op1 &= (1<<5) - 1; 04422 op1 <<= 16; 04423 Value |= op1; 04424 // op2: VB 04425 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04426 op2 &= (1<<5) - 1; 04427 op2 <<= 11; 04428 Value |= op2; 04429 break; 04430 } 04431 case PPC::VCMPEQUH: { 04432 DEBUG(std::cerr << "Emitting VCMPEQUH\n"); 04433 Value = 268435526U; 04434 04435 // op0: VD 04436 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04437 op0 &= (1<<5) - 1; 04438 op0 <<= 21; 04439 Value |= op0; 04440 // op1: VA 04441 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04442 op1 &= (1<<5) - 1; 04443 op1 <<= 16; 04444 Value |= op1; 04445 // op2: VB 04446 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04447 op2 &= (1<<5) - 1; 04448 op2 <<= 11; 04449 Value |= op2; 04450 break; 04451 } 04452 case PPC::VCMPEQUHo: { 04453 DEBUG(std::cerr << "Emitting VCMPEQUHo\n"); 04454 Value = 268436550U; 04455 04456 // op0: VD 04457 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04458 op0 &= (1<<5) - 1; 04459 op0 <<= 21; 04460 Value |= op0; 04461 // op1: VA 04462 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04463 op1 &= (1<<5) - 1; 04464 op1 <<= 16; 04465 Value |= op1; 04466 // op2: VB 04467 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04468 op2 &= (1<<5) - 1; 04469 op2 <<= 11; 04470 Value |= op2; 04471 break; 04472 } 04473 case PPC::VCMPEQUW: { 04474 DEBUG(std::cerr << "Emitting VCMPEQUW\n"); 04475 Value = 268435590U; 04476 04477 // op0: VD 04478 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04479 op0 &= (1<<5) - 1; 04480 op0 <<= 21; 04481 Value |= op0; 04482 // op1: VA 04483 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04484 op1 &= (1<<5) - 1; 04485 op1 <<= 16; 04486 Value |= op1; 04487 // op2: VB 04488 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04489 op2 &= (1<<5) - 1; 04490 op2 <<= 11; 04491 Value |= op2; 04492 break; 04493 } 04494 case PPC::VCMPEQUWo: { 04495 DEBUG(std::cerr << "Emitting VCMPEQUWo\n"); 04496 Value = 268436614U; 04497 04498 // op0: VD 04499 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04500 op0 &= (1<<5) - 1; 04501 op0 <<= 21; 04502 Value |= op0; 04503 // op1: VA 04504 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04505 op1 &= (1<<5) - 1; 04506 op1 <<= 16; 04507 Value |= op1; 04508 // op2: VB 04509 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04510 op2 &= (1<<5) - 1; 04511 op2 <<= 11; 04512 Value |= op2; 04513 break; 04514 } 04515 case PPC::VCMPGEFP: { 04516 DEBUG(std::cerr << "Emitting VCMPGEFP\n"); 04517 Value = 268435910U; 04518 04519 // op0: VD 04520 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04521 op0 &= (1<<5) - 1; 04522 op0 <<= 21; 04523 Value |= op0; 04524 // op1: VA 04525 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04526 op1 &= (1<<5) - 1; 04527 op1 <<= 16; 04528 Value |= op1; 04529 // op2: VB 04530 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04531 op2 &= (1<<5) - 1; 04532 op2 <<= 11; 04533 Value |= op2; 04534 break; 04535 } 04536 case PPC::VCMPGEFPo: { 04537 DEBUG(std::cerr << "Emitting VCMPGEFPo\n"); 04538 Value = 268436934U; 04539 04540 // op0: VD 04541 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04542 op0 &= (1<<5) - 1; 04543 op0 <<= 21; 04544 Value |= op0; 04545 // op1: VA 04546 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04547 op1 &= (1<<5) - 1; 04548 op1 <<= 16; 04549 Value |= op1; 04550 // op2: VB 04551 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04552 op2 &= (1<<5) - 1; 04553 op2 <<= 11; 04554 Value |= op2; 04555 break; 04556 } 04557 case PPC::VCMPGTFP: { 04558 DEBUG(std::cerr << "Emitting VCMPGTFP\n"); 04559 Value = 268436166U; 04560 04561 // op0: VD 04562 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04563 op0 &= (1<<5) - 1; 04564 op0 <<= 21; 04565 Value |= op0; 04566 // op1: VA 04567 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04568 op1 &= (1<<5) - 1; 04569 op1 <<= 16; 04570 Value |= op1; 04571 // op2: VB 04572 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04573 op2 &= (1<<5) - 1; 04574 op2 <<= 11; 04575 Value |= op2; 04576 break; 04577 } 04578 case PPC::VCMPGTFPo: { 04579 DEBUG(std::cerr << "Emitting VCMPGTFPo\n"); 04580 Value = 268437190U; 04581 04582 // op0: VD 04583 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04584 op0 &= (1<<5) - 1; 04585 op0 <<= 21; 04586 Value |= op0; 04587 // op1: VA 04588 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04589 op1 &= (1<<5) - 1; 04590 op1 <<= 16; 04591 Value |= op1; 04592 // op2: VB 04593 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04594 op2 &= (1<<5) - 1; 04595 op2 <<= 11; 04596 Value |= op2; 04597 break; 04598 } 04599 case PPC::VCMPGTSB: { 04600 DEBUG(std::cerr << "Emitting VCMPGTSB\n"); 04601 Value = 268436230U; 04602 04603 // op0: VD 04604 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04605 op0 &= (1<<5) - 1; 04606 op0 <<= 21; 04607 Value |= op0; 04608 // op1: VA 04609 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04610 op1 &= (1<<5) - 1; 04611 op1 <<= 16; 04612 Value |= op1; 04613 // op2: VB 04614 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04615 op2 &= (1<<5) - 1; 04616 op2 <<= 11; 04617 Value |= op2; 04618 break; 04619 } 04620 case PPC::VCMPGTSBo: { 04621 DEBUG(std::cerr << "Emitting VCMPGTSBo\n"); 04622 Value = 268437254U; 04623 04624 // op0: VD 04625 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04626 op0 &= (1<<5) - 1; 04627 op0 <<= 21; 04628 Value |= op0; 04629 // op1: VA 04630 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04631 op1 &= (1<<5) - 1; 04632 op1 <<= 16; 04633 Value |= op1; 04634 // op2: VB 04635 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04636 op2 &= (1<<5) - 1; 04637 op2 <<= 11; 04638 Value |= op2; 04639 break; 04640 } 04641 case PPC::VCMPGTSH: { 04642 DEBUG(std::cerr << "Emitting VCMPGTSH\n"); 04643 Value = 268436294U; 04644 04645 // op0: VD 04646 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04647 op0 &= (1<<5) - 1; 04648 op0 <<= 21; 04649 Value |= op0; 04650 // op1: VA 04651 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04652 op1 &= (1<<5) - 1; 04653 op1 <<= 16; 04654 Value |= op1; 04655 // op2: VB 04656 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04657 op2 &= (1<<5) - 1; 04658 op2 <<= 11; 04659 Value |= op2; 04660 break; 04661 } 04662 case PPC::VCMPGTSHo: { 04663 DEBUG(std::cerr << "Emitting VCMPGTSHo\n"); 04664 Value = 268437318U; 04665 04666 // op0: VD 04667 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04668 op0 &= (1<<5) - 1; 04669 op0 <<= 21; 04670 Value |= op0; 04671 // op1: VA 04672 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04673 op1 &= (1<<5) - 1; 04674 op1 <<= 16; 04675 Value |= op1; 04676 // op2: VB 04677 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04678 op2 &= (1<<5) - 1; 04679 op2 <<= 11; 04680 Value |= op2; 04681 break; 04682 } 04683 case PPC::VCMPGTSW: { 04684 DEBUG(std::cerr << "Emitting VCMPGTSW\n"); 04685 Value = 268436358U; 04686 04687 // op0: VD 04688 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04689 op0 &= (1<<5) - 1; 04690 op0 <<= 21; 04691 Value |= op0; 04692 // op1: VA 04693 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04694 op1 &= (1<<5) - 1; 04695 op1 <<= 16; 04696 Value |= op1; 04697 // op2: VB 04698 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04699 op2 &= (1<<5) - 1; 04700 op2 <<= 11; 04701 Value |= op2; 04702 break; 04703 } 04704 case PPC::VCMPGTSWo: { 04705 DEBUG(std::cerr << "Emitting VCMPGTSWo\n"); 04706 Value = 268437382U; 04707 04708 // op0: VD 04709 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04710 op0 &= (1<<5) - 1; 04711 op0 <<= 21; 04712 Value |= op0; 04713 // op1: VA 04714 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04715 op1 &= (1<<5) - 1; 04716 op1 <<= 16; 04717 Value |= op1; 04718 // op2: VB 04719 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04720 op2 &= (1<<5) - 1; 04721 op2 <<= 11; 04722 Value |= op2; 04723 break; 04724 } 04725 case PPC::VCMPGTUB: { 04726 DEBUG(std::cerr << "Emitting VCMPGTUB\n"); 04727 Value = 268435974U; 04728 04729 // op0: VD 04730 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04731 op0 &= (1<<5) - 1; 04732 op0 <<= 21; 04733 Value |= op0; 04734 // op1: VA 04735 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04736 op1 &= (1<<5) - 1; 04737 op1 <<= 16; 04738 Value |= op1; 04739 // op2: VB 04740 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04741 op2 &= (1<<5) - 1; 04742 op2 <<= 11; 04743 Value |= op2; 04744 break; 04745 } 04746 case PPC::VCMPGTUBo: { 04747 DEBUG(std::cerr << "Emitting VCMPGTUBo\n"); 04748 Value = 268436998U; 04749 04750 // op0: VD 04751 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04752 op0 &= (1<<5) - 1; 04753 op0 <<= 21; 04754 Value |= op0; 04755 // op1: VA 04756 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04757 op1 &= (1<<5) - 1; 04758 op1 <<= 16; 04759 Value |= op1; 04760 // op2: VB 04761 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04762 op2 &= (1<<5) - 1; 04763 op2 <<= 11; 04764 Value |= op2; 04765 break; 04766 } 04767 case PPC::VCMPGTUH: { 04768 DEBUG(std::cerr << "Emitting VCMPGTUH\n"); 04769 Value = 268436038U; 04770 04771 // op0: VD 04772 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04773 op0 &= (1<<5) - 1; 04774 op0 <<= 21; 04775 Value |= op0; 04776 // op1: VA 04777 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04778 op1 &= (1<<5) - 1; 04779 op1 <<= 16; 04780 Value |= op1; 04781 // op2: VB 04782 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04783 op2 &= (1<<5) - 1; 04784 op2 <<= 11; 04785 Value |= op2; 04786 break; 04787 } 04788 case PPC::VCMPGTUHo: { 04789 DEBUG(std::cerr << "Emitting VCMPGTUHo\n"); 04790 Value = 268437062U; 04791 04792 // op0: VD 04793 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04794 op0 &= (1<<5) - 1; 04795 op0 <<= 21; 04796 Value |= op0; 04797 // op1: VA 04798 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04799 op1 &= (1<<5) - 1; 04800 op1 <<= 16; 04801 Value |= op1; 04802 // op2: VB 04803 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04804 op2 &= (1<<5) - 1; 04805 op2 <<= 11; 04806 Value |= op2; 04807 break; 04808 } 04809 case PPC::VCMPGTUW: { 04810 DEBUG(std::cerr << "Emitting VCMPGTUW\n"); 04811 Value = 268436102U; 04812 04813 // op0: VD 04814 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04815 op0 &= (1<<5) - 1; 04816 op0 <<= 21; 04817 Value |= op0; 04818 // op1: VA 04819 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04820 op1 &= (1<<5) - 1; 04821 op1 <<= 16; 04822 Value |= op1; 04823 // op2: VB 04824 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04825 op2 &= (1<<5) - 1; 04826 op2 <<= 11; 04827 Value |= op2; 04828 break; 04829 } 04830 case PPC::VCMPGTUWo: { 04831 DEBUG(std::cerr << "Emitting VCMPGTUWo\n"); 04832 Value = 268437126U; 04833 04834 // op0: VD 04835 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04836 op0 &= (1<<5) - 1; 04837 op0 <<= 21; 04838 Value |= op0; 04839 // op1: VA 04840 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04841 op1 &= (1<<5) - 1; 04842 op1 <<= 16; 04843 Value |= op1; 04844 // op2: VB 04845 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04846 op2 &= (1<<5) - 1; 04847 op2 <<= 11; 04848 Value |= op2; 04849 break; 04850 } 04851 case PPC::VCTSXS: { 04852 DEBUG(std::cerr << "Emitting VCTSXS\n"); 04853 Value = 268436426U; 04854 04855 // op0: VD 04856 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04857 op0 &= (1<<5) - 1; 04858 op0 <<= 21; 04859 Value |= op0; 04860 // op1: VA 04861 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04862 op1 &= (1<<5) - 1; 04863 op1 <<= 16; 04864 Value |= op1; 04865 // op2: VB 04866 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04867 op2 &= (1<<5) - 1; 04868 op2 <<= 11; 04869 Value |= op2; 04870 break; 04871 } 04872 case PPC::VCTUXS: { 04873 DEBUG(std::cerr << "Emitting VCTUXS\n"); 04874 Value = 268436362U; 04875 04876 // op0: VD 04877 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04878 op0 &= (1<<5) - 1; 04879 op0 <<= 21; 04880 Value |= op0; 04881 // op1: VA 04882 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04883 op1 &= (1<<5) - 1; 04884 op1 <<= 16; 04885 Value |= op1; 04886 // op2: VB 04887 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04888 op2 &= (1<<5) - 1; 04889 op2 <<= 11; 04890 Value |= op2; 04891 break; 04892 } 04893 case PPC::VEXPTEFP: { 04894 DEBUG(std::cerr << "Emitting VEXPTEFP\n"); 04895 Value = 268435850U; 04896 04897 // op0: VD 04898 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04899 op0 &= (1<<5) - 1; 04900 op0 <<= 21; 04901 Value |= op0; 04902 // op1: VB 04903 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04904 op1 &= (1<<5) - 1; 04905 op1 <<= 11; 04906 Value |= op1; 04907 break; 04908 } 04909 case PPC::VLOGEFP: { 04910 DEBUG(std::cerr << "Emitting VLOGEFP\n"); 04911 Value = 268435914U; 04912 04913 // op0: VD 04914 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04915 op0 &= (1<<5) - 1; 04916 op0 <<= 21; 04917 Value |= op0; 04918 // op1: VB 04919 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04920 op1 &= (1<<5) - 1; 04921 op1 <<= 11; 04922 Value |= op1; 04923 break; 04924 } 04925 case PPC::VMADDFP: { 04926 DEBUG(std::cerr << "Emitting VMADDFP\n"); 04927 Value = 268435502U; 04928 04929 // op0: VD 04930 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04931 op0 &= (1<<5) - 1; 04932 op0 <<= 21; 04933 Value |= op0; 04934 // op1: VA 04935 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04936 op1 &= (1<<5) - 1; 04937 op1 <<= 16; 04938 Value |= op1; 04939 // op2: VC 04940 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04941 op2 &= (1<<5) - 1; 04942 op2 <<= 6; 04943 Value |= op2; 04944 // op3: VB 04945 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 04946 op3 &= (1<<5) - 1; 04947 op3 <<= 11; 04948 Value |= op3; 04949 break; 04950 } 04951 case PPC::VMAXFP: { 04952 DEBUG(std::cerr << "Emitting VMAXFP\n"); 04953 Value = 268436490U; 04954 04955 // op0: VD 04956 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04957 op0 &= (1<<5) - 1; 04958 op0 <<= 21; 04959 Value |= op0; 04960 // op1: VA 04961 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04962 op1 &= (1<<5) - 1; 04963 op1 <<= 16; 04964 Value |= op1; 04965 // op2: VB 04966 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04967 op2 &= (1<<5) - 1; 04968 op2 <<= 11; 04969 Value |= op2; 04970 break; 04971 } 04972 case PPC::VMAXSB: { 04973 DEBUG(std::cerr << "Emitting VMAXSB\n"); 04974 Value = 268435714U; 04975 04976 // op0: VD 04977 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04978 op0 &= (1<<5) - 1; 04979 op0 <<= 21; 04980 Value |= op0; 04981 // op1: VA 04982 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 04983 op1 &= (1<<5) - 1; 04984 op1 <<= 16; 04985 Value |= op1; 04986 // op2: VB 04987 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 04988 op2 &= (1<<5) - 1; 04989 op2 <<= 11; 04990 Value |= op2; 04991 break; 04992 } 04993 case PPC::VMAXSH: { 04994 DEBUG(std::cerr << "Emitting VMAXSH\n"); 04995 Value = 268435778U; 04996 04997 // op0: VD 04998 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 04999 op0 &= (1<<5) - 1; 05000 op0 <<= 21; 05001 Value |= op0; 05002 // op1: VA 05003 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05004 op1 &= (1<<5) - 1; 05005 op1 <<= 16; 05006 Value |= op1; 05007 // op2: VB 05008 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05009 op2 &= (1<<5) - 1; 05010 op2 <<= 11; 05011 Value |= op2; 05012 break; 05013 } 05014 case PPC::VMAXSW: { 05015 DEBUG(std::cerr << "Emitting VMAXSW\n"); 05016 Value = 268435842U; 05017 05018 // op0: VD 05019 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05020 op0 &= (1<<5) - 1; 05021 op0 <<= 21; 05022 Value |= op0; 05023 // op1: VA 05024 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05025 op1 &= (1<<5) - 1; 05026 op1 <<= 16; 05027 Value |= op1; 05028 // op2: VB 05029 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05030 op2 &= (1<<5) - 1; 05031 op2 <<= 11; 05032 Value |= op2; 05033 break; 05034 } 05035 case PPC::VMAXUB: { 05036 DEBUG(std::cerr << "Emitting VMAXUB\n"); 05037 Value = 268435458U; 05038 05039 // op0: VD 05040 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05041 op0 &= (1<<5) - 1; 05042 op0 <<= 21; 05043 Value |= op0; 05044 // op1: VA 05045 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05046 op1 &= (1<<5) - 1; 05047 op1 <<= 16; 05048 Value |= op1; 05049 // op2: VB 05050 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05051 op2 &= (1<<5) - 1; 05052 op2 <<= 11; 05053 Value |= op2; 05054 break; 05055 } 05056 case PPC::VMAXUH: { 05057 DEBUG(std::cerr << "Emitting VMAXUH\n"); 05058 Value = 268435522U; 05059 05060 // op0: VD 05061 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05062 op0 &= (1<<5) - 1; 05063 op0 <<= 21; 05064 Value |= op0; 05065 // op1: VA 05066 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05067 op1 &= (1<<5) - 1; 05068 op1 <<= 16; 05069 Value |= op1; 05070 // op2: VB 05071 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05072 op2 &= (1<<5) - 1; 05073 op2 <<= 11; 05074 Value |= op2; 05075 break; 05076 } 05077 case PPC::VMAXUW: { 05078 DEBUG(std::cerr << "Emitting VMAXUW\n"); 05079 Value = 268435586U; 05080 05081 // op0: VD 05082 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05083 op0 &= (1<<5) - 1; 05084 op0 <<= 21; 05085 Value |= op0; 05086 // op1: VA 05087 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05088 op1 &= (1<<5) - 1; 05089 op1 <<= 16; 05090 Value |= op1; 05091 // op2: VB 05092 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05093 op2 &= (1<<5) - 1; 05094 op2 <<= 11; 05095 Value |= op2; 05096 break; 05097 } 05098 case PPC::VMHADDSHS: { 05099 DEBUG(std::cerr << "Emitting VMHADDSHS\n"); 05100 Value = 268435488U; 05101 05102 // op0: VD 05103 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05104 op0 &= (1<<5) - 1; 05105 op0 <<= 21; 05106 Value |= op0; 05107 // op1: VA 05108 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05109 op1 &= (1<<5) - 1; 05110 op1 <<= 16; 05111 Value |= op1; 05112 // op2: VB 05113 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05114 op2 &= (1<<5) - 1; 05115 op2 <<= 11; 05116 Value |= op2; 05117 // op3: VC 05118 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05119 op3 &= (1<<5) - 1; 05120 op3 <<= 6; 05121 Value |= op3; 05122 break; 05123 } 05124 case PPC::VMHRADDSHS: { 05125 DEBUG(std::cerr << "Emitting VMHRADDSHS\n"); 05126 Value = 268435489U; 05127 05128 // op0: VD 05129 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05130 op0 &= (1<<5) - 1; 05131 op0 <<= 21; 05132 Value |= op0; 05133 // op1: VA 05134 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05135 op1 &= (1<<5) - 1; 05136 op1 <<= 16; 05137 Value |= op1; 05138 // op2: VB 05139 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05140 op2 &= (1<<5) - 1; 05141 op2 <<= 11; 05142 Value |= op2; 05143 // op3: VC 05144 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05145 op3 &= (1<<5) - 1; 05146 op3 <<= 6; 05147 Value |= op3; 05148 break; 05149 } 05150 case PPC::VMINFP: { 05151 DEBUG(std::cerr << "Emitting VMINFP\n"); 05152 Value = 268436554U; 05153 05154 // op0: VD 05155 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05156 op0 &= (1<<5) - 1; 05157 op0 <<= 21; 05158 Value |= op0; 05159 // op1: VA 05160 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05161 op1 &= (1<<5) - 1; 05162 op1 <<= 16; 05163 Value |= op1; 05164 // op2: VB 05165 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05166 op2 &= (1<<5) - 1; 05167 op2 <<= 11; 05168 Value |= op2; 05169 break; 05170 } 05171 case PPC::VMINSB: { 05172 DEBUG(std::cerr << "Emitting VMINSB\n"); 05173 Value = 268436226U; 05174 05175 // op0: VD 05176 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05177 op0 &= (1<<5) - 1; 05178 op0 <<= 21; 05179 Value |= op0; 05180 // op1: VA 05181 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05182 op1 &= (1<<5) - 1; 05183 op1 <<= 16; 05184 Value |= op1; 05185 // op2: VB 05186 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05187 op2 &= (1<<5) - 1; 05188 op2 <<= 11; 05189 Value |= op2; 05190 break; 05191 } 05192 case PPC::VMINSH: { 05193 DEBUG(std::cerr << "Emitting VMINSH\n"); 05194 Value = 268436290U; 05195 05196 // op0: VD 05197 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05198 op0 &= (1<<5) - 1; 05199 op0 <<= 21; 05200 Value |= op0; 05201 // op1: VA 05202 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05203 op1 &= (1<<5) - 1; 05204 op1 <<= 16; 05205 Value |= op1; 05206 // op2: VB 05207 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05208 op2 &= (1<<5) - 1; 05209 op2 <<= 11; 05210 Value |= op2; 05211 break; 05212 } 05213 case PPC::VMINSW: { 05214 DEBUG(std::cerr << "Emitting VMINSW\n"); 05215 Value = 268436352U; 05216 05217 // op0: VD 05218 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05219 op0 &= (1<<5) - 1; 05220 op0 <<= 21; 05221 Value |= op0; 05222 // op1: VA 05223 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05224 op1 &= (1<<5) - 1; 05225 op1 <<= 16; 05226 Value |= op1; 05227 // op2: VB 05228 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05229 op2 &= (1<<5) - 1; 05230 op2 <<= 11; 05231 Value |= op2; 05232 break; 05233 } 05234 case PPC::VMINUB: { 05235 DEBUG(std::cerr << "Emitting VMINUB\n"); 05236 Value = 268435970U; 05237 05238 // op0: VD 05239 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05240 op0 &= (1<<5) - 1; 05241 op0 <<= 21; 05242 Value |= op0; 05243 // op1: VA 05244 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05245 op1 &= (1<<5) - 1; 05246 op1 <<= 16; 05247 Value |= op1; 05248 // op2: VB 05249 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05250 op2 &= (1<<5) - 1; 05251 op2 <<= 11; 05252 Value |= op2; 05253 break; 05254 } 05255 case PPC::VMINUH: { 05256 DEBUG(std::cerr << "Emitting VMINUH\n"); 05257 Value = 268436034U; 05258 05259 // op0: VD 05260 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05261 op0 &= (1<<5) - 1; 05262 op0 <<= 21; 05263 Value |= op0; 05264 // op1: VA 05265 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05266 op1 &= (1<<5) - 1; 05267 op1 <<= 16; 05268 Value |= op1; 05269 // op2: VB 05270 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05271 op2 &= (1<<5) - 1; 05272 op2 <<= 11; 05273 Value |= op2; 05274 break; 05275 } 05276 case PPC::VMINUW: { 05277 DEBUG(std::cerr << "Emitting VMINUW\n"); 05278 Value = 268436098U; 05279 05280 // op0: VD 05281 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05282 op0 &= (1<<5) - 1; 05283 op0 <<= 21; 05284 Value |= op0; 05285 // op1: VA 05286 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05287 op1 &= (1<<5) - 1; 05288 op1 <<= 16; 05289 Value |= op1; 05290 // op2: VB 05291 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05292 op2 &= (1<<5) - 1; 05293 op2 <<= 11; 05294 Value |= op2; 05295 break; 05296 } 05297 case PPC::VMLADDUHM: { 05298 DEBUG(std::cerr << "Emitting VMLADDUHM\n"); 05299 Value = 268435490U; 05300 05301 // op0: VD 05302 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05303 op0 &= (1<<5) - 1; 05304 op0 <<= 21; 05305 Value |= op0; 05306 // op1: VA 05307 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05308 op1 &= (1<<5) - 1; 05309 op1 <<= 16; 05310 Value |= op1; 05311 // op2: VB 05312 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05313 op2 &= (1<<5) - 1; 05314 op2 <<= 11; 05315 Value |= op2; 05316 // op3: VC 05317 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05318 op3 &= (1<<5) - 1; 05319 op3 <<= 6; 05320 Value |= op3; 05321 break; 05322 } 05323 case PPC::VMRGHB: { 05324 DEBUG(std::cerr << "Emitting VMRGHB\n"); 05325 Value = 268435468U; 05326 05327 // op0: VD 05328 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05329 op0 &= (1<<5) - 1; 05330 op0 <<= 21; 05331 Value |= op0; 05332 // op1: VA 05333 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05334 op1 &= (1<<5) - 1; 05335 op1 <<= 16; 05336 Value |= op1; 05337 // op2: VB 05338 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05339 op2 &= (1<<5) - 1; 05340 op2 <<= 11; 05341 Value |= op2; 05342 break; 05343 } 05344 case PPC::VMRGHH: { 05345 DEBUG(std::cerr << "Emitting VMRGHH\n"); 05346 Value = 268435532U; 05347 05348 // op0: VD 05349 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05350 op0 &= (1<<5) - 1; 05351 op0 <<= 21; 05352 Value |= op0; 05353 // op1: VA 05354 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05355 op1 &= (1<<5) - 1; 05356 op1 <<= 16; 05357 Value |= op1; 05358 // op2: VB 05359 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05360 op2 &= (1<<5) - 1; 05361 op2 <<= 11; 05362 Value |= op2; 05363 break; 05364 } 05365 case PPC::VMRGHW: { 05366 DEBUG(std::cerr << "Emitting VMRGHW\n"); 05367 Value = 268435596U; 05368 05369 // op0: VD 05370 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05371 op0 &= (1<<5) - 1; 05372 op0 <<= 21; 05373 Value |= op0; 05374 // op1: VA 05375 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05376 op1 &= (1<<5) - 1; 05377 op1 <<= 16; 05378 Value |= op1; 05379 // op2: VB 05380 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05381 op2 &= (1<<5) - 1; 05382 op2 <<= 11; 05383 Value |= op2; 05384 break; 05385 } 05386 case PPC::VMRGLB: { 05387 DEBUG(std::cerr << "Emitting VMRGLB\n"); 05388 Value = 268435724U; 05389 05390 // op0: VD 05391 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05392 op0 &= (1<<5) - 1; 05393 op0 <<= 21; 05394 Value |= op0; 05395 // op1: VA 05396 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05397 op1 &= (1<<5) - 1; 05398 op1 <<= 16; 05399 Value |= op1; 05400 // op2: VB 05401 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05402 op2 &= (1<<5) - 1; 05403 op2 <<= 11; 05404 Value |= op2; 05405 break; 05406 } 05407 case PPC::VMRGLH: { 05408 DEBUG(std::cerr << "Emitting VMRGLH\n"); 05409 Value = 268435788U; 05410 05411 // op0: VD 05412 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05413 op0 &= (1<<5) - 1; 05414 op0 <<= 21; 05415 Value |= op0; 05416 // op1: VA 05417 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05418 op1 &= (1<<5) - 1; 05419 op1 <<= 16; 05420 Value |= op1; 05421 // op2: VB 05422 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05423 op2 &= (1<<5) - 1; 05424 op2 <<= 11; 05425 Value |= op2; 05426 break; 05427 } 05428 case PPC::VMRGLW: { 05429 DEBUG(std::cerr << "Emitting VMRGLW\n"); 05430 Value = 268435852U; 05431 05432 // op0: VD 05433 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05434 op0 &= (1<<5) - 1; 05435 op0 <<= 21; 05436 Value |= op0; 05437 // op1: VA 05438 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05439 op1 &= (1<<5) - 1; 05440 op1 <<= 16; 05441 Value |= op1; 05442 // op2: VB 05443 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05444 op2 &= (1<<5) - 1; 05445 op2 <<= 11; 05446 Value |= op2; 05447 break; 05448 } 05449 case PPC::VMSUMMBM: { 05450 DEBUG(std::cerr << "Emitting VMSUMMBM\n"); 05451 Value = 268435493U; 05452 05453 // op0: VD 05454 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05455 op0 &= (1<<5) - 1; 05456 op0 <<= 21; 05457 Value |= op0; 05458 // op1: VA 05459 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05460 op1 &= (1<<5) - 1; 05461 op1 <<= 16; 05462 Value |= op1; 05463 // op2: VB 05464 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05465 op2 &= (1<<5) - 1; 05466 op2 <<= 11; 05467 Value |= op2; 05468 // op3: VC 05469 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05470 op3 &= (1<<5) - 1; 05471 op3 <<= 6; 05472 Value |= op3; 05473 break; 05474 } 05475 case PPC::VMSUMSHM: { 05476 DEBUG(std::cerr << "Emitting VMSUMSHM\n"); 05477 Value = 268435496U; 05478 05479 // op0: VD 05480 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05481 op0 &= (1<<5) - 1; 05482 op0 <<= 21; 05483 Value |= op0; 05484 // op1: VA 05485 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05486 op1 &= (1<<5) - 1; 05487 op1 <<= 16; 05488 Value |= op1; 05489 // op2: VB 05490 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05491 op2 &= (1<<5) - 1; 05492 op2 <<= 11; 05493 Value |= op2; 05494 // op3: VC 05495 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05496 op3 &= (1<<5) - 1; 05497 op3 <<= 6; 05498 Value |= op3; 05499 break; 05500 } 05501 case PPC::VMSUMSHS: { 05502 DEBUG(std::cerr << "Emitting VMSUMSHS\n"); 05503 Value = 268435497U; 05504 05505 // op0: VD 05506 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05507 op0 &= (1<<5) - 1; 05508 op0 <<= 21; 05509 Value |= op0; 05510 // op1: VA 05511 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05512 op1 &= (1<<5) - 1; 05513 op1 <<= 16; 05514 Value |= op1; 05515 // op2: VB 05516 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05517 op2 &= (1<<5) - 1; 05518 op2 <<= 11; 05519 Value |= op2; 05520 // op3: VC 05521 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05522 op3 &= (1<<5) - 1; 05523 op3 <<= 6; 05524 Value |= op3; 05525 break; 05526 } 05527 case PPC::VMSUMUBM: { 05528 DEBUG(std::cerr << "Emitting VMSUMUBM\n"); 05529 Value = 268435492U; 05530 05531 // op0: VD 05532 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05533 op0 &= (1<<5) - 1; 05534 op0 <<= 21; 05535 Value |= op0; 05536 // op1: VA 05537 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05538 op1 &= (1<<5) - 1; 05539 op1 <<= 16; 05540 Value |= op1; 05541 // op2: VB 05542 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05543 op2 &= (1<<5) - 1; 05544 op2 <<= 11; 05545 Value |= op2; 05546 // op3: VC 05547 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05548 op3 &= (1<<5) - 1; 05549 op3 <<= 6; 05550 Value |= op3; 05551 break; 05552 } 05553 case PPC::VMSUMUHM: { 05554 DEBUG(std::cerr << "Emitting VMSUMUHM\n"); 05555 Value = 268435494U; 05556 05557 // op0: VD 05558 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05559 op0 &= (1<<5) - 1; 05560 op0 <<= 21; 05561 Value |= op0; 05562 // op1: VA 05563 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05564 op1 &= (1<<5) - 1; 05565 op1 <<= 16; 05566 Value |= op1; 05567 // op2: VB 05568 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05569 op2 &= (1<<5) - 1; 05570 op2 <<= 11; 05571 Value |= op2; 05572 // op3: VC 05573 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05574 op3 &= (1<<5) - 1; 05575 op3 <<= 6; 05576 Value |= op3; 05577 break; 05578 } 05579 case PPC::VMSUMUHS: { 05580 DEBUG(std::cerr << "Emitting VMSUMUHS\n"); 05581 Value = 268435495U; 05582 05583 // op0: VD 05584 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05585 op0 &= (1<<5) - 1; 05586 op0 <<= 21; 05587 Value |= op0; 05588 // op1: VA 05589 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05590 op1 &= (1<<5) - 1; 05591 op1 <<= 16; 05592 Value |= op1; 05593 // op2: VB 05594 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05595 op2 &= (1<<5) - 1; 05596 op2 <<= 11; 05597 Value |= op2; 05598 // op3: VC 05599 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05600 op3 &= (1<<5) - 1; 05601 op3 <<= 6; 05602 Value |= op3; 05603 break; 05604 } 05605 case PPC::VMULESB: { 05606 DEBUG(std::cerr << "Emitting VMULESB\n"); 05607 Value = 268436232U; 05608 05609 // op0: VD 05610 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05611 op0 &= (1<<5) - 1; 05612 op0 <<= 21; 05613 Value |= op0; 05614 // op1: VA 05615 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05616 op1 &= (1<<5) - 1; 05617 op1 <<= 16; 05618 Value |= op1; 05619 // op2: VB 05620 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05621 op2 &= (1<<5) - 1; 05622 op2 <<= 11; 05623 Value |= op2; 05624 break; 05625 } 05626 case PPC::VMULESH: { 05627 DEBUG(std::cerr << "Emitting VMULESH\n"); 05628 Value = 268436296U; 05629 05630 // op0: VD 05631 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05632 op0 &= (1<<5) - 1; 05633 op0 <<= 21; 05634 Value |= op0; 05635 // op1: VA 05636 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05637 op1 &= (1<<5) - 1; 05638 op1 <<= 16; 05639 Value |= op1; 05640 // op2: VB 05641 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05642 op2 &= (1<<5) - 1; 05643 op2 <<= 11; 05644 Value |= op2; 05645 break; 05646 } 05647 case PPC::VMULEUB: { 05648 DEBUG(std::cerr << "Emitting VMULEUB\n"); 05649 Value = 268435976U; 05650 05651 // op0: VD 05652 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05653 op0 &= (1<<5) - 1; 05654 op0 <<= 21; 05655 Value |= op0; 05656 // op1: VA 05657 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05658 op1 &= (1<<5) - 1; 05659 op1 <<= 16; 05660 Value |= op1; 05661 // op2: VB 05662 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05663 op2 &= (1<<5) - 1; 05664 op2 <<= 11; 05665 Value |= op2; 05666 break; 05667 } 05668 case PPC::VMULEUH: { 05669 DEBUG(std::cerr << "Emitting VMULEUH\n"); 05670 Value = 268436040U; 05671 05672 // op0: VD 05673 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05674 op0 &= (1<<5) - 1; 05675 op0 <<= 21; 05676 Value |= op0; 05677 // op1: VA 05678 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05679 op1 &= (1<<5) - 1; 05680 op1 <<= 16; 05681 Value |= op1; 05682 // op2: VB 05683 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05684 op2 &= (1<<5) - 1; 05685 op2 <<= 11; 05686 Value |= op2; 05687 break; 05688 } 05689 case PPC::VMULOSB: { 05690 DEBUG(std::cerr << "Emitting VMULOSB\n"); 05691 Value = 268435720U; 05692 05693 // op0: VD 05694 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05695 op0 &= (1<<5) - 1; 05696 op0 <<= 21; 05697 Value |= op0; 05698 // op1: VA 05699 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05700 op1 &= (1<<5) - 1; 05701 op1 <<= 16; 05702 Value |= op1; 05703 // op2: VB 05704 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05705 op2 &= (1<<5) - 1; 05706 op2 <<= 11; 05707 Value |= op2; 05708 break; 05709 } 05710 case PPC::VMULOSH: { 05711 DEBUG(std::cerr << "Emitting VMULOSH\n"); 05712 Value = 268435784U; 05713 05714 // op0: VD 05715 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05716 op0 &= (1<<5) - 1; 05717 op0 <<= 21; 05718 Value |= op0; 05719 // op1: VA 05720 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05721 op1 &= (1<<5) - 1; 05722 op1 <<= 16; 05723 Value |= op1; 05724 // op2: VB 05725 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05726 op2 &= (1<<5) - 1; 05727 op2 <<= 11; 05728 Value |= op2; 05729 break; 05730 } 05731 case PPC::VMULOUB: { 05732 DEBUG(std::cerr << "Emitting VMULOUB\n"); 05733 Value = 268435464U; 05734 05735 // op0: VD 05736 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05737 op0 &= (1<<5) - 1; 05738 op0 <<= 21; 05739 Value |= op0; 05740 // op1: VA 05741 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05742 op1 &= (1<<5) - 1; 05743 op1 <<= 16; 05744 Value |= op1; 05745 // op2: VB 05746 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05747 op2 &= (1<<5) - 1; 05748 op2 <<= 11; 05749 Value |= op2; 05750 break; 05751 } 05752 case PPC::VMULOUH: { 05753 DEBUG(std::cerr << "Emitting VMULOUH\n"); 05754 Value = 268435528U; 05755 05756 // op0: VD 05757 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05758 op0 &= (1<<5) - 1; 05759 op0 <<= 21; 05760 Value |= op0; 05761 // op1: VA 05762 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05763 op1 &= (1<<5) - 1; 05764 op1 <<= 16; 05765 Value |= op1; 05766 // op2: VB 05767 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05768 op2 &= (1<<5) - 1; 05769 op2 <<= 11; 05770 Value |= op2; 05771 break; 05772 } 05773 case PPC::VNMSUBFP: { 05774 DEBUG(std::cerr << "Emitting VNMSUBFP\n"); 05775 Value = 268435503U; 05776 05777 // op0: VD 05778 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05779 op0 &= (1<<5) - 1; 05780 op0 <<= 21; 05781 Value |= op0; 05782 // op1: VA 05783 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05784 op1 &= (1<<5) - 1; 05785 op1 <<= 16; 05786 Value |= op1; 05787 // op2: VC 05788 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05789 op2 &= (1<<5) - 1; 05790 op2 <<= 6; 05791 Value |= op2; 05792 // op3: VB 05793 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05794 op3 &= (1<<5) - 1; 05795 op3 <<= 11; 05796 Value |= op3; 05797 break; 05798 } 05799 case PPC::VNOR: { 05800 DEBUG(std::cerr << "Emitting VNOR\n"); 05801 Value = 268436740U; 05802 05803 // op0: VD 05804 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05805 op0 &= (1<<5) - 1; 05806 op0 <<= 21; 05807 Value |= op0; 05808 // op1: VA 05809 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05810 op1 &= (1<<5) - 1; 05811 op1 <<= 16; 05812 Value |= op1; 05813 // op2: VB 05814 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05815 op2 &= (1<<5) - 1; 05816 op2 <<= 11; 05817 Value |= op2; 05818 break; 05819 } 05820 case PPC::VOR: { 05821 DEBUG(std::cerr << "Emitting VOR\n"); 05822 Value = 268436612U; 05823 05824 // op0: VD 05825 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05826 op0 &= (1<<5) - 1; 05827 op0 <<= 21; 05828 Value |= op0; 05829 // op1: VA 05830 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05831 op1 &= (1<<5) - 1; 05832 op1 <<= 16; 05833 Value |= op1; 05834 // op2: VB 05835 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05836 op2 &= (1<<5) - 1; 05837 op2 <<= 11; 05838 Value |= op2; 05839 break; 05840 } 05841 case PPC::VPERM: { 05842 DEBUG(std::cerr << "Emitting VPERM\n"); 05843 Value = 268435499U; 05844 05845 // op0: VD 05846 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05847 op0 &= (1<<5) - 1; 05848 op0 <<= 21; 05849 Value |= op0; 05850 // op1: VA 05851 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05852 op1 &= (1<<5) - 1; 05853 op1 <<= 16; 05854 Value |= op1; 05855 // op2: VB 05856 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05857 op2 &= (1<<5) - 1; 05858 op2 <<= 11; 05859 Value |= op2; 05860 // op3: VC 05861 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 05862 op3 &= (1<<5) - 1; 05863 op3 <<= 6; 05864 Value |= op3; 05865 break; 05866 } 05867 case PPC::VPKPX: { 05868 DEBUG(std::cerr << "Emitting VPKPX\n"); 05869 Value = 268436238U; 05870 05871 // op0: VD 05872 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05873 op0 &= (1<<5) - 1; 05874 op0 <<= 21; 05875 Value |= op0; 05876 // op1: VA 05877 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05878 op1 &= (1<<5) - 1; 05879 op1 <<= 16; 05880 Value |= op1; 05881 // op2: VB 05882 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05883 op2 &= (1<<5) - 1; 05884 op2 <<= 11; 05885 Value |= op2; 05886 break; 05887 } 05888 case PPC::VPKSHSS: { 05889 DEBUG(std::cerr << "Emitting VPKSHSS\n"); 05890 Value = 268435854U; 05891 05892 // op0: VD 05893 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05894 op0 &= (1<<5) - 1; 05895 op0 <<= 21; 05896 Value |= op0; 05897 // op1: VA 05898 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05899 op1 &= (1<<5) - 1; 05900 op1 <<= 16; 05901 Value |= op1; 05902 // op2: VB 05903 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05904 op2 &= (1<<5) - 1; 05905 op2 <<= 11; 05906 Value |= op2; 05907 break; 05908 } 05909 case PPC::VPKSHUS: { 05910 DEBUG(std::cerr << "Emitting VPKSHUS\n"); 05911 Value = 268435726U; 05912 05913 // op0: VD 05914 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05915 op0 &= (1<<5) - 1; 05916 op0 <<= 21; 05917 Value |= op0; 05918 // op1: VA 05919 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05920 op1 &= (1<<5) - 1; 05921 op1 <<= 16; 05922 Value |= op1; 05923 // op2: VB 05924 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05925 op2 &= (1<<5) - 1; 05926 op2 <<= 11; 05927 Value |= op2; 05928 break; 05929 } 05930 case PPC::VPKSWSS: { 05931 DEBUG(std::cerr << "Emitting VPKSWSS\n"); 05932 Value = 268435918U; 05933 05934 // op0: VD 05935 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05936 op0 &= (1<<5) - 1; 05937 op0 <<= 21; 05938 Value |= op0; 05939 // op1: VA 05940 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05941 op1 &= (1<<5) - 1; 05942 op1 <<= 16; 05943 Value |= op1; 05944 // op2: VB 05945 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05946 op2 &= (1<<5) - 1; 05947 op2 <<= 11; 05948 Value |= op2; 05949 break; 05950 } 05951 case PPC::VPKSWUS: { 05952 DEBUG(std::cerr << "Emitting VPKSWUS\n"); 05953 Value = 268435790U; 05954 05955 // op0: VD 05956 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05957 op0 &= (1<<5) - 1; 05958 op0 <<= 21; 05959 Value |= op0; 05960 // op1: VA 05961 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05962 op1 &= (1<<5) - 1; 05963 op1 <<= 16; 05964 Value |= op1; 05965 // op2: VB 05966 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05967 op2 &= (1<<5) - 1; 05968 op2 <<= 11; 05969 Value |= op2; 05970 break; 05971 } 05972 case PPC::VPKUHUM: { 05973 DEBUG(std::cerr << "Emitting VPKUHUM\n"); 05974 Value = 268435470U; 05975 05976 // op0: VD 05977 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05978 op0 &= (1<<5) - 1; 05979 op0 <<= 21; 05980 Value |= op0; 05981 // op1: VA 05982 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 05983 op1 &= (1<<5) - 1; 05984 op1 <<= 16; 05985 Value |= op1; 05986 // op2: VB 05987 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 05988 op2 &= (1<<5) - 1; 05989 op2 <<= 11; 05990 Value |= op2; 05991 break; 05992 } 05993 case PPC::VPKUHUS: { 05994 DEBUG(std::cerr << "Emitting VPKUHUS\n"); 05995 Value = 268435598U; 05996 05997 // op0: VD 05998 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 05999 op0 &= (1<<5) - 1; 06000 op0 <<= 21; 06001 Value |= op0; 06002 // op1: VA 06003 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06004 op1 &= (1<<5) - 1; 06005 op1 <<= 16; 06006 Value |= op1; 06007 // op2: VB 06008 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06009 op2 &= (1<<5) - 1; 06010 op2 <<= 11; 06011 Value |= op2; 06012 break; 06013 } 06014 case PPC::VPKUWUM: { 06015 DEBUG(std::cerr << "Emitting VPKUWUM\n"); 06016 Value = 268435534U; 06017 06018 // op0: VD 06019 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06020 op0 &= (1<<5) - 1; 06021 op0 <<= 21; 06022 Value |= op0; 06023 // op1: VA 06024 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06025 op1 &= (1<<5) - 1; 06026 op1 <<= 16; 06027 Value |= op1; 06028 // op2: VB 06029 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06030 op2 &= (1<<5) - 1; 06031 op2 <<= 11; 06032 Value |= op2; 06033 break; 06034 } 06035 case PPC::VPKUWUS: { 06036 DEBUG(std::cerr << "Emitting VPKUWUS\n"); 06037 Value = 268435662U; 06038 06039 // op0: VD 06040 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06041 op0 &= (1<<5) - 1; 06042 op0 <<= 21; 06043 Value |= op0; 06044 // op1: VA 06045 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06046 op1 &= (1<<5) - 1; 06047 op1 <<= 16; 06048 Value |= op1; 06049 // op2: VB 06050 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06051 op2 &= (1<<5) - 1; 06052 op2 <<= 11; 06053 Value |= op2; 06054 break; 06055 } 06056 case PPC::VREFP: { 06057 DEBUG(std::cerr << "Emitting VREFP\n"); 06058 Value = 268435722U; 06059 06060 // op0: VD 06061 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06062 op0 &= (1<<5) - 1; 06063 op0 <<= 21; 06064 Value |= op0; 06065 // op1: VB 06066 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06067 op1 &= (1<<5) - 1; 06068 op1 <<= 11; 06069 Value |= op1; 06070 break; 06071 } 06072 case PPC::VRFIM: { 06073 DEBUG(std::cerr << "Emitting VRFIM\n"); 06074 Value = 268436170U; 06075 06076 // op0: VD 06077 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06078 op0 &= (1<<5) - 1; 06079 op0 <<= 21; 06080 Value |= op0; 06081 // op1: VB 06082 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06083 op1 &= (1<<5) - 1; 06084 op1 <<= 11; 06085 Value |= op1; 06086 break; 06087 } 06088 case PPC::VRFIN: { 06089 DEBUG(std::cerr << "Emitting VRFIN\n"); 06090 Value = 268435978U; 06091 06092 // op0: VD 06093 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06094 op0 &= (1<<5) - 1; 06095 op0 <<= 21; 06096 Value |= op0; 06097 // op1: VB 06098 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06099 op1 &= (1<<5) - 1; 06100 op1 <<= 11; 06101 Value |= op1; 06102 break; 06103 } 06104 case PPC::VRFIP: { 06105 DEBUG(std::cerr << "Emitting VRFIP\n"); 06106 Value = 268436106U; 06107 06108 // op0: VD 06109 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06110 op0 &= (1<<5) - 1; 06111 op0 <<= 21; 06112 Value |= op0; 06113 // op1: VB 06114 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06115 op1 &= (1<<5) - 1; 06116 op1 <<= 11; 06117 Value |= op1; 06118 break; 06119 } 06120 case PPC::VRFIZ: { 06121 DEBUG(std::cerr << "Emitting VRFIZ\n"); 06122 Value = 268436042U; 06123 06124 // op0: VD 06125 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06126 op0 &= (1<<5) - 1; 06127 op0 <<= 21; 06128 Value |= op0; 06129 // op1: VB 06130 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06131 op1 &= (1<<5) - 1; 06132 op1 <<= 11; 06133 Value |= op1; 06134 break; 06135 } 06136 case PPC::VRLB: { 06137 DEBUG(std::cerr << "Emitting VRLB\n"); 06138 Value = 268435460U; 06139 06140 // op0: VD 06141 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06142 op0 &= (1<<5) - 1; 06143 op0 <<= 21; 06144 Value |= op0; 06145 // op1: VA 06146 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06147 op1 &= (1<<5) - 1; 06148 op1 <<= 16; 06149 Value |= op1; 06150 // op2: VB 06151 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06152 op2 &= (1<<5) - 1; 06153 op2 <<= 11; 06154 Value |= op2; 06155 break; 06156 } 06157 case PPC::VRLH: { 06158 DEBUG(std::cerr << "Emitting VRLH\n"); 06159 Value = 268435524U; 06160 06161 // op0: VD 06162 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06163 op0 &= (1<<5) - 1; 06164 op0 <<= 21; 06165 Value |= op0; 06166 // op1: VA 06167 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06168 op1 &= (1<<5) - 1; 06169 op1 <<= 16; 06170 Value |= op1; 06171 // op2: VB 06172 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06173 op2 &= (1<<5) - 1; 06174 op2 <<= 11; 06175 Value |= op2; 06176 break; 06177 } 06178 case PPC::VRLW: { 06179 DEBUG(std::cerr << "Emitting VRLW\n"); 06180 Value = 268435588U; 06181 06182 // op0: VD 06183 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06184 op0 &= (1<<5) - 1; 06185 op0 <<= 21; 06186 Value |= op0; 06187 // op1: VA 06188 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06189 op1 &= (1<<5) - 1; 06190 op1 <<= 16; 06191 Value |= op1; 06192 // op2: VB 06193 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06194 op2 &= (1<<5) - 1; 06195 op2 <<= 11; 06196 Value |= op2; 06197 break; 06198 } 06199 case PPC::VRSQRTEFP: { 06200 DEBUG(std::cerr << "Emitting VRSQRTEFP\n"); 06201 Value = 268435786U; 06202 06203 // op0: VD 06204 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06205 op0 &= (1<<5) - 1; 06206 op0 <<= 21; 06207 Value |= op0; 06208 // op1: VB 06209 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06210 op1 &= (1<<5) - 1; 06211 op1 <<= 11; 06212 Value |= op1; 06213 break; 06214 } 06215 case PPC::VSEL: { 06216 DEBUG(std::cerr << "Emitting VSEL\n"); 06217 Value = 268435498U; 06218 06219 // op0: VD 06220 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06221 op0 &= (1<<5) - 1; 06222 op0 <<= 21; 06223 Value |= op0; 06224 // op1: VA 06225 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06226 op1 &= (1<<5) - 1; 06227 op1 <<= 16; 06228 Value |= op1; 06229 // op2: VB 06230 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06231 op2 &= (1<<5) - 1; 06232 op2 <<= 11; 06233 Value |= op2; 06234 // op3: VC 06235 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 06236 op3 &= (1<<5) - 1; 06237 op3 <<= 6; 06238 Value |= op3; 06239 break; 06240 } 06241 case PPC::VSL: { 06242 DEBUG(std::cerr << "Emitting VSL\n"); 06243 Value = 268435908U; 06244 06245 // op0: VD 06246 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06247 op0 &= (1<<5) - 1; 06248 op0 <<= 21; 06249 Value |= op0; 06250 // op1: VA 06251 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06252 op1 &= (1<<5) - 1; 06253 op1 <<= 16; 06254 Value |= op1; 06255 // op2: VB 06256 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06257 op2 &= (1<<5) - 1; 06258 op2 <<= 11; 06259 Value |= op2; 06260 break; 06261 } 06262 case PPC::VSLB: { 06263 DEBUG(std::cerr << "Emitting VSLB\n"); 06264 Value = 268435716U; 06265 06266 // op0: VD 06267 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06268 op0 &= (1<<5) - 1; 06269 op0 <<= 21; 06270 Value |= op0; 06271 // op1: VA 06272 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06273 op1 &= (1<<5) - 1; 06274 op1 <<= 16; 06275 Value |= op1; 06276 // op2: VB 06277 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06278 op2 &= (1<<5) - 1; 06279 op2 <<= 11; 06280 Value |= op2; 06281 break; 06282 } 06283 case PPC::VSLDOI: { 06284 DEBUG(std::cerr << "Emitting VSLDOI\n"); 06285 Value = 268435500U; 06286 06287 // op0: VD 06288 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06289 op0 &= (1<<5) - 1; 06290 op0 <<= 21; 06291 Value |= op0; 06292 // op1: VA 06293 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06294 op1 &= (1<<5) - 1; 06295 op1 <<= 16; 06296 Value |= op1; 06297 // op2: VB 06298 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06299 op2 &= (1<<5) - 1; 06300 op2 <<= 11; 06301 Value |= op2; 06302 // op3: SH 06303 int op3 = getMachineOpValue(MI, MI.getOperand(3)); 06304 op3 &= (1<<4) - 1; 06305 op3 <<= 6; 06306 Value |= op3; 06307 break; 06308 } 06309 case PPC::VSLH: { 06310 DEBUG(std::cerr << "Emitting VSLH\n"); 06311 Value = 268435780U; 06312 06313 // op0: VD 06314 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06315 op0 &= (1<<5) - 1; 06316 op0 <<= 21; 06317 Value |= op0; 06318 // op1: VA 06319 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06320 op1 &= (1<<5) - 1; 06321 op1 <<= 16; 06322 Value |= op1; 06323 // op2: VB 06324 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06325 op2 &= (1<<5) - 1; 06326 op2 <<= 11; 06327 Value |= op2; 06328 break; 06329 } 06330 case PPC::VSLO: { 06331 DEBUG(std::cerr << "Emitting VSLO\n"); 06332 Value = 268436492U; 06333 06334 // op0: VD 06335 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06336 op0 &= (1<<5) - 1; 06337 op0 <<= 21; 06338 Value |= op0; 06339 // op1: VA 06340 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06341 op1 &= (1<<5) - 1; 06342 op1 <<= 16; 06343 Value |= op1; 06344 // op2: VB 06345 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06346 op2 &= (1<<5) - 1; 06347 op2 <<= 11; 06348 Value |= op2; 06349 break; 06350 } 06351 case PPC::VSLW: { 06352 DEBUG(std::cerr << "Emitting VSLW\n"); 06353 Value = 268435844U; 06354 06355 // op0: VD 06356 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06357 op0 &= (1<<5) - 1; 06358 op0 <<= 21; 06359 Value |= op0; 06360 // op1: VA 06361 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06362 op1 &= (1<<5) - 1; 06363 op1 <<= 16; 06364 Value |= op1; 06365 // op2: VB 06366 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06367 op2 &= (1<<5) - 1; 06368 op2 <<= 11; 06369 Value |= op2; 06370 break; 06371 } 06372 case PPC::VSPLTB: { 06373 DEBUG(std::cerr << "Emitting VSPLTB\n"); 06374 Value = 268435980U; 06375 06376 // op0: VD 06377 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06378 op0 &= (1<<5) - 1; 06379 op0 <<= 21; 06380 Value |= op0; 06381 // op1: VA 06382 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06383 op1 &= (1<<5) - 1; 06384 op1 <<= 16; 06385 Value |= op1; 06386 // op2: VB 06387 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06388 op2 &= (1<<5) - 1; 06389 op2 <<= 11; 06390 Value |= op2; 06391 break; 06392 } 06393 case PPC::VSPLTH: { 06394 DEBUG(std::cerr << "Emitting VSPLTH\n"); 06395 Value = 268436044U; 06396 06397 // op0: VD 06398 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06399 op0 &= (1<<5) - 1; 06400 op0 <<= 21; 06401 Value |= op0; 06402 // op1: VA 06403 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06404 op1 &= (1<<5) - 1; 06405 op1 <<= 16; 06406 Value |= op1; 06407 // op2: VB 06408 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06409 op2 &= (1<<5) - 1; 06410 op2 <<= 11; 06411 Value |= op2; 06412 break; 06413 } 06414 case PPC::VSPLTISB: { 06415 DEBUG(std::cerr << "Emitting VSPLTISB\n"); 06416 Value = 268436236U; 06417 06418 // op0: VD 06419 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06420 op0 &= (1<<5) - 1; 06421 op0 <<= 21; 06422 Value |= op0; 06423 // op1: IMM 06424 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06425 op1 &= (1<<5) - 1; 06426 op1 <<= 16; 06427 Value |= op1; 06428 break; 06429 } 06430 case PPC::VSPLTISH: { 06431 DEBUG(std::cerr << "Emitting VSPLTISH\n"); 06432 Value = 268436300U; 06433 06434 // op0: VD 06435 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06436 op0 &= (1<<5) - 1; 06437 op0 <<= 21; 06438 Value |= op0; 06439 // op1: IMM 06440 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06441 op1 &= (1<<5) - 1; 06442 op1 <<= 16; 06443 Value |= op1; 06444 break; 06445 } 06446 case PPC::VSPLTISW: { 06447 DEBUG(std::cerr << "Emitting VSPLTISW\n"); 06448 Value = 268436364U; 06449 06450 // op0: VD 06451 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06452 op0 &= (1<<5) - 1; 06453 op0 <<= 21; 06454 Value |= op0; 06455 // op1: IMM 06456 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06457 op1 &= (1<<5) - 1; 06458 op1 <<= 16; 06459 Value |= op1; 06460 break; 06461 } 06462 case PPC::VSPLTW: { 06463 DEBUG(std::cerr << "Emitting VSPLTW\n"); 06464 Value = 268436108U; 06465 06466 // op0: VD 06467 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06468 op0 &= (1<<5) - 1; 06469 op0 <<= 21; 06470 Value |= op0; 06471 // op1: VA 06472 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06473 op1 &= (1<<5) - 1; 06474 op1 <<= 16; 06475 Value |= op1; 06476 // op2: VB 06477 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06478 op2 &= (1<<5) - 1; 06479 op2 <<= 11; 06480 Value |= op2; 06481 break; 06482 } 06483 case PPC::VSR: { 06484 DEBUG(std::cerr << "Emitting VSR\n"); 06485 Value = 268436164U; 06486 06487 // op0: VD 06488 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06489 op0 &= (1<<5) - 1; 06490 op0 <<= 21; 06491 Value |= op0; 06492 // op1: VA 06493 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06494 op1 &= (1<<5) - 1; 06495 op1 <<= 16; 06496 Value |= op1; 06497 // op2: VB 06498 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06499 op2 &= (1<<5) - 1; 06500 op2 <<= 11; 06501 Value |= op2; 06502 break; 06503 } 06504 case PPC::VSRAB: { 06505 DEBUG(std::cerr << "Emitting VSRAB\n"); 06506 Value = 268436228U; 06507 06508 // op0: VD 06509 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06510 op0 &= (1<<5) - 1; 06511 op0 <<= 21; 06512 Value |= op0; 06513 // op1: VA 06514 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06515 op1 &= (1<<5) - 1; 06516 op1 <<= 16; 06517 Value |= op1; 06518 // op2: VB 06519 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06520 op2 &= (1<<5) - 1; 06521 op2 <<= 11; 06522 Value |= op2; 06523 break; 06524 } 06525 case PPC::VSRAH: { 06526 DEBUG(std::cerr << "Emitting VSRAH\n"); 06527 Value = 268436292U; 06528 06529 // op0: VD 06530 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06531 op0 &= (1<<5) - 1; 06532 op0 <<= 21; 06533 Value |= op0; 06534 // op1: VA 06535 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06536 op1 &= (1<<5) - 1; 06537 op1 <<= 16; 06538 Value |= op1; 06539 // op2: VB 06540 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06541 op2 &= (1<<5) - 1; 06542 op2 <<= 11; 06543 Value |= op2; 06544 break; 06545 } 06546 case PPC::VSRAW: { 06547 DEBUG(std::cerr << "Emitting VSRAW\n"); 06548 Value = 268436356U; 06549 06550 // op0: VD 06551 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06552 op0 &= (1<<5) - 1; 06553 op0 <<= 21; 06554 Value |= op0; 06555 // op1: VA 06556 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06557 op1 &= (1<<5) - 1; 06558 op1 <<= 16; 06559 Value |= op1; 06560 // op2: VB 06561 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06562 op2 &= (1<<5) - 1; 06563 op2 <<= 11; 06564 Value |= op2; 06565 break; 06566 } 06567 case PPC::VSRB: { 06568 DEBUG(std::cerr << "Emitting VSRB\n"); 06569 Value = 268435972U; 06570 06571 // op0: VD 06572 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06573 op0 &= (1<<5) - 1; 06574 op0 <<= 21; 06575 Value |= op0; 06576 // op1: VA 06577 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06578 op1 &= (1<<5) - 1; 06579 op1 <<= 16; 06580 Value |= op1; 06581 // op2: VB 06582 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06583 op2 &= (1<<5) - 1; 06584 op2 <<= 11; 06585 Value |= op2; 06586 break; 06587 } 06588 case PPC::VSRH: { 06589 DEBUG(std::cerr << "Emitting VSRH\n"); 06590 Value = 268436036U; 06591 06592 // op0: VD 06593 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06594 op0 &= (1<<5) - 1; 06595 op0 <<= 21; 06596 Value |= op0; 06597 // op1: VA 06598 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06599 op1 &= (1<<5) - 1; 06600 op1 <<= 16; 06601 Value |= op1; 06602 // op2: VB 06603 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06604 op2 &= (1<<5) - 1; 06605 op2 <<= 11; 06606 Value |= op2; 06607 break; 06608 } 06609 case PPC::VSRO: { 06610 DEBUG(std::cerr << "Emitting VSRO\n"); 06611 Value = 268436556U; 06612 06613 // op0: VD 06614 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06615 op0 &= (1<<5) - 1; 06616 op0 <<= 21; 06617 Value |= op0; 06618 // op1: VA 06619 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06620 op1 &= (1<<5) - 1; 06621 op1 <<= 16; 06622 Value |= op1; 06623 // op2: VB 06624 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06625 op2 &= (1<<5) - 1; 06626 op2 <<= 11; 06627 Value |= op2; 06628 break; 06629 } 06630 case PPC::VSRW: { 06631 DEBUG(std::cerr << "Emitting VSRW\n"); 06632 Value = 268436100U; 06633 06634 // op0: VD 06635 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06636 op0 &= (1<<5) - 1; 06637 op0 <<= 21; 06638 Value |= op0; 06639 // op1: VA 06640 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06641 op1 &= (1<<5) - 1; 06642 op1 <<= 16; 06643 Value |= op1; 06644 // op2: VB 06645 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06646 op2 &= (1<<5) - 1; 06647 op2 <<= 11; 06648 Value |= op2; 06649 break; 06650 } 06651 case PPC::VSUBCUW: { 06652 DEBUG(std::cerr << "Emitting VSUBCUW\n"); 06653 Value = 268435530U; 06654 06655 // op0: VD 06656 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06657 op0 &= (1<<5) - 1; 06658 op0 <<= 21; 06659 Value |= op0; 06660 // op1: VA 06661 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06662 op1 &= (1<<5) - 1; 06663 op1 <<= 16; 06664 Value |= op1; 06665 // op2: VB 06666 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06667 op2 &= (1<<5) - 1; 06668 op2 <<= 11; 06669 Value |= op2; 06670 break; 06671 } 06672 case PPC::VSUBFP: { 06673 DEBUG(std::cerr << "Emitting VSUBFP\n"); 06674 Value = 268435530U; 06675 06676 // op0: VD 06677 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06678 op0 &= (1<<5) - 1; 06679 op0 <<= 21; 06680 Value |= op0; 06681 // op1: VA 06682 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06683 op1 &= (1<<5) - 1; 06684 op1 <<= 16; 06685 Value |= op1; 06686 // op2: VB 06687 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06688 op2 &= (1<<5) - 1; 06689 op2 <<= 11; 06690 Value |= op2; 06691 break; 06692 } 06693 case PPC::VSUBSBS: { 06694 DEBUG(std::cerr << "Emitting VSUBSBS\n"); 06695 Value = 268437248U; 06696 06697 // op0: VD 06698 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06699 op0 &= (1<<5) - 1; 06700 op0 <<= 21; 06701 Value |= op0; 06702 // op1: VA 06703 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06704 op1 &= (1<<5) - 1; 06705 op1 <<= 16; 06706 Value |= op1; 06707 // op2: VB 06708 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06709 op2 &= (1<<5) - 1; 06710 op2 <<= 11; 06711 Value |= op2; 06712 break; 06713 } 06714 case PPC::VSUBSHS: { 06715 DEBUG(std::cerr << "Emitting VSUBSHS\n"); 06716 Value = 268437312U; 06717 06718 // op0: VD 06719 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06720 op0 &= (1<<5) - 1; 06721 op0 <<= 21; 06722 Value |= op0; 06723 // op1: VA 06724 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06725 op1 &= (1<<5) - 1; 06726 op1 <<= 16; 06727 Value |= op1; 06728 // op2: VB 06729 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06730 op2 &= (1<<5) - 1; 06731 op2 <<= 11; 06732 Value |= op2; 06733 break; 06734 } 06735 case PPC::VSUBSWS: { 06736 DEBUG(std::cerr << "Emitting VSUBSWS\n"); 06737 Value = 268437376U; 06738 06739 // op0: VD 06740 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06741 op0 &= (1<<5) - 1; 06742 op0 <<= 21; 06743 Value |= op0; 06744 // op1: VA 06745 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06746 op1 &= (1<<5) - 1; 06747 op1 <<= 16; 06748 Value |= op1; 06749 // op2: VB 06750 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06751 op2 &= (1<<5) - 1; 06752 op2 <<= 11; 06753 Value |= op2; 06754 break; 06755 } 06756 case PPC::VSUBUBM: { 06757 DEBUG(std::cerr << "Emitting VSUBUBM\n"); 06758 Value = 268436480U; 06759 06760 // op0: VD 06761 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06762 op0 &= (1<<5) - 1; 06763 op0 <<= 21; 06764 Value |= op0; 06765 // op1: VA 06766 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06767 op1 &= (1<<5) - 1; 06768 op1 <<= 16; 06769 Value |= op1; 06770 // op2: VB 06771 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06772 op2 &= (1<<5) - 1; 06773 op2 <<= 11; 06774 Value |= op2; 06775 break; 06776 } 06777 case PPC::VSUBUBS: { 06778 DEBUG(std::cerr << "Emitting VSUBUBS\n"); 06779 Value = 268436992U; 06780 06781 // op0: VD 06782 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06783 op0 &= (1<<5) - 1; 06784 op0 <<= 21; 06785 Value |= op0; 06786 // op1: VA 06787 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06788 op1 &= (1<<5) - 1; 06789 op1 <<= 16; 06790 Value |= op1; 06791 // op2: VB 06792 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06793 op2 &= (1<<5) - 1; 06794 op2 <<= 11; 06795 Value |= op2; 06796 break; 06797 } 06798 case PPC::VSUBUHM: { 06799 DEBUG(std::cerr << "Emitting VSUBUHM\n"); 06800 Value = 268436544U; 06801 06802 // op0: VD 06803 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06804 op0 &= (1<<5) - 1; 06805 op0 <<= 21; 06806 Value |= op0; 06807 // op1: VA 06808 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06809 op1 &= (1<<5) - 1; 06810 op1 <<= 16; 06811 Value |= op1; 06812 // op2: VB 06813 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06814 op2 &= (1<<5) - 1; 06815 op2 <<= 11; 06816 Value |= op2; 06817 break; 06818 } 06819 case PPC::VSUBUHS: { 06820 DEBUG(std::cerr << "Emitting VSUBUHS\n"); 06821 Value = 268437056U; 06822 06823 // op0: VD 06824 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06825 op0 &= (1<<5) - 1; 06826 op0 <<= 21; 06827 Value |= op0; 06828 // op1: VA 06829 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06830 op1 &= (1<<5) - 1; 06831 op1 <<= 16; 06832 Value |= op1; 06833 // op2: VB 06834 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06835 op2 &= (1<<5) - 1; 06836 op2 <<= 11; 06837 Value |= op2; 06838 break; 06839 } 06840 case PPC::VSUBUWM: { 06841 DEBUG(std::cerr << "Emitting VSUBUWM\n"); 06842 Value = 268436608U; 06843 06844 // op0: VD 06845 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06846 op0 &= (1<<5) - 1; 06847 op0 <<= 21; 06848 Value |= op0; 06849 // op1: VA 06850 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06851 op1 &= (1<<5) - 1; 06852 op1 <<= 16; 06853 Value |= op1; 06854 // op2: VB 06855 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06856 op2 &= (1<<5) - 1; 06857 op2 <<= 11; 06858 Value |= op2; 06859 break; 06860 } 06861 case PPC::VSUBUWS: { 06862 DEBUG(std::cerr << "Emitting VSUBUWS\n"); 06863 Value = 268437120U; 06864 06865 // op0: VD 06866 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06867 op0 &= (1<<5) - 1; 06868 op0 <<= 21; 06869 Value |= op0; 06870 // op1: VA 06871 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06872 op1 &= (1<<5) - 1; 06873 op1 <<= 16; 06874 Value |= op1; 06875 // op2: VB 06876 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06877 op2 &= (1<<5) - 1; 06878 op2 <<= 11; 06879 Value |= op2; 06880 break; 06881 } 06882 case PPC::VSUM2SWS: { 06883 DEBUG(std::cerr << "Emitting VSUM2SWS\n"); 06884 Value = 268437128U; 06885 06886 // op0: VD 06887 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06888 op0 &= (1<<5) - 1; 06889 op0 <<= 21; 06890 Value |= op0; 06891 // op1: VA 06892 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06893 op1 &= (1<<5) - 1; 06894 op1 <<= 16; 06895 Value |= op1; 06896 // op2: VB 06897 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06898 op2 &= (1<<5) - 1; 06899 op2 <<= 11; 06900 Value |= op2; 06901 break; 06902 } 06903 case PPC::VSUM4SBS: { 06904 DEBUG(std::cerr << "Emitting VSUM4SBS\n"); 06905 Value = 268437128U; 06906 06907 // op0: VD 06908 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06909 op0 &= (1<<5) - 1; 06910 op0 <<= 21; 06911 Value |= op0; 06912 // op1: VA 06913 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06914 op1 &= (1<<5) - 1; 06915 op1 <<= 16; 06916 Value |= op1; 06917 // op2: VB 06918 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06919 op2 &= (1<<5) - 1; 06920 op2 <<= 11; 06921 Value |= op2; 06922 break; 06923 } 06924 case PPC::VSUM4SHS: { 06925 DEBUG(std::cerr << "Emitting VSUM4SHS\n"); 06926 Value = 268437064U; 06927 06928 // op0: VD 06929 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06930 op0 &= (1<<5) - 1; 06931 op0 <<= 21; 06932 Value |= op0; 06933 // op1: VA 06934 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06935 op1 &= (1<<5) - 1; 06936 op1 <<= 16; 06937 Value |= op1; 06938 // op2: VB 06939 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06940 op2 &= (1<<5) - 1; 06941 op2 <<= 11; 06942 Value |= op2; 06943 break; 06944 } 06945 case PPC::VSUM4UBS: { 06946 DEBUG(std::cerr << "Emitting VSUM4UBS\n"); 06947 Value = 268437000U; 06948 06949 // op0: VD 06950 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06951 op0 &= (1<<5) - 1; 06952 op0 <<= 21; 06953 Value |= op0; 06954 // op1: VA 06955 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06956 op1 &= (1<<5) - 1; 06957 op1 <<= 16; 06958 Value |= op1; 06959 // op2: VB 06960 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06961 op2 &= (1<<5) - 1; 06962 op2 <<= 11; 06963 Value |= op2; 06964 break; 06965 } 06966 case PPC::VSUMSWS: { 06967 DEBUG(std::cerr << "Emitting VSUMSWS\n"); 06968 Value = 268437384U; 06969 06970 // op0: VD 06971 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06972 op0 &= (1<<5) - 1; 06973 op0 <<= 21; 06974 Value |= op0; 06975 // op1: VA 06976 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06977 op1 &= (1<<5) - 1; 06978 op1 <<= 16; 06979 Value |= op1; 06980 // op2: VB 06981 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 06982 op2 &= (1<<5) - 1; 06983 op2 <<= 11; 06984 Value |= op2; 06985 break; 06986 } 06987 case PPC::VUPKHPX: { 06988 DEBUG(std::cerr << "Emitting VUPKHPX\n"); 06989 Value = 268436302U; 06990 06991 // op0: VD 06992 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 06993 op0 &= (1<<5) - 1; 06994 op0 <<= 21; 06995 Value |= op0; 06996 // op1: VB 06997 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 06998 op1 &= (1<<5) - 1; 06999 op1 <<= 11; 07000 Value |= op1; 07001 break; 07002 } 07003 case PPC::VUPKHSB: { 07004 DEBUG(std::cerr << "Emitting VUPKHSB\n"); 07005 Value = 268435982U; 07006 07007 // op0: VD 07008 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07009 op0 &= (1<<5) - 1; 07010 op0 <<= 21; 07011 Value |= op0; 07012 // op1: VB 07013 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07014 op1 &= (1<<5) - 1; 07015 op1 <<= 11; 07016 Value |= op1; 07017 break; 07018 } 07019 case PPC::VUPKHSH: { 07020 DEBUG(std::cerr << "Emitting VUPKHSH\n"); 07021 Value = 268436046U; 07022 07023 // op0: VD 07024 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07025 op0 &= (1<<5) - 1; 07026 op0 <<= 21; 07027 Value |= op0; 07028 // op1: VB 07029 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07030 op1 &= (1<<5) - 1; 07031 op1 <<= 11; 07032 Value |= op1; 07033 break; 07034 } 07035 case PPC::VUPKLPX: { 07036 DEBUG(std::cerr << "Emitting VUPKLPX\n"); 07037 Value = 268436430U; 07038 07039 // op0: VD 07040 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07041 op0 &= (1<<5) - 1; 07042 op0 <<= 21; 07043 Value |= op0; 07044 // op1: VB 07045 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07046 op1 &= (1<<5) - 1; 07047 op1 <<= 11; 07048 Value |= op1; 07049 break; 07050 } 07051 case PPC::VUPKLSB: { 07052 DEBUG(std::cerr << "Emitting VUPKLSB\n"); 07053 Value = 268436110U; 07054 07055 // op0: VD 07056 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07057 op0 &= (1<<5) - 1; 07058 op0 <<= 21; 07059 Value |= op0; 07060 // op1: VB 07061 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07062 op1 &= (1<<5) - 1; 07063 op1 <<= 11; 07064 Value |= op1; 07065 break; 07066 } 07067 case PPC::VUPKLSH: { 07068 DEBUG(std::cerr << "Emitting VUPKLSH\n"); 07069 Value = 268436174U; 07070 07071 // op0: VD 07072 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07073 op0 &= (1<<5) - 1; 07074 op0 <<= 21; 07075 Value |= op0; 07076 // op1: VB 07077 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07078 op1 &= (1<<5) - 1; 07079 op1 <<= 11; 07080 Value |= op1; 07081 break; 07082 } 07083 case PPC::VXOR: { 07084 DEBUG(std::cerr << "Emitting VXOR\n"); 07085 Value = 268436676U; 07086 07087 // op0: VD 07088 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07089 op0 &= (1<<5) - 1; 07090 op0 <<= 21; 07091 Value |= op0; 07092 // op1: VA 07093 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07094 op1 &= (1<<5) - 1; 07095 op1 <<= 16; 07096 Value |= op1; 07097 // op2: VB 07098 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 07099 op2 &= (1<<5) - 1; 07100 op2 <<= 11; 07101 Value |= op2; 07102 break; 07103 } 07104 case PPC::V_SET0: { 07105 DEBUG(std::cerr << "Emitting V_SET0\n"); 07106 Value = 268436676U; 07107 07108 // op0: VD 07109 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07110 Value |= getValueBit(op0, 4) << 25; 07111 Value |= getValueBit(op0, 3) << 24; 07112 Value |= getValueBit(op0, 2) << 23; 07113 Value |= getValueBit(op0, 1) << 22; 07114 Value |= getValueBit(op0, 0) << 21; 07115 Value |= getValueBit(op0, 4) << 20; 07116 Value |= getValueBit(op0, 3) << 19; 07117 Value |= getValueBit(op0, 2) << 18; 07118 Value |= getValueBit(op0, 1) << 17; 07119 Value |= getValueBit(op0, 0) << 16; 07120 Value |= getValueBit(op0, 4) << 15; 07121 Value |= getValueBit(op0, 3) << 14; 07122 Value |= getValueBit(op0, 2) << 13; 07123 Value |= getValueBit(op0, 1) << 12; 07124 Value |= getValueBit(op0, 0) << 11; 07125 break; 07126 } 07127 case PPC::XOR: { 07128 DEBUG(std::cerr << "Emitting XOR\n"); 07129 Value = 2080375416U; 07130 07131 // op0: A 07132 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07133 op0 &= (1<<5) - 1; 07134 op0 <<= 16; 07135 Value |= op0; 07136 // op1: RST 07137 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07138 op1 &= (1<<5) - 1; 07139 op1 <<= 21; 07140 Value |= op1; 07141 // op2: B 07142 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 07143 op2 &= (1<<5) - 1; 07144 op2 <<= 11; 07145 Value |= op2; 07146 break; 07147 } 07148 case PPC::XORI: { 07149 DEBUG(std::cerr << "Emitting XORI\n"); 07150 Value = 1744830464U; 07151 07152 // op0: B 07153 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07154 op0 &= (1<<5) - 1; 07155 op0 <<= 16; 07156 Value |= op0; 07157 // op1: A 07158 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07159 op1 &= (1<<5) - 1; 07160 op1 <<= 21; 07161 Value |= op1; 07162 // op2: C 07163 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 07164 op2 &= (1<<16) - 1; 07165 Value |= op2; 07166 break; 07167 } 07168 case PPC::XORIS: { 07169 DEBUG(std::cerr << "Emitting XORIS\n"); 07170 Value = 1811939328U; 07171 07172 // op0: B 07173 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 07174 op0 &= (1<<5) - 1; 07175 op0 <<= 16; 07176 Value |= op0; 07177 // op1: A 07178 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 07179 op1 &= (1<<5) - 1; 07180 op1 <<= 21; 07181 Value |= op1; 07182 // op2: C 07183 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 07184 op2 &= (1<<16) - 1; 07185 Value |= op2; 07186 break; 07187 } 07188 default: 07189 std::cerr << "Not supported instr: " << MI << "\n"; 07190 abort(); 07191 } 07192 return Value; 07193 } 07194