LLVM API Documentation

IA64GenAsmWriter.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Assembly Writer Source Fragment
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 /// printInstruction - This method is automatically generated by tablegen
00010 /// from the instruction set description.  This method returns true if the
00011 /// machine instruction was sufficiently described to print it, otherwise
00012 /// it returns false.
00013 bool IA64AsmPrinter::printInstruction(const MachineInstr *MI) {
00014   static const char * const OpStrs[] = {
00015     "PHINODE\n",  // PHI
00016     0,  // INLINEASM
00017     "add ", // ADD
00018     "add ", // ADD1
00019     "adds ",  // ADDIMM14
00020     "add ", // ADDIMM22
00021     "addl ",  // ADDL_EA
00022     "addl ",  // ADDL_GA
00023     "adds ",  // ADDS
00024     "// ADJUSTCALLSTACKDOWN\n", // ADJUSTCALLSTACKDOWN
00025     "// ADJUSTCALLSTACKUP\n", // ADJUSTCALLSTACKUP
00026     "alloc ", // ALLOC
00027     "and ", // AND
00028     "andcm ", // ANDCM
00029     "cmp.eq ",  // BCMPEQ
00030     "br.call.sptk rp = ", // BRCALL
00031     "br.call.sptk rp = ", // BRCALL_INDIRECT
00032     "br.call.sptk rp = ", // BRCALL_IPREL_ES
00033     "br.call.sptk rp = ", // BRCALL_IPREL_GA
00034     "(",  // BRCOND_CALL
00035     "(",  // BRCOND_NOTCALL
00036     "(",  // BRLCOND_CALL
00037     "(",  // BRLCOND_NOTCALL
00038     "(p0) brl.cond.sptk ",  // BRL_NOTCALL
00039     "(",  // CADDIMM22
00040     "(",  // CFMADS0
00041     "(",  // CFMADS1
00042     "(",  // CFMAS1
00043     "(",  // CFMOV
00044     "(",  // CFNMADS1
00045     "(",  // CFNMAS1
00046     "(",  // CMOV
00047     "cmp.eq ",  // CMPEQ
00048     "cmp.ge ",  // CMPGE
00049     "cmp.geu ", // CMPGEU
00050     "cmp.gt ",  // CMPGT
00051     "cmp.gtu ", // CMPGTU
00052     "cmp.le ",  // CMPLE
00053     "cmp.leu ", // CMPLEU
00054     "cmp.lt ",  // CMPLT
00055     "cmp.ltu ", // CMPLTU
00056     "cmp.ne ",  // CMPNE
00057     "dep.z ", // DEPZ
00058     "extr.u ",  // EXTRU
00059     "fabs ",  // FABS
00060     "fadd ",  // FADD
00061     "fadd.s ",  // FADDS
00062     "fcmp.eq ", // FCMPEQ
00063     "fcmp.ge ", // FCMPGE
00064     "fcmp.geu ",  // FCMPGEU
00065     "fcmp.gt ", // FCMPGT
00066     "fcmp.gtu ",  // FCMPGTU
00067     "fcmp.le ", // FCMPLE
00068     "fcmp.leu ",  // FCMPLEU
00069     "fcmp.lt ", // FCMPLT
00070     "fcmp.ltu ",  // FCMPLTU
00071     "fcmp.neq ",  // FCMPNE
00072     "fcvt.fx ", // FCVTFX
00073     "fcvt.fx.trunc ", // FCVTFXTRUNC
00074     "fcvt.fx.trunc.s1 ",  // FCVTFXTRUNCS1
00075     "fcvt.fxu ",  // FCVTFXU
00076     "fcvt.fxu.trunc ",  // FCVTFXUTRUNC
00077     "fcvt.fxu.trunc.s1 ", // FCVTFXUTRUNCS1
00078     "fcvt.xf ", // FCVTXF
00079     "fcvt.xuf ",  // FCVTXUF
00080     "fcvt.xuf.s1 ", // FCVTXUFS1
00081     "mov pr = ",  // FILL_ALL_PREDICATES_FROM_GR
00082     "fma ", // FMA
00083     "mov ", // FMOV
00084     "fmpy ",  // FMPY
00085     "fms ", // FMS
00086     "fneg ",  // FNEG
00087     "fnegabs ", // FNEGABS
00088     "fnma ",  // FNMA
00089     "fnorm.d ", // FNORMD
00090     "frcpa.s0 ",  // FRCPAS0
00091     "frcpa.s1 ",  // FRCPAS1
00092     "fsub ",  // FSUB
00093     "getf.d ",  // GETFD
00094     "getf.sig ",  // GETFSIG
00095     "getf.sig ",  // GETFSIGD
00096     "// IDEF\n",  // IDEF
00097     "// ",  // IDEF_FP_D
00098     "// ",  // IDEF_GR_D
00099     "// ",  // IDEF_PR_D
00100     "// IUSE\n",  // IUSE
00101     "ld1 ", // LD1
00102     "ld2 ", // LD2
00103     "ld4 ", // LD4
00104     "ld8 ", // LD8
00105     "ldfs ",  // LDF4
00106     "ldfd ",  // LDF8
00107     "ldf.fill ",  // LDF_FILL
00108     "mix1.l ",  // MIX1L
00109     "mix1.r ",  // MIX1R
00110     "mix2.l ",  // MIX2L
00111     "mix2.r ",  // MIX2R
00112     "mix4.l ",  // MIX4L
00113     "mix4.r ",  // MIX4R
00114     "mov ", // MOV
00115     "movl ",  // MOVL
00116     "movl ",  // MOVLIMM64
00117     "mov ", // MOVSIMM14
00118     "mov ", // MOVSIMM22
00119     "or ",  // OR
00120     "(",  // PCMPEQOR
00121     "(",  // PCMPEQUNC
00122     "(",  // PCMPEQUNCR0R0
00123     "(",  // PCMPNE
00124     "(",  // PFMOV
00125     "(",  // PMOV
00126     "popcnt ",  // POPCNT
00127     "// PSEUDO_ALLOC\n",  // PSEUDO_ALLOC
00128     "br.ret.sptk.many rp\n",  // RET
00129     "setf.d ",  // SETFD
00130     "setf.sig ",  // SETFSIG
00131     "setf.sig ",  // SETFSIGD
00132     "shl ", // SHL
00133     "shladd ",  // SHLADD
00134     "shl ", // SHLI
00135     "shr ", // SHRS
00136     "shr ", // SHRSI
00137     "shr.u ", // SHRU
00138     "shr.u ", // SHRUI
00139     "mov ", // SPILL_ALL_PREDICATES_TO_GR
00140     "st1 [",  // ST1
00141     "st2 [",  // ST2
00142     "st4 [",  // ST4
00143     "st8 [",  // ST8
00144     "stfs [", // STF4
00145     "stfd [", // STF8
00146     "stf.spill [",  // STF_SPILL
00147     ";;\n", // STOP
00148     "sub ", // SUB
00149     "sub ", // SUB1
00150     "sub ", // SUBIMM8
00151     "sxt1 ",  // SXT1
00152     "sxt2 ",  // SXT2
00153     "sxt4 ",  // SXT4
00154     "(",  // TCFMADS0
00155     "(",  // TCFMAS1
00156     "cmp.ne ",  // TCMPNE
00157     "(",  // TPCADDIMM22
00158     "(",  // TPCADDS
00159     "(",  // TPCMPEQ
00160     "(",  // TPCMPEQOR
00161     "(",  // TPCMPEQR0R0
00162     "(",  // TPCMPIMM8NE
00163     "(",  // TPCMPNE
00164     "(",  // TPCMPNER0R0
00165     "xma.h ", // XMAHD
00166     "xma.hu ",  // XMAHUD
00167     "xma.l ", // XMAL
00168     "xma.l ", // XMALD
00169     "xor ", // XOR
00170     "zxt1 ",  // ZXT1
00171     "zxt2 ",  // ZXT2
00172     "zxt4 ",  // ZXT4
00173     "(",  // pOR
00174   };
00175 
00176   // Emit the opcode for the instruction.
00177   if (const char *AsmStr = OpStrs[MI->getOpcode()])
00178     O << AsmStr;
00179 
00180   switch (MI->getOpcode()) {
00181   default: return false;
00182   case IA64::INLINEASM: printInlineAsm(MI); break;
00183   case IA64::ADD:
00184   case IA64::ADD1:
00185   case IA64::AND:
00186   case IA64::ANDCM:
00187   case IA64::FADD:
00188   case IA64::FADDS:
00189   case IA64::FMPY:
00190   case IA64::FSUB:
00191   case IA64::MIX1L:
00192   case IA64::MIX1R:
00193   case IA64::MIX2L:
00194   case IA64::MIX2R:
00195   case IA64::MIX4L:
00196   case IA64::MIX4R:
00197   case IA64::OR:
00198   case IA64::SHL:
00199   case IA64::SHLI:
00200   case IA64::SHRS:
00201   case IA64::SHRSI:
00202   case IA64::SHRU:
00203   case IA64::SHRUI:
00204   case IA64::SUB:
00205   case IA64::SUB1:
00206   case IA64::XOR:
00207     printOperand(MI, 0); 
00208     O << " = "; 
00209     printOperand(MI, 1); 
00210     O << ", "; 
00211     printOperand(MI, 2); 
00212     switch (MI->getOpcode()) {
00213     case IA64::ADD: 
00214     case IA64::AND: 
00215     case IA64::ANDCM: 
00216     case IA64::FADD: 
00217     case IA64::FADDS: 
00218     case IA64::FMPY: 
00219     case IA64::FSUB: 
00220     case IA64::MIX1L: 
00221     case IA64::MIX1R: 
00222     case IA64::MIX2L: 
00223     case IA64::MIX2R: 
00224     case IA64::MIX4L: 
00225     case IA64::MIX4R: 
00226     case IA64::OR: 
00227     case IA64::SHL: 
00228     case IA64::SHLI: 
00229     case IA64::SHRS: 
00230     case IA64::SHRSI: 
00231     case IA64::SHRU: 
00232     case IA64::SHRUI: 
00233     case IA64::SUB: 
00234     case IA64::XOR: O << "\n"; break;
00235     case IA64::ADD1: 
00236     case IA64::SUB1: O << ", 1\n"; break;
00237     }
00238     break;
00239   case IA64::ADDIMM14:
00240   case IA64::ADDIMM22:
00241   case IA64::ADDL_EA:
00242   case IA64::ADDL_GA:
00243   case IA64::ADDS:
00244     printOperand(MI, 0); 
00245     O << " = "; 
00246     switch (MI->getOpcode()) {
00247     case IA64::ADDIMM14: 
00248     case IA64::ADDS: printS14ImmOperand(MI, 2); break;
00249     case IA64::ADDIMM22: printS22ImmOperand(MI, 2); break;
00250     case IA64::ADDL_EA: printCallOperand(MI, 2); break;
00251     case IA64::ADDL_GA: printGlobalOperand(MI, 2); break;
00252     }
00253     O << ", "; 
00254     printOperand(MI, 1); 
00255     O << "\n"; 
00256     break;
00257   case IA64::ADJUSTCALLSTACKDOWN:
00258   case IA64::ADJUSTCALLSTACKUP:
00259   case IA64::IDEF:
00260   case IA64::IUSE:
00261   case IA64::PHI:
00262   case IA64::PSEUDO_ALLOC:
00263   case IA64::RET:
00264   case IA64::STOP:
00265     break;
00266   case IA64::ALLOC:
00267     printOperand(MI, 0); 
00268     O << " = ar.pfs,"; 
00269     printOperand(MI, 1); 
00270     O << ","; 
00271     printOperand(MI, 2); 
00272     O << ","; 
00273     printOperand(MI, 3); 
00274     O << ","; 
00275     printOperand(MI, 4); 
00276     O << "\n"; 
00277     break;
00278   case IA64::BCMPEQ:
00279     printOperand(MI, 0); 
00280     O << ", dst2 = "; 
00281     printOperand(MI, 2); 
00282     O << ", "; 
00283     printOperand(MI, 3); 
00284     O << "\n"; 
00285     break;
00286   case IA64::BRCALL:
00287   case IA64::BRCALL_INDIRECT:
00288   case IA64::BRCALL_IPREL_ES:
00289   case IA64::BRCALL_IPREL_GA:
00290   case IA64::BRL_NOTCALL:
00291   case IA64::FILL_ALL_PREDICATES_FROM_GR:
00292     switch (MI->getOpcode()) {
00293     case IA64::BRCALL: 
00294     case IA64::BRCALL_IPREL_ES: 
00295     case IA64::BRCALL_IPREL_GA: printCallOperand(MI, 0); break;
00296     case IA64::BRCALL_INDIRECT: 
00297     case IA64::BRL_NOTCALL: 
00298     case IA64::FILL_ALL_PREDICATES_FROM_GR: printOperand(MI, 0); break;
00299     }
00300     O << "\n"; 
00301     break;
00302   case IA64::BRCOND_CALL:
00303   case IA64::BRCOND_NOTCALL:
00304   case IA64::BRLCOND_CALL:
00305   case IA64::BRLCOND_NOTCALL:
00306   case IA64::FABS:
00307   case IA64::FCVTFX:
00308   case IA64::FCVTFXTRUNC:
00309   case IA64::FCVTFXTRUNCS1:
00310   case IA64::FCVTFXU:
00311   case IA64::FCVTFXUTRUNC:
00312   case IA64::FCVTFXUTRUNCS1:
00313   case IA64::FCVTXF:
00314   case IA64::FCVTXUF:
00315   case IA64::FCVTXUFS1:
00316   case IA64::FMOV:
00317   case IA64::FNEG:
00318   case IA64::FNEGABS:
00319   case IA64::FNORMD:
00320   case IA64::GETFD:
00321   case IA64::GETFSIG:
00322   case IA64::GETFSIGD:
00323   case IA64::MOV:
00324   case IA64::POPCNT:
00325   case IA64::SETFD:
00326   case IA64::SETFSIG:
00327   case IA64::SETFSIGD:
00328   case IA64::ST1:
00329   case IA64::ST2:
00330   case IA64::ST4:
00331   case IA64::ST8:
00332   case IA64::STF4:
00333   case IA64::STF8:
00334   case IA64::STF_SPILL:
00335   case IA64::SXT1:
00336   case IA64::SXT2:
00337   case IA64::SXT4:
00338   case IA64::ZXT1:
00339   case IA64::ZXT2:
00340   case IA64::ZXT4:
00341     printOperand(MI, 0); 
00342     switch (MI->getOpcode()) {
00343     case IA64::BRCOND_CALL: O << ") br.cond.call.sptk "; break;
00344     case IA64::BRCOND_NOTCALL: O << ") br.cond.sptk "; break;
00345     case IA64::BRLCOND_CALL: O << ") brl.cond.call.sptk "; break;
00346     case IA64::BRLCOND_NOTCALL: O << ") brl.cond.sptk "; break;
00347     case IA64::FABS: 
00348     case IA64::FCVTFX: 
00349     case IA64::FCVTFXTRUNC: 
00350     case IA64::FCVTFXTRUNCS1: 
00351     case IA64::FCVTFXU: 
00352     case IA64::FCVTFXUTRUNC: 
00353     case IA64::FCVTFXUTRUNCS1: 
00354     case IA64::FCVTXF: 
00355     case IA64::FCVTXUF: 
00356     case IA64::FCVTXUFS1: 
00357     case IA64::FMOV: 
00358     case IA64::FNEG: 
00359     case IA64::FNEGABS: 
00360     case IA64::FNORMD: 
00361     case IA64::GETFD: 
00362     case IA64::GETFSIG: 
00363     case IA64::GETFSIGD: 
00364     case IA64::MOV: 
00365     case IA64::POPCNT: 
00366     case IA64::SETFD: 
00367     case IA64::SETFSIG: 
00368     case IA64::SETFSIGD: 
00369     case IA64::SXT1: 
00370     case IA64::SXT2: 
00371     case IA64::SXT4: 
00372     case IA64::ZXT1: 
00373     case IA64::ZXT2: 
00374     case IA64::ZXT4: O << " = "; break;
00375     case IA64::ST1: 
00376     case IA64::ST2: 
00377     case IA64::ST4: 
00378     case IA64::ST8: 
00379     case IA64::STF4: 
00380     case IA64::STF8: 
00381     case IA64::STF_SPILL: O << "] = "; break;
00382     }
00383     printOperand(MI, 1); 
00384     O << "\n"; 
00385     break;
00386   case IA64::CADDIMM22:
00387     printOperand(MI, 3); 
00388     O << ") add "; 
00389     printOperand(MI, 0); 
00390     O << " = "; 
00391     printS22ImmOperand(MI, 2); 
00392     O << ", "; 
00393     printOperand(MI, 1); 
00394     O << "\n"; 
00395     break;
00396   case IA64::CFMADS0:
00397   case IA64::CFMADS1:
00398   case IA64::CFMAS1:
00399   case IA64::CFNMADS1:
00400   case IA64::CFNMAS1:
00401   case IA64::TCFMADS0:
00402   case IA64::TCFMAS1:
00403     printOperand(MI, 4); 
00404     switch (MI->getOpcode()) {
00405     case IA64::CFMADS0: 
00406     case IA64::TCFMADS0: O << ") fma.d.s0 "; break;
00407     case IA64::CFMADS1: O << ") fma.d.s1 "; break;
00408     case IA64::CFMAS1: 
00409     case IA64::TCFMAS1: O << ") fma.s1 "; break;
00410     case IA64::CFNMADS1: O << ") fnma.d.s1 "; break;
00411     case IA64::CFNMAS1: O << ") fnma.s1 "; break;
00412     }
00413     printOperand(MI, 0); 
00414     O << " = "; 
00415     printOperand(MI, 1); 
00416     O << ", "; 
00417     printOperand(MI, 2); 
00418     O << ", "; 
00419     printOperand(MI, 3); 
00420     O << "\n"; 
00421     break;
00422   case IA64::CFMOV:
00423   case IA64::CMOV:
00424   case IA64::PFMOV:
00425   case IA64::PMOV:
00426     printOperand(MI, 2); 
00427     O << ") mov "; 
00428     printOperand(MI, 0); 
00429     O << " = "; 
00430     printOperand(MI, 1); 
00431     O << "\n"; 
00432     break;
00433   case IA64::CMPEQ:
00434   case IA64::CMPGE:
00435   case IA64::CMPGEU:
00436   case IA64::CMPGT:
00437   case IA64::CMPGTU:
00438   case IA64::CMPLE:
00439   case IA64::CMPLEU:
00440   case IA64::CMPLT:
00441   case IA64::CMPLTU:
00442   case IA64::CMPNE:
00443   case IA64::FCMPEQ:
00444   case IA64::FCMPGE:
00445   case IA64::FCMPGEU:
00446   case IA64::FCMPGT:
00447   case IA64::FCMPGTU:
00448   case IA64::FCMPLE:
00449   case IA64::FCMPLEU:
00450   case IA64::FCMPLT:
00451   case IA64::FCMPLTU:
00452   case IA64::FCMPNE:
00453   case IA64::TCMPNE:
00454     printOperand(MI, 0); 
00455     O << ", p0 = "; 
00456     printOperand(MI, 1); 
00457     O << ", "; 
00458     printOperand(MI, 2); 
00459     O << "\n"; 
00460     break;
00461   case IA64::DEPZ:
00462   case IA64::EXTRU:
00463   case IA64::FMA:
00464   case IA64::FMS:
00465   case IA64::FNMA:
00466   case IA64::SHLADD:
00467   case IA64::XMAHD:
00468   case IA64::XMAHUD:
00469   case IA64::XMAL:
00470   case IA64::XMALD:
00471     printOperand(MI, 0); 
00472     O << " = "; 
00473     printOperand(MI, 1); 
00474     O << ", "; 
00475     switch (MI->getOpcode()) {
00476     case IA64::DEPZ: 
00477     case IA64::EXTRU: 
00478     case IA64::FMA: 
00479     case IA64::FMS: 
00480     case IA64::FNMA: 
00481     case IA64::XMAHD: 
00482     case IA64::XMAHUD: 
00483     case IA64::XMAL: 
00484     case IA64::XMALD: printOperand(MI, 2); break;
00485     case IA64::SHLADD: printS64ImmOperand(MI, 2); break;
00486     }
00487     O << ", "; 
00488     printOperand(MI, 3); 
00489     O << "\n"; 
00490     break;
00491   case IA64::FRCPAS0:
00492   case IA64::FRCPAS1:
00493     printOperand(MI, 0); 
00494     O << ", "; 
00495     printOperand(MI, 1); 
00496     O << " = "; 
00497     printOperand(MI, 2); 
00498     O << ", "; 
00499     printOperand(MI, 3); 
00500     O << "\n"; 
00501     break;
00502   case IA64::IDEF_FP_D:
00503   case IA64::IDEF_GR_D:
00504   case IA64::IDEF_PR_D:
00505   case IA64::SPILL_ALL_PREDICATES_TO_GR:
00506     printOperand(MI, 0); 
00507     switch (MI->getOpcode()) {
00508     case IA64::IDEF_FP_D: 
00509     case IA64::IDEF_GR_D: 
00510     case IA64::IDEF_PR_D: O << " = IDEF\n"; break;
00511     case IA64::SPILL_ALL_PREDICATES_TO_GR: O << " = pr\n"; break;
00512     }
00513     break;
00514   case IA64::LD1:
00515   case IA64::LD2:
00516   case IA64::LD4:
00517   case IA64::LD8:
00518   case IA64::LDF4:
00519   case IA64::LDF8:
00520   case IA64::LDF_FILL:
00521     printOperand(MI, 0); 
00522     O << " = ["; 
00523     printOperand(MI, 1); 
00524     O << "]\n"; 
00525     break;
00526   case IA64::MOVL:
00527   case IA64::MOVLIMM64:
00528   case IA64::MOVSIMM14:
00529   case IA64::MOVSIMM22:
00530     printOperand(MI, 0); 
00531     O << " = "; 
00532     switch (MI->getOpcode()) {
00533     case IA64::MOVL: 
00534     case IA64::MOVLIMM64: printS64ImmOperand(MI, 1); break;
00535     case IA64::MOVSIMM14: printS14ImmOperand(MI, 1); break;
00536     case IA64::MOVSIMM22: printS22ImmOperand(MI, 1); break;
00537     }
00538     O << "\n"; 
00539     break;
00540   case IA64::PCMPEQOR:
00541   case IA64::PCMPEQUNC:
00542   case IA64::PCMPNE:
00543   case IA64::TPCMPEQ:
00544   case IA64::TPCMPEQOR:
00545   case IA64::TPCMPNE:
00546     printOperand(MI, 3); 
00547     switch (MI->getOpcode()) {
00548     case IA64::PCMPEQOR: 
00549     case IA64::TPCMPEQOR: O << ") cmp.eq.or "; break;
00550     case IA64::PCMPEQUNC: O << ") cmp.eq.unc "; break;
00551     case IA64::PCMPNE: 
00552     case IA64::TPCMPNE: O << ") cmp.ne "; break;
00553     case IA64::TPCMPEQ: O << ") cmp.eq "; break;
00554     }
00555     printOperand(MI, 0); 
00556     O << ", p0 = "; 
00557     printOperand(MI, 1); 
00558     O << ", "; 
00559     printOperand(MI, 2); 
00560     O << "\n"; 
00561     break;
00562   case IA64::PCMPEQUNCR0R0:
00563   case IA64::TPCMPEQR0R0:
00564   case IA64::TPCMPNER0R0:
00565     printOperand(MI, 1); 
00566     switch (MI->getOpcode()) {
00567     case IA64::PCMPEQUNCR0R0: O << ") cmp.eq.unc "; break;
00568     case IA64::TPCMPEQR0R0: O << ") cmp.eq "; break;
00569     case IA64::TPCMPNER0R0: O << ") cmp.ne "; break;
00570     }
00571     printOperand(MI, 0); 
00572     O << ", p0 = r0, r0\n"; 
00573     break;
00574   case IA64::SUBIMM8:
00575     printOperand(MI, 0); 
00576     O << " = "; 
00577     printS8ImmOperand(MI, 1); 
00578     O << ", "; 
00579     printOperand(MI, 2); 
00580     O << "\n"; 
00581     break;
00582   case IA64::TPCADDIMM22:
00583     printOperand(MI, 2); 
00584     O << ") add "; 
00585     printOperand(MI, 0); 
00586     O << " = "; 
00587     printS22ImmOperand(MI, 1); 
00588     O << ", "; 
00589     printOperand(MI, 0); 
00590     O << "\n"; 
00591     break;
00592   case IA64::TPCADDS:
00593     printOperand(MI, 2); 
00594     O << ") adds "; 
00595     printOperand(MI, 0); 
00596     O << " = "; 
00597     printS14ImmOperand(MI, 1); 
00598     O << ", "; 
00599     printOperand(MI, 0); 
00600     O << "\n"; 
00601     break;
00602   case IA64::TPCMPIMM8NE:
00603     printOperand(MI, 3); 
00604     O << ") cmp.ne "; 
00605     printOperand(MI, 0); 
00606     O << " , p0 = "; 
00607     printS22ImmOperand(MI, 1); 
00608     O << ", "; 
00609     printOperand(MI, 2); 
00610     O << "\n"; 
00611     break;
00612   case IA64::pOR:
00613     printOperand(MI, 3); 
00614     O << ") or "; 
00615     printOperand(MI, 0); 
00616     O << " = "; 
00617     printOperand(MI, 1); 
00618     O << ", "; 
00619     printOperand(MI, 2); 
00620     O << "\n"; 
00621     break;
00622   }
00623   return true;
00624 }