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AlphaISelDAGToDAG.cpp

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00001 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Andrew Lenharth and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines a pattern matching instruction selector for Alpha,
00011 // converting from a legalized dag to a Alpha dag.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "Alpha.h"
00016 #include "AlphaTargetMachine.h"
00017 #include "AlphaISelLowering.h"
00018 #include "llvm/CodeGen/MachineInstrBuilder.h"
00019 #include "llvm/CodeGen/MachineFrameInfo.h"
00020 #include "llvm/CodeGen/MachineFunction.h"
00021 #include "llvm/CodeGen/SSARegMap.h"
00022 #include "llvm/CodeGen/SelectionDAG.h"
00023 #include "llvm/CodeGen/SelectionDAGISel.h"
00024 #include "llvm/Target/TargetOptions.h"
00025 #include "llvm/ADT/Statistic.h"
00026 #include "llvm/Constants.h"
00027 #include "llvm/GlobalValue.h"
00028 #include "llvm/Intrinsics.h"
00029 #include "llvm/Support/Debug.h"
00030 #include "llvm/Support/MathExtras.h"
00031 #include <algorithm>
00032 #include <iostream>
00033 #include <set>
00034 using namespace llvm;
00035 
00036 namespace {
00037 
00038   //===--------------------------------------------------------------------===//
00039   /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
00040   /// instructions for SelectionDAG operations.
00041   class AlphaDAGToDAGISel : public SelectionDAGISel {
00042     AlphaTargetLowering AlphaLowering;
00043 
00044     static const int64_t IMM_LOW  = -32768;
00045     static const int64_t IMM_HIGH = 32767;
00046     static const int64_t IMM_MULT = 65536;
00047     static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
00048     static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW  * IMM_MULT;
00049 
00050     static int64_t get_ldah16(int64_t x) {
00051       int64_t y = x / IMM_MULT;
00052       if (x % IMM_MULT > IMM_HIGH)
00053   ++y;
00054       return y;
00055     }
00056 
00057     static int64_t get_lda16(int64_t x) {
00058       return x - get_ldah16(x) * IMM_MULT;
00059     }
00060 
00061     static uint64_t get_zapImm(uint64_t x) {
00062       unsigned int build = 0;
00063       for(int i = 0; i < 8; ++i)
00064   {
00065     if ((x & 0x00FF) == 0x00FF)
00066       build |= 1 << i;
00067     else if ((x & 0x00FF) != 0)
00068       { build = 0; break; }
00069     x >>= 8;
00070   }
00071       return build;
00072     }
00073 
00074     static uint64_t getNearPower2(uint64_t x) {
00075       if (!x) return 0;
00076       unsigned at = CountLeadingZeros_64(x);
00077       uint64_t complow = 1 << (63 - at);
00078       uint64_t comphigh = 1 << (64 - at);
00079       //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
00080       if (abs(complow - x) <= abs(comphigh - x))
00081         return complow;
00082       else
00083         return comphigh;
00084     }
00085 
00086     static bool isFPZ(SDOperand N) {
00087       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
00088       return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
00089     }
00090     static bool isFPZn(SDOperand N) {
00091       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
00092       return (CN && CN->isExactlyValue(-0.0));
00093     }
00094     static bool isFPZp(SDOperand N) {
00095       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
00096       return (CN && CN->isExactlyValue(+0.0));
00097     }
00098 
00099   public:
00100     AlphaDAGToDAGISel(TargetMachine &TM)
00101       : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) 
00102     {}
00103 
00104     /// getI64Imm - Return a target constant with the specified value, of type
00105     /// i64.
00106     inline SDOperand getI64Imm(int64_t Imm) {
00107       return CurDAG->getTargetConstant(Imm, MVT::i64);
00108     }
00109 
00110     // Select - Convert the specified operand from a target-independent to a
00111     // target-specific node if it hasn't already been changed.
00112     void Select(SDOperand &Result, SDOperand Op);
00113     
00114     /// InstructionSelectBasicBlock - This callback is invoked by
00115     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
00116     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
00117     
00118     virtual const char *getPassName() const {
00119       return "Alpha DAG->DAG Pattern Instruction Selection";
00120     } 
00121 
00122 // Include the pieces autogenerated from the target description.
00123 #include "AlphaGenDAGISel.inc"
00124     
00125 private:
00126     SDOperand getGlobalBaseReg();
00127     SDOperand getRASaveReg();
00128     SDOperand SelectCALL(SDOperand Op);
00129 
00130   };
00131 }
00132 
00133 /// getGlobalBaseReg - Output the instructions required to put the
00134 /// GOT address into a register.
00135 ///
00136 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
00137   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
00138                                 AlphaLowering.getVRegGP(), 
00139                                 MVT::i64);
00140 }
00141 
00142 /// getRASaveReg - Grab the return address
00143 ///
00144 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
00145   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
00146                                 AlphaLowering.getVRegRA(), 
00147                                 MVT::i64);
00148 }
00149 
00150 /// InstructionSelectBasicBlock - This callback is invoked by
00151 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
00152 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
00153   DEBUG(BB->dump());
00154   
00155   // Select target instructions for the DAG.
00156   DAG.setRoot(SelectRoot(DAG.getRoot()));
00157   CodeGenMap.clear();
00158   DAG.RemoveDeadNodes();
00159   
00160   // Emit machine code to BB. 
00161   ScheduleAndEmitDAG(DAG);
00162 }
00163 
00164 // Select - Convert the specified operand from a target-independent to a
00165 // target-specific node if it hasn't already been changed.
00166 void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
00167   SDNode *N = Op.Val;
00168   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
00169       N->getOpcode() < AlphaISD::FIRST_NUMBER) {
00170     Result = Op;
00171     return;   // Already selected.
00172   }
00173 
00174   // If this has already been converted, use it.
00175   std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
00176   if (CGMI != CodeGenMap.end()) {
00177     Result = CGMI->second;
00178     return;
00179   }
00180 
00181   switch (N->getOpcode()) {
00182   default: break;
00183   case AlphaISD::CALL:
00184     Result = SelectCALL(Op);
00185     return;
00186 
00187   case ISD::FrameIndex: {
00188     int FI = cast<FrameIndexSDNode>(N)->getIndex();
00189     Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
00190                                   CurDAG->getTargetFrameIndex(FI, MVT::i32),
00191                                   getI64Imm(0));
00192     return;
00193   }
00194   case AlphaISD::GlobalBaseReg: 
00195     Result = getGlobalBaseReg();
00196     return;
00197   
00198   case AlphaISD::DivCall: {
00199     SDOperand Chain = CurDAG->getEntryNode();
00200     SDOperand N0, N1, N2;
00201     Select(N0, Op.getOperand(0));
00202     Select(N1, Op.getOperand(1));
00203     Select(N2, Op.getOperand(2));
00204     Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, 
00205          SDOperand(0,0));
00206     Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, 
00207          Chain.getValue(1));
00208     Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, 
00209          Chain.getValue(1));
00210     SDNode *CNode =
00211       CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, 
00212                             Chain, Chain.getValue(1));
00213     Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, 
00214           SDOperand(CNode, 1));
00215     Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
00216     return;
00217   }
00218 
00219   case ISD::READCYCLECOUNTER: {
00220     SDOperand Chain;
00221     Select(Chain, N->getOperand(0)); //Select chain
00222     Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
00223     return;
00224   }
00225 
00226   case ISD::RET: {
00227     SDOperand Chain;
00228     Select(Chain, N->getOperand(0));     // Token chain.
00229     SDOperand InFlag(0,0);
00230 
00231     if (N->getNumOperands() == 2) {
00232       SDOperand Val;
00233       Select(Val, N->getOperand(1));
00234       if (N->getOperand(1).getValueType() == MVT::i64) {
00235         Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
00236         InFlag = Chain.getValue(1);
00237       } else if (N->getOperand(1).getValueType() == MVT::f64 ||
00238                  N->getOperand(1).getValueType() == MVT::f32) {
00239         Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
00240         InFlag = Chain.getValue(1);
00241       }
00242     }
00243     Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
00244     InFlag = Chain.getValue(1);
00245     
00246     // Finally, select this to a ret instruction.
00247     Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
00248     return;
00249   }
00250   case ISD::Constant: {
00251     uint64_t uval = cast<ConstantSDNode>(N)->getValue();
00252     
00253     if (uval == 0) {
00254       Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
00255                                       MVT::i64);
00256       return;
00257     }
00258 
00259     int64_t val = (int64_t)uval;
00260     int32_t val32 = (int32_t)val;
00261     if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
00262   val >= IMM_LOW  + IMM_LOW  * IMM_MULT)
00263       break; //(LDAH (LDA))
00264     if ((uval >> 32) == 0 && //empty upper bits
00265   val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
00266       //  val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
00267       break; //(zext (LDAH (LDA)))
00268     //Else use the constant pool
00269     MachineConstantPool *CP = BB->getParent()->getConstantPool();
00270     ConstantUInt *C =
00271       ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
00272     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
00273     SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
00274                                         getGlobalBaseReg());
00275     Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, 
00276                                   CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
00277     return;
00278   }
00279   case ISD::TargetConstantFP: {
00280     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
00281     bool isDouble = N->getValueType(0) == MVT::f64;
00282     MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
00283     if (CN->isExactlyValue(+0.0)) {
00284       Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
00285                                     T, CurDAG->getRegister(Alpha::F31, T),
00286                                     CurDAG->getRegister(Alpha::F31, T));
00287       return;
00288     } else if ( CN->isExactlyValue(-0.0)) {
00289       Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
00290                                     T, CurDAG->getRegister(Alpha::F31, T),
00291                                     CurDAG->getRegister(Alpha::F31, T));
00292       return;
00293     } else {
00294       abort();
00295     }
00296     break;
00297   }
00298 
00299   case ISD::SETCC:
00300     if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
00301       unsigned Opc = Alpha::WTF;
00302       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
00303       bool rev = false;
00304       bool isNE = false;
00305       switch(CC) {
00306       default: N->dump(); assert(0 && "Unknown FP comparison!");
00307       case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
00308       case ISD::SETLT: Opc = Alpha::CMPTLT; break;
00309       case ISD::SETLE: Opc = Alpha::CMPTLE; break;
00310       case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
00311       case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
00312       case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
00313       };
00314       SDOperand tmp1, tmp2;
00315       Select(tmp1, N->getOperand(0));
00316       Select(tmp2, N->getOperand(1));
00317       SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, 
00318                                           rev?tmp2:tmp1,
00319                                           rev?tmp1:tmp2);
00320       if (isNE) 
00321         cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0), 
00322                                     CurDAG->getRegister(Alpha::F31, MVT::f64));
00323       
00324       SDOperand LD;
00325       if (AlphaLowering.hasITOF()) {
00326         LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0));
00327       } else {
00328         int FrameIdx =
00329           CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
00330         SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
00331         SDOperand ST =
00332           SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other, 
00333                                           SDOperand(cmp, 0), FI,
00334                                           CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
00335         LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, 
00336                                              CurDAG->getRegister(Alpha::R31, MVT::i64),
00337                                              ST), 0);
00338       }
00339       Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, 
00340                                                CurDAG->getRegister(Alpha::R31, MVT::i64),
00341                                                LD), 0);
00342       return;
00343     }
00344     break;
00345 
00346   case ISD::SELECT:
00347     if (MVT::isFloatingPoint(N->getValueType(0)) &&
00348   (N->getOperand(0).getOpcode() != ISD::SETCC ||
00349    !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
00350       //This should be the condition not covered by the Patterns
00351       //FIXME: Don't have SelectCode die, but rather return something testable
00352       // so that things like this can be caught in fall though code
00353       //move int to fp
00354       bool isDouble = N->getValueType(0) == MVT::f64;
00355       SDOperand LD, cond, TV, FV;
00356       Select(cond, N->getOperand(0));
00357       Select(TV, N->getOperand(1));
00358       Select(FV, N->getOperand(2));
00359       
00360       if (AlphaLowering.hasITOF()) {
00361   LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
00362       } else {
00363   int FrameIdx =
00364     CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
00365   SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
00366   SDOperand ST =
00367           SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
00368                                           cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)), 0);
00369   LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
00370                                              CurDAG->getRegister(Alpha::R31, MVT::i64),
00371                                              ST), 0);
00372       }
00373       Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
00374                                                MVT::f64, FV, TV, LD), 0);
00375       return;
00376     }
00377     break;
00378 
00379   case ISD::AND: {
00380     ConstantSDNode* SC;
00381     ConstantSDNode* MC;
00382     if (N->getOperand(0).getOpcode() == ISD::SRL &&
00383   (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
00384   (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
00385       {
00386   uint64_t sval = SC->getValue();
00387   uint64_t mval = MC->getValue();
00388   if (get_zapImm(mval)) //the result is a zap, let the autogened stuff deal
00389     break;
00390   // given mask X, and shift S, we want to see if there is any zap in the mask
00391   // if we play around with the botton S bits
00392   uint64_t dontcare = (~0ULL) >> (64 - sval);
00393   uint64_t mask = mval << sval;
00394 
00395   if (get_zapImm(mask | dontcare))
00396     mask = mask | dontcare;
00397 
00398   if (get_zapImm(mask)) {
00399     SDOperand Src;
00400     Select(Src, N->getOperand(0).getOperand(0));
00401     SDOperand Z = 
00402       SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, Src, 
00403               getI64Imm(get_zapImm(mask))), 0);
00404     Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z, 
00405                getI64Imm(sval)), 0);
00406     return;
00407   }
00408       }
00409     break;
00410   }
00411 
00412   }
00413 
00414   SelectCode(Result, Op);
00415 }
00416 
00417 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
00418   //TODO: add flag stuff to prevent nondeturministic breakage!
00419 
00420   SDNode *N = Op.Val;
00421   SDOperand Chain;
00422   SDOperand Addr = N->getOperand(1);
00423   SDOperand InFlag(0,0);  // Null incoming flag value.
00424   Select(Chain, N->getOperand(0));
00425 
00426    std::vector<SDOperand> CallOperands;
00427    std::vector<MVT::ValueType> TypeOperands;
00428   
00429    //grab the arguments
00430    for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
00431      SDOperand Tmp;
00432      TypeOperands.push_back(N->getOperand(i).getValueType());
00433      Select(Tmp, N->getOperand(i));
00434      CallOperands.push_back(Tmp);
00435    }
00436    int count = N->getNumOperands() - 2;
00437 
00438    static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
00439                                        Alpha::R19, Alpha::R20, Alpha::R21};
00440    static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
00441                                          Alpha::F19, Alpha::F20, Alpha::F21};
00442    
00443    for (int i = 6; i < count; ++i) {
00444      unsigned Opc = Alpha::WTF;
00445      if (MVT::isInteger(TypeOperands[i])) {
00446        Opc = Alpha::STQ;
00447      } else if (TypeOperands[i] == MVT::f32) {
00448        Opc = Alpha::STS;
00449      } else if (TypeOperands[i] == MVT::f64) {
00450        Opc = Alpha::STT;
00451      } else
00452        assert(0 && "Unknown operand"); 
00453      Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], 
00454                                              getI64Imm((i - 6) * 8), 
00455                                              CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
00456                                              Chain), 0);
00457    }
00458    for (int i = 0; i < std::min(6, count); ++i) {
00459      if (MVT::isInteger(TypeOperands[i])) {
00460        Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
00461        InFlag = Chain.getValue(1);
00462      } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
00463        Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
00464        InFlag = Chain.getValue(1);
00465      } else
00466        assert(0 && "Unknown operand"); 
00467    }
00468 
00469 
00470    // Finally, once everything is in registers to pass to the call, emit the
00471    // call itself.
00472    if (Addr.getOpcode() == AlphaISD::GPRelLo) {
00473      SDOperand GOT = getGlobalBaseReg();
00474      Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
00475      InFlag = Chain.getValue(1);
00476      Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, 
00477                                              Addr.getOperand(0), Chain, InFlag), 0);
00478    } else {
00479      Select(Addr, Addr);
00480      Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
00481      InFlag = Chain.getValue(1);
00482      Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, 
00483                                              Chain, InFlag), 0);
00484    }
00485    InFlag = Chain.getValue(1);
00486 
00487    std::vector<SDOperand> CallResults;
00488   
00489    switch (N->getValueType(0)) {
00490    default: assert(0 && "Unexpected ret value!");
00491      case MVT::Other: break;
00492    case MVT::i64:
00493      Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
00494      CallResults.push_back(Chain.getValue(0));
00495      break;
00496    case MVT::f32:
00497      Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
00498      CallResults.push_back(Chain.getValue(0));
00499      break;
00500    case MVT::f64:
00501      Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
00502      CallResults.push_back(Chain.getValue(0));
00503      break;
00504    }
00505 
00506    CallResults.push_back(Chain);
00507    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
00508      CodeGenMap[Op.getValue(i)] = CallResults[i];
00509    return CallResults[Op.ResNo];
00510 }
00511 
00512 
00513 /// createAlphaISelDag - This pass converts a legalized DAG into a 
00514 /// Alpha-specific DAG, ready for instruction scheduling.
00515 ///
00516 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
00517   return new AlphaDAGToDAGISel(TM);
00518 }