LLVM API Documentation

X86GenRegisterInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Register Information Source Fragment
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 namespace {     // Register classes...
00012   // FR32 Register Class...
00013   const unsigned FR32[] = {
00014     X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
00015   };
00016 
00017   // FR64 Register Class...
00018   const unsigned FR64[] = {
00019     X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
00020   };
00021 
00022   // R16 Register Class...
00023   const unsigned R16[] = {
00024     X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
00025   };
00026 
00027   // R32 Register Class...
00028   const unsigned R32[] = {
00029     X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
00030   };
00031 
00032   // R8 Register Class...
00033   const unsigned R8[] = {
00034     X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 
00035   };
00036 
00037   // RFP Register Class...
00038   const unsigned RFP[] = {
00039     X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
00040   };
00041 
00042   // RST Register Class...
00043   const unsigned RST[] = {
00044     X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
00045   };
00046 
00047   // VR128 Register Class...
00048   const unsigned VR128[] = {
00049     X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 
00050   };
00051 
00052   // VR64 Register Class...
00053   const unsigned VR64[] = {
00054     X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 
00055   };
00056 
00057   // FR32VTs Register Class Value Types...
00058   const MVT::ValueType FR32VTs[] = {
00059     MVT::f32, MVT::Other
00060   };
00061 
00062   // FR64VTs Register Class Value Types...
00063   const MVT::ValueType FR64VTs[] = {
00064     MVT::f64, MVT::Other
00065   };
00066 
00067   // R16VTs Register Class Value Types...
00068   const MVT::ValueType R16VTs[] = {
00069     MVT::i16, MVT::Other
00070   };
00071 
00072   // R32VTs Register Class Value Types...
00073   const MVT::ValueType R32VTs[] = {
00074     MVT::i32, MVT::Other
00075   };
00076 
00077   // R8VTs Register Class Value Types...
00078   const MVT::ValueType R8VTs[] = {
00079     MVT::i8, MVT::Other
00080   };
00081 
00082   // RFPVTs Register Class Value Types...
00083   const MVT::ValueType RFPVTs[] = {
00084     MVT::f64, MVT::Other
00085   };
00086 
00087   // RSTVTs Register Class Value Types...
00088   const MVT::ValueType RSTVTs[] = {
00089     MVT::f64, MVT::Other
00090   };
00091 
00092   // VR128VTs Register Class Value Types...
00093   const MVT::ValueType VR128VTs[] = {
00094     MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
00095   };
00096 
00097   // VR64VTs Register Class Value Types...
00098   const MVT::ValueType VR64VTs[] = {
00099     MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other
00100   };
00101 
00102 }  // end anonymous namespace
00103 
00104 namespace X86 {   // Register class instances
00105   FR32Class FR32RegClass;
00106   FR64Class FR64RegClass;
00107   R16Class  R16RegClass;
00108   R32Class  R32RegClass;
00109   R8Class R8RegClass;
00110   RFPClass  RFPRegClass;
00111   RSTClass  RSTRegClass;
00112   VR128Class  VR128RegClass;
00113   VR64Class VR64RegClass;
00114 
00115 FR32Class::FR32Class()  : TargetRegisterClass(FR32VTs, 4, 4, FR32, FR32 + 8) {}
00116 
00117 FR64Class::FR64Class()  : TargetRegisterClass(FR64VTs, 8, 8, FR64, FR64 + 8) {}
00118 
00119     R16Class::iterator
00120     R16Class::allocation_order_end(MachineFunction &MF) const {
00121       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
00122         return end()-2;  // If so, don't allocate SP or BP
00123       else
00124         return end()-1;  // If not, just don't allocate SP
00125     }
00126   
00127 R16Class::R16Class()  : TargetRegisterClass(R16VTs, 2, 2, R16, R16 + 8) {}
00128 
00129     R32Class::iterator
00130     R32Class::allocation_order_end(MachineFunction &MF) const {
00131       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
00132         return end()-2;  // If so, don't allocate ESP or EBP
00133       else
00134         return end()-1;  // If not, just don't allocate ESP
00135     }
00136   
00137 R32Class::R32Class()  : TargetRegisterClass(R32VTs, 4, 4, R32, R32 + 8) {}
00138 
00139 R8Class::R8Class()  : TargetRegisterClass(R8VTs, 1, 1, R8, R8 + 8) {}
00140 
00141 RFPClass::RFPClass()  : TargetRegisterClass(RFPVTs, 8, 4, RFP, RFP + 7) {}
00142 
00143     RSTClass::iterator
00144     RSTClass::allocation_order_end(MachineFunction &MF) const {
00145       return begin();
00146     }
00147   
00148 RSTClass::RSTClass()  : TargetRegisterClass(RSTVTs, 8, 4, RST, RST + 8) {}
00149 
00150 VR128Class::VR128Class()  : TargetRegisterClass(VR128VTs, 16, 16, VR128, VR128 + 8) {}
00151 
00152 VR64Class::VR64Class()  : TargetRegisterClass(VR64VTs, 8, 8, VR64, VR64 + 8) {}
00153 }
00154 
00155 namespace {
00156   const TargetRegisterClass* const RegisterClasses[] = {
00157     &X86::FR32RegClass,
00158     &X86::FR64RegClass,
00159     &X86::R16RegClass,
00160     &X86::R32RegClass,
00161     &X86::R8RegClass,
00162     &X86::RFPRegClass,
00163     &X86::RSTRegClass,
00164     &X86::VR128RegClass,
00165     &X86::VR64RegClass,
00166   };
00167 
00168 
00169   // Register Alias Sets...
00170   const unsigned Empty_AliasSet[] = { 0 };
00171   const unsigned EAX_AliasSet[] = { X86::AX, X86::AL, X86::AH, 0 };
00172   const unsigned ECX_AliasSet[] = { X86::CX, X86::CL, X86::CH, 0 };
00173   const unsigned EDX_AliasSet[] = { X86::DX, X86::DL, X86::DH, 0 };
00174   const unsigned EBX_AliasSet[] = { X86::BX, X86::BL, X86::BH, 0 };
00175   const unsigned ESP_AliasSet[] = { X86::SP, 0 };
00176   const unsigned EBP_AliasSet[] = { X86::BP, 0 };
00177   const unsigned ESI_AliasSet[] = { X86::SI, 0 };
00178   const unsigned EDI_AliasSet[] = { X86::DI, 0 };
00179   const unsigned AX_AliasSet[] = { X86::EAX, X86::AL, X86::AH, 0 };
00180   const unsigned CX_AliasSet[] = { X86::ECX, X86::CL, X86::CH, 0 };
00181   const unsigned DX_AliasSet[] = { X86::EDX, X86::DL, X86::DH, 0 };
00182   const unsigned BX_AliasSet[] = { X86::EBX, X86::BL, X86::BH, 0 };
00183   const unsigned SP_AliasSet[] = { X86::ESP, 0 };
00184   const unsigned BP_AliasSet[] = { X86::EBP, 0 };
00185   const unsigned SI_AliasSet[] = { X86::ESI, 0 };
00186   const unsigned DI_AliasSet[] = { X86::EDI, 0 };
00187   const unsigned AL_AliasSet[] = { X86::EAX, X86::AX, 0 };
00188   const unsigned CL_AliasSet[] = { X86::ECX, X86::CX, 0 };
00189   const unsigned DL_AliasSet[] = { X86::EDX, X86::DX, 0 };
00190   const unsigned BL_AliasSet[] = { X86::EBX, X86::BX, 0 };
00191   const unsigned AH_AliasSet[] = { X86::EAX, X86::AX, 0 };
00192   const unsigned CH_AliasSet[] = { X86::ECX, X86::CX, 0 };
00193   const unsigned DH_AliasSet[] = { X86::EDX, X86::DX, 0 };
00194   const unsigned BH_AliasSet[] = { X86::EBX, X86::BX, 0 };
00195 
00196   const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors
00197     { "NOREG",  0 },
00198     { "AH", AH_AliasSet },
00199     { "AL", AL_AliasSet },
00200     { "AX", AX_AliasSet },
00201     { "BH", BH_AliasSet },
00202     { "BL", BL_AliasSet },
00203     { "BP", BP_AliasSet },
00204     { "BX", BX_AliasSet },
00205     { "CH", CH_AliasSet },
00206     { "CL", CL_AliasSet },
00207     { "CX", CX_AliasSet },
00208     { "DH", DH_AliasSet },
00209     { "DI", DI_AliasSet },
00210     { "DL", DL_AliasSet },
00211     { "DX", DX_AliasSet },
00212     { "EAX",  EAX_AliasSet },
00213     { "EBP",  EBP_AliasSet },
00214     { "EBX",  EBX_AliasSet },
00215     { "ECX",  ECX_AliasSet },
00216     { "EDI",  EDI_AliasSet },
00217     { "EDX",  EDX_AliasSet },
00218     { "ESI",  ESI_AliasSet },
00219     { "ESP",  ESP_AliasSet },
00220     { "FP0",  Empty_AliasSet },
00221     { "FP1",  Empty_AliasSet },
00222     { "FP2",  Empty_AliasSet },
00223     { "FP3",  Empty_AliasSet },
00224     { "FP4",  Empty_AliasSet },
00225     { "FP5",  Empty_AliasSet },
00226     { "FP6",  Empty_AliasSet },
00227     { "MM0",  Empty_AliasSet },
00228     { "MM1",  Empty_AliasSet },
00229     { "MM2",  Empty_AliasSet },
00230     { "MM3",  Empty_AliasSet },
00231     { "MM4",  Empty_AliasSet },
00232     { "MM5",  Empty_AliasSet },
00233     { "MM6",  Empty_AliasSet },
00234     { "MM7",  Empty_AliasSet },
00235     { "SI", SI_AliasSet },
00236     { "SP", SP_AliasSet },
00237     { "ST(0)",  Empty_AliasSet },
00238     { "ST(1)",  Empty_AliasSet },
00239     { "ST(2)",  Empty_AliasSet },
00240     { "ST(3)",  Empty_AliasSet },
00241     { "ST(4)",  Empty_AliasSet },
00242     { "ST(5)",  Empty_AliasSet },
00243     { "ST(6)",  Empty_AliasSet },
00244     { "ST(7)",  Empty_AliasSet },
00245     { "XMM0", Empty_AliasSet },
00246     { "XMM1", Empty_AliasSet },
00247     { "XMM2", Empty_AliasSet },
00248     { "XMM3", Empty_AliasSet },
00249     { "XMM4", Empty_AliasSet },
00250     { "XMM5", Empty_AliasSet },
00251     { "XMM6", Empty_AliasSet },
00252     { "XMM7", Empty_AliasSet },
00253   };
00254 }
00255 
00256 X86GenRegisterInfo::X86GenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
00257   : MRegisterInfo(RegisterDescriptors, 56, RegisterClasses, RegisterClasses+9,
00258                   CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
00259 
00260 const unsigned* X86GenRegisterInfo::getCalleeSaveRegs() const {
00261   static const unsigned CalleeSaveRegs[] = {
00262     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
00263   };
00264   return CalleeSaveRegs;
00265 }
00266 
00267 const TargetRegisterClass* const*
00268 X86GenRegisterInfo::getCalleeSaveRegClasses() const {
00269   static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
00270     &X86::R32RegClass, &X86::R32RegClass, &X86::R32RegClass, &X86::R32RegClass,  0
00271   };
00272   return CalleeSaveRegClasses;
00273 }
00274 
00275 int X86GenRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
00276   static const int DwarfRegNums[] = { -1, // NoRegister
00277     2, 0, 0, 3, 0, 6, 3, 2, 2, 2, 1, 5, 1, 1, 0, 6, 
00278     3, 2, 5, 1, 4, 7, -1, -1, -1, -1, -1, -1, -1, 29, 30, 31, 
00279     32, 33, 34, 35, 36, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 
00280     22, 23, 24, 25, 26, 27, 28
00281   };
00282   assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&
00283          "RegNum exceeds number of registers");
00284   return DwarfRegNums[RegNum];
00285 }
00286 
00287 } // End llvm namespace