LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Machine Code Emitter 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 unsigned AlphaCodeEmitter::getBinaryCodeForInstr(MachineInstr &MI) { 00010 unsigned Value = 0; 00011 DEBUG(std::cerr << MI); 00012 switch (MI.getOpcode()) { 00013 case Alpha::ADDL: { 00014 DEBUG(std::cerr << "Emitting ADDL\n"); 00015 Value = 1073741824U; 00016 00017 // op0: Rc 00018 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00019 op0 &= (1<<5) - 1; 00020 Value |= op0; 00021 // op1: Ra 00022 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00023 op1 &= (1<<5) - 1; 00024 op1 <<= 21; 00025 Value |= op1; 00026 // op2: Rb 00027 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00028 op2 &= (1<<5) - 1; 00029 op2 <<= 16; 00030 Value |= op2; 00031 break; 00032 } 00033 case Alpha::ADDLi: { 00034 DEBUG(std::cerr << "Emitting ADDLi\n"); 00035 Value = 1073745920U; 00036 00037 // op0: Rc 00038 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00039 op0 &= (1<<5) - 1; 00040 Value |= op0; 00041 // op1: Ra 00042 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00043 op1 &= (1<<5) - 1; 00044 op1 <<= 21; 00045 Value |= op1; 00046 // op2: LIT 00047 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00048 op2 &= (1<<8) - 1; 00049 op2 <<= 13; 00050 Value |= op2; 00051 break; 00052 } 00053 case Alpha::ADDQ: { 00054 DEBUG(std::cerr << "Emitting ADDQ\n"); 00055 Value = 1073742848U; 00056 00057 // op0: Rc 00058 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00059 op0 &= (1<<5) - 1; 00060 Value |= op0; 00061 // op1: Ra 00062 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00063 op1 &= (1<<5) - 1; 00064 op1 <<= 21; 00065 Value |= op1; 00066 // op2: Rb 00067 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00068 op2 &= (1<<5) - 1; 00069 op2 <<= 16; 00070 Value |= op2; 00071 break; 00072 } 00073 case Alpha::ADDQi: { 00074 DEBUG(std::cerr << "Emitting ADDQi\n"); 00075 Value = 1073746944U; 00076 00077 // op0: Rc 00078 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00079 op0 &= (1<<5) - 1; 00080 Value |= op0; 00081 // op1: Ra 00082 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00083 op1 &= (1<<5) - 1; 00084 op1 <<= 21; 00085 Value |= op1; 00086 // op2: LIT 00087 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00088 op2 &= (1<<8) - 1; 00089 op2 <<= 13; 00090 Value |= op2; 00091 break; 00092 } 00093 case Alpha::ADDS: { 00094 DEBUG(std::cerr << "Emitting ADDS\n"); 00095 Value = 1476440064U; 00096 00097 // op0: Fc 00098 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00099 op0 &= (1<<5) - 1; 00100 Value |= op0; 00101 // op1: Fa 00102 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00103 op1 &= (1<<5) - 1; 00104 op1 <<= 21; 00105 Value |= op1; 00106 // op2: Fb 00107 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00108 op2 &= (1<<5) - 1; 00109 op2 <<= 16; 00110 Value |= op2; 00111 break; 00112 } 00113 case Alpha::ADDT: { 00114 DEBUG(std::cerr << "Emitting ADDT\n"); 00115 Value = 1476441088U; 00116 00117 // op0: Fc 00118 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00119 op0 &= (1<<5) - 1; 00120 Value |= op0; 00121 // op1: Fa 00122 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00123 op1 &= (1<<5) - 1; 00124 op1 <<= 21; 00125 Value |= op1; 00126 // op2: Fb 00127 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00128 op2 &= (1<<5) - 1; 00129 op2 <<= 16; 00130 Value |= op2; 00131 break; 00132 } 00133 case Alpha::ADJUSTSTACKDOWN: { 00134 DEBUG(std::cerr << "Emitting ADJUSTSTACKDOWN\n"); 00135 Value = 0U; 00136 00137 break; 00138 } 00139 case Alpha::ADJUSTSTACKUP: { 00140 DEBUG(std::cerr << "Emitting ADJUSTSTACKUP\n"); 00141 Value = 0U; 00142 00143 break; 00144 } 00145 case Alpha::ALTENT: { 00146 DEBUG(std::cerr << "Emitting ALTENT\n"); 00147 Value = 0U; 00148 00149 break; 00150 } 00151 case Alpha::AND: { 00152 DEBUG(std::cerr << "Emitting AND\n"); 00153 Value = 1140850688U; 00154 00155 // op0: Rc 00156 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00157 op0 &= (1<<5) - 1; 00158 Value |= op0; 00159 // op1: Ra 00160 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00161 op1 &= (1<<5) - 1; 00162 op1 <<= 21; 00163 Value |= op1; 00164 // op2: Rb 00165 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00166 op2 &= (1<<5) - 1; 00167 op2 <<= 16; 00168 Value |= op2; 00169 break; 00170 } 00171 case Alpha::ANDi: { 00172 DEBUG(std::cerr << "Emitting ANDi\n"); 00173 Value = 1140854784U; 00174 00175 // op0: Rc 00176 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00177 op0 &= (1<<5) - 1; 00178 Value |= op0; 00179 // op1: Ra 00180 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00181 op1 &= (1<<5) - 1; 00182 op1 <<= 21; 00183 Value |= op1; 00184 // op2: LIT 00185 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00186 op2 &= (1<<8) - 1; 00187 op2 <<= 13; 00188 Value |= op2; 00189 break; 00190 } 00191 case Alpha::BEQ: { 00192 DEBUG(std::cerr << "Emitting BEQ\n"); 00193 Value = 3825205248U; 00194 00195 // op0: Ra 00196 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00197 op0 &= (1<<5) - 1; 00198 op0 <<= 21; 00199 Value |= op0; 00200 // op1: disp 00201 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00202 op1 &= (1<<21) - 1; 00203 Value |= op1; 00204 break; 00205 } 00206 case Alpha::BGE: { 00207 DEBUG(std::cerr << "Emitting BGE\n"); 00208 Value = 4160749568U; 00209 00210 // op0: Ra 00211 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00212 op0 &= (1<<5) - 1; 00213 op0 <<= 21; 00214 Value |= op0; 00215 // op1: disp 00216 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00217 op1 &= (1<<21) - 1; 00218 Value |= op1; 00219 break; 00220 } 00221 case Alpha::BGT: { 00222 DEBUG(std::cerr << "Emitting BGT\n"); 00223 Value = 4227858432U; 00224 00225 // op0: Ra 00226 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00227 op0 &= (1<<5) - 1; 00228 op0 <<= 21; 00229 Value |= op0; 00230 // op1: disp 00231 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00232 op1 &= (1<<21) - 1; 00233 Value |= op1; 00234 break; 00235 } 00236 case Alpha::BIC: { 00237 DEBUG(std::cerr << "Emitting BIC\n"); 00238 Value = 1140850944U; 00239 00240 // op0: Rc 00241 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00242 op0 &= (1<<5) - 1; 00243 Value |= op0; 00244 // op1: Ra 00245 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00246 op1 &= (1<<5) - 1; 00247 op1 <<= 21; 00248 Value |= op1; 00249 // op2: Rb 00250 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00251 op2 &= (1<<5) - 1; 00252 op2 <<= 16; 00253 Value |= op2; 00254 break; 00255 } 00256 case Alpha::BICi: { 00257 DEBUG(std::cerr << "Emitting BICi\n"); 00258 Value = 1140855040U; 00259 00260 // op0: Rc 00261 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00262 op0 &= (1<<5) - 1; 00263 Value |= op0; 00264 // op1: Ra 00265 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00266 op1 &= (1<<5) - 1; 00267 op1 <<= 21; 00268 Value |= op1; 00269 // op2: LIT 00270 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00271 op2 &= (1<<8) - 1; 00272 op2 <<= 13; 00273 Value |= op2; 00274 break; 00275 } 00276 case Alpha::BIS: { 00277 DEBUG(std::cerr << "Emitting BIS\n"); 00278 Value = 1140851712U; 00279 00280 // op0: Rc 00281 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00282 op0 &= (1<<5) - 1; 00283 Value |= op0; 00284 // op1: Ra 00285 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00286 op1 &= (1<<5) - 1; 00287 op1 <<= 21; 00288 Value |= op1; 00289 // op2: Rb 00290 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00291 op2 &= (1<<5) - 1; 00292 op2 <<= 16; 00293 Value |= op2; 00294 break; 00295 } 00296 case Alpha::BISi: { 00297 DEBUG(std::cerr << "Emitting BISi\n"); 00298 Value = 1140855808U; 00299 00300 // op0: Rc 00301 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00302 op0 &= (1<<5) - 1; 00303 Value |= op0; 00304 // op1: Ra 00305 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00306 op1 &= (1<<5) - 1; 00307 op1 <<= 21; 00308 Value |= op1; 00309 // op2: LIT 00310 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00311 op2 &= (1<<8) - 1; 00312 op2 <<= 13; 00313 Value |= op2; 00314 break; 00315 } 00316 case Alpha::BLBC: { 00317 DEBUG(std::cerr << "Emitting BLBC\n"); 00318 Value = 3758096384U; 00319 00320 // op0: Ra 00321 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00322 op0 &= (1<<5) - 1; 00323 op0 <<= 21; 00324 Value |= op0; 00325 // op1: disp 00326 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00327 op1 &= (1<<21) - 1; 00328 Value |= op1; 00329 break; 00330 } 00331 case Alpha::BLBS: { 00332 DEBUG(std::cerr << "Emitting BLBS\n"); 00333 Value = 4026531840U; 00334 00335 // op0: Ra 00336 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00337 op0 &= (1<<5) - 1; 00338 op0 <<= 21; 00339 Value |= op0; 00340 // op1: disp 00341 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00342 op1 &= (1<<21) - 1; 00343 Value |= op1; 00344 break; 00345 } 00346 case Alpha::BLE: { 00347 DEBUG(std::cerr << "Emitting BLE\n"); 00348 Value = 3959422976U; 00349 00350 // op0: Ra 00351 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00352 op0 &= (1<<5) - 1; 00353 op0 <<= 21; 00354 Value |= op0; 00355 // op1: disp 00356 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00357 op1 &= (1<<21) - 1; 00358 Value |= op1; 00359 break; 00360 } 00361 case Alpha::BLT: { 00362 DEBUG(std::cerr << "Emitting BLT\n"); 00363 Value = 3892314112U; 00364 00365 // op0: Ra 00366 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00367 op0 &= (1<<5) - 1; 00368 op0 <<= 21; 00369 Value |= op0; 00370 // op1: disp 00371 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00372 op1 &= (1<<21) - 1; 00373 Value |= op1; 00374 break; 00375 } 00376 case Alpha::BNE: { 00377 DEBUG(std::cerr << "Emitting BNE\n"); 00378 Value = 4093640704U; 00379 00380 // op0: Ra 00381 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00382 op0 &= (1<<5) - 1; 00383 op0 <<= 21; 00384 Value |= op0; 00385 // op1: disp 00386 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00387 op1 &= (1<<21) - 1; 00388 Value |= op1; 00389 break; 00390 } 00391 case Alpha::BR: { 00392 DEBUG(std::cerr << "Emitting BR\n"); 00393 Value = 3286237184U; 00394 00395 // op0: disp 00396 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00397 op0 &= (1<<21) - 1; 00398 Value |= op0; 00399 break; 00400 } 00401 case Alpha::BSR: { 00402 DEBUG(std::cerr << "Emitting BSR\n"); 00403 Value = 3544186880U; 00404 00405 // op0: disp 00406 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00407 op0 &= (1<<21) - 1; 00408 Value |= op0; 00409 break; 00410 } 00411 case Alpha::CMOVEQ: { 00412 DEBUG(std::cerr << "Emitting CMOVEQ\n"); 00413 Value = 1140851840U; 00414 00415 // op0: Rc 00416 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00417 op0 &= (1<<5) - 1; 00418 Value |= op0; 00419 // op1: Rb 00420 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00421 op1 &= (1<<5) - 1; 00422 op1 <<= 16; 00423 Value |= op1; 00424 // op2: Ra 00425 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00426 op2 &= (1<<5) - 1; 00427 op2 <<= 21; 00428 Value |= op2; 00429 break; 00430 } 00431 case Alpha::CMOVEQi: { 00432 DEBUG(std::cerr << "Emitting CMOVEQi\n"); 00433 Value = 1140855936U; 00434 00435 // op0: Rc 00436 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00437 op0 &= (1<<5) - 1; 00438 Value |= op0; 00439 // op1: LIT 00440 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00441 op1 &= (1<<8) - 1; 00442 op1 <<= 13; 00443 Value |= op1; 00444 // op2: Ra 00445 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00446 op2 &= (1<<5) - 1; 00447 op2 <<= 21; 00448 Value |= op2; 00449 break; 00450 } 00451 case Alpha::CMOVGE: { 00452 DEBUG(std::cerr << "Emitting CMOVGE\n"); 00453 Value = 1140852928U; 00454 00455 // op0: Rc 00456 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00457 op0 &= (1<<5) - 1; 00458 Value |= op0; 00459 // op1: Rb 00460 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00461 op1 &= (1<<5) - 1; 00462 op1 <<= 16; 00463 Value |= op1; 00464 // op2: Ra 00465 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00466 op2 &= (1<<5) - 1; 00467 op2 <<= 21; 00468 Value |= op2; 00469 break; 00470 } 00471 case Alpha::CMOVGEi: { 00472 DEBUG(std::cerr << "Emitting CMOVGEi\n"); 00473 Value = 1140857024U; 00474 00475 // op0: Rc 00476 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00477 op0 &= (1<<5) - 1; 00478 Value |= op0; 00479 // op1: LIT 00480 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00481 op1 &= (1<<8) - 1; 00482 op1 <<= 13; 00483 Value |= op1; 00484 // op2: Ra 00485 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00486 op2 &= (1<<5) - 1; 00487 op2 <<= 21; 00488 Value |= op2; 00489 break; 00490 } 00491 case Alpha::CMOVGT: { 00492 DEBUG(std::cerr << "Emitting CMOVGT\n"); 00493 Value = 1140853952U; 00494 00495 // op0: Rc 00496 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00497 op0 &= (1<<5) - 1; 00498 Value |= op0; 00499 // op1: Rb 00500 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00501 op1 &= (1<<5) - 1; 00502 op1 <<= 16; 00503 Value |= op1; 00504 // op2: Ra 00505 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00506 op2 &= (1<<5) - 1; 00507 op2 <<= 21; 00508 Value |= op2; 00509 break; 00510 } 00511 case Alpha::CMOVGTi: { 00512 DEBUG(std::cerr << "Emitting CMOVGTi\n"); 00513 Value = 1140858048U; 00514 00515 // op0: Rc 00516 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00517 op0 &= (1<<5) - 1; 00518 Value |= op0; 00519 // op1: LIT 00520 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00521 op1 &= (1<<8) - 1; 00522 op1 <<= 13; 00523 Value |= op1; 00524 // op2: Ra 00525 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00526 op2 &= (1<<5) - 1; 00527 op2 <<= 21; 00528 Value |= op2; 00529 break; 00530 } 00531 case Alpha::CMOVLBC: { 00532 DEBUG(std::cerr << "Emitting CMOVLBC\n"); 00533 Value = 1140851392U; 00534 00535 // op0: Rc 00536 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00537 op0 &= (1<<5) - 1; 00538 Value |= op0; 00539 // op1: Rb 00540 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00541 op1 &= (1<<5) - 1; 00542 op1 <<= 16; 00543 Value |= op1; 00544 // op2: Ra 00545 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00546 op2 &= (1<<5) - 1; 00547 op2 <<= 21; 00548 Value |= op2; 00549 break; 00550 } 00551 case Alpha::CMOVLBCi: { 00552 DEBUG(std::cerr << "Emitting CMOVLBCi\n"); 00553 Value = 1140855488U; 00554 00555 // op0: Rc 00556 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00557 op0 &= (1<<5) - 1; 00558 Value |= op0; 00559 // op1: LIT 00560 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00561 op1 &= (1<<8) - 1; 00562 op1 <<= 13; 00563 Value |= op1; 00564 // op2: Ra 00565 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00566 op2 &= (1<<5) - 1; 00567 op2 <<= 21; 00568 Value |= op2; 00569 break; 00570 } 00571 case Alpha::CMOVLBS: { 00572 DEBUG(std::cerr << "Emitting CMOVLBS\n"); 00573 Value = 1140851328U; 00574 00575 // op0: Rc 00576 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00577 op0 &= (1<<5) - 1; 00578 Value |= op0; 00579 // op1: Rb 00580 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00581 op1 &= (1<<5) - 1; 00582 op1 <<= 16; 00583 Value |= op1; 00584 // op2: Ra 00585 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00586 op2 &= (1<<5) - 1; 00587 op2 <<= 21; 00588 Value |= op2; 00589 break; 00590 } 00591 case Alpha::CMOVLBSi: { 00592 DEBUG(std::cerr << "Emitting CMOVLBSi\n"); 00593 Value = 1140855424U; 00594 00595 // op0: Rc 00596 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00597 op0 &= (1<<5) - 1; 00598 Value |= op0; 00599 // op1: LIT 00600 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00601 op1 &= (1<<8) - 1; 00602 op1 <<= 13; 00603 Value |= op1; 00604 // op2: Ra 00605 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00606 op2 &= (1<<5) - 1; 00607 op2 <<= 21; 00608 Value |= op2; 00609 break; 00610 } 00611 case Alpha::CMOVLE: { 00612 DEBUG(std::cerr << "Emitting CMOVLE\n"); 00613 Value = 1140853888U; 00614 00615 // op0: Rc 00616 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00617 op0 &= (1<<5) - 1; 00618 Value |= op0; 00619 // op1: Rb 00620 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00621 op1 &= (1<<5) - 1; 00622 op1 <<= 16; 00623 Value |= op1; 00624 // op2: Ra 00625 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00626 op2 &= (1<<5) - 1; 00627 op2 <<= 21; 00628 Value |= op2; 00629 break; 00630 } 00631 case Alpha::CMOVLEi: { 00632 DEBUG(std::cerr << "Emitting CMOVLEi\n"); 00633 Value = 1140857984U; 00634 00635 // op0: Rc 00636 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00637 op0 &= (1<<5) - 1; 00638 Value |= op0; 00639 // op1: LIT 00640 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00641 op1 &= (1<<8) - 1; 00642 op1 <<= 13; 00643 Value |= op1; 00644 // op2: Ra 00645 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00646 op2 &= (1<<5) - 1; 00647 op2 <<= 21; 00648 Value |= op2; 00649 break; 00650 } 00651 case Alpha::CMOVLT: { 00652 DEBUG(std::cerr << "Emitting CMOVLT\n"); 00653 Value = 1140852864U; 00654 00655 // op0: Rc 00656 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00657 op0 &= (1<<5) - 1; 00658 Value |= op0; 00659 // op1: Rb 00660 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00661 op1 &= (1<<5) - 1; 00662 op1 <<= 16; 00663 Value |= op1; 00664 // op2: Ra 00665 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00666 op2 &= (1<<5) - 1; 00667 op2 <<= 21; 00668 Value |= op2; 00669 break; 00670 } 00671 case Alpha::CMOVLTi: { 00672 DEBUG(std::cerr << "Emitting CMOVLTi\n"); 00673 Value = 1140856960U; 00674 00675 // op0: Rc 00676 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00677 op0 &= (1<<5) - 1; 00678 Value |= op0; 00679 // op1: LIT 00680 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00681 op1 &= (1<<8) - 1; 00682 op1 <<= 13; 00683 Value |= op1; 00684 // op2: Ra 00685 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00686 op2 &= (1<<5) - 1; 00687 op2 <<= 21; 00688 Value |= op2; 00689 break; 00690 } 00691 case Alpha::CMOVNE: { 00692 DEBUG(std::cerr << "Emitting CMOVNE\n"); 00693 Value = 1140851904U; 00694 00695 // op0: Rc 00696 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00697 op0 &= (1<<5) - 1; 00698 Value |= op0; 00699 // op1: Rb 00700 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00701 op1 &= (1<<5) - 1; 00702 op1 <<= 16; 00703 Value |= op1; 00704 // op2: Ra 00705 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00706 op2 &= (1<<5) - 1; 00707 op2 <<= 21; 00708 Value |= op2; 00709 break; 00710 } 00711 case Alpha::CMOVNEi: { 00712 DEBUG(std::cerr << "Emitting CMOVNEi\n"); 00713 Value = 1140856000U; 00714 00715 // op0: Rc 00716 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00717 op0 &= (1<<5) - 1; 00718 Value |= op0; 00719 // op1: LIT 00720 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00721 op1 &= (1<<8) - 1; 00722 op1 <<= 13; 00723 Value |= op1; 00724 // op2: Ra 00725 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00726 op2 &= (1<<5) - 1; 00727 op2 <<= 21; 00728 Value |= op2; 00729 break; 00730 } 00731 case Alpha::CMPBGE: { 00732 DEBUG(std::cerr << "Emitting CMPBGE\n"); 00733 Value = 1073742304U; 00734 00735 // op0: Rc 00736 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00737 op0 &= (1<<5) - 1; 00738 Value |= op0; 00739 // op1: Ra 00740 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00741 op1 &= (1<<5) - 1; 00742 op1 <<= 21; 00743 Value |= op1; 00744 // op2: Rb 00745 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00746 op2 &= (1<<5) - 1; 00747 op2 <<= 16; 00748 Value |= op2; 00749 break; 00750 } 00751 case Alpha::CMPBGEi: { 00752 DEBUG(std::cerr << "Emitting CMPBGEi\n"); 00753 Value = 1073746400U; 00754 00755 // op0: Rc 00756 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00757 op0 &= (1<<5) - 1; 00758 Value |= op0; 00759 // op1: Ra 00760 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00761 op1 &= (1<<5) - 1; 00762 op1 <<= 21; 00763 Value |= op1; 00764 // op2: LIT 00765 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00766 op2 &= (1<<8) - 1; 00767 op2 <<= 13; 00768 Value |= op2; 00769 break; 00770 } 00771 case Alpha::CMPEQ: { 00772 DEBUG(std::cerr << "Emitting CMPEQ\n"); 00773 Value = 1073743264U; 00774 00775 // op0: Rc 00776 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00777 op0 &= (1<<5) - 1; 00778 Value |= op0; 00779 // op1: Ra 00780 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00781 op1 &= (1<<5) - 1; 00782 op1 <<= 21; 00783 Value |= op1; 00784 // op2: Rb 00785 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00786 op2 &= (1<<5) - 1; 00787 op2 <<= 16; 00788 Value |= op2; 00789 break; 00790 } 00791 case Alpha::CMPEQi: { 00792 DEBUG(std::cerr << "Emitting CMPEQi\n"); 00793 Value = 1073747360U; 00794 00795 // op0: Rc 00796 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00797 op0 &= (1<<5) - 1; 00798 Value |= op0; 00799 // op1: Ra 00800 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00801 op1 &= (1<<5) - 1; 00802 op1 <<= 21; 00803 Value |= op1; 00804 // op2: LIT 00805 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00806 op2 &= (1<<8) - 1; 00807 op2 <<= 13; 00808 Value |= op2; 00809 break; 00810 } 00811 case Alpha::CMPLE: { 00812 DEBUG(std::cerr << "Emitting CMPLE\n"); 00813 Value = 1073745312U; 00814 00815 // op0: Rc 00816 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00817 op0 &= (1<<5) - 1; 00818 Value |= op0; 00819 // op1: Ra 00820 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00821 op1 &= (1<<5) - 1; 00822 op1 <<= 21; 00823 Value |= op1; 00824 // op2: Rb 00825 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00826 op2 &= (1<<5) - 1; 00827 op2 <<= 16; 00828 Value |= op2; 00829 break; 00830 } 00831 case Alpha::CMPLEi: { 00832 DEBUG(std::cerr << "Emitting CMPLEi\n"); 00833 Value = 1073749408U; 00834 00835 // op0: Rc 00836 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00837 op0 &= (1<<5) - 1; 00838 Value |= op0; 00839 // op1: Ra 00840 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00841 op1 &= (1<<5) - 1; 00842 op1 <<= 21; 00843 Value |= op1; 00844 // op2: LIT 00845 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00846 op2 &= (1<<8) - 1; 00847 op2 <<= 13; 00848 Value |= op2; 00849 break; 00850 } 00851 case Alpha::CMPLT: { 00852 DEBUG(std::cerr << "Emitting CMPLT\n"); 00853 Value = 1073744288U; 00854 00855 // op0: Rc 00856 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00857 op0 &= (1<<5) - 1; 00858 Value |= op0; 00859 // op1: Ra 00860 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00861 op1 &= (1<<5) - 1; 00862 op1 <<= 21; 00863 Value |= op1; 00864 // op2: Rb 00865 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00866 op2 &= (1<<5) - 1; 00867 op2 <<= 16; 00868 Value |= op2; 00869 break; 00870 } 00871 case Alpha::CMPLTi: { 00872 DEBUG(std::cerr << "Emitting CMPLTi\n"); 00873 Value = 1073748384U; 00874 00875 // op0: Rc 00876 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00877 op0 &= (1<<5) - 1; 00878 Value |= op0; 00879 // op1: Ra 00880 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00881 op1 &= (1<<5) - 1; 00882 op1 <<= 21; 00883 Value |= op1; 00884 // op2: LIT 00885 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00886 op2 &= (1<<8) - 1; 00887 op2 <<= 13; 00888 Value |= op2; 00889 break; 00890 } 00891 case Alpha::CMPTEQ: { 00892 DEBUG(std::cerr << "Emitting CMPTEQ\n"); 00893 Value = 1476441248U; 00894 00895 // op0: Fc 00896 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00897 op0 &= (1<<5) - 1; 00898 Value |= op0; 00899 // op1: Fa 00900 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00901 op1 &= (1<<5) - 1; 00902 op1 <<= 21; 00903 Value |= op1; 00904 // op2: Fb 00905 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00906 op2 &= (1<<5) - 1; 00907 op2 <<= 16; 00908 Value |= op2; 00909 break; 00910 } 00911 case Alpha::CMPTLE: { 00912 DEBUG(std::cerr << "Emitting CMPTLE\n"); 00913 Value = 1476441312U; 00914 00915 // op0: Fc 00916 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00917 op0 &= (1<<5) - 1; 00918 Value |= op0; 00919 // op1: Fa 00920 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00921 op1 &= (1<<5) - 1; 00922 op1 <<= 21; 00923 Value |= op1; 00924 // op2: Fb 00925 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00926 op2 &= (1<<5) - 1; 00927 op2 <<= 16; 00928 Value |= op2; 00929 break; 00930 } 00931 case Alpha::CMPTLT: { 00932 DEBUG(std::cerr << "Emitting CMPTLT\n"); 00933 Value = 1476441280U; 00934 00935 // op0: Fc 00936 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00937 op0 &= (1<<5) - 1; 00938 Value |= op0; 00939 // op1: Fa 00940 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00941 op1 &= (1<<5) - 1; 00942 op1 <<= 21; 00943 Value |= op1; 00944 // op2: Fb 00945 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00946 op2 &= (1<<5) - 1; 00947 op2 <<= 16; 00948 Value |= op2; 00949 break; 00950 } 00951 case Alpha::CMPTUN: { 00952 DEBUG(std::cerr << "Emitting CMPTUN\n"); 00953 Value = 1476441216U; 00954 00955 // op0: Fc 00956 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00957 op0 &= (1<<5) - 1; 00958 Value |= op0; 00959 // op1: Fa 00960 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00961 op1 &= (1<<5) - 1; 00962 op1 <<= 21; 00963 Value |= op1; 00964 // op2: Fb 00965 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00966 op2 &= (1<<5) - 1; 00967 op2 <<= 16; 00968 Value |= op2; 00969 break; 00970 } 00971 case Alpha::CMPULE: { 00972 DEBUG(std::cerr << "Emitting CMPULE\n"); 00973 Value = 1073743776U; 00974 00975 // op0: Rc 00976 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00977 op0 &= (1<<5) - 1; 00978 Value |= op0; 00979 // op1: Ra 00980 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 00981 op1 &= (1<<5) - 1; 00982 op1 <<= 21; 00983 Value |= op1; 00984 // op2: Rb 00985 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 00986 op2 &= (1<<5) - 1; 00987 op2 <<= 16; 00988 Value |= op2; 00989 break; 00990 } 00991 case Alpha::CMPULEi: { 00992 DEBUG(std::cerr << "Emitting CMPULEi\n"); 00993 Value = 1073747872U; 00994 00995 // op0: Rc 00996 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 00997 op0 &= (1<<5) - 1; 00998 Value |= op0; 00999 // op1: Ra 01000 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01001 op1 &= (1<<5) - 1; 01002 op1 <<= 21; 01003 Value |= op1; 01004 // op2: LIT 01005 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01006 op2 &= (1<<8) - 1; 01007 op2 <<= 13; 01008 Value |= op2; 01009 break; 01010 } 01011 case Alpha::CMPULT: { 01012 DEBUG(std::cerr << "Emitting CMPULT\n"); 01013 Value = 1073742752U; 01014 01015 // op0: Rc 01016 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01017 op0 &= (1<<5) - 1; 01018 Value |= op0; 01019 // op1: Ra 01020 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01021 op1 &= (1<<5) - 1; 01022 op1 <<= 21; 01023 Value |= op1; 01024 // op2: Rb 01025 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01026 op2 &= (1<<5) - 1; 01027 op2 <<= 16; 01028 Value |= op2; 01029 break; 01030 } 01031 case Alpha::CMPULTi: { 01032 DEBUG(std::cerr << "Emitting CMPULTi\n"); 01033 Value = 1073746848U; 01034 01035 // op0: Rc 01036 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01037 op0 &= (1<<5) - 1; 01038 Value |= op0; 01039 // op1: Ra 01040 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01041 op1 &= (1<<5) - 1; 01042 op1 <<= 21; 01043 Value |= op1; 01044 // op2: LIT 01045 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01046 op2 &= (1<<8) - 1; 01047 op2 <<= 13; 01048 Value |= op2; 01049 break; 01050 } 01051 case Alpha::CPYSES: { 01052 DEBUG(std::cerr << "Emitting CPYSES\n"); 01053 Value = 1543504960U; 01054 01055 // op0: Fc 01056 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01057 op0 &= (1<<5) - 1; 01058 Value |= op0; 01059 // op1: Fa 01060 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01061 op1 &= (1<<5) - 1; 01062 op1 <<= 21; 01063 Value |= op1; 01064 // op2: Fb 01065 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01066 op2 &= (1<<5) - 1; 01067 op2 <<= 16; 01068 Value |= op2; 01069 break; 01070 } 01071 case Alpha::CPYSESt: { 01072 DEBUG(std::cerr << "Emitting CPYSESt\n"); 01073 Value = 1543504960U; 01074 01075 // op0: Fc 01076 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01077 op0 &= (1<<5) - 1; 01078 Value |= op0; 01079 // op1: Fa 01080 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01081 op1 &= (1<<5) - 1; 01082 op1 <<= 21; 01083 Value |= op1; 01084 // op2: Fb 01085 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01086 op2 &= (1<<5) - 1; 01087 op2 <<= 16; 01088 Value |= op2; 01089 break; 01090 } 01091 case Alpha::CPYSET: { 01092 DEBUG(std::cerr << "Emitting CPYSET\n"); 01093 Value = 1543504960U; 01094 01095 // op0: Fc 01096 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01097 op0 &= (1<<5) - 1; 01098 Value |= op0; 01099 // op1: Fa 01100 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01101 op1 &= (1<<5) - 1; 01102 op1 <<= 21; 01103 Value |= op1; 01104 // op2: Fb 01105 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01106 op2 &= (1<<5) - 1; 01107 op2 <<= 16; 01108 Value |= op2; 01109 break; 01110 } 01111 case Alpha::CPYSNS: { 01112 DEBUG(std::cerr << "Emitting CPYSNS\n"); 01113 Value = 1543504928U; 01114 01115 // op0: Fc 01116 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01117 op0 &= (1<<5) - 1; 01118 Value |= op0; 01119 // op1: Fa 01120 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01121 op1 &= (1<<5) - 1; 01122 op1 <<= 21; 01123 Value |= op1; 01124 // op2: Fb 01125 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01126 op2 &= (1<<5) - 1; 01127 op2 <<= 16; 01128 Value |= op2; 01129 break; 01130 } 01131 case Alpha::CPYSNSt: { 01132 DEBUG(std::cerr << "Emitting CPYSNSt\n"); 01133 Value = 1543504928U; 01134 01135 // op0: Fc 01136 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01137 op0 &= (1<<5) - 1; 01138 Value |= op0; 01139 // op1: Fa 01140 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01141 op1 &= (1<<5) - 1; 01142 op1 <<= 21; 01143 Value |= op1; 01144 // op2: Fb 01145 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01146 op2 &= (1<<5) - 1; 01147 op2 <<= 16; 01148 Value |= op2; 01149 break; 01150 } 01151 case Alpha::CPYSNT: { 01152 DEBUG(std::cerr << "Emitting CPYSNT\n"); 01153 Value = 1543504928U; 01154 01155 // op0: Fc 01156 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01157 op0 &= (1<<5) - 1; 01158 Value |= op0; 01159 // op1: Fa 01160 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01161 op1 &= (1<<5) - 1; 01162 op1 <<= 21; 01163 Value |= op1; 01164 // op2: Fb 01165 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01166 op2 &= (1<<5) - 1; 01167 op2 <<= 16; 01168 Value |= op2; 01169 break; 01170 } 01171 case Alpha::CPYSNTs: { 01172 DEBUG(std::cerr << "Emitting CPYSNTs\n"); 01173 Value = 1543504928U; 01174 01175 // op0: Fc 01176 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01177 op0 &= (1<<5) - 1; 01178 Value |= op0; 01179 // op1: Fa 01180 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01181 op1 &= (1<<5) - 1; 01182 op1 <<= 21; 01183 Value |= op1; 01184 // op2: Fb 01185 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01186 op2 &= (1<<5) - 1; 01187 op2 <<= 16; 01188 Value |= op2; 01189 break; 01190 } 01191 case Alpha::CPYSS: { 01192 DEBUG(std::cerr << "Emitting CPYSS\n"); 01193 Value = 1543504896U; 01194 01195 // op0: Fc 01196 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01197 op0 &= (1<<5) - 1; 01198 Value |= op0; 01199 // op1: Fa 01200 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01201 op1 &= (1<<5) - 1; 01202 op1 <<= 21; 01203 Value |= op1; 01204 // op2: Fb 01205 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01206 op2 &= (1<<5) - 1; 01207 op2 <<= 16; 01208 Value |= op2; 01209 break; 01210 } 01211 case Alpha::CPYSSt: { 01212 DEBUG(std::cerr << "Emitting CPYSSt\n"); 01213 Value = 1543504896U; 01214 01215 // op0: Fc 01216 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01217 op0 &= (1<<5) - 1; 01218 Value |= op0; 01219 // op1: Fa 01220 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01221 op1 &= (1<<5) - 1; 01222 op1 <<= 21; 01223 Value |= op1; 01224 // op2: Fb 01225 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01226 op2 &= (1<<5) - 1; 01227 op2 <<= 16; 01228 Value |= op2; 01229 break; 01230 } 01231 case Alpha::CPYST: { 01232 DEBUG(std::cerr << "Emitting CPYST\n"); 01233 Value = 1543504896U; 01234 01235 // op0: Fc 01236 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01237 op0 &= (1<<5) - 1; 01238 Value |= op0; 01239 // op1: Fa 01240 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01241 op1 &= (1<<5) - 1; 01242 op1 <<= 21; 01243 Value |= op1; 01244 // op2: Fb 01245 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01246 op2 &= (1<<5) - 1; 01247 op2 <<= 16; 01248 Value |= op2; 01249 break; 01250 } 01251 case Alpha::CPYSTs: { 01252 DEBUG(std::cerr << "Emitting CPYSTs\n"); 01253 Value = 1543504896U; 01254 01255 // op0: Fc 01256 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01257 op0 &= (1<<5) - 1; 01258 Value |= op0; 01259 // op1: Fa 01260 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01261 op1 &= (1<<5) - 1; 01262 op1 <<= 21; 01263 Value |= op1; 01264 // op2: Fb 01265 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01266 op2 &= (1<<5) - 1; 01267 op2 <<= 16; 01268 Value |= op2; 01269 break; 01270 } 01271 case Alpha::CTLZ: { 01272 DEBUG(std::cerr << "Emitting CTLZ\n"); 01273 Value = 1944061504U; 01274 01275 // op0: Rc 01276 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01277 op0 &= (1<<5) - 1; 01278 Value |= op0; 01279 // op1: Rb 01280 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01281 op1 &= (1<<5) - 1; 01282 op1 <<= 16; 01283 Value |= op1; 01284 break; 01285 } 01286 case Alpha::CTPOP: { 01287 DEBUG(std::cerr << "Emitting CTPOP\n"); 01288 Value = 1944061440U; 01289 01290 // op0: Rc 01291 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01292 op0 &= (1<<5) - 1; 01293 Value |= op0; 01294 // op1: Rb 01295 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01296 op1 &= (1<<5) - 1; 01297 op1 <<= 16; 01298 Value |= op1; 01299 break; 01300 } 01301 case Alpha::CTTZ: { 01302 DEBUG(std::cerr << "Emitting CTTZ\n"); 01303 Value = 1944061536U; 01304 01305 // op0: Rc 01306 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01307 op0 &= (1<<5) - 1; 01308 Value |= op0; 01309 // op1: Rb 01310 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01311 op1 &= (1<<5) - 1; 01312 op1 <<= 16; 01313 Value |= op1; 01314 break; 01315 } 01316 case Alpha::CVTQS: { 01317 DEBUG(std::cerr << "Emitting CVTQS\n"); 01318 Value = 1541470080U; 01319 01320 // op0: Fc 01321 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01322 op0 &= (1<<5) - 1; 01323 Value |= op0; 01324 // op1: Fb 01325 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01326 op1 &= (1<<5) - 1; 01327 op1 <<= 16; 01328 Value |= op1; 01329 break; 01330 } 01331 case Alpha::CVTQT: { 01332 DEBUG(std::cerr << "Emitting CVTQT\n"); 01333 Value = 1541470144U; 01334 01335 // op0: Fc 01336 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01337 op0 &= (1<<5) - 1; 01338 Value |= op0; 01339 // op1: Fb 01340 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01341 op1 &= (1<<5) - 1; 01342 op1 <<= 16; 01343 Value |= op1; 01344 break; 01345 } 01346 case Alpha::CVTST: { 01347 DEBUG(std::cerr << "Emitting CVTST\n"); 01348 Value = 1541461376U; 01349 01350 // op0: Fc 01351 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01352 op0 &= (1<<5) - 1; 01353 Value |= op0; 01354 // op1: Fb 01355 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01356 op1 &= (1<<5) - 1; 01357 op1 <<= 16; 01358 Value |= op1; 01359 break; 01360 } 01361 case Alpha::CVTTQ: { 01362 DEBUG(std::cerr << "Emitting CVTTQ\n"); 01363 Value = 1541449184U; 01364 01365 // op0: Fc 01366 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01367 op0 &= (1<<5) - 1; 01368 Value |= op0; 01369 // op1: Fb 01370 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01371 op1 &= (1<<5) - 1; 01372 op1 <<= 16; 01373 Value |= op1; 01374 break; 01375 } 01376 case Alpha::CVTTS: { 01377 DEBUG(std::cerr << "Emitting CVTTS\n"); 01378 Value = 1541469568U; 01379 01380 // op0: Fc 01381 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01382 op0 &= (1<<5) - 1; 01383 Value |= op0; 01384 // op1: Fb 01385 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01386 op1 &= (1<<5) - 1; 01387 op1 <<= 16; 01388 Value |= op1; 01389 break; 01390 } 01391 case Alpha::DIVS: { 01392 DEBUG(std::cerr << "Emitting DIVS\n"); 01393 Value = 1476440160U; 01394 01395 // op0: Fc 01396 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01397 op0 &= (1<<5) - 1; 01398 Value |= op0; 01399 // op1: Fa 01400 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01401 op1 &= (1<<5) - 1; 01402 op1 <<= 21; 01403 Value |= op1; 01404 // op2: Fb 01405 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01406 op2 &= (1<<5) - 1; 01407 op2 <<= 16; 01408 Value |= op2; 01409 break; 01410 } 01411 case Alpha::DIVT: { 01412 DEBUG(std::cerr << "Emitting DIVT\n"); 01413 Value = 1476441184U; 01414 01415 // op0: Fc 01416 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01417 op0 &= (1<<5) - 1; 01418 Value |= op0; 01419 // op1: Fa 01420 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01421 op1 &= (1<<5) - 1; 01422 op1 <<= 21; 01423 Value |= op1; 01424 // op2: Fb 01425 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01426 op2 &= (1<<5) - 1; 01427 op2 <<= 16; 01428 Value |= op2; 01429 break; 01430 } 01431 case Alpha::EQV: { 01432 DEBUG(std::cerr << "Emitting EQV\n"); 01433 Value = 1140852992U; 01434 01435 // op0: Rc 01436 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01437 op0 &= (1<<5) - 1; 01438 Value |= op0; 01439 // op1: Ra 01440 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01441 op1 &= (1<<5) - 1; 01442 op1 <<= 21; 01443 Value |= op1; 01444 // op2: Rb 01445 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01446 op2 &= (1<<5) - 1; 01447 op2 <<= 16; 01448 Value |= op2; 01449 break; 01450 } 01451 case Alpha::EQVi: { 01452 DEBUG(std::cerr << "Emitting EQVi\n"); 01453 Value = 1140857088U; 01454 01455 // op0: Rc 01456 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01457 op0 &= (1<<5) - 1; 01458 Value |= op0; 01459 // op1: Ra 01460 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01461 op1 &= (1<<5) - 1; 01462 op1 <<= 21; 01463 Value |= op1; 01464 // op2: LIT 01465 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01466 op2 &= (1<<8) - 1; 01467 op2 <<= 13; 01468 Value |= op2; 01469 break; 01470 } 01471 case Alpha::EXTBL: { 01472 DEBUG(std::cerr << "Emitting EXTBL\n"); 01473 Value = 1207959744U; 01474 01475 // op0: Rc 01476 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01477 op0 &= (1<<5) - 1; 01478 Value |= op0; 01479 // op1: Ra 01480 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01481 op1 &= (1<<5) - 1; 01482 op1 <<= 21; 01483 Value |= op1; 01484 // op2: Rb 01485 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01486 op2 &= (1<<5) - 1; 01487 op2 <<= 16; 01488 Value |= op2; 01489 break; 01490 } 01491 case Alpha::EXTLL: { 01492 DEBUG(std::cerr << "Emitting EXTLL\n"); 01493 Value = 1207960768U; 01494 01495 // op0: Rc 01496 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01497 op0 &= (1<<5) - 1; 01498 Value |= op0; 01499 // op1: Ra 01500 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01501 op1 &= (1<<5) - 1; 01502 op1 <<= 21; 01503 Value |= op1; 01504 // op2: Rb 01505 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01506 op2 &= (1<<5) - 1; 01507 op2 <<= 16; 01508 Value |= op2; 01509 break; 01510 } 01511 case Alpha::EXTWL: { 01512 DEBUG(std::cerr << "Emitting EXTWL\n"); 01513 Value = 1207960256U; 01514 01515 // op0: Rc 01516 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01517 op0 &= (1<<5) - 1; 01518 Value |= op0; 01519 // op1: Ra 01520 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01521 op1 &= (1<<5) - 1; 01522 op1 <<= 21; 01523 Value |= op1; 01524 // op2: Rb 01525 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01526 op2 &= (1<<5) - 1; 01527 op2 <<= 16; 01528 Value |= op2; 01529 break; 01530 } 01531 case Alpha::FBEQ: { 01532 DEBUG(std::cerr << "Emitting FBEQ\n"); 01533 Value = 3288334336U; 01534 01535 // op0: Ra 01536 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01537 op0 &= (1<<5) - 1; 01538 op0 <<= 21; 01539 Value |= op0; 01540 // op1: disp 01541 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01542 op1 &= (1<<21) - 1; 01543 Value |= op1; 01544 break; 01545 } 01546 case Alpha::FBGE: { 01547 DEBUG(std::cerr << "Emitting FBGE\n"); 01548 Value = 3623878656U; 01549 01550 // op0: Ra 01551 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01552 op0 &= (1<<5) - 1; 01553 op0 <<= 21; 01554 Value |= op0; 01555 // op1: disp 01556 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01557 op1 &= (1<<21) - 1; 01558 Value |= op1; 01559 break; 01560 } 01561 case Alpha::FBGT: { 01562 DEBUG(std::cerr << "Emitting FBGT\n"); 01563 Value = 3690987520U; 01564 01565 // op0: Ra 01566 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01567 op0 &= (1<<5) - 1; 01568 op0 <<= 21; 01569 Value |= op0; 01570 // op1: disp 01571 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01572 op1 &= (1<<21) - 1; 01573 Value |= op1; 01574 break; 01575 } 01576 case Alpha::FBLE: { 01577 DEBUG(std::cerr << "Emitting FBLE\n"); 01578 Value = 3422552064U; 01579 01580 // op0: Ra 01581 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01582 op0 &= (1<<5) - 1; 01583 op0 <<= 21; 01584 Value |= op0; 01585 // op1: disp 01586 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01587 op1 &= (1<<21) - 1; 01588 Value |= op1; 01589 break; 01590 } 01591 case Alpha::FBLT: { 01592 DEBUG(std::cerr << "Emitting FBLT\n"); 01593 Value = 3355443200U; 01594 01595 // op0: Ra 01596 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01597 op0 &= (1<<5) - 1; 01598 op0 <<= 21; 01599 Value |= op0; 01600 // op1: disp 01601 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01602 op1 &= (1<<21) - 1; 01603 Value |= op1; 01604 break; 01605 } 01606 case Alpha::FBNE: { 01607 DEBUG(std::cerr << "Emitting FBNE\n"); 01608 Value = 3556769792U; 01609 01610 // op0: Ra 01611 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01612 op0 &= (1<<5) - 1; 01613 op0 <<= 21; 01614 Value |= op0; 01615 // op1: disp 01616 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01617 op1 &= (1<<21) - 1; 01618 Value |= op1; 01619 break; 01620 } 01621 case Alpha::FCMOVEQS: { 01622 DEBUG(std::cerr << "Emitting FCMOVEQS\n"); 01623 Value = 1543505216U; 01624 01625 // op0: Fc 01626 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01627 op0 &= (1<<5) - 1; 01628 Value |= op0; 01629 // op1: Fa 01630 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01631 op1 &= (1<<5) - 1; 01632 op1 <<= 21; 01633 Value |= op1; 01634 // op2: Fb 01635 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01636 op2 &= (1<<5) - 1; 01637 op2 <<= 16; 01638 Value |= op2; 01639 break; 01640 } 01641 case Alpha::FCMOVEQT: { 01642 DEBUG(std::cerr << "Emitting FCMOVEQT\n"); 01643 Value = 1543505216U; 01644 01645 // op0: Fc 01646 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01647 op0 &= (1<<5) - 1; 01648 Value |= op0; 01649 // op1: Fa 01650 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01651 op1 &= (1<<5) - 1; 01652 op1 <<= 21; 01653 Value |= op1; 01654 // op2: Fb 01655 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01656 op2 &= (1<<5) - 1; 01657 op2 <<= 16; 01658 Value |= op2; 01659 break; 01660 } 01661 case Alpha::FCMOVGES: { 01662 DEBUG(std::cerr << "Emitting FCMOVGES\n"); 01663 Value = 1543505312U; 01664 01665 // op0: Fc 01666 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01667 op0 &= (1<<5) - 1; 01668 Value |= op0; 01669 // op1: Fa 01670 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01671 op1 &= (1<<5) - 1; 01672 op1 <<= 21; 01673 Value |= op1; 01674 // op2: Fb 01675 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01676 op2 &= (1<<5) - 1; 01677 op2 <<= 16; 01678 Value |= op2; 01679 break; 01680 } 01681 case Alpha::FCMOVGET: { 01682 DEBUG(std::cerr << "Emitting FCMOVGET\n"); 01683 Value = 1543505312U; 01684 01685 // op0: Fc 01686 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01687 op0 &= (1<<5) - 1; 01688 Value |= op0; 01689 // op1: Fa 01690 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01691 op1 &= (1<<5) - 1; 01692 op1 <<= 21; 01693 Value |= op1; 01694 // op2: Fb 01695 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01696 op2 &= (1<<5) - 1; 01697 op2 <<= 16; 01698 Value |= op2; 01699 break; 01700 } 01701 case Alpha::FCMOVGTS: { 01702 DEBUG(std::cerr << "Emitting FCMOVGTS\n"); 01703 Value = 1543505376U; 01704 01705 // op0: Fc 01706 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01707 op0 &= (1<<5) - 1; 01708 Value |= op0; 01709 // op1: Fa 01710 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01711 op1 &= (1<<5) - 1; 01712 op1 <<= 21; 01713 Value |= op1; 01714 // op2: Fb 01715 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01716 op2 &= (1<<5) - 1; 01717 op2 <<= 16; 01718 Value |= op2; 01719 break; 01720 } 01721 case Alpha::FCMOVGTT: { 01722 DEBUG(std::cerr << "Emitting FCMOVGTT\n"); 01723 Value = 1543505376U; 01724 01725 // op0: Fc 01726 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01727 op0 &= (1<<5) - 1; 01728 Value |= op0; 01729 // op1: Fa 01730 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01731 op1 &= (1<<5) - 1; 01732 op1 <<= 21; 01733 Value |= op1; 01734 // op2: Fb 01735 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01736 op2 &= (1<<5) - 1; 01737 op2 <<= 16; 01738 Value |= op2; 01739 break; 01740 } 01741 case Alpha::FCMOVLES: { 01742 DEBUG(std::cerr << "Emitting FCMOVLES\n"); 01743 Value = 1543505344U; 01744 01745 // op0: Fc 01746 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01747 op0 &= (1<<5) - 1; 01748 Value |= op0; 01749 // op1: Fa 01750 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01751 op1 &= (1<<5) - 1; 01752 op1 <<= 21; 01753 Value |= op1; 01754 // op2: Fb 01755 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01756 op2 &= (1<<5) - 1; 01757 op2 <<= 16; 01758 Value |= op2; 01759 break; 01760 } 01761 case Alpha::FCMOVLET: { 01762 DEBUG(std::cerr << "Emitting FCMOVLET\n"); 01763 Value = 1543505344U; 01764 01765 // op0: Fc 01766 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01767 op0 &= (1<<5) - 1; 01768 Value |= op0; 01769 // op1: Fa 01770 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01771 op1 &= (1<<5) - 1; 01772 op1 <<= 21; 01773 Value |= op1; 01774 // op2: Fb 01775 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01776 op2 &= (1<<5) - 1; 01777 op2 <<= 16; 01778 Value |= op2; 01779 break; 01780 } 01781 case Alpha::FCMOVLTS: { 01782 DEBUG(std::cerr << "Emitting FCMOVLTS\n"); 01783 Value = 1543505280U; 01784 01785 // op0: Fc 01786 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01787 op0 &= (1<<5) - 1; 01788 Value |= op0; 01789 // op1: Fa 01790 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01791 op1 &= (1<<5) - 1; 01792 op1 <<= 21; 01793 Value |= op1; 01794 // op2: Fb 01795 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01796 op2 &= (1<<5) - 1; 01797 op2 <<= 16; 01798 Value |= op2; 01799 break; 01800 } 01801 case Alpha::FCMOVLTT: { 01802 DEBUG(std::cerr << "Emitting FCMOVLTT\n"); 01803 Value = 1543505280U; 01804 01805 // op0: Fc 01806 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01807 op0 &= (1<<5) - 1; 01808 Value |= op0; 01809 // op1: Fa 01810 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01811 op1 &= (1<<5) - 1; 01812 op1 <<= 21; 01813 Value |= op1; 01814 // op2: Fb 01815 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01816 op2 &= (1<<5) - 1; 01817 op2 <<= 16; 01818 Value |= op2; 01819 break; 01820 } 01821 case Alpha::FCMOVNES: { 01822 DEBUG(std::cerr << "Emitting FCMOVNES\n"); 01823 Value = 1543505248U; 01824 01825 // op0: Fc 01826 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01827 op0 &= (1<<5) - 1; 01828 Value |= op0; 01829 // op1: Fa 01830 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01831 op1 &= (1<<5) - 1; 01832 op1 <<= 21; 01833 Value |= op1; 01834 // op2: Fb 01835 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01836 op2 &= (1<<5) - 1; 01837 op2 <<= 16; 01838 Value |= op2; 01839 break; 01840 } 01841 case Alpha::FCMOVNET: { 01842 DEBUG(std::cerr << "Emitting FCMOVNET\n"); 01843 Value = 1543505248U; 01844 01845 // op0: Fc 01846 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01847 op0 &= (1<<5) - 1; 01848 Value |= op0; 01849 // op1: Fa 01850 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01851 op1 &= (1<<5) - 1; 01852 op1 <<= 21; 01853 Value |= op1; 01854 // op2: Fb 01855 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01856 op2 &= (1<<5) - 1; 01857 op2 <<= 16; 01858 Value |= op2; 01859 break; 01860 } 01861 case Alpha::FTOIS: { 01862 DEBUG(std::cerr << "Emitting FTOIS\n"); 01863 Value = 1881083648U; 01864 01865 // op0: Fc 01866 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01867 op0 &= (1<<5) - 1; 01868 Value |= op0; 01869 // op1: Fa 01870 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01871 op1 &= (1<<5) - 1; 01872 op1 <<= 21; 01873 Value |= op1; 01874 break; 01875 } 01876 case Alpha::FTOIT: { 01877 DEBUG(std::cerr << "Emitting FTOIT\n"); 01878 Value = 1881083392U; 01879 01880 // op0: Fc 01881 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01882 op0 &= (1<<5) - 1; 01883 Value |= op0; 01884 // op1: Fa 01885 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01886 op1 &= (1<<5) - 1; 01887 op1 <<= 21; 01888 Value |= op1; 01889 break; 01890 } 01891 case Alpha::IDEF_F32: { 01892 DEBUG(std::cerr << "Emitting IDEF_F32\n"); 01893 Value = 0U; 01894 01895 break; 01896 } 01897 case Alpha::IDEF_F64: { 01898 DEBUG(std::cerr << "Emitting IDEF_F64\n"); 01899 Value = 0U; 01900 01901 break; 01902 } 01903 case Alpha::IDEF_I: { 01904 DEBUG(std::cerr << "Emitting IDEF_I\n"); 01905 Value = 0U; 01906 01907 break; 01908 } 01909 case Alpha::ITOFS: { 01910 DEBUG(std::cerr << "Emitting ITOFS\n"); 01911 Value = 1344209024U; 01912 01913 // op0: Fc 01914 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01915 op0 &= (1<<5) - 1; 01916 Value |= op0; 01917 // op1: Fa 01918 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01919 op1 &= (1<<5) - 1; 01920 op1 <<= 21; 01921 Value |= op1; 01922 break; 01923 } 01924 case Alpha::ITOFT: { 01925 DEBUG(std::cerr << "Emitting ITOFT\n"); 01926 Value = 1344210048U; 01927 01928 // op0: Fc 01929 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01930 op0 &= (1<<5) - 1; 01931 Value |= op0; 01932 // op1: Fa 01933 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01934 op1 &= (1<<5) - 1; 01935 op1 <<= 21; 01936 Value |= op1; 01937 break; 01938 } 01939 case Alpha::JMP: { 01940 DEBUG(std::cerr << "Emitting JMP\n"); 01941 Value = 1744830464U; 01942 01943 // op0: Ra 01944 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01945 op0 &= (1<<5) - 1; 01946 op0 <<= 21; 01947 Value |= op0; 01948 // op1: Rb 01949 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01950 op1 &= (1<<5) - 1; 01951 op1 <<= 16; 01952 Value |= op1; 01953 // op2: disp 01954 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01955 op2 &= (1<<14) - 1; 01956 Value |= op2; 01957 break; 01958 } 01959 case Alpha::JSR: { 01960 DEBUG(std::cerr << "Emitting JSR\n"); 01961 Value = 1801142272U; 01962 01963 break; 01964 } 01965 case Alpha::JSR_COROUTINE: { 01966 DEBUG(std::cerr << "Emitting JSR_COROUTINE\n"); 01967 Value = 1744879616U; 01968 01969 // op0: Ra 01970 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01971 op0 &= (1<<5) - 1; 01972 op0 <<= 21; 01973 Value |= op0; 01974 // op1: Rb 01975 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 01976 op1 &= (1<<5) - 1; 01977 op1 <<= 16; 01978 Value |= op1; 01979 // op2: disp 01980 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 01981 op2 &= (1<<14) - 1; 01982 Value |= op2; 01983 break; 01984 } 01985 case Alpha::JSRs: { 01986 DEBUG(std::cerr << "Emitting JSRs\n"); 01987 Value = 1794850816U; 01988 01989 break; 01990 } 01991 case Alpha::LDA: { 01992 DEBUG(std::cerr << "Emitting LDA\n"); 01993 Value = 536870912U; 01994 01995 // op0: Ra 01996 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 01997 op0 &= (1<<5) - 1; 01998 op0 <<= 21; 01999 Value |= op0; 02000 // op1: disp 02001 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02002 op1 &= (1<<16) - 1; 02003 Value |= op1; 02004 // op2: Rb 02005 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02006 op2 &= (1<<5) - 1; 02007 op2 <<= 16; 02008 Value |= op2; 02009 break; 02010 } 02011 case Alpha::LDAH: { 02012 DEBUG(std::cerr << "Emitting LDAH\n"); 02013 Value = 603979776U; 02014 02015 // op0: Ra 02016 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02017 op0 &= (1<<5) - 1; 02018 op0 <<= 21; 02019 Value |= op0; 02020 // op1: disp 02021 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02022 op1 &= (1<<16) - 1; 02023 Value |= op1; 02024 // op2: Rb 02025 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02026 op2 &= (1<<5) - 1; 02027 op2 <<= 16; 02028 Value |= op2; 02029 break; 02030 } 02031 case Alpha::LDAHg: { 02032 DEBUG(std::cerr << "Emitting LDAHg\n"); 02033 Value = 603979776U; 02034 02035 // op0: Ra 02036 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02037 op0 &= (1<<5) - 1; 02038 op0 <<= 21; 02039 Value |= op0; 02040 // op1: disp 02041 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02042 op1 &= (1<<16) - 1; 02043 Value |= op1; 02044 // op2: Rb 02045 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02046 op2 &= (1<<5) - 1; 02047 op2 <<= 16; 02048 Value |= op2; 02049 break; 02050 } 02051 case Alpha::LDAHr: { 02052 DEBUG(std::cerr << "Emitting LDAHr\n"); 02053 Value = 603979776U; 02054 02055 // op0: Ra 02056 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02057 op0 &= (1<<5) - 1; 02058 op0 <<= 21; 02059 Value |= op0; 02060 // op1: disp 02061 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02062 op1 &= (1<<16) - 1; 02063 Value |= op1; 02064 // op2: Rb 02065 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02066 op2 &= (1<<5) - 1; 02067 op2 <<= 16; 02068 Value |= op2; 02069 break; 02070 } 02071 case Alpha::LDAg: { 02072 DEBUG(std::cerr << "Emitting LDAg\n"); 02073 Value = 536870912U; 02074 02075 // op0: Ra 02076 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02077 op0 &= (1<<5) - 1; 02078 op0 <<= 21; 02079 Value |= op0; 02080 // op1: disp 02081 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02082 op1 &= (1<<16) - 1; 02083 Value |= op1; 02084 // op2: Rb 02085 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02086 op2 &= (1<<5) - 1; 02087 op2 <<= 16; 02088 Value |= op2; 02089 break; 02090 } 02091 case Alpha::LDAr: { 02092 DEBUG(std::cerr << "Emitting LDAr\n"); 02093 Value = 536870912U; 02094 02095 // op0: Ra 02096 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02097 op0 &= (1<<5) - 1; 02098 op0 <<= 21; 02099 Value |= op0; 02100 // op1: disp 02101 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02102 op1 &= (1<<16) - 1; 02103 Value |= op1; 02104 // op2: Rb 02105 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02106 op2 &= (1<<5) - 1; 02107 op2 <<= 16; 02108 Value |= op2; 02109 break; 02110 } 02111 case Alpha::LDBU: { 02112 DEBUG(std::cerr << "Emitting LDBU\n"); 02113 Value = 671088640U; 02114 02115 // op0: Ra 02116 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02117 op0 &= (1<<5) - 1; 02118 op0 <<= 21; 02119 Value |= op0; 02120 // op1: disp 02121 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02122 op1 &= (1<<16) - 1; 02123 Value |= op1; 02124 // op2: Rb 02125 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02126 op2 &= (1<<5) - 1; 02127 op2 <<= 16; 02128 Value |= op2; 02129 break; 02130 } 02131 case Alpha::LDBUr: { 02132 DEBUG(std::cerr << "Emitting LDBUr\n"); 02133 Value = 671088640U; 02134 02135 // op0: Ra 02136 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02137 op0 &= (1<<5) - 1; 02138 op0 <<= 21; 02139 Value |= op0; 02140 // op1: disp 02141 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02142 op1 &= (1<<16) - 1; 02143 Value |= op1; 02144 // op2: Rb 02145 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02146 op2 &= (1<<5) - 1; 02147 op2 <<= 16; 02148 Value |= op2; 02149 break; 02150 } 02151 case Alpha::LDL: { 02152 DEBUG(std::cerr << "Emitting LDL\n"); 02153 Value = 2684354560U; 02154 02155 // op0: Ra 02156 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02157 op0 &= (1<<5) - 1; 02158 op0 <<= 21; 02159 Value |= op0; 02160 // op1: disp 02161 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02162 op1 &= (1<<16) - 1; 02163 Value |= op1; 02164 // op2: Rb 02165 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02166 op2 &= (1<<5) - 1; 02167 op2 <<= 16; 02168 Value |= op2; 02169 break; 02170 } 02171 case Alpha::LDLr: { 02172 DEBUG(std::cerr << "Emitting LDLr\n"); 02173 Value = 2684354560U; 02174 02175 // op0: Ra 02176 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02177 op0 &= (1<<5) - 1; 02178 op0 <<= 21; 02179 Value |= op0; 02180 // op1: disp 02181 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02182 op1 &= (1<<16) - 1; 02183 Value |= op1; 02184 // op2: Rb 02185 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02186 op2 &= (1<<5) - 1; 02187 op2 <<= 16; 02188 Value |= op2; 02189 break; 02190 } 02191 case Alpha::LDQ: { 02192 DEBUG(std::cerr << "Emitting LDQ\n"); 02193 Value = 2751463424U; 02194 02195 // op0: Ra 02196 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02197 op0 &= (1<<5) - 1; 02198 op0 <<= 21; 02199 Value |= op0; 02200 // op1: disp 02201 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02202 op1 &= (1<<16) - 1; 02203 Value |= op1; 02204 // op2: Rb 02205 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02206 op2 &= (1<<5) - 1; 02207 op2 <<= 16; 02208 Value |= op2; 02209 break; 02210 } 02211 case Alpha::LDQl: { 02212 DEBUG(std::cerr << "Emitting LDQl\n"); 02213 Value = 2751463424U; 02214 02215 // op0: Ra 02216 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02217 op0 &= (1<<5) - 1; 02218 op0 <<= 21; 02219 Value |= op0; 02220 // op1: disp 02221 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02222 op1 &= (1<<16) - 1; 02223 Value |= op1; 02224 // op2: Rb 02225 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02226 op2 &= (1<<5) - 1; 02227 op2 <<= 16; 02228 Value |= op2; 02229 break; 02230 } 02231 case Alpha::LDQr: { 02232 DEBUG(std::cerr << "Emitting LDQr\n"); 02233 Value = 2751463424U; 02234 02235 // op0: Ra 02236 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02237 op0 &= (1<<5) - 1; 02238 op0 <<= 21; 02239 Value |= op0; 02240 // op1: disp 02241 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02242 op1 &= (1<<16) - 1; 02243 Value |= op1; 02244 // op2: Rb 02245 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02246 op2 &= (1<<5) - 1; 02247 op2 <<= 16; 02248 Value |= op2; 02249 break; 02250 } 02251 case Alpha::LDS: { 02252 DEBUG(std::cerr << "Emitting LDS\n"); 02253 Value = 2281701376U; 02254 02255 // op0: Ra 02256 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02257 op0 &= (1<<5) - 1; 02258 op0 <<= 21; 02259 Value |= op0; 02260 // op1: disp 02261 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02262 op1 &= (1<<16) - 1; 02263 Value |= op1; 02264 // op2: Rb 02265 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02266 op2 &= (1<<5) - 1; 02267 op2 <<= 16; 02268 Value |= op2; 02269 break; 02270 } 02271 case Alpha::LDSr: { 02272 DEBUG(std::cerr << "Emitting LDSr\n"); 02273 Value = 2281701376U; 02274 02275 // op0: Ra 02276 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02277 op0 &= (1<<5) - 1; 02278 op0 <<= 21; 02279 Value |= op0; 02280 // op1: disp 02281 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02282 op1 &= (1<<16) - 1; 02283 Value |= op1; 02284 // op2: Rb 02285 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02286 op2 &= (1<<5) - 1; 02287 op2 <<= 16; 02288 Value |= op2; 02289 break; 02290 } 02291 case Alpha::LDT: { 02292 DEBUG(std::cerr << "Emitting LDT\n"); 02293 Value = 2348810240U; 02294 02295 // op0: Ra 02296 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02297 op0 &= (1<<5) - 1; 02298 op0 <<= 21; 02299 Value |= op0; 02300 // op1: disp 02301 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02302 op1 &= (1<<16) - 1; 02303 Value |= op1; 02304 // op2: Rb 02305 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02306 op2 &= (1<<5) - 1; 02307 op2 <<= 16; 02308 Value |= op2; 02309 break; 02310 } 02311 case Alpha::LDTr: { 02312 DEBUG(std::cerr << "Emitting LDTr\n"); 02313 Value = 2348810240U; 02314 02315 // op0: Ra 02316 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02317 op0 &= (1<<5) - 1; 02318 op0 <<= 21; 02319 Value |= op0; 02320 // op1: disp 02321 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02322 op1 &= (1<<16) - 1; 02323 Value |= op1; 02324 // op2: Rb 02325 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02326 op2 &= (1<<5) - 1; 02327 op2 <<= 16; 02328 Value |= op2; 02329 break; 02330 } 02331 case Alpha::LDWU: { 02332 DEBUG(std::cerr << "Emitting LDWU\n"); 02333 Value = 805306368U; 02334 02335 // op0: Ra 02336 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02337 op0 &= (1<<5) - 1; 02338 op0 <<= 21; 02339 Value |= op0; 02340 // op1: disp 02341 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02342 op1 &= (1<<16) - 1; 02343 Value |= op1; 02344 // op2: Rb 02345 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02346 op2 &= (1<<5) - 1; 02347 op2 <<= 16; 02348 Value |= op2; 02349 break; 02350 } 02351 case Alpha::LDWUr: { 02352 DEBUG(std::cerr << "Emitting LDWUr\n"); 02353 Value = 805306368U; 02354 02355 // op0: Ra 02356 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02357 op0 &= (1<<5) - 1; 02358 op0 <<= 21; 02359 Value |= op0; 02360 // op1: disp 02361 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02362 op1 &= (1<<16) - 1; 02363 Value |= op1; 02364 // op2: Rb 02365 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02366 op2 &= (1<<5) - 1; 02367 op2 <<= 16; 02368 Value |= op2; 02369 break; 02370 } 02371 case Alpha::MEMLABEL: { 02372 DEBUG(std::cerr << "Emitting MEMLABEL\n"); 02373 Value = 0U; 02374 02375 break; 02376 } 02377 case Alpha::MULL: { 02378 DEBUG(std::cerr << "Emitting MULL\n"); 02379 Value = 1275068416U; 02380 02381 // op0: Rc 02382 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02383 op0 &= (1<<5) - 1; 02384 Value |= op0; 02385 // op1: Ra 02386 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02387 op1 &= (1<<5) - 1; 02388 op1 <<= 21; 02389 Value |= op1; 02390 // op2: Rb 02391 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02392 op2 &= (1<<5) - 1; 02393 op2 <<= 16; 02394 Value |= op2; 02395 break; 02396 } 02397 case Alpha::MULLi: { 02398 DEBUG(std::cerr << "Emitting MULLi\n"); 02399 Value = 1275072512U; 02400 02401 // op0: Rc 02402 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02403 op0 &= (1<<5) - 1; 02404 Value |= op0; 02405 // op1: Ra 02406 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02407 op1 &= (1<<5) - 1; 02408 op1 <<= 21; 02409 Value |= op1; 02410 // op2: LIT 02411 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02412 op2 &= (1<<8) - 1; 02413 op2 <<= 13; 02414 Value |= op2; 02415 break; 02416 } 02417 case Alpha::MULQ: { 02418 DEBUG(std::cerr << "Emitting MULQ\n"); 02419 Value = 1275069440U; 02420 02421 // op0: Rc 02422 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02423 op0 &= (1<<5) - 1; 02424 Value |= op0; 02425 // op1: Ra 02426 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02427 op1 &= (1<<5) - 1; 02428 op1 <<= 21; 02429 Value |= op1; 02430 // op2: Rb 02431 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02432 op2 &= (1<<5) - 1; 02433 op2 <<= 16; 02434 Value |= op2; 02435 break; 02436 } 02437 case Alpha::MULQi: { 02438 DEBUG(std::cerr << "Emitting MULQi\n"); 02439 Value = 1275073536U; 02440 02441 // op0: Rc 02442 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02443 op0 &= (1<<5) - 1; 02444 Value |= op0; 02445 // op1: Ra 02446 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02447 op1 &= (1<<5) - 1; 02448 op1 <<= 21; 02449 Value |= op1; 02450 // op2: LIT 02451 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02452 op2 &= (1<<8) - 1; 02453 op2 <<= 13; 02454 Value |= op2; 02455 break; 02456 } 02457 case Alpha::MULS: { 02458 DEBUG(std::cerr << "Emitting MULS\n"); 02459 Value = 1476440128U; 02460 02461 // op0: Fc 02462 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02463 op0 &= (1<<5) - 1; 02464 Value |= op0; 02465 // op1: Fa 02466 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02467 op1 &= (1<<5) - 1; 02468 op1 <<= 21; 02469 Value |= op1; 02470 // op2: Fb 02471 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02472 op2 &= (1<<5) - 1; 02473 op2 <<= 16; 02474 Value |= op2; 02475 break; 02476 } 02477 case Alpha::MULT: { 02478 DEBUG(std::cerr << "Emitting MULT\n"); 02479 Value = 1476441152U; 02480 02481 // op0: Fc 02482 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02483 op0 &= (1<<5) - 1; 02484 Value |= op0; 02485 // op1: Fa 02486 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02487 op1 &= (1<<5) - 1; 02488 op1 <<= 21; 02489 Value |= op1; 02490 // op2: Fb 02491 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02492 op2 &= (1<<5) - 1; 02493 op2 <<= 16; 02494 Value |= op2; 02495 break; 02496 } 02497 case Alpha::ORNOT: { 02498 DEBUG(std::cerr << "Emitting ORNOT\n"); 02499 Value = 1140851968U; 02500 02501 // op0: Rc 02502 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02503 op0 &= (1<<5) - 1; 02504 Value |= op0; 02505 // op1: Ra 02506 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02507 op1 &= (1<<5) - 1; 02508 op1 <<= 21; 02509 Value |= op1; 02510 // op2: Rb 02511 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02512 op2 &= (1<<5) - 1; 02513 op2 <<= 16; 02514 Value |= op2; 02515 break; 02516 } 02517 case Alpha::ORNOTi: { 02518 DEBUG(std::cerr << "Emitting ORNOTi\n"); 02519 Value = 1140856064U; 02520 02521 // op0: Rc 02522 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02523 op0 &= (1<<5) - 1; 02524 Value |= op0; 02525 // op1: Ra 02526 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02527 op1 &= (1<<5) - 1; 02528 op1 <<= 21; 02529 Value |= op1; 02530 // op2: LIT 02531 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02532 op2 &= (1<<8) - 1; 02533 op2 <<= 13; 02534 Value |= op2; 02535 break; 02536 } 02537 case Alpha::PCLABEL: { 02538 DEBUG(std::cerr << "Emitting PCLABEL\n"); 02539 Value = 0U; 02540 02541 break; 02542 } 02543 case Alpha::RETDAG: { 02544 DEBUG(std::cerr << "Emitting RETDAG\n"); 02545 Value = 1811578881U; 02546 02547 break; 02548 } 02549 case Alpha::RPCC: { 02550 DEBUG(std::cerr << "Emitting RPCC\n"); 02551 Value = 1610661888U; 02552 02553 // op0: Ra 02554 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02555 op0 &= (1<<5) - 1; 02556 op0 <<= 21; 02557 Value |= op0; 02558 break; 02559 } 02560 case Alpha::S4ADDL: { 02561 DEBUG(std::cerr << "Emitting S4ADDL\n"); 02562 Value = 1073741888U; 02563 02564 // op0: Rc 02565 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02566 op0 &= (1<<5) - 1; 02567 Value |= op0; 02568 // op1: Ra 02569 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02570 op1 &= (1<<5) - 1; 02571 op1 <<= 21; 02572 Value |= op1; 02573 // op2: Rb 02574 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02575 op2 &= (1<<5) - 1; 02576 op2 <<= 16; 02577 Value |= op2; 02578 break; 02579 } 02580 case Alpha::S4ADDLi: { 02581 DEBUG(std::cerr << "Emitting S4ADDLi\n"); 02582 Value = 1073745984U; 02583 02584 // op0: Rc 02585 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02586 op0 &= (1<<5) - 1; 02587 Value |= op0; 02588 // op1: Ra 02589 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02590 op1 &= (1<<5) - 1; 02591 op1 <<= 21; 02592 Value |= op1; 02593 // op2: LIT 02594 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02595 op2 &= (1<<8) - 1; 02596 op2 <<= 13; 02597 Value |= op2; 02598 break; 02599 } 02600 case Alpha::S4ADDQ: { 02601 DEBUG(std::cerr << "Emitting S4ADDQ\n"); 02602 Value = 1073742912U; 02603 02604 // op0: Rc 02605 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02606 op0 &= (1<<5) - 1; 02607 Value |= op0; 02608 // op1: Ra 02609 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02610 op1 &= (1<<5) - 1; 02611 op1 <<= 21; 02612 Value |= op1; 02613 // op2: Rb 02614 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02615 op2 &= (1<<5) - 1; 02616 op2 <<= 16; 02617 Value |= op2; 02618 break; 02619 } 02620 case Alpha::S4ADDQi: { 02621 DEBUG(std::cerr << "Emitting S4ADDQi\n"); 02622 Value = 1073747008U; 02623 02624 // op0: Rc 02625 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02626 op0 &= (1<<5) - 1; 02627 Value |= op0; 02628 // op1: Ra 02629 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02630 op1 &= (1<<5) - 1; 02631 op1 <<= 21; 02632 Value |= op1; 02633 // op2: LIT 02634 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02635 op2 &= (1<<8) - 1; 02636 op2 <<= 13; 02637 Value |= op2; 02638 break; 02639 } 02640 case Alpha::S4SUBL: { 02641 DEBUG(std::cerr << "Emitting S4SUBL\n"); 02642 Value = 1073742176U; 02643 02644 // op0: Rc 02645 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02646 op0 &= (1<<5) - 1; 02647 Value |= op0; 02648 // op1: Ra 02649 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02650 op1 &= (1<<5) - 1; 02651 op1 <<= 21; 02652 Value |= op1; 02653 // op2: Rb 02654 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02655 op2 &= (1<<5) - 1; 02656 op2 <<= 16; 02657 Value |= op2; 02658 break; 02659 } 02660 case Alpha::S4SUBLi: { 02661 DEBUG(std::cerr << "Emitting S4SUBLi\n"); 02662 Value = 1073746272U; 02663 02664 // op0: Rc 02665 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02666 op0 &= (1<<5) - 1; 02667 Value |= op0; 02668 // op1: Ra 02669 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02670 op1 &= (1<<5) - 1; 02671 op1 <<= 21; 02672 Value |= op1; 02673 // op2: LIT 02674 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02675 op2 &= (1<<8) - 1; 02676 op2 <<= 13; 02677 Value |= op2; 02678 break; 02679 } 02680 case Alpha::S4SUBQ: { 02681 DEBUG(std::cerr << "Emitting S4SUBQ\n"); 02682 Value = 1073743200U; 02683 02684 // op0: Rc 02685 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02686 op0 &= (1<<5) - 1; 02687 Value |= op0; 02688 // op1: Ra 02689 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02690 op1 &= (1<<5) - 1; 02691 op1 <<= 21; 02692 Value |= op1; 02693 // op2: Rb 02694 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02695 op2 &= (1<<5) - 1; 02696 op2 <<= 16; 02697 Value |= op2; 02698 break; 02699 } 02700 case Alpha::S4SUBQi: { 02701 DEBUG(std::cerr << "Emitting S4SUBQi\n"); 02702 Value = 1073747296U; 02703 02704 // op0: Rc 02705 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02706 op0 &= (1<<5) - 1; 02707 Value |= op0; 02708 // op1: Ra 02709 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02710 op1 &= (1<<5) - 1; 02711 op1 <<= 21; 02712 Value |= op1; 02713 // op2: LIT 02714 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02715 op2 &= (1<<8) - 1; 02716 op2 <<= 13; 02717 Value |= op2; 02718 break; 02719 } 02720 case Alpha::S8ADDL: { 02721 DEBUG(std::cerr << "Emitting S8ADDL\n"); 02722 Value = 1073742400U; 02723 02724 // op0: Rc 02725 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02726 op0 &= (1<<5) - 1; 02727 Value |= op0; 02728 // op1: Ra 02729 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02730 op1 &= (1<<5) - 1; 02731 op1 <<= 21; 02732 Value |= op1; 02733 // op2: Rb 02734 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02735 op2 &= (1<<5) - 1; 02736 op2 <<= 16; 02737 Value |= op2; 02738 break; 02739 } 02740 case Alpha::S8ADDLi: { 02741 DEBUG(std::cerr << "Emitting S8ADDLi\n"); 02742 Value = 1073746496U; 02743 02744 // op0: Rc 02745 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02746 op0 &= (1<<5) - 1; 02747 Value |= op0; 02748 // op1: Ra 02749 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02750 op1 &= (1<<5) - 1; 02751 op1 <<= 21; 02752 Value |= op1; 02753 // op2: LIT 02754 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02755 op2 &= (1<<8) - 1; 02756 op2 <<= 13; 02757 Value |= op2; 02758 break; 02759 } 02760 case Alpha::S8ADDQ: { 02761 DEBUG(std::cerr << "Emitting S8ADDQ\n"); 02762 Value = 1073743424U; 02763 02764 // op0: Rc 02765 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02766 op0 &= (1<<5) - 1; 02767 Value |= op0; 02768 // op1: Ra 02769 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02770 op1 &= (1<<5) - 1; 02771 op1 <<= 21; 02772 Value |= op1; 02773 // op2: Rb 02774 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02775 op2 &= (1<<5) - 1; 02776 op2 <<= 16; 02777 Value |= op2; 02778 break; 02779 } 02780 case Alpha::S8ADDQi: { 02781 DEBUG(std::cerr << "Emitting S8ADDQi\n"); 02782 Value = 1073747520U; 02783 02784 // op0: Rc 02785 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02786 op0 &= (1<<5) - 1; 02787 Value |= op0; 02788 // op1: Ra 02789 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02790 op1 &= (1<<5) - 1; 02791 op1 <<= 21; 02792 Value |= op1; 02793 // op2: LIT 02794 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02795 op2 &= (1<<8) - 1; 02796 op2 <<= 13; 02797 Value |= op2; 02798 break; 02799 } 02800 case Alpha::S8SUBL: { 02801 DEBUG(std::cerr << "Emitting S8SUBL\n"); 02802 Value = 1073742688U; 02803 02804 // op0: Rc 02805 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02806 op0 &= (1<<5) - 1; 02807 Value |= op0; 02808 // op1: Ra 02809 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02810 op1 &= (1<<5) - 1; 02811 op1 <<= 21; 02812 Value |= op1; 02813 // op2: Rb 02814 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02815 op2 &= (1<<5) - 1; 02816 op2 <<= 16; 02817 Value |= op2; 02818 break; 02819 } 02820 case Alpha::S8SUBLi: { 02821 DEBUG(std::cerr << "Emitting S8SUBLi\n"); 02822 Value = 1073746784U; 02823 02824 // op0: Rc 02825 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02826 op0 &= (1<<5) - 1; 02827 Value |= op0; 02828 // op1: Ra 02829 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02830 op1 &= (1<<5) - 1; 02831 op1 <<= 21; 02832 Value |= op1; 02833 // op2: LIT 02834 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02835 op2 &= (1<<8) - 1; 02836 op2 <<= 13; 02837 Value |= op2; 02838 break; 02839 } 02840 case Alpha::S8SUBQ: { 02841 DEBUG(std::cerr << "Emitting S8SUBQ\n"); 02842 Value = 1073743712U; 02843 02844 // op0: Rc 02845 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02846 op0 &= (1<<5) - 1; 02847 Value |= op0; 02848 // op1: Ra 02849 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02850 op1 &= (1<<5) - 1; 02851 op1 <<= 21; 02852 Value |= op1; 02853 // op2: Rb 02854 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02855 op2 &= (1<<5) - 1; 02856 op2 <<= 16; 02857 Value |= op2; 02858 break; 02859 } 02860 case Alpha::S8SUBQi: { 02861 DEBUG(std::cerr << "Emitting S8SUBQi\n"); 02862 Value = 1073747808U; 02863 02864 // op0: Rc 02865 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02866 op0 &= (1<<5) - 1; 02867 Value |= op0; 02868 // op1: Ra 02869 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02870 op1 &= (1<<5) - 1; 02871 op1 <<= 21; 02872 Value |= op1; 02873 // op2: LIT 02874 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02875 op2 &= (1<<8) - 1; 02876 op2 <<= 13; 02877 Value |= op2; 02878 break; 02879 } 02880 case Alpha::SEXTB: { 02881 DEBUG(std::cerr << "Emitting SEXTB\n"); 02882 Value = 1944059904U; 02883 02884 // op0: Rc 02885 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02886 op0 &= (1<<5) - 1; 02887 Value |= op0; 02888 // op1: Rb 02889 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02890 op1 &= (1<<5) - 1; 02891 op1 <<= 16; 02892 Value |= op1; 02893 break; 02894 } 02895 case Alpha::SEXTW: { 02896 DEBUG(std::cerr << "Emitting SEXTW\n"); 02897 Value = 1944059936U; 02898 02899 // op0: Rc 02900 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02901 op0 &= (1<<5) - 1; 02902 Value |= op0; 02903 // op1: Rb 02904 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02905 op1 &= (1<<5) - 1; 02906 op1 <<= 16; 02907 Value |= op1; 02908 break; 02909 } 02910 case Alpha::SL: { 02911 DEBUG(std::cerr << "Emitting SL\n"); 02912 Value = 1207961376U; 02913 02914 // op0: Rc 02915 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02916 op0 &= (1<<5) - 1; 02917 Value |= op0; 02918 // op1: Ra 02919 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02920 op1 &= (1<<5) - 1; 02921 op1 <<= 21; 02922 Value |= op1; 02923 // op2: Rb 02924 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02925 op2 &= (1<<5) - 1; 02926 op2 <<= 16; 02927 Value |= op2; 02928 break; 02929 } 02930 case Alpha::SLi: { 02931 DEBUG(std::cerr << "Emitting SLi\n"); 02932 Value = 1207965472U; 02933 02934 // op0: Rc 02935 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02936 op0 &= (1<<5) - 1; 02937 Value |= op0; 02938 // op1: Ra 02939 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02940 op1 &= (1<<5) - 1; 02941 op1 <<= 21; 02942 Value |= op1; 02943 // op2: LIT 02944 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02945 op2 &= (1<<8) - 1; 02946 op2 <<= 13; 02947 Value |= op2; 02948 break; 02949 } 02950 case Alpha::SQRTS: { 02951 DEBUG(std::cerr << "Emitting SQRTS\n"); 02952 Value = 1407234400U; 02953 02954 // op0: Fc 02955 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02956 op0 &= (1<<5) - 1; 02957 Value |= op0; 02958 // op1: Fb 02959 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02960 op1 &= (1<<5) - 1; 02961 op1 <<= 16; 02962 Value |= op1; 02963 break; 02964 } 02965 case Alpha::SQRTT: { 02966 DEBUG(std::cerr << "Emitting SQRTT\n"); 02967 Value = 1407235424U; 02968 02969 // op0: Fc 02970 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02971 op0 &= (1<<5) - 1; 02972 Value |= op0; 02973 // op1: Fb 02974 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02975 op1 &= (1<<5) - 1; 02976 op1 <<= 16; 02977 Value |= op1; 02978 break; 02979 } 02980 case Alpha::SRA: { 02981 DEBUG(std::cerr << "Emitting SRA\n"); 02982 Value = 1207961472U; 02983 02984 // op0: Rc 02985 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 02986 op0 &= (1<<5) - 1; 02987 Value |= op0; 02988 // op1: Ra 02989 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 02990 op1 &= (1<<5) - 1; 02991 op1 <<= 21; 02992 Value |= op1; 02993 // op2: Rb 02994 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 02995 op2 &= (1<<5) - 1; 02996 op2 <<= 16; 02997 Value |= op2; 02998 break; 02999 } 03000 case Alpha::SRAi: { 03001 DEBUG(std::cerr << "Emitting SRAi\n"); 03002 Value = 1207965568U; 03003 03004 // op0: Rc 03005 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03006 op0 &= (1<<5) - 1; 03007 Value |= op0; 03008 // op1: Ra 03009 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03010 op1 &= (1<<5) - 1; 03011 op1 <<= 21; 03012 Value |= op1; 03013 // op2: LIT 03014 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03015 op2 &= (1<<8) - 1; 03016 op2 <<= 13; 03017 Value |= op2; 03018 break; 03019 } 03020 case Alpha::SRL: { 03021 DEBUG(std::cerr << "Emitting SRL\n"); 03022 Value = 1207961216U; 03023 03024 // op0: Rc 03025 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03026 op0 &= (1<<5) - 1; 03027 Value |= op0; 03028 // op1: Ra 03029 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03030 op1 &= (1<<5) - 1; 03031 op1 <<= 21; 03032 Value |= op1; 03033 // op2: Rb 03034 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03035 op2 &= (1<<5) - 1; 03036 op2 <<= 16; 03037 Value |= op2; 03038 break; 03039 } 03040 case Alpha::SRLi: { 03041 DEBUG(std::cerr << "Emitting SRLi\n"); 03042 Value = 1207965312U; 03043 03044 // op0: Rc 03045 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03046 op0 &= (1<<5) - 1; 03047 Value |= op0; 03048 // op1: Ra 03049 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03050 op1 &= (1<<5) - 1; 03051 op1 <<= 21; 03052 Value |= op1; 03053 // op2: LIT 03054 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03055 op2 &= (1<<8) - 1; 03056 op2 <<= 13; 03057 Value |= op2; 03058 break; 03059 } 03060 case Alpha::STB: { 03061 DEBUG(std::cerr << "Emitting STB\n"); 03062 Value = 939524096U; 03063 03064 // op0: Ra 03065 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03066 op0 &= (1<<5) - 1; 03067 op0 <<= 21; 03068 Value |= op0; 03069 // op1: disp 03070 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03071 op1 &= (1<<16) - 1; 03072 Value |= op1; 03073 // op2: Rb 03074 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03075 op2 &= (1<<5) - 1; 03076 op2 <<= 16; 03077 Value |= op2; 03078 break; 03079 } 03080 case Alpha::STBr: { 03081 DEBUG(std::cerr << "Emitting STBr\n"); 03082 Value = 939524096U; 03083 03084 // op0: Ra 03085 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03086 op0 &= (1<<5) - 1; 03087 op0 <<= 21; 03088 Value |= op0; 03089 // op1: disp 03090 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03091 op1 &= (1<<16) - 1; 03092 Value |= op1; 03093 // op2: Rb 03094 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03095 op2 &= (1<<5) - 1; 03096 op2 <<= 16; 03097 Value |= op2; 03098 break; 03099 } 03100 case Alpha::STL: { 03101 DEBUG(std::cerr << "Emitting STL\n"); 03102 Value = 2952790016U; 03103 03104 // op0: Ra 03105 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03106 op0 &= (1<<5) - 1; 03107 op0 <<= 21; 03108 Value |= op0; 03109 // op1: disp 03110 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03111 op1 &= (1<<16) - 1; 03112 Value |= op1; 03113 // op2: Rb 03114 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03115 op2 &= (1<<5) - 1; 03116 op2 <<= 16; 03117 Value |= op2; 03118 break; 03119 } 03120 case Alpha::STLr: { 03121 DEBUG(std::cerr << "Emitting STLr\n"); 03122 Value = 2952790016U; 03123 03124 // op0: Ra 03125 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03126 op0 &= (1<<5) - 1; 03127 op0 <<= 21; 03128 Value |= op0; 03129 // op1: disp 03130 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03131 op1 &= (1<<16) - 1; 03132 Value |= op1; 03133 // op2: Rb 03134 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03135 op2 &= (1<<5) - 1; 03136 op2 <<= 16; 03137 Value |= op2; 03138 break; 03139 } 03140 case Alpha::STQ: { 03141 DEBUG(std::cerr << "Emitting STQ\n"); 03142 Value = 3019898880U; 03143 03144 // op0: Ra 03145 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03146 op0 &= (1<<5) - 1; 03147 op0 <<= 21; 03148 Value |= op0; 03149 // op1: disp 03150 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03151 op1 &= (1<<16) - 1; 03152 Value |= op1; 03153 // op2: Rb 03154 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03155 op2 &= (1<<5) - 1; 03156 op2 <<= 16; 03157 Value |= op2; 03158 break; 03159 } 03160 case Alpha::STQr: { 03161 DEBUG(std::cerr << "Emitting STQr\n"); 03162 Value = 3019898880U; 03163 03164 // op0: Ra 03165 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03166 op0 &= (1<<5) - 1; 03167 op0 <<= 21; 03168 Value |= op0; 03169 // op1: disp 03170 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03171 op1 &= (1<<16) - 1; 03172 Value |= op1; 03173 // op2: Rb 03174 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03175 op2 &= (1<<5) - 1; 03176 op2 <<= 16; 03177 Value |= op2; 03178 break; 03179 } 03180 case Alpha::STS: { 03181 DEBUG(std::cerr << "Emitting STS\n"); 03182 Value = 2550136832U; 03183 03184 // op0: Ra 03185 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03186 op0 &= (1<<5) - 1; 03187 op0 <<= 21; 03188 Value |= op0; 03189 // op1: disp 03190 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03191 op1 &= (1<<16) - 1; 03192 Value |= op1; 03193 // op2: Rb 03194 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03195 op2 &= (1<<5) - 1; 03196 op2 <<= 16; 03197 Value |= op2; 03198 break; 03199 } 03200 case Alpha::STSr: { 03201 DEBUG(std::cerr << "Emitting STSr\n"); 03202 Value = 2550136832U; 03203 03204 // op0: Ra 03205 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03206 op0 &= (1<<5) - 1; 03207 op0 <<= 21; 03208 Value |= op0; 03209 // op1: disp 03210 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03211 op1 &= (1<<16) - 1; 03212 Value |= op1; 03213 // op2: Rb 03214 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03215 op2 &= (1<<5) - 1; 03216 op2 <<= 16; 03217 Value |= op2; 03218 break; 03219 } 03220 case Alpha::STT: { 03221 DEBUG(std::cerr << "Emitting STT\n"); 03222 Value = 2617245696U; 03223 03224 // op0: Ra 03225 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03226 op0 &= (1<<5) - 1; 03227 op0 <<= 21; 03228 Value |= op0; 03229 // op1: disp 03230 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03231 op1 &= (1<<16) - 1; 03232 Value |= op1; 03233 // op2: Rb 03234 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03235 op2 &= (1<<5) - 1; 03236 op2 <<= 16; 03237 Value |= op2; 03238 break; 03239 } 03240 case Alpha::STTr: { 03241 DEBUG(std::cerr << "Emitting STTr\n"); 03242 Value = 2617245696U; 03243 03244 // op0: Ra 03245 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03246 op0 &= (1<<5) - 1; 03247 op0 <<= 21; 03248 Value |= op0; 03249 // op1: disp 03250 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03251 op1 &= (1<<16) - 1; 03252 Value |= op1; 03253 // op2: Rb 03254 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03255 op2 &= (1<<5) - 1; 03256 op2 <<= 16; 03257 Value |= op2; 03258 break; 03259 } 03260 case Alpha::STW: { 03261 DEBUG(std::cerr << "Emitting STW\n"); 03262 Value = 872415232U; 03263 03264 // op0: Ra 03265 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03266 op0 &= (1<<5) - 1; 03267 op0 <<= 21; 03268 Value |= op0; 03269 // op1: disp 03270 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03271 op1 &= (1<<16) - 1; 03272 Value |= op1; 03273 // op2: Rb 03274 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03275 op2 &= (1<<5) - 1; 03276 op2 <<= 16; 03277 Value |= op2; 03278 break; 03279 } 03280 case Alpha::STWr: { 03281 DEBUG(std::cerr << "Emitting STWr\n"); 03282 Value = 872415232U; 03283 03284 // op0: Ra 03285 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03286 op0 &= (1<<5) - 1; 03287 op0 <<= 21; 03288 Value |= op0; 03289 // op1: disp 03290 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03291 op1 &= (1<<16) - 1; 03292 Value |= op1; 03293 // op2: Rb 03294 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03295 op2 &= (1<<5) - 1; 03296 op2 <<= 16; 03297 Value |= op2; 03298 break; 03299 } 03300 case Alpha::SUBL: { 03301 DEBUG(std::cerr << "Emitting SUBL\n"); 03302 Value = 1073742112U; 03303 03304 // op0: Rc 03305 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03306 op0 &= (1<<5) - 1; 03307 Value |= op0; 03308 // op1: Ra 03309 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03310 op1 &= (1<<5) - 1; 03311 op1 <<= 21; 03312 Value |= op1; 03313 // op2: Rb 03314 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03315 op2 &= (1<<5) - 1; 03316 op2 <<= 16; 03317 Value |= op2; 03318 break; 03319 } 03320 case Alpha::SUBLi: { 03321 DEBUG(std::cerr << "Emitting SUBLi\n"); 03322 Value = 1073746208U; 03323 03324 // op0: Rc 03325 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03326 op0 &= (1<<5) - 1; 03327 Value |= op0; 03328 // op1: Ra 03329 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03330 op1 &= (1<<5) - 1; 03331 op1 <<= 21; 03332 Value |= op1; 03333 // op2: LIT 03334 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03335 op2 &= (1<<8) - 1; 03336 op2 <<= 13; 03337 Value |= op2; 03338 break; 03339 } 03340 case Alpha::SUBQ: { 03341 DEBUG(std::cerr << "Emitting SUBQ\n"); 03342 Value = 1073743136U; 03343 03344 // op0: Rc 03345 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03346 op0 &= (1<<5) - 1; 03347 Value |= op0; 03348 // op1: Ra 03349 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03350 op1 &= (1<<5) - 1; 03351 op1 <<= 21; 03352 Value |= op1; 03353 // op2: Rb 03354 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03355 op2 &= (1<<5) - 1; 03356 op2 <<= 16; 03357 Value |= op2; 03358 break; 03359 } 03360 case Alpha::SUBQi: { 03361 DEBUG(std::cerr << "Emitting SUBQi\n"); 03362 Value = 1073747232U; 03363 03364 // op0: Rc 03365 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03366 op0 &= (1<<5) - 1; 03367 Value |= op0; 03368 // op1: Ra 03369 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03370 op1 &= (1<<5) - 1; 03371 op1 <<= 21; 03372 Value |= op1; 03373 // op2: LIT 03374 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03375 op2 &= (1<<8) - 1; 03376 op2 <<= 13; 03377 Value |= op2; 03378 break; 03379 } 03380 case Alpha::SUBS: { 03381 DEBUG(std::cerr << "Emitting SUBS\n"); 03382 Value = 1476440096U; 03383 03384 // op0: Fc 03385 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03386 op0 &= (1<<5) - 1; 03387 Value |= op0; 03388 // op1: Fa 03389 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03390 op1 &= (1<<5) - 1; 03391 op1 <<= 21; 03392 Value |= op1; 03393 // op2: Fb 03394 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03395 op2 &= (1<<5) - 1; 03396 op2 <<= 16; 03397 Value |= op2; 03398 break; 03399 } 03400 case Alpha::SUBT: { 03401 DEBUG(std::cerr << "Emitting SUBT\n"); 03402 Value = 1476441120U; 03403 03404 // op0: Fc 03405 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03406 op0 &= (1<<5) - 1; 03407 Value |= op0; 03408 // op1: Fa 03409 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03410 op1 &= (1<<5) - 1; 03411 op1 <<= 21; 03412 Value |= op1; 03413 // op2: Fb 03414 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03415 op2 &= (1<<5) - 1; 03416 op2 <<= 16; 03417 Value |= op2; 03418 break; 03419 } 03420 case Alpha::UMULH: { 03421 DEBUG(std::cerr << "Emitting UMULH\n"); 03422 Value = 1275069952U; 03423 03424 // op0: Rc 03425 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03426 op0 &= (1<<5) - 1; 03427 Value |= op0; 03428 // op1: Ra 03429 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03430 op1 &= (1<<5) - 1; 03431 op1 <<= 21; 03432 Value |= op1; 03433 // op2: Rb 03434 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03435 op2 &= (1<<5) - 1; 03436 op2 <<= 16; 03437 Value |= op2; 03438 break; 03439 } 03440 case Alpha::UMULHi: { 03441 DEBUG(std::cerr << "Emitting UMULHi\n"); 03442 Value = 1275074048U; 03443 03444 // op0: Rc 03445 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03446 op0 &= (1<<5) - 1; 03447 Value |= op0; 03448 // op1: Ra 03449 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03450 op1 &= (1<<5) - 1; 03451 op1 <<= 21; 03452 Value |= op1; 03453 // op2: LIT 03454 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03455 op2 &= (1<<8) - 1; 03456 op2 <<= 13; 03457 Value |= op2; 03458 break; 03459 } 03460 case Alpha::WTF: { 03461 DEBUG(std::cerr << "Emitting WTF\n"); 03462 Value = 0U; 03463 03464 break; 03465 } 03466 case Alpha::XOR: { 03467 DEBUG(std::cerr << "Emitting XOR\n"); 03468 Value = 1140852736U; 03469 03470 // op0: Rc 03471 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03472 op0 &= (1<<5) - 1; 03473 Value |= op0; 03474 // op1: Ra 03475 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03476 op1 &= (1<<5) - 1; 03477 op1 <<= 21; 03478 Value |= op1; 03479 // op2: Rb 03480 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03481 op2 &= (1<<5) - 1; 03482 op2 <<= 16; 03483 Value |= op2; 03484 break; 03485 } 03486 case Alpha::XORi: { 03487 DEBUG(std::cerr << "Emitting XORi\n"); 03488 Value = 1140856832U; 03489 03490 // op0: Rc 03491 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03492 op0 &= (1<<5) - 1; 03493 Value |= op0; 03494 // op1: Ra 03495 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03496 op1 &= (1<<5) - 1; 03497 op1 <<= 21; 03498 Value |= op1; 03499 // op2: LIT 03500 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03501 op2 &= (1<<8) - 1; 03502 op2 <<= 13; 03503 Value |= op2; 03504 break; 03505 } 03506 case Alpha::ZAP: { 03507 DEBUG(std::cerr << "Emitting ZAP\n"); 03508 Value = 1207961088U; 03509 03510 // op0: Rc 03511 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03512 op0 &= (1<<5) - 1; 03513 Value |= op0; 03514 // op1: Ra 03515 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03516 op1 &= (1<<5) - 1; 03517 op1 <<= 21; 03518 Value |= op1; 03519 // op2: Rb 03520 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03521 op2 &= (1<<5) - 1; 03522 op2 <<= 16; 03523 Value |= op2; 03524 break; 03525 } 03526 case Alpha::ZAPNOT: { 03527 DEBUG(std::cerr << "Emitting ZAPNOT\n"); 03528 Value = 1207961120U; 03529 03530 // op0: Rc 03531 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03532 op0 &= (1<<5) - 1; 03533 Value |= op0; 03534 // op1: Ra 03535 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03536 op1 &= (1<<5) - 1; 03537 op1 <<= 21; 03538 Value |= op1; 03539 // op2: Rb 03540 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03541 op2 &= (1<<5) - 1; 03542 op2 <<= 16; 03543 Value |= op2; 03544 break; 03545 } 03546 case Alpha::ZAPNOTi: { 03547 DEBUG(std::cerr << "Emitting ZAPNOTi\n"); 03548 Value = 1207965216U; 03549 03550 // op0: Rc 03551 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03552 op0 &= (1<<5) - 1; 03553 Value |= op0; 03554 // op1: Ra 03555 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03556 op1 &= (1<<5) - 1; 03557 op1 <<= 21; 03558 Value |= op1; 03559 // op2: LIT 03560 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03561 op2 &= (1<<8) - 1; 03562 op2 <<= 13; 03563 Value |= op2; 03564 break; 03565 } 03566 case Alpha::ZAPi: { 03567 DEBUG(std::cerr << "Emitting ZAPi\n"); 03568 Value = 1207965184U; 03569 03570 // op0: Rc 03571 int op0 = getMachineOpValue(MI, MI.getOperand(0)); 03572 op0 &= (1<<5) - 1; 03573 Value |= op0; 03574 // op1: Ra 03575 int op1 = getMachineOpValue(MI, MI.getOperand(1)); 03576 op1 &= (1<<5) - 1; 03577 op1 <<= 21; 03578 Value |= op1; 03579 // op2: LIT 03580 int op2 = getMachineOpValue(MI, MI.getOperand(2)); 03581 op2 &= (1<<8) - 1; 03582 op2 <<= 13; 03583 Value |= op2; 03584 break; 03585 } 03586 default: 03587 std::cerr << "Not supported instr: " << MI << "\n"; 03588 abort(); 03589 } 03590 return Value; 03591 } 03592