LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned EmptyImpList[] = { 0 }; 00012 static const unsigned ImplicitList1[] = { Alpha::R29, 0 }; 00013 static const unsigned ImplicitList2[] = { Alpha::R0, Alpha::R1, Alpha::R2, Alpha::R3, Alpha::R4, Alpha::R5, Alpha::R6, Alpha::R7, Alpha::R8, Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21, Alpha::R22, Alpha::R23, Alpha::R24, Alpha::R25, Alpha::R26, Alpha::R27, Alpha::R28, Alpha::R29, Alpha::F0, Alpha::F1, Alpha::F10, Alpha::F11, Alpha::F12, Alpha::F13, Alpha::F14, Alpha::F15, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21, Alpha::F22, Alpha::F23, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, 0 }; 00014 static const unsigned ImplicitList3[] = { Alpha::R27, Alpha::R29, 0 }; 00015 static const unsigned ImplicitList4[] = { Alpha::R24, Alpha::R25, Alpha::R27, 0 }; 00016 static const unsigned ImplicitList5[] = { Alpha::R23, Alpha::R24, Alpha::R25, Alpha::R27, Alpha::R28, 0 }; 00017 static const unsigned ImplicitList6[] = { Alpha::R28, 0 }; 00018 static const unsigned ImplicitList7[] = { Alpha::R26, 0 }; 00019 00020 static const TargetOperandInfo OperandInfo2[] = { { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, }; 00021 static const TargetOperandInfo OperandInfo3[] = { { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, { 0 }, }; 00022 static const TargetOperandInfo OperandInfo4[] = { { &Alpha::F4RCRegClass }, { &Alpha::F4RCRegClass }, { &Alpha::F4RCRegClass }, }; 00023 static const TargetOperandInfo OperandInfo5[] = { { &Alpha::F8RCRegClass }, { &Alpha::F8RCRegClass }, { &Alpha::F8RCRegClass }, }; 00024 static const TargetOperandInfo OperandInfo6[] = { { 0 }, }; 00025 static const TargetOperandInfo OperandInfo7[] = { { &Alpha::GPRCRegClass }, { 0 }, }; 00026 static const TargetOperandInfo OperandInfo8[] = { { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, }; 00027 static const TargetOperandInfo OperandInfo9[] = { { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, { 0 }, { &Alpha::GPRCRegClass }, }; 00028 static const TargetOperandInfo OperandInfo10[] = { { &Alpha::F4RCRegClass }, { &Alpha::F8RCRegClass }, { &Alpha::F4RCRegClass }, }; 00029 static const TargetOperandInfo OperandInfo11[] = { { &Alpha::F8RCRegClass }, { &Alpha::F4RCRegClass }, { &Alpha::F8RCRegClass }, }; 00030 static const TargetOperandInfo OperandInfo12[] = { { &Alpha::GPRCRegClass }, { &Alpha::GPRCRegClass }, }; 00031 static const TargetOperandInfo OperandInfo13[] = { { &Alpha::F4RCRegClass }, { &Alpha::F8RCRegClass }, }; 00032 static const TargetOperandInfo OperandInfo14[] = { { &Alpha::F8RCRegClass }, { &Alpha::F8RCRegClass }, }; 00033 static const TargetOperandInfo OperandInfo15[] = { { &Alpha::F8RCRegClass }, { &Alpha::F4RCRegClass }, }; 00034 static const TargetOperandInfo OperandInfo16[] = { { &Alpha::F8RCRegClass }, { 0 }, }; 00035 static const TargetOperandInfo OperandInfo17[] = { { &Alpha::F4RCRegClass }, { &Alpha::F4RCRegClass }, { &Alpha::F4RCRegClass }, { &Alpha::F8RCRegClass }, }; 00036 static const TargetOperandInfo OperandInfo18[] = { { &Alpha::F8RCRegClass }, { &Alpha::F8RCRegClass }, { &Alpha::F8RCRegClass }, { &Alpha::F8RCRegClass }, }; 00037 static const TargetOperandInfo OperandInfo19[] = { { &Alpha::GPRCRegClass }, { &Alpha::F4RCRegClass }, }; 00038 static const TargetOperandInfo OperandInfo20[] = { { &Alpha::GPRCRegClass }, { &Alpha::F8RCRegClass }, }; 00039 static const TargetOperandInfo OperandInfo21[] = { { &Alpha::F4RCRegClass }, }; 00040 static const TargetOperandInfo OperandInfo22[] = { { &Alpha::F8RCRegClass }, }; 00041 static const TargetOperandInfo OperandInfo23[] = { { &Alpha::GPRCRegClass }, }; 00042 static const TargetOperandInfo OperandInfo24[] = { { &Alpha::F4RCRegClass }, { &Alpha::GPRCRegClass }, }; 00043 static const TargetOperandInfo OperandInfo25[] = { { &Alpha::F8RCRegClass }, { &Alpha::GPRCRegClass }, }; 00044 static const TargetOperandInfo OperandInfo26[] = { { &Alpha::GPRCRegClass }, { 0 }, { &Alpha::GPRCRegClass }, }; 00045 static const TargetOperandInfo OperandInfo27[] = { { &Alpha::GPRCRegClass }, { 0 }, { &Alpha::GPRCRegClass }, { 0 }, }; 00046 static const TargetOperandInfo OperandInfo28[] = { { &Alpha::F4RCRegClass }, { 0 }, { &Alpha::GPRCRegClass }, }; 00047 static const TargetOperandInfo OperandInfo29[] = { { &Alpha::F8RCRegClass }, { 0 }, { &Alpha::GPRCRegClass }, }; 00048 static const TargetOperandInfo OperandInfo30[] = { { 0 }, { 0 }, { 0 }, { 0 }, }; 00049 static const TargetOperandInfo OperandInfo31[] = { { &Alpha::F4RCRegClass }, { &Alpha::F4RCRegClass }, }; 00050 00051 static const TargetInstrDescriptor AlphaInsts[] = { 00052 { "PHI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 }, // Inst #0 = PHI 00053 { "INLINEASM", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 }, // Inst #1 = INLINEASM 00054 { "ADDL", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #2 = ADDL 00055 { "ADDLi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #3 = ADDLi 00056 { "ADDQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #4 = ADDQ 00057 { "ADDQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #5 = ADDQi 00058 { "ADDS", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #6 = ADDS 00059 { "ADDT", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #7 = ADDT 00060 { "ADJUSTSTACKDOWN", 1, -1, 0, false, 0, 0, 25, 0|M_LOAD_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #8 = ADJUSTSTACKDOWN 00061 { "ADJUSTSTACKUP", 1, -1, 0, false, 0, 0, 25, 0|M_LOAD_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #9 = ADJUSTSTACKUP 00062 { "ALTENT", 1, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #10 = ALTENT 00063 { "AND", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #11 = AND 00064 { "ANDi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #12 = ANDi 00065 { "BEQ", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #13 = BEQ 00066 { "BGE", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #14 = BGE 00067 { "BGT", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #15 = BGT 00068 { "BIC", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #16 = BIC 00069 { "BICi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #17 = BICi 00070 { "BIS", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #18 = BIS 00071 { "BISi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #19 = BISi 00072 { "BLBC", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #20 = BLBC 00073 { "BLBS", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #21 = BLBS 00074 { "BLE", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #22 = BLE 00075 { "BLT", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #23 = BLT 00076 { "BNE", 2, -1, 0, false, 0, 0, 14, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #24 = BNE 00077 { "BR", 1, -1, 0, false, 0, 0, 28, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #25 = BR 00078 { "BSR", 1, -1, 0, false, 0, 0, 22, 0|M_BRANCH_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo6 }, // Inst #26 = BSR 00079 { "CMOVEQ", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #27 = CMOVEQ 00080 { "CMOVEQi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #28 = CMOVEQi 00081 { "CMOVGE", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #29 = CMOVGE 00082 { "CMOVGEi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #30 = CMOVGEi 00083 { "CMOVGT", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #31 = CMOVGT 00084 { "CMOVGTi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #32 = CMOVGTi 00085 { "CMOVLBC", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #33 = CMOVLBC 00086 { "CMOVLBCi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #34 = CMOVLBCi 00087 { "CMOVLBS", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #35 = CMOVLBS 00088 { "CMOVLBSi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #36 = CMOVLBSi 00089 { "CMOVLE", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #37 = CMOVLE 00090 { "CMOVLEi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #38 = CMOVLEi 00091 { "CMOVLT", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #39 = CMOVLT 00092 { "CMOVLTi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #40 = CMOVLTi 00093 { "CMOVNE", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #41 = CMOVNE 00094 { "CMOVNEi", 4, -1, 0, false, 0, 0, 1, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #42 = CMOVNEi 00095 { "CMPBGE", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #43 = CMPBGE 00096 { "CMPBGEi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #44 = CMPBGEi 00097 { "CMPEQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #45 = CMPEQ 00098 { "CMPEQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #46 = CMPEQi 00099 { "CMPLE", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #47 = CMPLE 00100 { "CMPLEi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #48 = CMPLEi 00101 { "CMPLT", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #49 = CMPLT 00102 { "CMPLTi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #50 = CMPLTi 00103 { "CMPTEQ", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #51 = CMPTEQ 00104 { "CMPTLE", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #52 = CMPTLE 00105 { "CMPTLT", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #53 = CMPTLT 00106 { "CMPTUN", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #54 = CMPTUN 00107 { "CMPULE", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #55 = CMPULE 00108 { "CMPULEi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #56 = CMPULEi 00109 { "CMPULT", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #57 = CMPULT 00110 { "CMPULTi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #58 = CMPULTi 00111 { "CPYSES", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #59 = CPYSES 00112 { "CPYSESt", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #60 = CPYSESt 00113 { "CPYSET", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #61 = CPYSET 00114 { "CPYSNS", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #62 = CPYSNS 00115 { "CPYSNSt", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #63 = CPYSNSt 00116 { "CPYSNT", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #64 = CPYSNT 00117 { "CPYSNTs", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo11 }, // Inst #65 = CPYSNTs 00118 { "CPYSS", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #66 = CPYSS 00119 { "CPYSSt", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #67 = CPYSSt 00120 { "CPYST", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #68 = CPYST 00121 { "CPYSTs", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo11 }, // Inst #69 = CPYSTs 00122 { "CTLZ", 2, -1, 0, false, 0, 0, 17, 0, 0, EmptyImpList, EmptyImpList, OperandInfo12 }, // Inst #70 = CTLZ 00123 { "CTPOP", 2, -1, 0, false, 0, 0, 17, 0, 0, EmptyImpList, EmptyImpList, OperandInfo12 }, // Inst #71 = CTPOP 00124 { "CTTZ", 2, -1, 0, false, 0, 0, 17, 0, 0, EmptyImpList, EmptyImpList, OperandInfo12 }, // Inst #72 = CTTZ 00125 { "CVTQS", 2, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo13 }, // Inst #73 = CVTQS 00126 { "CVTQT", 2, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo14 }, // Inst #74 = CVTQT 00127 { "CVTST", 2, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo15 }, // Inst #75 = CVTST 00128 { "CVTTQ", 2, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo14 }, // Inst #76 = CVTTQ 00129 { "CVTTS", 2, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo13 }, // Inst #77 = CVTTS 00130 { "DIVS", 3, -1, 0, false, 0, 0, 5, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #78 = DIVS 00131 { "DIVT", 3, -1, 0, false, 0, 0, 6, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #79 = DIVT 00132 { "EQV", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #80 = EQV 00133 { "EQVi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #81 = EQVi 00134 { "EXTBL", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #82 = EXTBL 00135 { "EXTLL", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #83 = EXTLL 00136 { "EXTWL", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #84 = EXTWL 00137 { "FBEQ", 2, -1, 0, false, 0, 0, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #85 = FBEQ 00138 { "FBGE", 2, -1, 0, false, 0, 0, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #86 = FBGE 00139 { "FBGT", 2, -1, 0, false, 0, 0, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #87 = FBGT 00140 { "FBLE", 2, -1, 0, false, 0, 0, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #88 = FBLE 00141 { "FBLT", 2, -1, 0, false, 0, 0, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #89 = FBLT 00142 { "FBNE", 2, -1, 0, false, 0, 0, 3, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #90 = FBNE 00143 { "FCMOVEQS", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #91 = FCMOVEQS 00144 { "FCMOVEQT", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #92 = FCMOVEQT 00145 { "FCMOVGES", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #93 = FCMOVGES 00146 { "FCMOVGET", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #94 = FCMOVGET 00147 { "FCMOVGTS", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #95 = FCMOVGTS 00148 { "FCMOVGTT", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #96 = FCMOVGTT 00149 { "FCMOVLES", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #97 = FCMOVLES 00150 { "FCMOVLET", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #98 = FCMOVLET 00151 { "FCMOVLTS", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #99 = FCMOVLTS 00152 { "FCMOVLTT", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #100 = FCMOVLTT 00153 { "FCMOVNES", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #101 = FCMOVNES 00154 { "FCMOVNET", 4, -1, 0, false, 0, 0, 4, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #102 = FCMOVNET 00155 { "FTOIS", 2, -1, 0, false, 0, 0, 12, 0, 0, EmptyImpList, EmptyImpList, OperandInfo19 }, // Inst #103 = FTOIS 00156 { "FTOIT", 2, -1, 0, false, 0, 0, 12, 0, 0, EmptyImpList, EmptyImpList, OperandInfo20 }, // Inst #104 = FTOIT 00157 { "IDEF_F32", 1, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, OperandInfo21 }, // Inst #105 = IDEF_F32 00158 { "IDEF_F64", 1, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, OperandInfo22 }, // Inst #106 = IDEF_F64 00159 { "IDEF_I", 1, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #107 = IDEF_I 00160 { "ITOFS", 2, -1, 0, false, 0, 0, 21, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 }, // Inst #108 = ITOFS 00161 { "ITOFT", 2, -1, 0, false, 0, 0, 21, 0, 0, EmptyImpList, EmptyImpList, OperandInfo25 }, // Inst #109 = ITOFT 00162 { "JMP", 3, -1, 0, false, 0, 0, 22, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #110 = JMP 00163 { "JSR", 0, -1, 0, false, 0, 0, 22, 0|M_CALL_FLAG, 0, ImplicitList3, ImplicitList2, 0 }, // Inst #111 = JSR 00164 { "JSR_COROUTINE", 3, -1, 0, false, 0, 0, 22, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #112 = JSR_COROUTINE 00165 { "JSRs", 0, -1, 0, false, 0, 0, 22, 0|M_CALL_FLAG, 0, ImplicitList4, ImplicitList5, 0 }, // Inst #113 = JSRs 00166 { "LDA", 3, -1, 0, false, 0, 0, 23, 0, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #114 = LDA 00167 { "LDAH", 3, -1, 0, false, 0, 0, 23, 0, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #115 = LDAH 00168 { "LDAHg", 4, -1, 0, false, 0, 0, 23, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo27 }, // Inst #116 = LDAHg 00169 { "LDAHr", 3, -1, 0, false, 0, 0, 23, 0, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #117 = LDAHr 00170 { "LDAg", 4, -1, 0, false, 0, 0, 23, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo27 }, // Inst #118 = LDAg 00171 { "LDAr", 3, -1, 0, false, 0, 0, 23, 0, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #119 = LDAr 00172 { "LDBU", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #120 = LDBU 00173 { "LDBUr", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #121 = LDBUr 00174 { "LDL", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #122 = LDL 00175 { "LDLr", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #123 = LDLr 00176 { "LDQ", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #124 = LDQ 00177 { "LDQl", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #125 = LDQl 00178 { "LDQr", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #126 = LDQr 00179 { "LDS", 3, -1, 0, false, 0, 0, 7, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo28 }, // Inst #127 = LDS 00180 { "LDSr", 3, -1, 0, false, 0, 0, 7, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo28 }, // Inst #128 = LDSr 00181 { "LDT", 3, -1, 0, false, 0, 0, 7, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo29 }, // Inst #129 = LDT 00182 { "LDTr", 3, -1, 0, false, 0, 0, 7, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo29 }, // Inst #130 = LDTr 00183 { "LDWU", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #131 = LDWU 00184 { "LDWUr", 3, -1, 0, false, 0, 0, 15, 0|M_LOAD_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #132 = LDWUr 00185 { "MEMLABEL", 4, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #133 = MEMLABEL 00186 { "MULL", 3, -1, 0, false, 0, 0, 18, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #134 = MULL 00187 { "MULLi", 3, -1, 0, false, 0, 0, 18, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #135 = MULLi 00188 { "MULQ", 3, -1, 0, false, 0, 0, 18, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #136 = MULQ 00189 { "MULQi", 3, -1, 0, false, 0, 0, 18, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #137 = MULQi 00190 { "MULS", 3, -1, 0, false, 0, 0, 8, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #138 = MULS 00191 { "MULT", 3, -1, 0, false, 0, 0, 8, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #139 = MULT 00192 { "ORNOT", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #140 = ORNOT 00193 { "ORNOTi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #141 = ORNOTi 00194 { "PCLABEL", 1, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #142 = PCLABEL 00195 { "RETDAG", 0, -1, 0, false, 0, 0, 22, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0, ImplicitList7, EmptyImpList, 0 }, // Inst #143 = RETDAG 00196 { "RPCC", 1, -1, 0, false, 0, 0, 26, 0, 0, EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #144 = RPCC 00197 { "S4ADDL", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #145 = S4ADDL 00198 { "S4ADDLi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #146 = S4ADDLi 00199 { "S4ADDQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #147 = S4ADDQ 00200 { "S4ADDQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #148 = S4ADDQi 00201 { "S4SUBL", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #149 = S4SUBL 00202 { "S4SUBLi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #150 = S4SUBLi 00203 { "S4SUBQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #151 = S4SUBQ 00204 { "S4SUBQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #152 = S4SUBQi 00205 { "S8ADDL", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #153 = S8ADDL 00206 { "S8ADDLi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #154 = S8ADDLi 00207 { "S8ADDQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #155 = S8ADDQ 00208 { "S8ADDQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #156 = S8ADDQi 00209 { "S8SUBL", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #157 = S8SUBL 00210 { "S8SUBLi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #158 = S8SUBLi 00211 { "S8SUBQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #159 = S8SUBQ 00212 { "S8SUBQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #160 = S8SUBQi 00213 { "SEXTB", 2, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo12 }, // Inst #161 = SEXTB 00214 { "SEXTW", 2, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo12 }, // Inst #162 = SEXTW 00215 { "SL", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #163 = SL 00216 { "SLi", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #164 = SLi 00217 { "SQRTS", 2, -1, 0, false, 0, 0, 9, 0, 0, EmptyImpList, EmptyImpList, OperandInfo31 }, // Inst #165 = SQRTS 00218 { "SQRTT", 2, -1, 0, false, 0, 0, 10, 0, 0, EmptyImpList, EmptyImpList, OperandInfo14 }, // Inst #166 = SQRTT 00219 { "SRA", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #167 = SRA 00220 { "SRAi", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #168 = SRAi 00221 { "SRL", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #169 = SRL 00222 { "SRLi", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #170 = SRLi 00223 { "STB", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #171 = STB 00224 { "STBr", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #172 = STBr 00225 { "STL", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #173 = STL 00226 { "STLr", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #174 = STLr 00227 { "STQ", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #175 = STQ 00228 { "STQr", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #176 = STQr 00229 { "STS", 3, -1, 0, false, 0, 0, 11, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo28 }, // Inst #177 = STS 00230 { "STSr", 3, -1, 0, false, 0, 0, 11, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo28 }, // Inst #178 = STSr 00231 { "STT", 3, -1, 0, false, 0, 0, 11, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo29 }, // Inst #179 = STT 00232 { "STTr", 3, -1, 0, false, 0, 0, 11, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo29 }, // Inst #180 = STTr 00233 { "STW", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #181 = STW 00234 { "STWr", 3, -1, 0, false, 0, 0, 20, 0|M_STORE_FLAG, 0, EmptyImpList, ImplicitList6, OperandInfo26 }, // Inst #182 = STWr 00235 { "SUBL", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #183 = SUBL 00236 { "SUBLi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #184 = SUBLi 00237 { "SUBQ", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #185 = SUBQ 00238 { "SUBQi", 3, -1, 0, false, 0, 0, 13, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #186 = SUBQi 00239 { "SUBS", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #187 = SUBS 00240 { "SUBT", 3, -1, 0, false, 0, 0, 2, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #188 = SUBT 00241 { "UMULH", 3, -1, 0, false, 0, 0, 18, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #189 = UMULH 00242 { "UMULHi", 3, -1, 0, false, 0, 0, 18, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #190 = UMULHi 00243 { "WTF", -1, -1, 0, false, 0, 0, 25, 0, 0, EmptyImpList, EmptyImpList, 0 }, // Inst #191 = WTF 00244 { "XOR", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #192 = XOR 00245 { "XORi", 3, -1, 0, false, 0, 0, 16, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #193 = XORi 00246 { "ZAP", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #194 = ZAP 00247 { "ZAPNOT", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #195 = ZAPNOT 00248 { "ZAPNOTi", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #196 = ZAPNOTi 00249 { "ZAPi", 3, -1, 0, false, 0, 0, 19, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #197 = ZAPi 00250 }; 00251 } // End llvm namespace