LLVM API Documentation
00001 //===- SparcV9RegisterInfo.h - SparcV9 Register Information Impl -*- C++ -*-==// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the SparcV9 implementation of the MRegisterInfo class. 00011 // It also contains stuff needed to instantiate that class, which would 00012 // ordinarily be provided by TableGen. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #ifndef SPARCV9REGISTERINFO_H 00017 #define SPARCV9REGISTERINFO_H 00018 00019 #include "llvm/Target/MRegisterInfo.h" 00020 00021 namespace llvm { 00022 00023 struct SparcV9RegisterInfo : public MRegisterInfo { 00024 SparcV9RegisterInfo (); 00025 const unsigned *getCalleeSaveRegs() const; 00026 const TargetRegisterClass* const *getCalleeSaveRegClasses() const { 00027 return 0; 00028 } 00029 00030 00031 // The rest of these are stubs... for now. 00032 void storeRegToStackSlot(MachineBasicBlock &MBB, 00033 MachineBasicBlock::iterator MI, 00034 unsigned SrcReg, int FrameIndex, 00035 const TargetRegisterClass *RC) const; 00036 void loadRegFromStackSlot(MachineBasicBlock &MBB, 00037 MachineBasicBlock::iterator MI, 00038 unsigned DestReg, int FrameIndex, 00039 const TargetRegisterClass *RC) const; 00040 void copyRegToReg(MachineBasicBlock &MBB, 00041 MachineBasicBlock::iterator MI, 00042 unsigned DestReg, unsigned SrcReg, 00043 const TargetRegisterClass *RC) const; 00044 void eliminateFrameIndex (MachineBasicBlock::iterator MI) const; 00045 void emitPrologue (MachineFunction &MF) const; 00046 void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const; 00047 00048 // Debug information queries. 00049 int getDwarfRegNum(unsigned RegNum) const; 00050 unsigned getRARegister() const; 00051 unsigned getFrameRegister(MachineFunction &MF) const; 00052 }; 00053 00054 } // End llvm namespace 00055 00056 //===----------------------------------------------------------------------===// 00057 // 00058 // The second section of this file (immediately following) contains 00059 // a *handwritten* SparcV9 unified register number enumeration, which 00060 // provides a flat namespace containing all the SparcV9 unified 00061 // register numbers. 00062 // 00063 // It would ordinarily be contained in the file SparcV9GenRegisterNames.inc 00064 // if we were using TableGen to generate the register file description 00065 // automatically. 00066 // 00067 //===----------------------------------------------------------------------===// 00068 00069 namespace llvm { 00070 namespace SparcV9 { 00071 enum { 00072 // FIXME - Register 0 is not a "non-register" like it is on other targets!! 00073 00074 // SparcV9IntRegClass(IntRegClassID) 00075 // - unified register numbers 0 ... 31 (32 regs) 00076 /* 0 */ o0, o1, o2, o3, o4, 00077 /* 5 */ o5, o7, l0, l1, l2, 00078 /* 10 */ l3, l4, l5, l6, l7, 00079 /* 15 */ i0, i1, i2, i3, i4, 00080 /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero 00081 /* 25 */ g2, g3, g4, g5, g6, 00082 /* 30 */ g7, o6, // o6 is stack ptr 00083 00084 // SparcV9FloatRegClass(FloatRegClassID) 00085 // - regs 32 .. 63 are FPSingleRegType, 64 .. 95 are FPDoubleRegType 00086 // - unified register numbers 32 ... 95 (64 regs) 00087 /* 32 */ f0, f1, f2, 00088 /* 35 */ f3, f4, f5, f6, f7, 00089 /* 40 */ f8, f9, f10, f11, f12, 00090 /* 45 */ f13, f14, f15, f16, f17, 00091 /* 50 */ f18, f19, f20, f21, f22, 00092 /* 55 */ f23, f24, f25, f26, f27, 00093 /* 60 */ f28, f29, f30, f31, f32, 00094 /* 65 */ f33, f34, f35, f36, f37, 00095 /* 70 */ f38, f39, f40, f41, f42, 00096 /* 75 */ f43, f44, f45, f46, f47, 00097 /* 80 */ f48, f49, f50, f51, f52, 00098 /* 85 */ f53, f54, f55, f56, f57, 00099 /* 90 */ f58, f59, f60, f61, f62, 00100 /* 95 */ f63, 00101 00102 // SparcV9IntCCRegClass(IntCCRegClassID) 00103 // - unified register numbers 96 ... 98 (3 regs) 00104 /* 96 */ xcc, icc, ccr, 00105 00106 // SparcV9FloatCCRegClass(FloatCCRegClassID) 00107 // - unified register numbers 99 ... 102 (4 regs) 00108 /* 99 */ fcc0, fcc1, fcc2, fcc3, 00109 00110 // SparcV9SpecialRegClass(SpecialRegClassID) 00111 // - unified register number 103 (1 reg) 00112 /* 103 */ fsr 00113 }; 00114 } // end namespace SparcV9 00115 } // end namespace llvm 00116 00117 #endif // SPARCV9REGISTERINFO_H