LLVM API Documentation
00001 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by James M. Laskey and is distributed under the 00006 // University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This implements a simple two pass scheduler. The first pass attempts to push 00011 // backward any lengthy instructions and critical paths. The second pass packs 00012 // instructions into semi-optimal time slots. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #include "llvm/CodeGen/ScheduleDAG.h" 00017 #include "llvm/CodeGen/MachineConstantPool.h" 00018 #include "llvm/CodeGen/MachineFunction.h" 00019 #include "llvm/CodeGen/SSARegMap.h" 00020 #include "llvm/Target/TargetMachine.h" 00021 #include "llvm/Target/TargetInstrInfo.h" 00022 #include "llvm/Target/TargetLowering.h" 00023 #include "llvm/Support/MathExtras.h" 00024 using namespace llvm; 00025 00026 00027 /// CountResults - The results of target nodes have register or immediate 00028 /// operands first, then an optional chain, and optional flag operands (which do 00029 /// not go into the machine instrs.) 00030 static unsigned CountResults(SDNode *Node) { 00031 unsigned N = Node->getNumValues(); 00032 while (N && Node->getValueType(N - 1) == MVT::Flag) 00033 --N; 00034 if (N && Node->getValueType(N - 1) == MVT::Other) 00035 --N; // Skip over chain result. 00036 return N; 00037 } 00038 00039 /// CountOperands The inputs to target nodes have any actual inputs first, 00040 /// followed by an optional chain operand, then flag operands. Compute the 00041 /// number of actual operands that will go into the machine instr. 00042 static unsigned CountOperands(SDNode *Node) { 00043 unsigned N = Node->getNumOperands(); 00044 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 00045 --N; 00046 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 00047 --N; // Ignore chain if it exists. 00048 return N; 00049 } 00050 00051 static unsigned CreateVirtualRegisters(MachineInstr *MI, 00052 unsigned NumResults, 00053 SSARegMap *RegMap, 00054 const TargetInstrDescriptor &II) { 00055 // Create the result registers for this node and add the result regs to 00056 // the machine instruction. 00057 const TargetOperandInfo *OpInfo = II.OpInfo; 00058 unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass); 00059 MI->addRegOperand(ResultReg, MachineOperand::Def); 00060 for (unsigned i = 1; i != NumResults; ++i) { 00061 assert(OpInfo[i].RegClass && "Isn't a register operand!"); 00062 MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass), 00063 MachineOperand::Def); 00064 } 00065 return ResultReg; 00066 } 00067 00068 /// getVR - Return the virtual register corresponding to the specified result 00069 /// of the specified node. 00070 static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) { 00071 std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val); 00072 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 00073 return I->second + Op.ResNo; 00074 } 00075 00076 00077 /// AddOperand - Add the specified operand to the specified machine instr. II 00078 /// specifies the instruction information for the node, and IIOpNum is the 00079 /// operand number (in the II) that we are adding. IIOpNum and II are used for 00080 /// assertions only. 00081 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, 00082 unsigned IIOpNum, 00083 const TargetInstrDescriptor *II, 00084 std::map<SDNode*, unsigned> &VRBaseMap) { 00085 if (Op.isTargetOpcode()) { 00086 // Note that this case is redundant with the final else block, but we 00087 // include it because it is the most common and it makes the logic 00088 // simpler here. 00089 assert(Op.getValueType() != MVT::Other && 00090 Op.getValueType() != MVT::Flag && 00091 "Chain and flag operands should occur at end of operand list!"); 00092 00093 // Get/emit the operand. 00094 unsigned VReg = getVR(Op, VRBaseMap); 00095 MI->addRegOperand(VReg, MachineOperand::Use); 00096 00097 // Verify that it is right. 00098 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 00099 if (II) { 00100 assert(II->OpInfo[IIOpNum].RegClass && 00101 "Don't have operand info for this instruction!"); 00102 assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass && 00103 "Register class of operand and regclass of use don't agree!"); 00104 } 00105 } else if (ConstantSDNode *C = 00106 dyn_cast<ConstantSDNode>(Op)) { 00107 MI->addZeroExtImm64Operand(C->getValue()); 00108 } else if (RegisterSDNode*R = 00109 dyn_cast<RegisterSDNode>(Op)) { 00110 MI->addRegOperand(R->getReg(), MachineOperand::Use); 00111 } else if (GlobalAddressSDNode *TGA = 00112 dyn_cast<GlobalAddressSDNode>(Op)) { 00113 MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset()); 00114 } else if (BasicBlockSDNode *BB = 00115 dyn_cast<BasicBlockSDNode>(Op)) { 00116 MI->addMachineBasicBlockOperand(BB->getBasicBlock()); 00117 } else if (FrameIndexSDNode *FI = 00118 dyn_cast<FrameIndexSDNode>(Op)) { 00119 MI->addFrameIndexOperand(FI->getIndex()); 00120 } else if (ConstantPoolSDNode *CP = 00121 dyn_cast<ConstantPoolSDNode>(Op)) { 00122 int Offset = CP->getOffset(); 00123 unsigned Align = CP->getAlignment(); 00124 // MachineConstantPool wants an explicit alignment. 00125 if (Align == 0) { 00126 if (CP->get()->getType() == Type::DoubleTy) 00127 Align = 3; // always 8-byte align doubles. 00128 else { 00129 Align = TM.getTargetData() 00130 .getTypeAlignmentShift(CP->get()->getType()); 00131 if (Align == 0) { 00132 // Alignment of packed types. FIXME! 00133 Align = TM.getTargetData().getTypeSize(CP->get()->getType()); 00134 Align = Log2_64(Align); 00135 } 00136 } 00137 } 00138 00139 unsigned Idx = ConstPool->getConstantPoolIndex(CP->get(), Align); 00140 MI->addConstantPoolIndexOperand(Idx, Offset); 00141 } else if (ExternalSymbolSDNode *ES = 00142 dyn_cast<ExternalSymbolSDNode>(Op)) { 00143 MI->addExternalSymbolOperand(ES->getSymbol(), false); 00144 } else { 00145 assert(Op.getValueType() != MVT::Other && 00146 Op.getValueType() != MVT::Flag && 00147 "Chain and flag operands should occur at end of operand list!"); 00148 unsigned VReg = getVR(Op, VRBaseMap); 00149 MI->addRegOperand(VReg, MachineOperand::Use); 00150 00151 // Verify that it is right. 00152 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 00153 if (II) { 00154 assert(II->OpInfo[IIOpNum].RegClass && 00155 "Don't have operand info for this instruction!"); 00156 assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass && 00157 "Register class of operand and regclass of use don't agree!"); 00158 } 00159 } 00160 00161 } 00162 00163 00164 /// EmitNode - Generate machine code for an node and needed dependencies. 00165 /// 00166 void ScheduleDAG::EmitNode(SDNode *Node, 00167 std::map<SDNode*, unsigned> &VRBaseMap) { 00168 unsigned VRBase = 0; // First virtual register for node 00169 00170 // If machine instruction 00171 if (Node->isTargetOpcode()) { 00172 unsigned Opc = Node->getTargetOpcode(); 00173 const TargetInstrDescriptor &II = TII->get(Opc); 00174 00175 unsigned NumResults = CountResults(Node); 00176 unsigned NodeOperands = CountOperands(Node); 00177 unsigned NumMIOperands = NodeOperands + NumResults; 00178 #ifndef NDEBUG 00179 assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&& 00180 "#operands for dag node doesn't match .td file!"); 00181 #endif 00182 00183 // Create the new machine instruction. 00184 MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true); 00185 00186 // Add result register values for things that are defined by this 00187 // instruction. 00188 00189 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 00190 // the CopyToReg'd destination register instead of creating a new vreg. 00191 if (NumResults == 1) { 00192 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 00193 UI != E; ++UI) { 00194 SDNode *Use = *UI; 00195 if (Use->getOpcode() == ISD::CopyToReg && 00196 Use->getOperand(2).Val == Node) { 00197 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); 00198 if (MRegisterInfo::isVirtualRegister(Reg)) { 00199 VRBase = Reg; 00200 MI->addRegOperand(Reg, MachineOperand::Def); 00201 break; 00202 } 00203 } 00204 } 00205 } 00206 00207 // Otherwise, create new virtual registers. 00208 if (NumResults && VRBase == 0) 00209 VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, II); 00210 00211 // Emit all of the actual operands of this instruction, adding them to the 00212 // instruction as appropriate. 00213 for (unsigned i = 0; i != NodeOperands; ++i) 00214 AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap); 00215 00216 // Now that we have emitted all operands, emit this instruction itself. 00217 if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) { 00218 BB->insert(BB->end(), MI); 00219 } else { 00220 // Insert this instruction into the end of the basic block, potentially 00221 // taking some custom action. 00222 BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB); 00223 } 00224 } else { 00225 switch (Node->getOpcode()) { 00226 default: 00227 Node->dump(); 00228 assert(0 && "This target-independent node should have been selected!"); 00229 case ISD::EntryToken: // fall thru 00230 case ISD::TokenFactor: 00231 break; 00232 case ISD::CopyToReg: { 00233 unsigned InReg = getVR(Node->getOperand(2), VRBaseMap); 00234 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 00235 if (InReg != DestReg) // Coalesced away the copy? 00236 MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, 00237 RegMap->getRegClass(InReg)); 00238 break; 00239 } 00240 case ISD::CopyFromReg: { 00241 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 00242 if (MRegisterInfo::isVirtualRegister(SrcReg)) { 00243 VRBase = SrcReg; // Just use the input register directly! 00244 break; 00245 } 00246 00247 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 00248 // the CopyToReg'd destination register instead of creating a new vreg. 00249 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 00250 UI != E; ++UI) { 00251 SDNode *Use = *UI; 00252 if (Use->getOpcode() == ISD::CopyToReg && 00253 Use->getOperand(2).Val == Node) { 00254 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); 00255 if (MRegisterInfo::isVirtualRegister(DestReg)) { 00256 VRBase = DestReg; 00257 break; 00258 } 00259 } 00260 } 00261 00262 // Figure out the register class to create for the destreg. 00263 const TargetRegisterClass *TRC = 0; 00264 if (VRBase) { 00265 TRC = RegMap->getRegClass(VRBase); 00266 } else { 00267 00268 // Pick the register class of the right type that contains this physreg. 00269 for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(), 00270 E = MRI->regclass_end(); I != E; ++I) 00271 if ((*I)->hasType(Node->getValueType(0)) && 00272 (*I)->contains(SrcReg)) { 00273 TRC = *I; 00274 break; 00275 } 00276 assert(TRC && "Couldn't find register class for reg copy!"); 00277 00278 // Create the reg, emit the copy. 00279 VRBase = RegMap->createVirtualRegister(TRC); 00280 } 00281 MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC); 00282 break; 00283 } 00284 case ISD::INLINEASM: { 00285 unsigned NumOps = Node->getNumOperands(); 00286 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 00287 --NumOps; // Ignore the flag operand. 00288 00289 // Create the inline asm machine instruction. 00290 MachineInstr *MI = 00291 new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1); 00292 00293 // Add the asm string as an external symbol operand. 00294 const char *AsmStr = 00295 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol(); 00296 MI->addExternalSymbolOperand(AsmStr, false); 00297 00298 // Add all of the operand registers to the instruction. 00299 for (unsigned i = 2; i != NumOps;) { 00300 unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); 00301 unsigned NumVals = Flags >> 3; 00302 00303 MI->addZeroExtImm64Operand(Flags); 00304 ++i; // Skip the ID value. 00305 00306 switch (Flags & 7) { 00307 default: assert(0 && "Bad flags!"); 00308 case 1: // Use of register. 00309 for (; NumVals; --NumVals, ++i) { 00310 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 00311 MI->addMachineRegOperand(Reg, MachineOperand::Use); 00312 } 00313 break; 00314 case 2: // Def of register. 00315 for (; NumVals; --NumVals, ++i) { 00316 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 00317 MI->addMachineRegOperand(Reg, MachineOperand::Def); 00318 } 00319 break; 00320 case 3: { // Immediate. 00321 assert(NumVals == 1 && "Unknown immediate value!"); 00322 uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue(); 00323 MI->addZeroExtImm64Operand(Val); 00324 ++i; 00325 break; 00326 } 00327 case 4: // Addressing mode. 00328 // The addressing mode has been selected, just add all of the 00329 // operands to the machine instruction. 00330 for (; NumVals; --NumVals, ++i) 00331 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 00332 break; 00333 } 00334 } 00335 break; 00336 } 00337 } 00338 } 00339 00340 assert(!VRBaseMap.count(Node) && "Node emitted out of order - early"); 00341 VRBaseMap[Node] = VRBase; 00342 } 00343 00344 void ScheduleDAG::EmitNoop() { 00345 TII->insertNoop(*BB, BB->end()); 00346 } 00347 00348 /// Run - perform scheduling. 00349 /// 00350 MachineBasicBlock *ScheduleDAG::Run() { 00351 TII = TM.getInstrInfo(); 00352 MRI = TM.getRegisterInfo(); 00353 RegMap = BB->getParent()->getSSARegMap(); 00354 ConstPool = BB->getParent()->getConstantPool(); 00355 00356 Schedule(); 00357 return BB; 00358 } 00359 00360