LLVM API Documentation

SelectionDAGISel.h

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00001 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the SelectionDAGISel class, which is used as the common
00011 // base class for SelectionDAG-based instruction selectors.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
00016 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
00017 
00018 #include "llvm/Pass.h"
00019 #include "llvm/Constant.h"
00020 #include "llvm/CodeGen/SelectionDAGNodes.h"
00021 
00022 namespace llvm {
00023   class SelectionDAG;
00024   class SelectionDAGLowering;
00025   class SDOperand;
00026   class SSARegMap;
00027   class MachineBasicBlock;
00028   class MachineFunction;
00029   class MachineInstr;
00030   class TargetLowering;
00031   class FunctionLoweringInfo;
00032   class HazardRecognizer;
00033 
00034 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
00035 /// pattern-matching instruction selectors.
00036 class SelectionDAGISel : public FunctionPass {
00037 public:
00038   TargetLowering &TLI;
00039   SSARegMap *RegMap;
00040   SelectionDAG *CurDAG;
00041   MachineBasicBlock *BB;
00042 
00043   SelectionDAGISel(TargetLowering &tli) : TLI(tli) {}
00044 
00045   virtual void getAnalysisUsage(AnalysisUsage &AU) const;
00046 
00047   virtual bool runOnFunction(Function &Fn);
00048 
00049   unsigned MakeReg(MVT::ValueType VT);
00050 
00051   virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
00052   virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
00053 
00054   /// SelectInlineAsmMemoryOperand - Select the specified address as a target
00055   /// addressing mode, according to the specified constraint code.  If this does
00056   /// not match or is not implemented, return true.  The resultant operands
00057   /// (which will appear in the machine instruction) should be added to the
00058   /// OutOps vector.
00059   virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
00060                                             char ConstraintCode,
00061                                             std::vector<SDOperand> &OutOps,
00062                                             SelectionDAG &DAG) {
00063     return true;
00064   }
00065   
00066   /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
00067   /// to use for this target when scheduling the DAG.
00068   virtual HazardRecognizer *CreateTargetHazardRecognizer();
00069   
00070   /// CaseBlock - This structure is used to communicate between SDLowering and
00071   /// SDISel for the code generation of additional basic blocks needed by multi-
00072   /// case switch statements.
00073   struct CaseBlock {
00074     CaseBlock(ISD::CondCode cc, Value *s, Constant *c, MachineBasicBlock *lhs,
00075               MachineBasicBlock *rhs, MachineBasicBlock *me) : 
00076     CC(cc), SwitchV(s), CaseC(c), LHSBB(lhs), RHSBB(rhs), ThisBB(me) {}
00077     // CC - the condition code to use for the case block's setcc node
00078     ISD::CondCode CC;
00079     // SwitchV - the value to be switched on, 'foo' in switch(foo)
00080     Value *SwitchV;
00081     // CaseC - the constant the setcc node will compare against SwitchV
00082     Constant *CaseC;
00083     // LHSBB - the block to branch to if the setcc is true
00084     MachineBasicBlock *LHSBB;
00085     // RHSBB - the block to branch to if the setcc is false
00086     MachineBasicBlock *RHSBB;
00087     // ThisBB - the blcok into which to emit the code for the setcc and branches
00088     MachineBasicBlock *ThisBB;
00089   };
00090   
00091 protected:
00092   /// Pick a safe ordering and emit instructions for each target node in the
00093   /// graph.
00094   void ScheduleAndEmitDAG(SelectionDAG &DAG);
00095   
00096   /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
00097   /// by tblgen.  Others should not call it.
00098   void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
00099                                      SelectionDAG &DAG);
00100   
00101 private:
00102   SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
00103                                        Value *V, unsigned Reg);
00104   void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
00105                         FunctionLoweringInfo &FuncInfo);
00106 
00107   void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
00108            std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
00109                          FunctionLoweringInfo &FuncInfo);
00110   void CodeGenAndEmitDAG(SelectionDAG &DAG);
00111   void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
00112                       std::vector<SDOperand> &UnorderedChains);
00113 
00114   /// SwitchCases - Vector of CaseBlock structures used to communicate
00115   /// SwitchInst code generation information.
00116   std::vector<CaseBlock> SwitchCases;
00117 };
00118 
00119 }
00120 
00121 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */