LLVM API Documentation

SparcGenRegisterInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Register Information Source Fragment
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 namespace {     // Register classes...
00012   // DFPRegs Register Class...
00013   const unsigned DFPRegs[] = {
00014     SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, 
00015   };
00016 
00017   // FPRegs Register Class...
00018   const unsigned FPRegs[] = {
00019     SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31, 
00020   };
00021 
00022   // IntRegs Register Class...
00023   const unsigned IntRegs[] = {
00024     SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3, SP::G4, SP::O6, SP::I6, SP::I7, SP::G0, SP::G5, SP::G6, SP::G7, 
00025   };
00026 
00027   // DFPRegsVTs Register Class Value Types...
00028   const MVT::ValueType DFPRegsVTs[] = {
00029     MVT::f64, MVT::Other
00030   };
00031 
00032   // FPRegsVTs Register Class Value Types...
00033   const MVT::ValueType FPRegsVTs[] = {
00034     MVT::f32, MVT::Other
00035   };
00036 
00037   // IntRegsVTs Register Class Value Types...
00038   const MVT::ValueType IntRegsVTs[] = {
00039     MVT::i32, MVT::Other
00040   };
00041 
00042 }  // end anonymous namespace
00043 
00044 namespace SP {   // Register class instances
00045   DFPRegsClass  DFPRegsRegClass;
00046   FPRegsClass FPRegsRegClass;
00047   IntRegsClass  IntRegsRegClass;
00048 
00049 DFPRegsClass::DFPRegsClass()  : TargetRegisterClass(DFPRegsVTs, 8, 8, DFPRegs, DFPRegs + 16) {}
00050 
00051 FPRegsClass::FPRegsClass()  : TargetRegisterClass(FPRegsVTs, 4, 4, FPRegs, FPRegs + 32) {}
00052 
00053     IntRegsClass::iterator
00054     IntRegsClass::allocation_order_end(MachineFunction &MF) const {
00055       // FIXME: These special regs should be taken out of the regclass!
00056       return end()-10  // Don't allocate special registers
00057          -1;  // FIXME: G1 reserved for large imm generation by frame code.
00058     }
00059   
00060 IntRegsClass::IntRegsClass()  : TargetRegisterClass(IntRegsVTs, 4, 4, IntRegs, IntRegs + 32) {}
00061 }
00062 
00063 namespace {
00064   const TargetRegisterClass* const RegisterClasses[] = {
00065     &SP::DFPRegsRegClass,
00066     &SP::FPRegsRegClass,
00067     &SP::IntRegsRegClass,
00068   };
00069 
00070 
00071   // Register Alias Sets...
00072   const unsigned Empty_AliasSet[] = { 0 };
00073   const unsigned F0_AliasSet[] = { SP::D0, 0 };
00074   const unsigned F1_AliasSet[] = { SP::D0, 0 };
00075   const unsigned F2_AliasSet[] = { SP::D1, 0 };
00076   const unsigned F3_AliasSet[] = { SP::D1, 0 };
00077   const unsigned F4_AliasSet[] = { SP::D2, 0 };
00078   const unsigned F5_AliasSet[] = { SP::D2, 0 };
00079   const unsigned F6_AliasSet[] = { SP::D3, 0 };
00080   const unsigned F7_AliasSet[] = { SP::D3, 0 };
00081   const unsigned F8_AliasSet[] = { SP::D4, 0 };
00082   const unsigned F9_AliasSet[] = { SP::D4, 0 };
00083   const unsigned F10_AliasSet[] = { SP::D5, 0 };
00084   const unsigned F11_AliasSet[] = { SP::D5, 0 };
00085   const unsigned F12_AliasSet[] = { SP::D6, 0 };
00086   const unsigned F13_AliasSet[] = { SP::D6, 0 };
00087   const unsigned F14_AliasSet[] = { SP::D7, 0 };
00088   const unsigned F15_AliasSet[] = { SP::D7, 0 };
00089   const unsigned F16_AliasSet[] = { SP::D8, 0 };
00090   const unsigned F17_AliasSet[] = { SP::D8, 0 };
00091   const unsigned F18_AliasSet[] = { SP::D9, 0 };
00092   const unsigned F19_AliasSet[] = { SP::D9, 0 };
00093   const unsigned F20_AliasSet[] = { SP::D10, 0 };
00094   const unsigned F21_AliasSet[] = { SP::D10, 0 };
00095   const unsigned F22_AliasSet[] = { SP::D11, 0 };
00096   const unsigned F23_AliasSet[] = { SP::D11, 0 };
00097   const unsigned F24_AliasSet[] = { SP::D12, 0 };
00098   const unsigned F25_AliasSet[] = { SP::D12, 0 };
00099   const unsigned F26_AliasSet[] = { SP::D13, 0 };
00100   const unsigned F27_AliasSet[] = { SP::D13, 0 };
00101   const unsigned F28_AliasSet[] = { SP::D14, 0 };
00102   const unsigned F29_AliasSet[] = { SP::D14, 0 };
00103   const unsigned F30_AliasSet[] = { SP::D15, 0 };
00104   const unsigned F31_AliasSet[] = { SP::D15, 0 };
00105   const unsigned D0_AliasSet[] = { SP::F0, SP::F1, 0 };
00106   const unsigned D1_AliasSet[] = { SP::F2, SP::F3, 0 };
00107   const unsigned D2_AliasSet[] = { SP::F4, SP::F5, 0 };
00108   const unsigned D3_AliasSet[] = { SP::F6, SP::F7, 0 };
00109   const unsigned D4_AliasSet[] = { SP::F8, SP::F9, 0 };
00110   const unsigned D5_AliasSet[] = { SP::F10, SP::F11, 0 };
00111   const unsigned D6_AliasSet[] = { SP::F12, SP::F13, 0 };
00112   const unsigned D7_AliasSet[] = { SP::F14, SP::F15, 0 };
00113   const unsigned D8_AliasSet[] = { SP::F16, SP::F17, 0 };
00114   const unsigned D9_AliasSet[] = { SP::F18, SP::F19, 0 };
00115   const unsigned D10_AliasSet[] = { SP::F20, SP::F21, 0 };
00116   const unsigned D11_AliasSet[] = { SP::F22, SP::F23, 0 };
00117   const unsigned D12_AliasSet[] = { SP::F24, SP::F25, 0 };
00118   const unsigned D13_AliasSet[] = { SP::F26, SP::F27, 0 };
00119   const unsigned D14_AliasSet[] = { SP::F28, SP::F29, 0 };
00120   const unsigned D15_AliasSet[] = { SP::F30, SP::F31, 0 };
00121 
00122   const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors
00123     { "NOREG",  0 },
00124     { "F0", D0_AliasSet },
00125     { "F2", D1_AliasSet },
00126     { "F20",  D10_AliasSet },
00127     { "F22",  D11_AliasSet },
00128     { "F24",  D12_AliasSet },
00129     { "F26",  D13_AliasSet },
00130     { "F28",  D14_AliasSet },
00131     { "F30",  D15_AliasSet },
00132     { "F4", D2_AliasSet },
00133     { "F6", D3_AliasSet },
00134     { "F8", D4_AliasSet },
00135     { "F10",  D5_AliasSet },
00136     { "F12",  D6_AliasSet },
00137     { "F14",  D7_AliasSet },
00138     { "F16",  D8_AliasSet },
00139     { "F18",  D9_AliasSet },
00140     { "F0", F0_AliasSet },
00141     { "F1", F1_AliasSet },
00142     { "F10",  F10_AliasSet },
00143     { "F11",  F11_AliasSet },
00144     { "F12",  F12_AliasSet },
00145     { "F13",  F13_AliasSet },
00146     { "F14",  F14_AliasSet },
00147     { "F15",  F15_AliasSet },
00148     { "F16",  F16_AliasSet },
00149     { "F17",  F17_AliasSet },
00150     { "F18",  F18_AliasSet },
00151     { "F19",  F19_AliasSet },
00152     { "F2", F2_AliasSet },
00153     { "F20",  F20_AliasSet },
00154     { "F21",  F21_AliasSet },
00155     { "F22",  F22_AliasSet },
00156     { "F23",  F23_AliasSet },
00157     { "F24",  F24_AliasSet },
00158     { "F25",  F25_AliasSet },
00159     { "F26",  F26_AliasSet },
00160     { "F27",  F27_AliasSet },
00161     { "F28",  F28_AliasSet },
00162     { "F29",  F29_AliasSet },
00163     { "F3", F3_AliasSet },
00164     { "F30",  F30_AliasSet },
00165     { "F31",  F31_AliasSet },
00166     { "F4", F4_AliasSet },
00167     { "F5", F5_AliasSet },
00168     { "F6", F6_AliasSet },
00169     { "F7", F7_AliasSet },
00170     { "F8", F8_AliasSet },
00171     { "F9", F9_AliasSet },
00172     { "G0", Empty_AliasSet },
00173     { "G1", Empty_AliasSet },
00174     { "G2", Empty_AliasSet },
00175     { "G3", Empty_AliasSet },
00176     { "G4", Empty_AliasSet },
00177     { "G5", Empty_AliasSet },
00178     { "G6", Empty_AliasSet },
00179     { "G7", Empty_AliasSet },
00180     { "I0", Empty_AliasSet },
00181     { "I1", Empty_AliasSet },
00182     { "I2", Empty_AliasSet },
00183     { "I3", Empty_AliasSet },
00184     { "I4", Empty_AliasSet },
00185     { "I5", Empty_AliasSet },
00186     { "I6", Empty_AliasSet },
00187     { "I7", Empty_AliasSet },
00188     { "L0", Empty_AliasSet },
00189     { "L1", Empty_AliasSet },
00190     { "L2", Empty_AliasSet },
00191     { "L3", Empty_AliasSet },
00192     { "L4", Empty_AliasSet },
00193     { "L5", Empty_AliasSet },
00194     { "L6", Empty_AliasSet },
00195     { "L7", Empty_AliasSet },
00196     { "O0", Empty_AliasSet },
00197     { "O1", Empty_AliasSet },
00198     { "O2", Empty_AliasSet },
00199     { "O3", Empty_AliasSet },
00200     { "O4", Empty_AliasSet },
00201     { "O5", Empty_AliasSet },
00202     { "O6", Empty_AliasSet },
00203     { "O7", Empty_AliasSet },
00204   };
00205 }
00206 
00207 SparcGenRegisterInfo::SparcGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
00208   : MRegisterInfo(RegisterDescriptors, 81, RegisterClasses, RegisterClasses+3,
00209                   CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
00210 
00211 const unsigned* SparcGenRegisterInfo::getCalleeSaveRegs() const {
00212   static const unsigned CalleeSaveRegs[] = {
00213      0
00214   };
00215   return CalleeSaveRegs;
00216 }
00217 
00218 const TargetRegisterClass* const*
00219 SparcGenRegisterInfo::getCalleeSaveRegClasses() const {
00220   static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
00221      0
00222   };
00223   return CalleeSaveRegClasses;
00224 }
00225 
00226 int SparcGenRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
00227   static const int DwarfRegNums[] = { -1, // NoRegister
00228     32, 34, 52, 54, 56, 58, 60, 62, 36, 38, 40, 42, 44, 46, 48, 50, 
00229     32, 33, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 34, 52, 53, 54, 
00230     55, 56, 57, 58, 59, 60, 61, 35, 62, 63, 36, 37, 38, 39, 40, 41, 
00231     0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31, 
00232     16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 12, 13, 14, 15
00233   };
00234   assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&
00235          "RegNum exceeds number of registers");
00236   return DwarfRegNums[RegNum];
00237 }
00238 
00239 } // End llvm namespace