LLVM API Documentation

X86GenInstrInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Target Instruction Descriptors
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 static const unsigned EmptyImpList[] = { 0 };
00012 static const unsigned ImplicitList1[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
00013 static const unsigned ImplicitList2[] = { X86::AL, 0 };
00014 static const unsigned ImplicitList3[] = { X86::AH, 0 };
00015 static const unsigned ImplicitList4[] = { X86::EAX, 0 };
00016 static const unsigned ImplicitList5[] = { X86::EDX, 0 };
00017 static const unsigned ImplicitList6[] = { X86::AX, 0 };
00018 static const unsigned ImplicitList7[] = { X86::DX, 0 };
00019 static const unsigned ImplicitList8[] = { X86::AX, X86::DX, 0 };
00020 static const unsigned ImplicitList9[] = { X86::EAX, X86::EDX, 0 };
00021 static const unsigned ImplicitList10[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 };
00022 static const unsigned ImplicitList11[] = { X86::ST0, 0 };
00023 static const unsigned ImplicitList12[] = { X86::EBP, X86::ESP, 0 };
00024 static const unsigned ImplicitList13[] = { X86::EDI, 0 };
00025 static const unsigned ImplicitList14[] = { X86::DX, X86::AX, 0 };
00026 static const unsigned ImplicitList15[] = { X86::DX, X86::EAX, 0 };
00027 static const unsigned ImplicitList16[] = { X86::DX, X86::AL, 0 };
00028 static const unsigned ImplicitList17[] = { X86::ESP, 0 };
00029 static const unsigned ImplicitList18[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
00030 static const unsigned ImplicitList19[] = { X86::AL, X86::ECX, X86::EDI, 0 };
00031 static const unsigned ImplicitList20[] = { X86::ECX, X86::EDI, 0 };
00032 static const unsigned ImplicitList21[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
00033 static const unsigned ImplicitList22[] = { X86::AX, X86::ECX, X86::EDI, 0 };
00034 static const unsigned ImplicitList23[] = { X86::CL, 0 };
00035 
00036 static const TargetOperandInfo OperandInfo2[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00037 static const TargetOperandInfo OperandInfo3[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, };
00038 static const TargetOperandInfo OperandInfo4[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, { 0 }, };
00039 static const TargetOperandInfo OperandInfo5[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00040 static const TargetOperandInfo OperandInfo6[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, { &X86::R32RegClass }, };
00041 static const TargetOperandInfo OperandInfo7[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::R16RegClass }, };
00042 static const TargetOperandInfo OperandInfo8[] = { { &X86::R16RegClass }, { &X86::R16RegClass }, { 0 }, };
00043 static const TargetOperandInfo OperandInfo9[] = { { &X86::R16RegClass }, { &X86::R16RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00044 static const TargetOperandInfo OperandInfo10[] = { { &X86::R16RegClass }, { &X86::R16RegClass }, { &X86::R16RegClass }, };
00045 static const TargetOperandInfo OperandInfo11[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::R8RegClass }, };
00046 static const TargetOperandInfo OperandInfo12[] = { { &X86::R8RegClass }, { &X86::R8RegClass }, { 0 }, };
00047 static const TargetOperandInfo OperandInfo13[] = { { &X86::R8RegClass }, { &X86::R8RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00048 static const TargetOperandInfo OperandInfo14[] = { { &X86::R8RegClass }, { &X86::R8RegClass }, { &X86::R8RegClass }, };
00049 static const TargetOperandInfo OperandInfo15[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00050 static const TargetOperandInfo OperandInfo16[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::VR128RegClass }, };
00051 static const TargetOperandInfo OperandInfo17[] = { { &X86::FR64RegClass }, { &X86::FR64RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00052 static const TargetOperandInfo OperandInfo18[] = { { &X86::FR64RegClass }, { &X86::FR64RegClass }, { &X86::FR64RegClass }, };
00053 static const TargetOperandInfo OperandInfo19[] = { { &X86::FR32RegClass }, { &X86::FR32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00054 static const TargetOperandInfo OperandInfo20[] = { { &X86::FR32RegClass }, { &X86::FR32RegClass }, { &X86::FR32RegClass }, };
00055 static const TargetOperandInfo OperandInfo21[] = { { 0 }, };
00056 static const TargetOperandInfo OperandInfo22[] = { { 0 }, { 0 }, };
00057 static const TargetOperandInfo OperandInfo23[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, };
00058 static const TargetOperandInfo OperandInfo24[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00059 static const TargetOperandInfo OperandInfo25[] = { { &X86::R32RegClass }, };
00060 static const TargetOperandInfo OperandInfo26[] = { { &X86::FR32RegClass }, { &X86::FR32RegClass }, { &X86::FR32RegClass }, { 0 }, };
00061 static const TargetOperandInfo OperandInfo27[] = { { &X86::FR64RegClass }, { &X86::FR64RegClass }, { &X86::FR64RegClass }, { 0 }, };
00062 static const TargetOperandInfo OperandInfo28[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::VR128RegClass }, { 0 }, };
00063 static const TargetOperandInfo OperandInfo29[] = { { &X86::R16RegClass }, { 0 }, };
00064 static const TargetOperandInfo OperandInfo30[] = { { &X86::R16RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00065 static const TargetOperandInfo OperandInfo31[] = { { &X86::R16RegClass }, { &X86::R16RegClass }, };
00066 static const TargetOperandInfo OperandInfo32[] = { { &X86::R32RegClass }, { 0 }, };
00067 static const TargetOperandInfo OperandInfo33[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00068 static const TargetOperandInfo OperandInfo34[] = { { &X86::R8RegClass }, { 0 }, };
00069 static const TargetOperandInfo OperandInfo35[] = { { &X86::R8RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00070 static const TargetOperandInfo OperandInfo36[] = { { &X86::R8RegClass }, { &X86::R8RegClass }, };
00071 static const TargetOperandInfo OperandInfo37[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00072 static const TargetOperandInfo OperandInfo38[] = { { &X86::FR64RegClass }, { &X86::FR64RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00073 static const TargetOperandInfo OperandInfo39[] = { { &X86::FR32RegClass }, { &X86::FR32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00074 static const TargetOperandInfo OperandInfo40[] = { { &X86::VR128RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00075 static const TargetOperandInfo OperandInfo41[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, };
00076 static const TargetOperandInfo OperandInfo42[] = { { &X86::VR64RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00077 static const TargetOperandInfo OperandInfo43[] = { { &X86::VR64RegClass }, { &X86::VR128RegClass }, };
00078 static const TargetOperandInfo OperandInfo44[] = { { &X86::VR128RegClass }, { &X86::VR64RegClass }, };
00079 static const TargetOperandInfo OperandInfo45[] = { { &X86::R32RegClass }, { &X86::VR128RegClass }, };
00080 static const TargetOperandInfo OperandInfo46[] = { { &X86::FR32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00081 static const TargetOperandInfo OperandInfo47[] = { { &X86::FR32RegClass }, { &X86::FR64RegClass }, };
00082 static const TargetOperandInfo OperandInfo48[] = { { &X86::FR64RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00083 static const TargetOperandInfo OperandInfo49[] = { { &X86::FR64RegClass }, { &X86::R32RegClass }, };
00084 static const TargetOperandInfo OperandInfo50[] = { { &X86::FR32RegClass }, { &X86::R32RegClass }, };
00085 static const TargetOperandInfo OperandInfo51[] = { { &X86::FR64RegClass }, { &X86::FR32RegClass }, };
00086 static const TargetOperandInfo OperandInfo52[] = { { &X86::R32RegClass }, { &X86::FR64RegClass }, };
00087 static const TargetOperandInfo OperandInfo53[] = { { &X86::R32RegClass }, { &X86::FR32RegClass }, };
00088 static const TargetOperandInfo OperandInfo54[] = { { &X86::R16RegClass }, };
00089 static const TargetOperandInfo OperandInfo55[] = { { &X86::R8RegClass }, };
00090 static const TargetOperandInfo OperandInfo56[] = { { 0 }, { 0 }, { 0 }, };
00091 static const TargetOperandInfo OperandInfo57[] = { { &X86::RSTRegClass }, };
00092 static const TargetOperandInfo OperandInfo58[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::RFPRegClass }, };
00093 static const TargetOperandInfo OperandInfo59[] = { { &X86::RFPRegClass }, { &X86::RFPRegClass }, };
00094 static const TargetOperandInfo OperandInfo60[] = { { &X86::RFPRegClass }, { &X86::RFPRegClass }, { &X86::RFPRegClass }, };
00095 static const TargetOperandInfo OperandInfo61[] = { { &X86::RFPRegClass }, { &X86::RFPRegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00096 static const TargetOperandInfo OperandInfo62[] = { { &X86::RFPRegClass }, };
00097 static const TargetOperandInfo OperandInfo63[] = { { &X86::RFPRegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00098 static const TargetOperandInfo OperandInfo64[] = { { &X86::FR64RegClass }, };
00099 static const TargetOperandInfo OperandInfo65[] = { { &X86::FR32RegClass }, };
00100 static const TargetOperandInfo OperandInfo66[] = { { &X86::FR64RegClass }, { &X86::FR64RegClass }, };
00101 static const TargetOperandInfo OperandInfo67[] = { { &X86::FR32RegClass }, { &X86::FR32RegClass }, };
00102 static const TargetOperandInfo OperandInfo68[] = { { &X86::VR128RegClass }, };
00103 static const TargetOperandInfo OperandInfo69[] = { { &X86::VR64RegClass }, };
00104 static const TargetOperandInfo OperandInfo70[] = { { &X86::R16RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00105 static const TargetOperandInfo OperandInfo71[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00106 static const TargetOperandInfo OperandInfo72[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::R32RegClass }, };
00107 static const TargetOperandInfo OperandInfo73[] = { { &X86::VR64RegClass }, { &X86::VR64RegClass }, };
00108 static const TargetOperandInfo OperandInfo74[] = { { &X86::FR64RegClass }, { &X86::FR32RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00109 static const TargetOperandInfo OperandInfo75[] = { { &X86::FR64RegClass }, { &X86::FR32RegClass }, { &X86::FR64RegClass }, };
00110 static const TargetOperandInfo OperandInfo76[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::VR128RegClass }, };
00111 static const TargetOperandInfo OperandInfo77[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::VR64RegClass }, };
00112 static const TargetOperandInfo OperandInfo78[] = { { &X86::VR64RegClass }, { &X86::R32RegClass }, };
00113 static const TargetOperandInfo OperandInfo79[] = { { &X86::VR128RegClass }, { &X86::R32RegClass }, };
00114 static const TargetOperandInfo OperandInfo80[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::FR64RegClass }, };
00115 static const TargetOperandInfo OperandInfo81[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::FR32RegClass }, };
00116 static const TargetOperandInfo OperandInfo82[] = { { &X86::FR64RegClass }, { &X86::VR128RegClass }, };
00117 static const TargetOperandInfo OperandInfo83[] = { { &X86::FR32RegClass }, { &X86::VR128RegClass }, };
00118 static const TargetOperandInfo OperandInfo84[] = { { &X86::VR128RegClass }, { &X86::FR64RegClass }, };
00119 static const TargetOperandInfo OperandInfo85[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::FR64RegClass }, };
00120 static const TargetOperandInfo OperandInfo86[] = { { &X86::VR128RegClass }, { &X86::FR32RegClass }, };
00121 static const TargetOperandInfo OperandInfo87[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::FR32RegClass }, };
00122 static const TargetOperandInfo OperandInfo88[] = { { &X86::R16RegClass }, { &X86::R8RegClass }, };
00123 static const TargetOperandInfo OperandInfo89[] = { { &X86::R32RegClass }, { &X86::R16RegClass }, };
00124 static const TargetOperandInfo OperandInfo90[] = { { &X86::R32RegClass }, { &X86::R8RegClass }, };
00125 static const TargetOperandInfo OperandInfo91[] = { { &X86::R32RegClass }, { &X86::VR128RegClass }, { 0 }, };
00126 static const TargetOperandInfo OperandInfo92[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { &X86::R32RegClass }, { 0 }, };
00127 static const TargetOperandInfo OperandInfo93[] = { { &X86::VR128RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00128 static const TargetOperandInfo OperandInfo94[] = { { &X86::VR128RegClass }, { &X86::VR128RegClass }, { 0 }, };
00129 static const TargetOperandInfo OperandInfo95[] = { { &X86::VR64RegClass }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { 0 }, };
00130 static const TargetOperandInfo OperandInfo96[] = { { &X86::VR64RegClass }, { &X86::VR64RegClass }, { 0 }, };
00131 static const TargetOperandInfo OperandInfo97[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::R16RegClass }, { 0 }, };
00132 static const TargetOperandInfo OperandInfo98[] = { { &X86::R16RegClass }, { &X86::R16RegClass }, { &X86::R16RegClass }, { 0 }, };
00133 static const TargetOperandInfo OperandInfo99[] = { { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, { &X86::R32RegClass }, { 0 }, };
00134 static const TargetOperandInfo OperandInfo100[] = { { &X86::R32RegClass }, { &X86::R32RegClass }, { &X86::R32RegClass }, { 0 }, };
00135 
00136 static const TargetInstrDescriptor X86Insts[] = {
00137   { "PHI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #0 = PHI
00138   { "INLINEASM",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #1 = INLINEASM
00139   { "ADC32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|26|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #2 = ADC32mi
00140   { "ADC32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|26|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #3 = ADC32mi8
00141   { "ADC32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(17<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #4 = ADC32mr
00142   { "ADC32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|18|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #5 = ADC32ri
00143   { "ADC32ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #6 = ADC32ri8
00144   { "ADC32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(19<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #7 = ADC32rm
00145   { "ADC32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(17<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #8 = ADC32rr
00146   { "ADD16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #9 = ADD16mi
00147   { "ADD16mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #10 = ADD16mi8
00148   { "ADD16mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #11 = ADD16mr
00149   { "ADD16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #12 = ADD16ri
00150   { "ADD16ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #13 = ADD16ri8
00151   { "ADD16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(3<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #14 = ADD16rm
00152   { "ADD16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR|M_COMMUTABLE, 0|3|(1<<6)|(1<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #15 = ADD16rr
00153   { "ADD32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #16 = ADD32mi
00154   { "ADD32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #17 = ADD32mi8
00155   { "ADD32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #18 = ADD32mr
00156   { "ADD32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #19 = ADD32ri
00157   { "ADD32ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #20 = ADD32ri8
00158   { "ADD32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(3<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #21 = ADD32rm
00159   { "ADD32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR|M_COMMUTABLE, 0|3|(1<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #22 = ADD32rr
00160   { "ADD8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #23 = ADD8mi
00161   { "ADD8mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4, EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #24 = ADD8mr
00162   { "ADD8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #25 = ADD8ri
00163   { "ADD8rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(2<<17), EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #26 = ADD8rm
00164   { "ADD8rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3, EmptyImpList, EmptyImpList, OperandInfo14 },  // Inst #27 = ADD8rr
00165   { "ADDPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #28 = ADDPDrm
00166   { "ADDPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #29 = ADDPDrr
00167   { "ADDPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #30 = ADDPSrm
00168   { "ADDPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #31 = ADDPSrr
00169   { "ADDSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #32 = ADDSDrm
00170   { "ADDSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #33 = ADDSDrr
00171   { "ADDSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #34 = ADDSSrm
00172   { "ADDSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #35 = ADDSSrr
00173   { "ADJCALLSTACKDOWN", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #36 = ADJCALLSTACKDOWN
00174   { "ADJCALLSTACKUP", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo22 },  // Inst #37 = ADJCALLSTACKUP
00175   { "ADJSTACKPTRri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_TERMINATOR_FLAG, 0|16|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #38 = ADJSTACKPTRri
00176   { "AND16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #39 = AND16mi
00177   { "AND16mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #40 = AND16mi8
00178   { "AND16mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(33<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #41 = AND16mr
00179   { "AND16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #42 = AND16ri
00180   { "AND16ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #43 = AND16ri8
00181   { "AND16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(35<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #44 = AND16rm
00182   { "AND16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(33<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #45 = AND16rr
00183   { "AND32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|28|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #46 = AND32mi
00184   { "AND32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #47 = AND32mi8
00185   { "AND32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(33<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #48 = AND32mr
00186   { "AND32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #49 = AND32ri
00187   { "AND32ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #50 = AND32ri8
00188   { "AND32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(35<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #51 = AND32rm
00189   { "AND32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(33<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #52 = AND32rr
00190   { "AND8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #53 = AND8mi
00191   { "AND8mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(32<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #54 = AND8mr
00192   { "AND8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #55 = AND8ri
00193   { "AND8rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(34<<17), EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #56 = AND8rm
00194   { "AND8rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(32<<17), EmptyImpList, EmptyImpList, OperandInfo14 },  // Inst #57 = AND8rr
00195   { "ANDNPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #58 = ANDNPDrm
00196   { "ANDNPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #59 = ANDNPDrr
00197   { "ANDNPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #60 = ANDNPSrm
00198   { "ANDNPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #61 = ANDNPSrr
00199   { "ANDPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #62 = ANDPDrm
00200   { "ANDPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #63 = ANDPDrr
00201   { "ANDPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #64 = ANDPSrm
00202   { "ANDPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #65 = ANDPSrr
00203   { "BSWAP32r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|2|(1<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #66 = BSWAP32r
00204   { "CALL32m",  4, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|26|(255<<17), EmptyImpList, ImplicitList1, OperandInfo24 },  // Inst #67 = CALL32m
00205   { "CALL32r",  1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|18|(255<<17), EmptyImpList, ImplicitList1, OperandInfo25 },  // Inst #68 = CALL32r
00206   { "CALLpcrel32",  1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|1|(232<<17), EmptyImpList, ImplicitList1, OperandInfo21 },  // Inst #69 = CALLpcrel32
00207   { "CBW",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(152<<17), ImplicitList2, ImplicitList3, 0 },  // Inst #70 = CBW
00208   { "CDQ",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(153<<17), ImplicitList4, ImplicitList5, 0 },  // Inst #71 = CDQ
00209   { "CMOVA16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(71<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #72 = CMOVA16rm
00210   { "CMOVA16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(71<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #73 = CMOVA16rr
00211   { "CMOVA32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(71<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #74 = CMOVA32rm
00212   { "CMOVA32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(71<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #75 = CMOVA32rr
00213   { "CMOVAE16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(67<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #76 = CMOVAE16rm
00214   { "CMOVAE16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(67<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #77 = CMOVAE16rr
00215   { "CMOVAE32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(67<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #78 = CMOVAE32rm
00216   { "CMOVAE32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(67<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #79 = CMOVAE32rr
00217   { "CMOVB16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(66<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #80 = CMOVB16rm
00218   { "CMOVB16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(66<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #81 = CMOVB16rr
00219   { "CMOVB32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(66<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #82 = CMOVB32rm
00220   { "CMOVB32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(66<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #83 = CMOVB32rr
00221   { "CMOVBE16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(70<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #84 = CMOVBE16rm
00222   { "CMOVBE16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(70<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #85 = CMOVBE16rr
00223   { "CMOVBE32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(70<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #86 = CMOVBE32rm
00224   { "CMOVBE32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(70<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #87 = CMOVBE32rr
00225   { "CMOVE16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(68<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #88 = CMOVE16rm
00226   { "CMOVE16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(68<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #89 = CMOVE16rr
00227   { "CMOVE32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(68<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #90 = CMOVE32rm
00228   { "CMOVE32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(68<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #91 = CMOVE32rr
00229   { "CMOVG16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(79<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #92 = CMOVG16rm
00230   { "CMOVG16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(79<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #93 = CMOVG16rr
00231   { "CMOVG32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(79<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #94 = CMOVG32rm
00232   { "CMOVG32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(79<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #95 = CMOVG32rr
00233   { "CMOVGE16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(77<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #96 = CMOVGE16rm
00234   { "CMOVGE16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(77<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #97 = CMOVGE16rr
00235   { "CMOVGE32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(77<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #98 = CMOVGE32rm
00236   { "CMOVGE32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(77<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #99 = CMOVGE32rr
00237   { "CMOVL16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(76<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #100 = CMOVL16rm
00238   { "CMOVL16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(76<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #101 = CMOVL16rr
00239   { "CMOVL32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(76<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #102 = CMOVL32rm
00240   { "CMOVL32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(76<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #103 = CMOVL32rr
00241   { "CMOVLE16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(78<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #104 = CMOVLE16rm
00242   { "CMOVLE16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(78<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #105 = CMOVLE16rr
00243   { "CMOVLE32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(78<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #106 = CMOVLE32rm
00244   { "CMOVLE32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(78<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #107 = CMOVLE32rr
00245   { "CMOVNE16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(69<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #108 = CMOVNE16rm
00246   { "CMOVNE16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(69<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #109 = CMOVNE16rr
00247   { "CMOVNE32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(69<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #110 = CMOVNE32rm
00248   { "CMOVNE32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(69<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #111 = CMOVNE32rr
00249   { "CMOVNP16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(75<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #112 = CMOVNP16rm
00250   { "CMOVNP16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(75<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #113 = CMOVNP16rr
00251   { "CMOVNP32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(75<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #114 = CMOVNP32rm
00252   { "CMOVNP32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(75<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #115 = CMOVNP32rr
00253   { "CMOVNS16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(73<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #116 = CMOVNS16rm
00254   { "CMOVNS16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(73<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #117 = CMOVNS16rr
00255   { "CMOVNS32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(73<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #118 = CMOVNS32rm
00256   { "CMOVNS32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(73<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #119 = CMOVNS32rr
00257   { "CMOVP16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(74<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #120 = CMOVP16rm
00258   { "CMOVP16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(74<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #121 = CMOVP16rr
00259   { "CMOVP32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(74<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #122 = CMOVP32rm
00260   { "CMOVP32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(74<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #123 = CMOVP32rr
00261   { "CMOVS16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(72<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #124 = CMOVS16rm
00262   { "CMOVS16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(72<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #125 = CMOVS16rr
00263   { "CMOVS32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(72<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #126 = CMOVS32rm
00264   { "CMOVS32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(72<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #127 = CMOVS32rr
00265   { "CMOV_FR32",  4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo26 },  // Inst #128 = CMOV_FR32
00266   { "CMOV_FR64",  4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo27 },  // Inst #129 = CMOV_FR64
00267   { "CMOV_V2F64", 4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #130 = CMOV_V2F64
00268   { "CMOV_V2I64", 4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #131 = CMOV_V2I64
00269   { "CMOV_V4F32", 4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #132 = CMOV_V4F32
00270   { "CMP16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #133 = CMP16mi
00271   { "CMP16mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #134 = CMP16mi8
00272   { "CMP16mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(57<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #135 = CMP16mr
00273   { "CMP16ri",  2, -1, 0, false, 0, 0, 0, 0, 0|23|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo29 },  // Inst #136 = CMP16ri
00274   { "CMP16ri8", 2, -1, 0, false, 0, 0, 0, 0, 0|23|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo29 },  // Inst #137 = CMP16ri8
00275   { "CMP16rm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(59<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #138 = CMP16rm
00276   { "CMP16rr",  2, -1, 0, false, 0, 0, 0, 0, 0|3|(1<<6)|(57<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #139 = CMP16rr
00277   { "CMP32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|31|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #140 = CMP32mi
00278   { "CMP32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #141 = CMP32mi8
00279   { "CMP32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(57<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #142 = CMP32mr
00280   { "CMP32ri",  2, -1, 0, false, 0, 0, 0, 0, 0|23|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo32 },  // Inst #143 = CMP32ri
00281   { "CMP32ri8", 2, -1, 0, false, 0, 0, 0, 0, 0|23|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo32 },  // Inst #144 = CMP32ri8
00282   { "CMP32rm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(59<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #145 = CMP32rm
00283   { "CMP32rr",  2, -1, 0, false, 0, 0, 0, 0, 0|3|(57<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #146 = CMP32rr
00284   { "CMP8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #147 = CMP8mi
00285   { "CMP8mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(56<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #148 = CMP8mr
00286   { "CMP8ri", 2, -1, 0, false, 0, 0, 0, 0, 0|23|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo34 },  // Inst #149 = CMP8ri
00287   { "CMP8rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(58<<17), EmptyImpList, EmptyImpList, OperandInfo35 },  // Inst #150 = CMP8rm
00288   { "CMP8rr", 2, -1, 0, false, 0, 0, 0, 0, 0|3|(56<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #151 = CMP8rr
00289   { "CMPPDrm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #152 = CMPPDrm
00290   { "CMPPDrr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #153 = CMPPDrr
00291   { "CMPPSrm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(1<<11)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #154 = CMPPSrm
00292   { "CMPPSrr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(1<<11)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #155 = CMPPSrr
00293   { "CMPSDrm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo38 },  // Inst #156 = CMPSDrm
00294   { "CMPSDrr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo27 },  // Inst #157 = CMPSDrr
00295   { "CMPSSrm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo39 },  // Inst #158 = CMPSSrm
00296   { "CMPSSrr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo26 },  // Inst #159 = CMPSSrr
00297   { "CVTDQ2PDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(230<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #160 = CVTDQ2PDrm
00298   { "CVTDQ2PDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(230<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #161 = CVTDQ2PDrr
00299   { "CVTDQ2PSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(91<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #162 = CVTDQ2PSrm
00300   { "CVTDQ2PSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(91<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #163 = CVTDQ2PSrr
00301   { "CVTPD2DQrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(230<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #164 = CVTPD2DQrm
00302   { "CVTPD2DQrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(230<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #165 = CVTPD2DQrr
00303   { "CVTPD2PIrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo42 },  // Inst #166 = CVTPD2PIrm
00304   { "CVTPD2PIrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo43 },  // Inst #167 = CVTPD2PIrr
00305   { "CVTPD2PSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #168 = CVTPD2PSrm
00306   { "CVTPD2PSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #169 = CVTPD2PSrr
00307   { "CVTPI2PDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #170 = CVTPI2PDrm
00308   { "CVTPI2PDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo44 },  // Inst #171 = CVTPI2PDrr
00309   { "CVTPI2PSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #172 = CVTPI2PSrm
00310   { "CVTPI2PSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo44 },  // Inst #173 = CVTPI2PSrr
00311   { "CVTPS2DQrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(91<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #174 = CVTPS2DQrm
00312   { "CVTPS2DQrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(91<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #175 = CVTPS2DQrr
00313   { "CVTPS2PDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #176 = CVTPS2PDrm
00314   { "CVTPS2PDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #177 = CVTPS2PDrr
00315   { "CVTPS2PIrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo42 },  // Inst #178 = CVTPS2PIrm
00316   { "CVTPS2PIrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo43 },  // Inst #179 = CVTPS2PIrr
00317   { "CVTSD2SIrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #180 = CVTSD2SIrm
00318   { "CVTSD2SIrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #181 = CVTSD2SIrr
00319   { "CVTSD2SSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #182 = CVTSD2SSrm
00320   { "CVTSD2SSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo47 },  // Inst #183 = CVTSD2SSrr
00321   { "CVTSI2SDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo48 },  // Inst #184 = CVTSI2SDrm
00322   { "CVTSI2SDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo49 },  // Inst #185 = CVTSI2SDrr
00323   { "CVTSI2SSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #186 = CVTSI2SSrm
00324   { "CVTSI2SSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo50 },  // Inst #187 = CVTSI2SSrr
00325   { "CVTSS2SDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo48 },  // Inst #188 = CVTSS2SDrm
00326   { "CVTSS2SDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo51 },  // Inst #189 = CVTSS2SDrr
00327   { "CVTSS2SIrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #190 = CVTSS2SIrm
00328   { "CVTSS2SIrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(45<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #191 = CVTSS2SIrr
00329   { "CVTTPD2DQrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(230<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #192 = CVTTPD2DQrm
00330   { "CVTTPD2DQrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(230<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #193 = CVTTPD2DQrr
00331   { "CVTTPS2DQrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(91<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #194 = CVTTPS2DQrm
00332   { "CVTTPS2DQrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(91<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #195 = CVTTPS2DQrr
00333   { "CVTTPS2PIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo42 },  // Inst #196 = CVTTPS2PIrm
00334   { "CVTTPS2PIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo43 },  // Inst #197 = CVTTPS2PIrr
00335   { "CVTTSD2SIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #198 = CVTTSD2SIrm
00336   { "CVTTSD2SIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo52 },  // Inst #199 = CVTTSD2SIrr
00337   { "CVTTSS2SIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #200 = CVTTSS2SIrm
00338   { "CVTTSS2SIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo53 },  // Inst #201 = CVTTSS2SIrr
00339   { "CWD",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(153<<17), ImplicitList6, ImplicitList7, 0 },  // Inst #202 = CWD
00340   { "DEC16m", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<6)|(255<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #203 = DEC16m
00341   { "DEC16r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|17|(1<<6)|(255<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #204 = DEC16r
00342   { "DEC32m", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(255<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #205 = DEC32m
00343   { "DEC32r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|17|(255<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #206 = DEC32r
00344   { "DEC8m",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(254<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #207 = DEC8m
00345   { "DEC8r",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(254<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #208 = DEC8r
00346   { "DIV16m", 4, -1, 0, false, 0, 0, 0, 0, 0|30|(1<<6)|(247<<17), ImplicitList8, ImplicitList8, OperandInfo24 },  // Inst #209 = DIV16m
00347   { "DIV16r", 1, -1, 0, false, 0, 0, 0, 0, 0|22|(1<<6)|(247<<17), ImplicitList8, ImplicitList8, OperandInfo54 },  // Inst #210 = DIV16r
00348   { "DIV32m", 4, -1, 0, false, 0, 0, 0, 0, 0|30|(247<<17), ImplicitList9, ImplicitList9, OperandInfo24 },  // Inst #211 = DIV32m
00349   { "DIV32r", 1, -1, 0, false, 0, 0, 0, 0, 0|22|(247<<17), ImplicitList9, ImplicitList9, OperandInfo25 },  // Inst #212 = DIV32r
00350   { "DIV8m",  4, -1, 0, false, 0, 0, 0, 0, 0|30|(246<<17), ImplicitList6, ImplicitList6, OperandInfo24 },  // Inst #213 = DIV8m
00351   { "DIV8r",  1, -1, 0, false, 0, 0, 0, 0, 0|22|(246<<17), ImplicitList6, ImplicitList6, OperandInfo55 },  // Inst #214 = DIV8r
00352   { "DIVPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #215 = DIVPDrm
00353   { "DIVPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #216 = DIVPDrr
00354   { "DIVPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #217 = DIVPSrm
00355   { "DIVPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #218 = DIVPSrr
00356   { "DIVSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #219 = DIVSDrm
00357   { "DIVSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #220 = DIVSDrr
00358   { "DIVSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #221 = DIVSSrm
00359   { "DIVSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #222 = DIVSSrr
00360   { "DWARF_LABEL",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #223 = DWARF_LABEL
00361   { "DWARF_LOC",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo56 },  // Inst #224 = DWARF_LOC
00362   { "FABS", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(225<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #225 = FABS
00363   { "FADD32m",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(216<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #226 = FADD32m
00364   { "FADD64m",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(220<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #227 = FADD64m
00365   { "FADDPrST0",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(9<<7)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #228 = FADDPrST0
00366   { "FADDST0r", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<7)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #229 = FADDST0r
00367   { "FADDrST0", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(7<<7)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #230 = FADDrST0
00368   { "FCHS", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(224<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #231 = FCHS
00369   { "FCMOVB", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(5<<7)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #232 = FCMOVB
00370   { "FCMOVBE",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(5<<7)|(208<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #233 = FCMOVBE
00371   { "FCMOVE", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(5<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #234 = FCMOVE
00372   { "FCMOVNB",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(6<<7)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #235 = FCMOVNB
00373   { "FCMOVNBE", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(6<<7)|(208<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #236 = FCMOVNBE
00374   { "FCMOVNE",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(6<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #237 = FCMOVNE
00375   { "FCMOVNP",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(6<<7)|(216<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #238 = FCMOVNP
00376   { "FCMOVP", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(5<<7)|(216<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #239 = FCMOVP
00377   { "FCOS", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(255<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #240 = FCOS
00378   { "FDIV32m",  4, -1, 0, false, 0, 0, 0, 0, 0|30|(216<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #241 = FDIV32m
00379   { "FDIV64m",  4, -1, 0, false, 0, 0, 0, 0, 0|30|(220<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #242 = FDIV64m
00380   { "FDIVPrST0",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(9<<7)|(248<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #243 = FDIVPrST0
00381   { "FDIVR32m", 4, -1, 0, false, 0, 0, 0, 0, 0|31|(216<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #244 = FDIVR32m
00382   { "FDIVR64m", 4, -1, 0, false, 0, 0, 0, 0, 0|31|(220<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #245 = FDIVR64m
00383   { "FDIVRPrST0", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(9<<7)|(240<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #246 = FDIVRPrST0
00384   { "FDIVRST0r",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<7)|(248<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #247 = FDIVRST0r
00385   { "FDIVRrST0",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(7<<7)|(240<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #248 = FDIVRrST0
00386   { "FDIVST0r", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<7)|(240<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #249 = FDIVST0r
00387   { "FDIVrST0", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(7<<7)|(248<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #250 = FDIVrST0
00388   { "FIADD16m", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(222<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #251 = FIADD16m
00389   { "FIADD32m", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(218<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #252 = FIADD32m
00390   { "FIDIV16m", 4, -1, 0, false, 0, 0, 0, 0, 0|30|(222<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #253 = FIDIV16m
00391   { "FIDIV32m", 4, -1, 0, false, 0, 0, 0, 0, 0|30|(218<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #254 = FIDIV32m
00392   { "FIDIVR16m",  4, -1, 0, false, 0, 0, 0, 0, 0|31|(222<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #255 = FIDIVR16m
00393   { "FIDIVR32m",  4, -1, 0, false, 0, 0, 0, 0, 0|31|(218<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #256 = FIDIVR32m
00394   { "FILD16m",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(223<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #257 = FILD16m
00395   { "FILD32m",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(219<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #258 = FILD32m
00396   { "FILD64m",  4, -1, 0, false, 0, 0, 0, 0, 0|29|(223<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #259 = FILD64m
00397   { "FIMUL16m", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(222<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #260 = FIMUL16m
00398   { "FIMUL32m", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(218<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #261 = FIMUL32m
00399   { "FIST16m",  4, -1, 0, false, 0, 0, 0, 0, 0|26|(223<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #262 = FIST16m
00400   { "FIST32m",  4, -1, 0, false, 0, 0, 0, 0, 0|26|(219<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #263 = FIST32m
00401   { "FISTP16m", 4, -1, 0, false, 0, 0, 0, 0, 0|27|(223<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #264 = FISTP16m
00402   { "FISTP32m", 4, -1, 0, false, 0, 0, 0, 0, 0|27|(219<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #265 = FISTP32m
00403   { "FISTP64m", 4, -1, 0, false, 0, 0, 0, 0, 0|31|(223<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #266 = FISTP64m
00404   { "FISTTP16m",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(223<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #267 = FISTTP16m
00405   { "FISTTP32m",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(219<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #268 = FISTTP32m
00406   { "FISTTP64m",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(221<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #269 = FISTTP64m
00407   { "FISUB16m", 4, -1, 0, false, 0, 0, 0, 0, 0|28|(222<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #270 = FISUB16m
00408   { "FISUB32m", 4, -1, 0, false, 0, 0, 0, 0, 0|28|(218<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #271 = FISUB32m
00409   { "FISUBR16m",  4, -1, 0, false, 0, 0, 0, 0, 0|29|(222<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #272 = FISUBR16m
00410   { "FISUBR32m",  4, -1, 0, false, 0, 0, 0, 0, 0|29|(218<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #273 = FISUBR32m
00411   { "FLD0", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(238<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #274 = FLD0
00412   { "FLD1", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(232<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #275 = FLD1
00413   { "FLD32m", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(217<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #276 = FLD32m
00414   { "FLD64m", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(221<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #277 = FLD64m
00415   { "FLDCW16m", 4, -1, 0, false, 0, 0, 0, 0, 0|29|(217<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #278 = FLDCW16m
00416   { "FLDrr",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(4<<7)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #279 = FLDrr
00417   { "FMUL32m",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(216<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #280 = FMUL32m
00418   { "FMUL64m",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(220<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #281 = FMUL64m
00419   { "FMULPrST0",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(9<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #282 = FMULPrST0
00420   { "FMULST0r", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #283 = FMULST0r
00421   { "FMULrST0", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(7<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #284 = FMULrST0
00422   { "FNSTCW16m",  4, -1, 0, false, 0, 0, 0, 0, 0|31|(217<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #285 = FNSTCW16m
00423   { "FNSTSW8r", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(10<<7)|(224<<17), EmptyImpList, ImplicitList6, 0 },  // Inst #286 = FNSTSW8r
00424   { "FP_REG_KILL",  0, -1, 0, false, 0, 0, 0, 0|M_TERMINATOR_FLAG, 0, EmptyImpList, ImplicitList10, 0 },  // Inst #287 = FP_REG_KILL
00425   { "FP_TO_INT16_IN_MEM", 5, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #288 = FP_TO_INT16_IN_MEM
00426   { "FP_TO_INT32_IN_MEM", 5, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #289 = FP_TO_INT32_IN_MEM
00427   { "FP_TO_INT64_IN_MEM", 5, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #290 = FP_TO_INT64_IN_MEM
00428   { "FSIN", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(254<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #291 = FSIN
00429   { "FSQRT",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(250<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #292 = FSQRT
00430   { "FST32m", 4, -1, 0, false, 0, 0, 0, 0, 0|26|(217<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #293 = FST32m
00431   { "FST64m", 4, -1, 0, false, 0, 0, 0, 0, 0|26|(221<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #294 = FST64m
00432   { "FSTP32m",  4, -1, 0, false, 0, 0, 0, 0, 0|27|(217<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #295 = FSTP32m
00433   { "FSTP64m",  4, -1, 0, false, 0, 0, 0, 0, 0|27|(221<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #296 = FSTP64m
00434   { "FSTPrr", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(8<<7)|(216<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #297 = FSTPrr
00435   { "FSTrr",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(8<<7)|(208<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #298 = FSTrr
00436   { "FSUB32m",  4, -1, 0, false, 0, 0, 0, 0, 0|28|(216<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #299 = FSUB32m
00437   { "FSUB64m",  4, -1, 0, false, 0, 0, 0, 0, 0|28|(220<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #300 = FSUB64m
00438   { "FSUBPrST0",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(9<<7)|(232<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #301 = FSUBPrST0
00439   { "FSUBR32m", 4, -1, 0, false, 0, 0, 0, 0, 0|29|(216<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #302 = FSUBR32m
00440   { "FSUBR64m", 4, -1, 0, false, 0, 0, 0, 0, 0|29|(220<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #303 = FSUBR64m
00441   { "FSUBRPrST0", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(9<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #304 = FSUBRPrST0
00442   { "FSUBRST0r",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<7)|(232<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #305 = FSUBRST0r
00443   { "FSUBRrST0",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(7<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #306 = FSUBRrST0
00444   { "FSUBST0r", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #307 = FSUBST0r
00445   { "FSUBrST0", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(7<<7)|(232<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #308 = FSUBrST0
00446   { "FTST", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(4<<7)|(228<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #309 = FTST
00447   { "FUCOMIPr", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(10<<7)|(232<<17), ImplicitList11, EmptyImpList, OperandInfo57 },  // Inst #310 = FUCOMIPr
00448   { "FUCOMIr",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(6<<7)|(232<<17), ImplicitList11, EmptyImpList, OperandInfo57 },  // Inst #311 = FUCOMIr
00449   { "FUCOMPPr", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(5<<7)|(233<<17), ImplicitList11, EmptyImpList, 0 },  // Inst #312 = FUCOMPPr
00450   { "FUCOMPr",  1, -1, 0, false, 0, 0, 0, 0, 0|2|(8<<7)|(232<<17), ImplicitList11, EmptyImpList, OperandInfo57 },  // Inst #313 = FUCOMPr
00451   { "FUCOMr", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(8<<7)|(224<<17), ImplicitList11, EmptyImpList, OperandInfo57 },  // Inst #314 = FUCOMr
00452   { "FXCH", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(4<<7)|(200<<17), EmptyImpList, EmptyImpList, OperandInfo57 },  // Inst #315 = FXCH
00453   { "FpABS",  2, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #316 = FpABS
00454   { "FpADD",  3, -1, 0, false, 0, 0, 0, 0, 0|(4<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #317 = FpADD
00455   { "FpADD32m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #318 = FpADD32m
00456   { "FpADD64m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #319 = FpADD64m
00457   { "FpCHS",  2, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #320 = FpCHS
00458   { "FpCMOVB",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #321 = FpCMOVB
00459   { "FpCMOVBE", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #322 = FpCMOVBE
00460   { "FpCMOVE",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #323 = FpCMOVE
00461   { "FpCMOVNB", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #324 = FpCMOVNB
00462   { "FpCMOVNBE",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #325 = FpCMOVNBE
00463   { "FpCMOVNE", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #326 = FpCMOVNE
00464   { "FpCMOVNP", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #327 = FpCMOVNP
00465   { "FpCMOVP",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #328 = FpCMOVP
00466   { "FpCOS",  2, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #329 = FpCOS
00467   { "FpDIV",  3, -1, 0, false, 0, 0, 0, 0, 0|(4<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #330 = FpDIV
00468   { "FpDIV32m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #331 = FpDIV32m
00469   { "FpDIV64m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #332 = FpDIV64m
00470   { "FpDIVR32m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #333 = FpDIVR32m
00471   { "FpDIVR64m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #334 = FpDIVR64m
00472   { "FpGETRESULT",  1, -1, 0, false, 0, 0, 0, 0, 0|(7<<13), EmptyImpList, EmptyImpList, OperandInfo62 },  // Inst #335 = FpGETRESULT
00473   { "FpIADD16m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #336 = FpIADD16m
00474   { "FpIADD32m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #337 = FpIADD32m
00475   { "FpIDIV16m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #338 = FpIDIV16m
00476   { "FpIDIV32m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #339 = FpIDIV32m
00477   { "FpIDIVR16m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #340 = FpIDIVR16m
00478   { "FpIDIVR32m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #341 = FpIDIVR32m
00479   { "FpILD16m", 5, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo63 },  // Inst #342 = FpILD16m
00480   { "FpILD32m", 5, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo63 },  // Inst #343 = FpILD32m
00481   { "FpILD64m", 5, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo63 },  // Inst #344 = FpILD64m
00482   { "FpIMUL16m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #345 = FpIMUL16m
00483   { "FpIMUL32m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #346 = FpIMUL32m
00484   { "FpIST16m", 5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #347 = FpIST16m
00485   { "FpIST32m", 5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #348 = FpIST32m
00486   { "FpIST64m", 5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #349 = FpIST64m
00487   { "FpISTT16m",  5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #350 = FpISTT16m
00488   { "FpISTT32m",  5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #351 = FpISTT32m
00489   { "FpISTT64m",  5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #352 = FpISTT64m
00490   { "FpISUB16m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #353 = FpISUB16m
00491   { "FpISUB32m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #354 = FpISUB32m
00492   { "FpISUBR16m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #355 = FpISUBR16m
00493   { "FpISUBR32m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #356 = FpISUBR32m
00494   { "FpLD0",  1, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo62 },  // Inst #357 = FpLD0
00495   { "FpLD1",  1, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo62 },  // Inst #358 = FpLD1
00496   { "FpLD32m",  5, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo63 },  // Inst #359 = FpLD32m
00497   { "FpLD64m",  5, -1, 0, false, 0, 0, 0, 0, 0|(1<<13), EmptyImpList, EmptyImpList, OperandInfo63 },  // Inst #360 = FpLD64m
00498   { "FpMOV",  2, -1, 0, false, 0, 0, 0, 0, 0|(7<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #361 = FpMOV
00499   { "FpMUL",  3, -1, 0, false, 0, 0, 0, 0, 0|(4<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #362 = FpMUL
00500   { "FpMUL32m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #363 = FpMUL32m
00501   { "FpMUL64m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #364 = FpMUL64m
00502   { "FpSETRESULT",  1, -1, 0, false, 0, 0, 0, 0, 0|(7<<13), EmptyImpList, ImplicitList11, OperandInfo62 },  // Inst #365 = FpSETRESULT
00503   { "FpSIN",  2, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #366 = FpSIN
00504   { "FpSQRT", 2, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #367 = FpSQRT
00505   { "FpST32m",  5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #368 = FpST32m
00506   { "FpST64m",  5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #369 = FpST64m
00507   { "FpSTP32m", 5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #370 = FpSTP32m
00508   { "FpSTP64m", 5, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo58 },  // Inst #371 = FpSTP64m
00509   { "FpSUB",  3, -1, 0, false, 0, 0, 0, 0, 0|(4<<13), EmptyImpList, EmptyImpList, OperandInfo60 },  // Inst #372 = FpSUB
00510   { "FpSUB32m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #373 = FpSUB32m
00511   { "FpSUB64m", 6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #374 = FpSUB64m
00512   { "FpSUBR32m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #375 = FpSUBR32m
00513   { "FpSUBR64m",  6, -1, 0, false, 0, 0, 0, 0, 0|(3<<13), EmptyImpList, EmptyImpList, OperandInfo61 },  // Inst #376 = FpSUBR64m
00514   { "FpTST",  1, -1, 0, false, 0, 0, 0, 0, 0|(2<<13), EmptyImpList, EmptyImpList, OperandInfo62 },  // Inst #377 = FpTST
00515   { "FpUCOMIr", 2, -1, 0, false, 0, 0, 0, 0, 0|(5<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #378 = FpUCOMIr
00516   { "FpUCOMr",  2, -1, 0, false, 0, 0, 0, 0, 0|(5<<13), EmptyImpList, EmptyImpList, OperandInfo59 },  // Inst #379 = FpUCOMr
00517   { "FsANDNPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #380 = FsANDNPDrm
00518   { "FsANDNPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #381 = FsANDNPDrr
00519   { "FsANDNPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #382 = FsANDNPSrm
00520   { "FsANDNPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(85<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #383 = FsANDNPSrr
00521   { "FsANDPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #384 = FsANDPDrm
00522   { "FsANDPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #385 = FsANDPDrr
00523   { "FsANDPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #386 = FsANDPSrm
00524   { "FsANDPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(84<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #387 = FsANDPSrr
00525   { "FsFLD0SD", 1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<6)|(1<<7)|(239<<17), EmptyImpList, EmptyImpList, OperandInfo64 },  // Inst #388 = FsFLD0SD
00526   { "FsFLD0SS", 1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<6)|(1<<7)|(239<<17), EmptyImpList, EmptyImpList, OperandInfo65 },  // Inst #389 = FsFLD0SS
00527   { "FsMOVAPDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo48 },  // Inst #390 = FsMOVAPDrm
00528   { "FsMOVAPDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo66 },  // Inst #391 = FsMOVAPDrr
00529   { "FsMOVAPSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #392 = FsMOVAPSrm
00530   { "FsMOVAPSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo67 },  // Inst #393 = FsMOVAPSrr
00531   { "FsORPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #394 = FsORPDrm
00532   { "FsORPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #395 = FsORPDrr
00533   { "FsORPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #396 = FsORPSrm
00534   { "FsORPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #397 = FsORPSrr
00535   { "FsXORPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #398 = FsXORPDrm
00536   { "FsXORPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #399 = FsXORPDrr
00537   { "FsXORPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #400 = FsXORPSrm
00538   { "FsXORPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #401 = FsXORPSrr
00539   { "HADDPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #402 = HADDPDrm
00540   { "HADDPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #403 = HADDPDrr
00541   { "HADDPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #404 = HADDPSrm
00542   { "HADDPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #405 = HADDPSrr
00543   { "HSUBPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #406 = HSUBPDrm
00544   { "HSUBPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #407 = HSUBPDrr
00545   { "HSUBPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #408 = HSUBPSrm
00546   { "HSUBPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(124<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #409 = HSUBPSrr
00547   { "IDIV16m",  4, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<6)|(247<<17), ImplicitList8, ImplicitList8, OperandInfo24 },  // Inst #410 = IDIV16m
00548   { "IDIV16r",  1, -1, 0, false, 0, 0, 0, 0, 0|23|(1<<6)|(247<<17), ImplicitList8, ImplicitList8, OperandInfo54 },  // Inst #411 = IDIV16r
00549   { "IDIV32m",  4, -1, 0, false, 0, 0, 0, 0, 0|31|(247<<17), ImplicitList9, ImplicitList9, OperandInfo24 },  // Inst #412 = IDIV32m
00550   { "IDIV32r",  1, -1, 0, false, 0, 0, 0, 0, 0|23|(247<<17), ImplicitList9, ImplicitList9, OperandInfo25 },  // Inst #413 = IDIV32r
00551   { "IDIV8m", 4, -1, 0, false, 0, 0, 0, 0, 0|31|(246<<17), ImplicitList6, ImplicitList6, OperandInfo24 },  // Inst #414 = IDIV8m
00552   { "IDIV8r", 1, -1, 0, false, 0, 0, 0, 0, 0|23|(246<<17), ImplicitList6, ImplicitList6, OperandInfo55 },  // Inst #415 = IDIV8r
00553   { "IMPLICIT_DEF", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #416 = IMPLICIT_DEF
00554   { "IMPLICIT_DEF_FR32",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo65 },  // Inst #417 = IMPLICIT_DEF_FR32
00555   { "IMPLICIT_DEF_FR64",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo64 },  // Inst #418 = IMPLICIT_DEF_FR64
00556   { "IMPLICIT_DEF_R16", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo54 },  // Inst #419 = IMPLICIT_DEF_R16
00557   { "IMPLICIT_DEF_R32", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo25 },  // Inst #420 = IMPLICIT_DEF_R32
00558   { "IMPLICIT_DEF_R8",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #421 = IMPLICIT_DEF_R8
00559   { "IMPLICIT_DEF_VR128", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo68 },  // Inst #422 = IMPLICIT_DEF_VR128
00560   { "IMPLICIT_DEF_VR64",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo69 },  // Inst #423 = IMPLICIT_DEF_VR64
00561   { "IMPLICIT_USE", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #424 = IMPLICIT_USE
00562   { "IMUL16m",  4, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<6)|(247<<17), ImplicitList6, ImplicitList8, OperandInfo24 },  // Inst #425 = IMUL16m
00563   { "IMUL16r",  1, -1, 0, false, 0, 0, 0, 0, 0|21|(1<<6)|(247<<17), ImplicitList6, ImplicitList8, OperandInfo54 },  // Inst #426 = IMUL16r
00564   { "IMUL16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(175<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #427 = IMUL16rm
00565   { "IMUL16rmi",  6, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(2<<11)|(105<<17), EmptyImpList, EmptyImpList, OperandInfo70 },  // Inst #428 = IMUL16rmi
00566   { "IMUL16rmi8", 6, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<11)|(107<<17), EmptyImpList, EmptyImpList, OperandInfo70 },  // Inst #429 = IMUL16rmi8
00567   { "IMUL16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(175<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #430 = IMUL16rr
00568   { "IMUL16rri",  3, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(2<<11)|(105<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #431 = IMUL16rri
00569   { "IMUL16rri8", 3, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<11)|(107<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #432 = IMUL16rri8
00570   { "IMUL32m",  4, -1, 0, false, 0, 0, 0, 0, 0|29|(247<<17), ImplicitList4, ImplicitList9, OperandInfo24 },  // Inst #433 = IMUL32m
00571   { "IMUL32r",  1, -1, 0, false, 0, 0, 0, 0, 0|21|(247<<17), ImplicitList4, ImplicitList9, OperandInfo25 },  // Inst #434 = IMUL32r
00572   { "IMUL32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(175<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #435 = IMUL32rm
00573   { "IMUL32rmi",  6, -1, 0, false, 0, 0, 0, 0, 0|6|(3<<11)|(105<<17), EmptyImpList, EmptyImpList, OperandInfo71 },  // Inst #436 = IMUL32rmi
00574   { "IMUL32rmi8", 6, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<11)|(107<<17), EmptyImpList, EmptyImpList, OperandInfo71 },  // Inst #437 = IMUL32rmi8
00575   { "IMUL32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(175<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #438 = IMUL32rr
00576   { "IMUL32rri",  3, -1, 0, false, 0, 0, 0, 0, 0|5|(3<<11)|(105<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #439 = IMUL32rri
00577   { "IMUL32rri8", 3, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<11)|(107<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #440 = IMUL32rri8
00578   { "IMUL8m", 4, -1, 0, false, 0, 0, 0, 0, 0|29|(246<<17), ImplicitList2, ImplicitList6, OperandInfo24 },  // Inst #441 = IMUL8m
00579   { "IMUL8r", 1, -1, 0, false, 0, 0, 0, 0, 0|21|(246<<17), ImplicitList2, ImplicitList6, OperandInfo55 },  // Inst #442 = IMUL8r
00580   { "IN16ri", 1, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(1<<11)|(229<<17), EmptyImpList, ImplicitList6, OperandInfo21 },  // Inst #443 = IN16ri
00581   { "IN16rr", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(237<<17), ImplicitList7, ImplicitList6, 0 },  // Inst #444 = IN16rr
00582   { "IN32ri", 1, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<11)|(229<<17), EmptyImpList, ImplicitList4, OperandInfo21 },  // Inst #445 = IN32ri
00583   { "IN32rr", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(237<<17), ImplicitList7, ImplicitList4, 0 },  // Inst #446 = IN32rr
00584   { "IN8ri",  1, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<11)|(228<<17), EmptyImpList, ImplicitList2, OperandInfo21 },  // Inst #447 = IN8ri
00585   { "IN8rr",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(236<<17), ImplicitList7, ImplicitList2, 0 },  // Inst #448 = IN8rr
00586   { "INC16m", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(255<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #449 = INC16m
00587   { "INC16r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(1<<6)|(255<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #450 = INC16r
00588   { "INC32m", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(255<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #451 = INC32m
00589   { "INC32r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|16|(255<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #452 = INC32r
00590   { "INC8m",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(254<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #453 = INC8m
00591   { "INC8r",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(254<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #454 = INC8r
00592   { "Int_ADDSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #455 = Int_ADDSDrm
00593   { "Int_ADDSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #456 = Int_ADDSDrr
00594   { "Int_ADDSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #457 = Int_ADDSSrm
00595   { "Int_ADDSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(88<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #458 = Int_ADDSSrr
00596   { "Int_CMPSDrm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #459 = Int_CMPSDrm
00597   { "Int_CMPSDrr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #460 = Int_CMPSDrr
00598   { "Int_CMPSSrm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #461 = Int_CMPSSrm
00599   { "Int_CMPSSrr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #462 = Int_CMPSSrr
00600   { "Int_COMISDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(47<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #463 = Int_COMISDrm
00601   { "Int_COMISDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(47<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #464 = Int_COMISDrr
00602   { "Int_COMISSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(47<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #465 = Int_COMISSrm
00603   { "Int_COMISSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(47<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #466 = Int_COMISSrr
00604   { "Int_CVTSD2SSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #467 = Int_CVTSD2SSrm
00605   { "Int_CVTSD2SSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #468 = Int_CVTSD2SSrr
00606   { "Int_CVTSI2SDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #469 = Int_CVTSI2SDrm
00607   { "Int_CVTSI2SDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo72 },  // Inst #470 = Int_CVTSI2SDrr
00608   { "Int_CVTSI2SSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #471 = Int_CVTSI2SSrm
00609   { "Int_CVTSI2SSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(42<<17), EmptyImpList, EmptyImpList, OperandInfo72 },  // Inst #472 = Int_CVTSI2SSrr
00610   { "Int_CVTSS2SDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #473 = Int_CVTSS2SDrm
00611   { "Int_CVTSS2SDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(90<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #474 = Int_CVTSS2SDrr
00612   { "Int_CVTTSD2SIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #475 = Int_CVTTSD2SIrm
00613   { "Int_CVTTSD2SIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #476 = Int_CVTTSD2SIrr
00614   { "Int_CVTTSS2SIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #477 = Int_CVTTSS2SIrm
00615   { "Int_CVTTSS2SIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(44<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #478 = Int_CVTTSS2SIrr
00616   { "Int_DIVSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #479 = Int_DIVSDrm
00617   { "Int_DIVSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #480 = Int_DIVSDrr
00618   { "Int_DIVSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #481 = Int_DIVSSrm
00619   { "Int_DIVSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(94<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #482 = Int_DIVSSrr
00620   { "Int_MAXSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #483 = Int_MAXSDrm
00621   { "Int_MAXSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #484 = Int_MAXSDrr
00622   { "Int_MAXSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #485 = Int_MAXSSrm
00623   { "Int_MAXSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #486 = Int_MAXSSrr
00624   { "Int_MINSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #487 = Int_MINSDrm
00625   { "Int_MINSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #488 = Int_MINSDrr
00626   { "Int_MINSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #489 = Int_MINSSrm
00627   { "Int_MINSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #490 = Int_MINSSrr
00628   { "Int_MULSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #491 = Int_MULSDrm
00629   { "Int_MULSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #492 = Int_MULSDrr
00630   { "Int_MULSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #493 = Int_MULSSrm
00631   { "Int_MULSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #494 = Int_MULSSrr
00632   { "Int_RCPSSm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(83<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #495 = Int_RCPSSm
00633   { "Int_RCPSSr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(83<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #496 = Int_RCPSSr
00634   { "Int_RSQRTSSm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(82<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #497 = Int_RSQRTSSm
00635   { "Int_RSQRTSSr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(82<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #498 = Int_RSQRTSSr
00636   { "Int_SQRTSDm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #499 = Int_SQRTSDm
00637   { "Int_SQRTSDr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #500 = Int_SQRTSDr
00638   { "Int_SQRTSSm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #501 = Int_SQRTSSm
00639   { "Int_SQRTSSr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #502 = Int_SQRTSSr
00640   { "Int_SUBSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #503 = Int_SUBSDrm
00641   { "Int_SUBSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #504 = Int_SUBSDrr
00642   { "Int_SUBSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #505 = Int_SUBSSrm
00643   { "Int_SUBSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #506 = Int_SUBSSrr
00644   { "Int_UCOMISDrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #507 = Int_UCOMISDrm
00645   { "Int_UCOMISDrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #508 = Int_UCOMISDrr
00646   { "Int_UCOMISSrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #509 = Int_UCOMISSrm
00647   { "Int_UCOMISSrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #510 = Int_UCOMISSrr
00648   { "JA", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(135<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #511 = JA
00649   { "JAE",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #512 = JAE
00650   { "JB", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(130<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #513 = JB
00651   { "JBE",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(134<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #514 = JBE
00652   { "JE", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(132<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #515 = JE
00653   { "JG", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(143<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #516 = JG
00654   { "JGE",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(141<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #517 = JGE
00655   { "JL", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(140<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #518 = JL
00656   { "JLE",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(142<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #519 = JLE
00657   { "JMP",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|1|(233<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #520 = JMP
00658   { "JNE",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(133<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #521 = JNE
00659   { "JNO",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #522 = JNO
00660   { "JNP",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(139<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #523 = JNP
00661   { "JNS",  1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(137<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #524 = JNS
00662   { "JO", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #525 = JO
00663   { "JP", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(138<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #526 = JP
00664   { "JS", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|1|(1<<7)|(136<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #527 = JS
00665   { "LAHF", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(159<<17), EmptyImpList, ImplicitList3, 0 },  // Inst #528 = LAHF
00666   { "LDMXCSR",  4, -1, 0, false, 0, 0, 0, 0, 0|26|(1<<7)|(174<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #529 = LDMXCSR
00667   { "LEA16r", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(141<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #530 = LEA16r
00668   { "LEA32r", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(141<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #531 = LEA32r
00669   { "LEAVE",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(201<<17), ImplicitList12, ImplicitList12, 0 },  // Inst #532 = LEAVE
00670   { "MASKMOVDQU", 2, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(1<<7)|(247<<17), ImplicitList13, EmptyImpList, OperandInfo41 },  // Inst #533 = MASKMOVDQU
00671   { "MASKMOVQ", 2, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo73 },  // Inst #534 = MASKMOVQ
00672   { "MAXPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #535 = MAXPDrm
00673   { "MAXPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #536 = MAXPDrr
00674   { "MAXPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #537 = MAXPSrm
00675   { "MAXPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #538 = MAXPSrr
00676   { "MAXSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo74 },  // Inst #539 = MAXSDrm
00677   { "MAXSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo75 },  // Inst #540 = MAXSDrr
00678   { "MAXSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #541 = MAXSSrm
00679   { "MAXSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(95<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #542 = MAXSSrr
00680   { "MINPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #543 = MINPDrm
00681   { "MINPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #544 = MINPDrr
00682   { "MINPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #545 = MINPSrm
00683   { "MINPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #546 = MINPSrr
00684   { "MINSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo74 },  // Inst #547 = MINSDrm
00685   { "MINSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo75 },  // Inst #548 = MINSDrr
00686   { "MINSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #549 = MINSSrm
00687   { "MINSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(93<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #550 = MINSSrr
00688   { "MOV16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(2<<11)|(199<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #551 = MOV16mi
00689   { "MOV16mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(137<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #552 = MOV16mr
00690   { "MOV16r0",  1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<6)|(49<<17), EmptyImpList, EmptyImpList, OperandInfo54 },  // Inst #553 = MOV16r0
00691   { "MOV16ri",  2, -1, 0, false, 0, 0, 0, 0, 0|2|(1<<6)|(2<<11)|(184<<17), EmptyImpList, EmptyImpList, OperandInfo29 },  // Inst #554 = MOV16ri
00692   { "MOV16rm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(139<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #555 = MOV16rm
00693   { "MOV16rr",  2, -1, 0, false, 0, 0, 0, 0, 0|3|(1<<6)|(137<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #556 = MOV16rr
00694   { "MOV32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(3<<11)|(199<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #557 = MOV32mi
00695   { "MOV32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(137<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #558 = MOV32mr
00696   { "MOV32r0",  1, -1, 0, false, 0, 0, 0, 0, 0|32|(49<<17), EmptyImpList, EmptyImpList, OperandInfo25 },  // Inst #559 = MOV32r0
00697   { "MOV32ri",  2, -1, 0, false, 0, 0, 0, 0, 0|2|(3<<11)|(184<<17), EmptyImpList, EmptyImpList, OperandInfo32 },  // Inst #560 = MOV32ri
00698   { "MOV32rm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(139<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #561 = MOV32rm
00699   { "MOV32rr",  2, -1, 0, false, 0, 0, 0, 0, 0|3|(137<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #562 = MOV32rr
00700   { "MOV8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<11)|(198<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #563 = MOV8mi
00701   { "MOV8mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(136<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #564 = MOV8mr
00702   { "MOV8r0", 1, -1, 0, false, 0, 0, 0, 0, 0|32|(48<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #565 = MOV8r0
00703   { "MOV8ri", 2, -1, 0, false, 0, 0, 0, 0, 0|2|(1<<11)|(176<<17), EmptyImpList, EmptyImpList, OperandInfo34 },  // Inst #566 = MOV8ri
00704   { "MOV8rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(138<<17), EmptyImpList, EmptyImpList, OperandInfo35 },  // Inst #567 = MOV8rm
00705   { "MOV8rr", 2, -1, 0, false, 0, 0, 0, 0, 0|3|(136<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #568 = MOV8rr
00706   { "MOVAPDmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(41<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #569 = MOVAPDmr
00707   { "MOVAPDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #570 = MOVAPDrm
00708   { "MOVAPDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #571 = MOVAPDrr
00709   { "MOVAPSmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(41<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #572 = MOVAPSmr
00710   { "MOVAPSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #573 = MOVAPSrm
00711   { "MOVAPSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(40<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #574 = MOVAPSrr
00712   { "MOVD64mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(126<<17), EmptyImpList, EmptyImpList, OperandInfo77 },  // Inst #575 = MOVD64mr
00713   { "MOVD64rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo42 },  // Inst #576 = MOVD64rm
00714   { "MOVD64rr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo78 },  // Inst #577 = MOVD64rr
00715   { "MOVDI2PDIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #578 = MOVDI2PDIrm
00716   { "MOVDI2PDIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo79 },  // Inst #579 = MOVDI2PDIrr
00717   { "MOVDQAmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(127<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #580 = MOVDQAmr
00718   { "MOVDQArm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(111<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #581 = MOVDQArm
00719   { "MOVDQArr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(111<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #582 = MOVDQArr
00720   { "MOVDQUmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(12<<7)|(127<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #583 = MOVDQUmr
00721   { "MOVDQUrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(111<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #584 = MOVDQUrm
00722   { "MOVHLPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(18<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #585 = MOVHLPSrr
00723   { "MOVHPDmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(23<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #586 = MOVHPDmr
00724   { "MOVHPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(22<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #587 = MOVHPDrm
00725   { "MOVHPSmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(23<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #588 = MOVHPSmr
00726   { "MOVHPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(22<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #589 = MOVHPSrm
00727   { "MOVLDI2PDIrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo72 },  // Inst #590 = MOVLDI2PDIrr
00728   { "MOVLHPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(22<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #591 = MOVLHPSrr
00729   { "MOVLPDmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(19<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #592 = MOVLPDmr
00730   { "MOVLPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(18<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #593 = MOVLPDrm
00731   { "MOVLPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #594 = MOVLPDrr
00732   { "MOVLPSmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(19<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #595 = MOVLPSmr
00733   { "MOVLPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(18<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #596 = MOVLPSrm
00734   { "MOVLPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #597 = MOVLPSrr
00735   { "MOVLQ128mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(214<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #598 = MOVLQ128mr
00736   { "MOVLQ128rr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(214<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #599 = MOVLQ128rr
00737   { "MOVLSD2PDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo80 },  // Inst #600 = MOVLSD2PDrr
00738   { "MOVLSS2PSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo81 },  // Inst #601 = MOVLSS2PSrr
00739   { "MOVMSKPDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(80<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #602 = MOVMSKPDrr
00740   { "MOVMSKPSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(80<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #603 = MOVMSKPSrr
00741   { "MOVNTDQmr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(231<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #604 = MOVNTDQmr
00742   { "MOVNTImr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(195<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #605 = MOVNTImr
00743   { "MOVNTPDmr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(43<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #606 = MOVNTPDmr
00744   { "MOVNTPSmr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(43<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #607 = MOVNTPSmr
00745   { "MOVNTQ", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(231<<17), EmptyImpList, EmptyImpList, OperandInfo77 },  // Inst #608 = MOVNTQ
00746   { "MOVPD2SDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo82 },  // Inst #609 = MOVPD2SDrr
00747   { "MOVPDI2DImr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(126<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #610 = MOVPDI2DImr
00748   { "MOVPDI2DIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #611 = MOVPDI2DIrr
00749   { "MOVPS2SSmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(12<<7)|(17<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #612 = MOVPS2SSmr
00750   { "MOVPS2SSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo83 },  // Inst #613 = MOVPS2SSrr
00751   { "MOVQ64mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(127<<17), EmptyImpList, EmptyImpList, OperandInfo77 },  // Inst #614 = MOVQ64mr
00752   { "MOVQ64rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(111<<17), EmptyImpList, EmptyImpList, OperandInfo42 },  // Inst #615 = MOVQ64rm
00753   { "MOVQ64rr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(111<<17), EmptyImpList, EmptyImpList, OperandInfo73 },  // Inst #616 = MOVQ64rr
00754   { "MOVQI2PQIrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(126<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #617 = MOVQI2PQIrm
00755   { "MOVQI2PQIrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(126<<17), EmptyImpList, EmptyImpList, OperandInfo44 },  // Inst #618 = MOVQI2PQIrr
00756   { "MOVSD2PDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #619 = MOVSD2PDrm
00757   { "MOVSD2PDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo84 },  // Inst #620 = MOVSD2PDrr
00758   { "MOVSDmr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(11<<7)|(17<<17), EmptyImpList, EmptyImpList, OperandInfo85 },  // Inst #621 = MOVSDmr
00759   { "MOVSDrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo48 },  // Inst #622 = MOVSDrm
00760   { "MOVSDrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo66 },  // Inst #623 = MOVSDrr
00761   { "MOVSS2PSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #624 = MOVSS2PSrm
00762   { "MOVSS2PSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo86 },  // Inst #625 = MOVSS2PSrr
00763   { "MOVSSmr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(12<<7)|(17<<17), EmptyImpList, EmptyImpList, OperandInfo87 },  // Inst #626 = MOVSSmr
00764   { "MOVSSrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #627 = MOVSSrm
00765   { "MOVSSrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo67 },  // Inst #628 = MOVSSrr
00766   { "MOVSX16rm8", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(190<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #629 = MOVSX16rm8
00767   { "MOVSX16rr8", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(190<<17), EmptyImpList, EmptyImpList, OperandInfo88 },  // Inst #630 = MOVSX16rr8
00768   { "MOVSX32rm16",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(191<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #631 = MOVSX32rm16
00769   { "MOVSX32rm8", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(190<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #632 = MOVSX32rm8
00770   { "MOVSX32rr16",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(191<<17), EmptyImpList, EmptyImpList, OperandInfo89 },  // Inst #633 = MOVSX32rr16
00771   { "MOVSX32rr8", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(190<<17), EmptyImpList, EmptyImpList, OperandInfo90 },  // Inst #634 = MOVSX32rr8
00772   { "MOVUPDmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(17<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #635 = MOVUPDmr
00773   { "MOVUPDrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #636 = MOVUPDrm
00774   { "MOVUPDrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #637 = MOVUPDrr
00775   { "MOVUPSmr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(17<<17), EmptyImpList, EmptyImpList, OperandInfo76 },  // Inst #638 = MOVUPSmr
00776   { "MOVUPSrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #639 = MOVUPSrm
00777   { "MOVUPSrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #640 = MOVUPSrr
00778   { "MOVZDI2PDIrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(110<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #641 = MOVZDI2PDIrm
00779   { "MOVZQI2PQIrm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(126<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #642 = MOVZQI2PQIrm
00780   { "MOVZSD2PDrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #643 = MOVZSD2PDrm
00781   { "MOVZSS2PSrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(16<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #644 = MOVZSS2PSrm
00782   { "MOVZX16rm8", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(182<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #645 = MOVZX16rm8
00783   { "MOVZX16rr8", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(182<<17), EmptyImpList, EmptyImpList, OperandInfo88 },  // Inst #646 = MOVZX16rr8
00784   { "MOVZX32rm16",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(183<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #647 = MOVZX32rm16
00785   { "MOVZX32rm8", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(182<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #648 = MOVZX32rm8
00786   { "MOVZX32rr16",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(183<<17), EmptyImpList, EmptyImpList, OperandInfo89 },  // Inst #649 = MOVZX32rr16
00787   { "MOVZX32rr8", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(182<<17), EmptyImpList, EmptyImpList, OperandInfo90 },  // Inst #650 = MOVZX32rr8
00788   { "MUL16m", 4, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<6)|(247<<17), ImplicitList6, ImplicitList8, OperandInfo24 },  // Inst #651 = MUL16m
00789   { "MUL16r", 1, -1, 0, false, 0, 0, 0, 0, 0|20|(1<<6)|(247<<17), ImplicitList6, ImplicitList8, OperandInfo54 },  // Inst #652 = MUL16r
00790   { "MUL32m", 4, -1, 0, false, 0, 0, 0, 0, 0|28|(247<<17), ImplicitList4, ImplicitList9, OperandInfo24 },  // Inst #653 = MUL32m
00791   { "MUL32r", 1, -1, 0, false, 0, 0, 0, 0, 0|20|(247<<17), ImplicitList4, ImplicitList9, OperandInfo25 },  // Inst #654 = MUL32r
00792   { "MUL8m",  4, -1, 0, false, 0, 0, 0, 0, 0|28|(246<<17), ImplicitList2, ImplicitList6, OperandInfo24 },  // Inst #655 = MUL8m
00793   { "MUL8r",  1, -1, 0, false, 0, 0, 0, 0, 0|20|(246<<17), ImplicitList2, ImplicitList6, OperandInfo55 },  // Inst #656 = MUL8r
00794   { "MULPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #657 = MULPDrm
00795   { "MULPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #658 = MULPDrr
00796   { "MULPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #659 = MULPSrm
00797   { "MULPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #660 = MULPSrr
00798   { "MULSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #661 = MULSDrm
00799   { "MULSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(11<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #662 = MULSDrr
00800   { "MULSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #663 = MULSSrm
00801   { "MULSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(12<<7)|(89<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #664 = MULSSrr
00802   { "MovePCtoStack",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #665 = MovePCtoStack
00803   { "NEG16m", 4, -1, 0, false, 0, 0, 0, 0, 0|27|(1<<6)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #666 = NEG16m
00804   { "NEG16r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|19|(1<<6)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #667 = NEG16r
00805   { "NEG32m", 4, -1, 0, false, 0, 0, 0, 0, 0|27|(247<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #668 = NEG32m
00806   { "NEG32r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|19|(247<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #669 = NEG32r
00807   { "NEG8m",  4, -1, 0, false, 0, 0, 0, 0, 0|27|(246<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #670 = NEG8m
00808   { "NEG8r",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|19|(246<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #671 = NEG8r
00809   { "NOOP", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(144<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #672 = NOOP
00810   { "NOT16m", 4, -1, 0, false, 0, 0, 0, 0, 0|26|(1<<6)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #673 = NOT16m
00811   { "NOT16r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|18|(1<<6)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #674 = NOT16r
00812   { "NOT32m", 4, -1, 0, false, 0, 0, 0, 0, 0|26|(247<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #675 = NOT32m
00813   { "NOT32r", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|18|(247<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #676 = NOT32r
00814   { "NOT8m",  4, -1, 0, false, 0, 0, 0, 0, 0|26|(246<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #677 = NOT8m
00815   { "NOT8r",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|18|(246<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #678 = NOT8r
00816   { "OR16mi", 5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #679 = OR16mi
00817   { "OR16mi8",  5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #680 = OR16mi8
00818   { "OR16mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(9<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #681 = OR16mr
00819   { "OR16ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #682 = OR16ri
00820   { "OR16ri8",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #683 = OR16ri8
00821   { "OR16rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(11<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #684 = OR16rm
00822   { "OR16rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(9<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #685 = OR16rr
00823   { "OR32mi", 5, -1, 0, false, 0, 0, 0, 0, 0|25|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #686 = OR32mi
00824   { "OR32mi8",  5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #687 = OR32mi8
00825   { "OR32mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(9<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #688 = OR32mr
00826   { "OR32ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #689 = OR32ri
00827   { "OR32ri8",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #690 = OR32ri8
00828   { "OR32rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #691 = OR32rm
00829   { "OR32rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(9<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #692 = OR32rr
00830   { "OR8mi",  5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #693 = OR8mi
00831   { "OR8mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(8<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #694 = OR8mr
00832   { "OR8ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #695 = OR8ri
00833   { "OR8rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(10<<17), EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #696 = OR8rm
00834   { "OR8rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(8<<17), EmptyImpList, EmptyImpList, OperandInfo14 },  // Inst #697 = OR8rr
00835   { "ORPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #698 = ORPDrm
00836   { "ORPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #699 = ORPDrr
00837   { "ORPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #700 = ORPSrm
00838   { "ORPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(86<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #701 = ORPSrr
00839   { "OUT16ir",  1, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(1<<11)|(231<<17), ImplicitList6, EmptyImpList, OperandInfo21 },  // Inst #702 = OUT16ir
00840   { "OUT16rr",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(239<<17), ImplicitList14, EmptyImpList, 0 },  // Inst #703 = OUT16rr
00841   { "OUT32ir",  1, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<11)|(231<<17), ImplicitList4, EmptyImpList, OperandInfo21 },  // Inst #704 = OUT32ir
00842   { "OUT32rr",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(239<<17), ImplicitList15, EmptyImpList, 0 },  // Inst #705 = OUT32rr
00843   { "OUT8ir", 1, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<11)|(230<<17), ImplicitList2, EmptyImpList, OperandInfo21 },  // Inst #706 = OUT8ir
00844   { "OUT8rr", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(238<<17), ImplicitList16, EmptyImpList, 0 },  // Inst #707 = OUT8rr
00845   { "PACKSSDWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(107<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #708 = PACKSSDWrm
00846   { "PACKSSDWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(107<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #709 = PACKSSDWrr
00847   { "PACKSSWBrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(99<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #710 = PACKSSWBrm
00848   { "PACKSSWBrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(99<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #711 = PACKSSWBrr
00849   { "PACKUSWBrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(103<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #712 = PACKUSWBrm
00850   { "PACKUSWBrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(103<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #713 = PACKUSWBrr
00851   { "PADDBrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(252<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #714 = PADDBrm
00852   { "PADDBrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(252<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #715 = PADDBrr
00853   { "PADDDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(254<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #716 = PADDDrm
00854   { "PADDDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(254<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #717 = PADDDrr
00855   { "PADDQrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(212<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #718 = PADDQrm
00856   { "PADDQrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(212<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #719 = PADDQrr
00857   { "PADDSBrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(236<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #720 = PADDSBrm
00858   { "PADDSBrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(236<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #721 = PADDSBrr
00859   { "PADDSWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(237<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #722 = PADDSWrm
00860   { "PADDSWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(237<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #723 = PADDSWrr
00861   { "PADDUSBrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(220<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #724 = PADDUSBrm
00862   { "PADDUSBrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(220<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #725 = PADDUSBrr
00863   { "PADDUSWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(221<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #726 = PADDUSWrm
00864   { "PADDUSWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(221<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #727 = PADDUSWrr
00865   { "PADDWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(253<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #728 = PADDWrm
00866   { "PADDWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(253<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #729 = PADDWrr
00867   { "PANDNrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(223<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #730 = PANDNrm
00868   { "PANDNrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(223<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #731 = PANDNrr
00869   { "PANDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(219<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #732 = PANDrm
00870   { "PANDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(219<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #733 = PANDrr
00871   { "PAVGBrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #734 = PAVGBrm
00872   { "PAVGBrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #735 = PAVGBrr
00873   { "PAVGWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(227<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #736 = PAVGWrm
00874   { "PAVGWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(227<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #737 = PAVGWrr
00875   { "PEXTRWm",  6, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(1<<11)|(197<<17), EmptyImpList, EmptyImpList, OperandInfo71 },  // Inst #738 = PEXTRWm
00876   { "PEXTRWr",  3, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(1<<11)|(197<<17), EmptyImpList, EmptyImpList, OperandInfo91 },  // Inst #739 = PEXTRWr
00877   { "PINSRWm",  7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(196<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #740 = PINSRWm
00878   { "PINSRWr",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(196<<17), EmptyImpList, EmptyImpList, OperandInfo92 },  // Inst #741 = PINSRWr
00879   { "PMADDWDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(245<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #742 = PMADDWDrm
00880   { "PMADDWDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(245<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #743 = PMADDWDrr
00881   { "PMAXSWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(238<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #744 = PMAXSWrm
00882   { "PMAXSWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(238<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #745 = PMAXSWrr
00883   { "PMAXUBrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(222<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #746 = PMAXUBrm
00884   { "PMAXUBrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(222<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #747 = PMAXUBrr
00885   { "PMINSWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(234<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #748 = PMINSWrm
00886   { "PMINSWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(234<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #749 = PMINSWrr
00887   { "PMINUBrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(218<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #750 = PMINUBrm
00888   { "PMINUBrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(218<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #751 = PMINUBrr
00889   { "PMOVMSKBrr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(215<<17), EmptyImpList, EmptyImpList, OperandInfo45 },  // Inst #752 = PMOVMSKBrr
00890   { "PMULHUWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(228<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #753 = PMULHUWrm
00891   { "PMULHUWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(228<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #754 = PMULHUWrr
00892   { "PMULHWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(229<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #755 = PMULHWrm
00893   { "PMULHWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(229<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #756 = PMULHWrr
00894   { "PMULLWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(213<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #757 = PMULLWrm
00895   { "PMULLWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(213<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #758 = PMULLWrr
00896   { "PMULUDQrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(244<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #759 = PMULUDQrm
00897   { "PMULUDQrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(244<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #760 = PMULUDQrr
00898   { "POP32r", 1, -1, 0, false, 0, 0, 0, 0, 0|2|(88<<17), ImplicitList17, ImplicitList17, OperandInfo25 },  // Inst #761 = POP32r
00899   { "PORrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(235<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #762 = PORrm
00900   { "PORrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(235<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #763 = PORrr
00901   { "PREFETCHT0", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<7)|(24<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #764 = PREFETCHT0
00902   { "PREFETCHT1", 4, -1, 0, false, 0, 0, 0, 0, 0|26|(1<<7)|(24<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #765 = PREFETCHT1
00903   { "PREFETCHT2", 4, -1, 0, false, 0, 0, 0, 0, 0|27|(1<<7)|(24<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #766 = PREFETCHT2
00904   { "PREFETCHTNTA", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(24<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #767 = PREFETCHTNTA
00905   { "PSADBWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #768 = PSADBWrm
00906   { "PSADBWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(224<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #769 = PSADBWrr
00907   { "PSHUFDmi", 6, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo93 },  // Inst #770 = PSHUFDmi
00908   { "PSHUFDri", 3, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo94 },  // Inst #771 = PSHUFDri
00909   { "PSHUFHWmi",  6, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo93 },  // Inst #772 = PSHUFHWmi
00910   { "PSHUFHWri",  3, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo94 },  // Inst #773 = PSHUFHWri
00911   { "PSHUFLWmi",  6, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo93 },  // Inst #774 = PSHUFLWmi
00912   { "PSHUFLWri",  3, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo94 },  // Inst #775 = PSHUFLWri
00913   { "PSHUFWmi", 6, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo95 },  // Inst #776 = PSHUFWmi
00914   { "PSHUFWri", 3, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(1<<11)|(112<<17), EmptyImpList, EmptyImpList, OperandInfo96 },  // Inst #777 = PSHUFWri
00915   { "PSLLDQri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(1<<7)|(1<<11)|(115<<17), EmptyImpList, EmptyImpList, OperandInfo94 },  // Inst #778 = PSLLDQri
00916   { "PSRLDQri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(1<<7)|(1<<11)|(115<<17), EmptyImpList, EmptyImpList, OperandInfo94 },  // Inst #779 = PSRLDQri
00917   { "PSUBBrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(248<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #780 = PSUBBrm
00918   { "PSUBBrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(248<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #781 = PSUBBrr
00919   { "PSUBDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(250<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #782 = PSUBDrm
00920   { "PSUBDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(250<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #783 = PSUBDrr
00921   { "PSUBQrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(251<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #784 = PSUBQrm
00922   { "PSUBQrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(251<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #785 = PSUBQrr
00923   { "PSUBSBrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(232<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #786 = PSUBSBrm
00924   { "PSUBSBrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(232<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #787 = PSUBSBrr
00925   { "PSUBSWrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(233<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #788 = PSUBSWrm
00926   { "PSUBSWrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(233<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #789 = PSUBSWrr
00927   { "PSUBUSBrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(216<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #790 = PSUBUSBrm
00928   { "PSUBUSBrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(216<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #791 = PSUBUSBrr
00929   { "PSUBUSWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(217<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #792 = PSUBUSWrm
00930   { "PSUBUSWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(217<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #793 = PSUBUSWrr
00931   { "PSUBWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(249<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #794 = PSUBWrm
00932   { "PSUBWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(249<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #795 = PSUBWrr
00933   { "PUNPCKHBWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(104<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #796 = PUNPCKHBWrm
00934   { "PUNPCKHBWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(104<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #797 = PUNPCKHBWrr
00935   { "PUNPCKHDQrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(106<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #798 = PUNPCKHDQrm
00936   { "PUNPCKHDQrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(106<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #799 = PUNPCKHDQrr
00937   { "PUNPCKHQDQrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(109<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #800 = PUNPCKHQDQrm
00938   { "PUNPCKHQDQrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(109<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #801 = PUNPCKHQDQrr
00939   { "PUNPCKHWDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(105<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #802 = PUNPCKHWDrm
00940   { "PUNPCKHWDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(105<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #803 = PUNPCKHWDrr
00941   { "PUNPCKLBWrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(96<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #804 = PUNPCKLBWrm
00942   { "PUNPCKLBWrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(96<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #805 = PUNPCKLBWrr
00943   { "PUNPCKLDQrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(98<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #806 = PUNPCKLDQrm
00944   { "PUNPCKLDQrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(98<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #807 = PUNPCKLDQrr
00945   { "PUNPCKLQDQrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(108<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #808 = PUNPCKLQDQrm
00946   { "PUNPCKLQDQrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(108<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #809 = PUNPCKLQDQrr
00947   { "PUNPCKLWDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(97<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #810 = PUNPCKLWDrm
00948   { "PUNPCKLWDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(97<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #811 = PUNPCKLWDrr
00949   { "PXORrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(239<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #812 = PXORrm
00950   { "PXORrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(239<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #813 = PXORrr
00951   { "RCPPSm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(83<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #814 = RCPPSm
00952   { "RCPPSr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(83<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #815 = RCPPSr
00953   { "RCPSSm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(83<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #816 = RCPSSm
00954   { "RCPSSr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(83<<17), EmptyImpList, EmptyImpList, OperandInfo67 },  // Inst #817 = RCPSSr
00955   { "RDTSC",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<7)|(49<<17), EmptyImpList, ImplicitList9, 0 },  // Inst #818 = RDTSC
00956   { "REP_MOVSB",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(2<<7)|(164<<17), ImplicitList18, ImplicitList18, 0 },  // Inst #819 = REP_MOVSB
00957   { "REP_MOVSD",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(2<<7)|(165<<17), ImplicitList18, ImplicitList18, 0 },  // Inst #820 = REP_MOVSD
00958   { "REP_MOVSW",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(2<<7)|(165<<17), ImplicitList18, ImplicitList18, 0 },  // Inst #821 = REP_MOVSW
00959   { "REP_STOSB",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(2<<7)|(170<<17), ImplicitList19, ImplicitList20, 0 },  // Inst #822 = REP_STOSB
00960   { "REP_STOSD",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(2<<7)|(171<<17), ImplicitList21, ImplicitList20, 0 },  // Inst #823 = REP_STOSD
00961   { "REP_STOSW",  0, -1, 0, false, 0, 0, 0, 0, 0|1|(1<<6)|(2<<7)|(171<<17), ImplicitList22, ImplicitList20, 0 },  // Inst #824 = REP_STOSW
00962   { "RET",  0, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|1|(195<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #825 = RET
00963   { "RETI", 1, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|1|(2<<11)|(194<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #826 = RETI
00964   { "ROL16mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #827 = ROL16mCL
00965   { "ROL16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #828 = ROL16mi
00966   { "ROL16rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo31 },  // Inst #829 = ROL16rCL
00967   { "ROL16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #830 = ROL16ri
00968   { "ROL32mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #831 = ROL32mCL
00969   { "ROL32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #832 = ROL32mi
00970   { "ROL32rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(211<<17), ImplicitList23, EmptyImpList, OperandInfo23 },  // Inst #833 = ROL32rCL
00971   { "ROL32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #834 = ROL32ri
00972   { "ROL8mCL",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(210<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #835 = ROL8mCL
00973   { "ROL8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #836 = ROL8mi
00974   { "ROL8rCL",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(210<<17), ImplicitList23, EmptyImpList, OperandInfo36 },  // Inst #837 = ROL8rCL
00975   { "ROL8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|16|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #838 = ROL8ri
00976   { "ROR16mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #839 = ROR16mCL
00977   { "ROR16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #840 = ROR16mi
00978   { "ROR16rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo31 },  // Inst #841 = ROR16rCL
00979   { "ROR16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #842 = ROR16ri
00980   { "ROR32mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|25|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #843 = ROR32mCL
00981   { "ROR32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #844 = ROR32mi
00982   { "ROR32rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(211<<17), ImplicitList23, EmptyImpList, OperandInfo23 },  // Inst #845 = ROR32rCL
00983   { "ROR32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #846 = ROR32ri
00984   { "ROR8mCL",  4, -1, 0, false, 0, 0, 0, 0, 0|25|(210<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #847 = ROR8mCL
00985   { "ROR8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|25|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #848 = ROR8mi
00986   { "ROR8rCL",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(210<<17), ImplicitList23, EmptyImpList, OperandInfo36 },  // Inst #849 = ROR8rCL
00987   { "ROR8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|17|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #850 = ROR8ri
00988   { "RSQRTPSm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(82<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #851 = RSQRTPSm
00989   { "RSQRTPSr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(82<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #852 = RSQRTPSr
00990   { "RSQRTSSm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(82<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #853 = RSQRTSSm
00991   { "RSQRTSSr", 2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(82<<17), EmptyImpList, EmptyImpList, OperandInfo67 },  // Inst #854 = RSQRTSSr
00992   { "SAHF", 0, -1, 0, false, 0, 0, 0, 0, 0|1|(158<<17), ImplicitList3, EmptyImpList, 0 },  // Inst #855 = SAHF
00993   { "SAR16mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #856 = SAR16mCL
00994   { "SAR16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #857 = SAR16mi
00995   { "SAR16rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo31 },  // Inst #858 = SAR16rCL
00996   { "SAR16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #859 = SAR16ri
00997   { "SAR32mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|31|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #860 = SAR32mCL
00998   { "SAR32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #861 = SAR32mi
00999   { "SAR32rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(211<<17), ImplicitList23, EmptyImpList, OperandInfo23 },  // Inst #862 = SAR32rCL
01000   { "SAR32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #863 = SAR32ri
01001   { "SAR8mCL",  4, -1, 0, false, 0, 0, 0, 0, 0|31|(210<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #864 = SAR8mCL
01002   { "SAR8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #865 = SAR8mi
01003   { "SAR8rCL",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(210<<17), ImplicitList23, EmptyImpList, OperandInfo36 },  // Inst #866 = SAR8rCL
01004   { "SAR8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|23|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #867 = SAR8ri
01005   { "SBB32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|27|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #868 = SBB32mi
01006   { "SBB32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|27|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #869 = SBB32mi8
01007   { "SBB32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(25<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #870 = SBB32mr
01008   { "SBB32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|19|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #871 = SBB32ri
01009   { "SBB32ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|19|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #872 = SBB32ri8
01010   { "SBB32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(27<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #873 = SBB32rm
01011   { "SBB32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(25<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #874 = SBB32rr
01012   { "SBB8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|27|(3<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #875 = SBB8mi
01013   { "SETAEm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(147<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #876 = SETAEm
01014   { "SETAEr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(147<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #877 = SETAEr
01015   { "SETAm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(151<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #878 = SETAm
01016   { "SETAr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(151<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #879 = SETAr
01017   { "SETBEm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(150<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #880 = SETBEm
01018   { "SETBEr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(150<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #881 = SETBEr
01019   { "SETBm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(146<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #882 = SETBm
01020   { "SETBr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(146<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #883 = SETBr
01021   { "SETEm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(148<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #884 = SETEm
01022   { "SETEr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(148<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #885 = SETEr
01023   { "SETGEm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(157<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #886 = SETGEm
01024   { "SETGEr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(157<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #887 = SETGEr
01025   { "SETGm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(159<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #888 = SETGm
01026   { "SETGr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(159<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #889 = SETGr
01027   { "SETLEm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(158<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #890 = SETLEm
01028   { "SETLEr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(158<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #891 = SETLEr
01029   { "SETLm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(156<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #892 = SETLm
01030   { "SETLr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(156<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #893 = SETLr
01031   { "SETNEm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(149<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #894 = SETNEm
01032   { "SETNEr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(149<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #895 = SETNEr
01033   { "SETNPm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(155<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #896 = SETNPm
01034   { "SETNPr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(155<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #897 = SETNPr
01035   { "SETNSm", 4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(153<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #898 = SETNSm
01036   { "SETNSr", 1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(153<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #899 = SETNSr
01037   { "SETPm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(154<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #900 = SETPm
01038   { "SETPr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(154<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #901 = SETPr
01039   { "SETSm",  4, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<7)|(152<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #902 = SETSm
01040   { "SETSr",  1, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<7)|(152<<17), EmptyImpList, EmptyImpList, OperandInfo55 },  // Inst #903 = SETSr
01041   { "SFENCE", 0, -1, 0, false, 0, 0, 0, 0, 0|31|(1<<7)|(174<<17), EmptyImpList, EmptyImpList, 0 },  // Inst #904 = SFENCE
01042   { "SHL16mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #905 = SHL16mCL
01043   { "SHL16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #906 = SHL16mi
01044   { "SHL16rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo31 },  // Inst #907 = SHL16rCL
01045   { "SHL16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|20|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #908 = SHL16ri
01046   { "SHL32mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|28|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #909 = SHL32mCL
01047   { "SHL32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #910 = SHL32mi
01048   { "SHL32rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(211<<17), ImplicitList23, EmptyImpList, OperandInfo23 },  // Inst #911 = SHL32rCL
01049   { "SHL32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_CONVERTIBLE_TO_3_ADDR, 0|20|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #912 = SHL32ri
01050   { "SHL8mCL",  4, -1, 0, false, 0, 0, 0, 0, 0|28|(210<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #913 = SHL8mCL
01051   { "SHL8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|28|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #914 = SHL8mi
01052   { "SHL8rCL",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(210<<17), ImplicitList23, EmptyImpList, OperandInfo36 },  // Inst #915 = SHL8rCL
01053   { "SHL8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|20|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #916 = SHL8ri
01054   { "SHLD16mrCL", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(165<<17), ImplicitList23, EmptyImpList, OperandInfo7 },  // Inst #917 = SHLD16mrCL
01055   { "SHLD16mri8", 6, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(1<<11)|(164<<17), EmptyImpList, EmptyImpList, OperandInfo97 },  // Inst #918 = SHLD16mri8
01056   { "SHLD16rrCL", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<6)|(1<<7)|(165<<17), ImplicitList23, EmptyImpList, OperandInfo10 },  // Inst #919 = SHLD16rrCL
01057   { "SHLD16rri8", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(1<<7)|(1<<11)|(164<<17), EmptyImpList, EmptyImpList, OperandInfo98 },  // Inst #920 = SHLD16rri8
01058   { "SHLD32mrCL", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(165<<17), ImplicitList23, EmptyImpList, OperandInfo3 },  // Inst #921 = SHLD32mrCL
01059   { "SHLD32mri8", 6, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(1<<11)|(164<<17), EmptyImpList, EmptyImpList, OperandInfo99 },  // Inst #922 = SHLD32mri8
01060   { "SHLD32rrCL", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<7)|(165<<17), ImplicitList23, EmptyImpList, OperandInfo6 },  // Inst #923 = SHLD32rrCL
01061   { "SHLD32rri8", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<7)|(1<<11)|(164<<17), EmptyImpList, EmptyImpList, OperandInfo100 },  // Inst #924 = SHLD32rri8
01062   { "SHR16mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #925 = SHR16mCL
01063   { "SHR16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #926 = SHR16mi
01064   { "SHR16rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(211<<17), ImplicitList23, EmptyImpList, OperandInfo31 },  // Inst #927 = SHR16rCL
01065   { "SHR16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #928 = SHR16ri
01066   { "SHR32mCL", 4, -1, 0, false, 0, 0, 0, 0, 0|29|(211<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #929 = SHR32mCL
01067   { "SHR32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #930 = SHR32mi
01068   { "SHR32rCL", 2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(211<<17), ImplicitList23, EmptyImpList, OperandInfo23 },  // Inst #931 = SHR32rCL
01069   { "SHR32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(193<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #932 = SHR32ri
01070   { "SHR8mCL",  4, -1, 0, false, 0, 0, 0, 0, 0|29|(210<<17), ImplicitList23, EmptyImpList, OperandInfo24 },  // Inst #933 = SHR8mCL
01071   { "SHR8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #934 = SHR8mi
01072   { "SHR8rCL",  2, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(210<<17), ImplicitList23, EmptyImpList, OperandInfo36 },  // Inst #935 = SHR8rCL
01073   { "SHR8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(192<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #936 = SHR8ri
01074   { "SHRD16mrCL", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(173<<17), ImplicitList23, EmptyImpList, OperandInfo7 },  // Inst #937 = SHRD16mrCL
01075   { "SHRD16mri8", 6, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(1<<7)|(1<<11)|(172<<17), EmptyImpList, EmptyImpList, OperandInfo97 },  // Inst #938 = SHRD16mri8
01076   { "SHRD16rrCL", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<6)|(1<<7)|(173<<17), ImplicitList23, EmptyImpList, OperandInfo10 },  // Inst #939 = SHRD16rrCL
01077   { "SHRD16rri8", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(1<<7)|(1<<11)|(172<<17), EmptyImpList, EmptyImpList, OperandInfo98 },  // Inst #940 = SHRD16rri8
01078   { "SHRD32mrCL", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(173<<17), ImplicitList23, EmptyImpList, OperandInfo3 },  // Inst #941 = SHRD32mrCL
01079   { "SHRD32mri8", 6, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<7)|(1<<11)|(172<<17), EmptyImpList, EmptyImpList, OperandInfo99 },  // Inst #942 = SHRD32mri8
01080   { "SHRD32rrCL", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<7)|(173<<17), ImplicitList23, EmptyImpList, OperandInfo6 },  // Inst #943 = SHRD32rrCL
01081   { "SHRD32rri8", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<7)|(1<<11)|(172<<17), EmptyImpList, EmptyImpList, OperandInfo100 },  // Inst #944 = SHRD32rri8
01082   { "SHUFPDrm", 7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(1<<11)|(198<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #945 = SHUFPDrm
01083   { "SHUFPDrr", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(1<<11)|(198<<17), EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #946 = SHUFPDrr
01084   { "SHUFPSrm", 7, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(1<<11)|(198<<17), EmptyImpList, EmptyImpList, OperandInfo37 },  // Inst #947 = SHUFPSrm
01085   { "SHUFPSrr", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(1<<11)|(198<<17), EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #948 = SHUFPSrr
01086   { "SQRTPDm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #949 = SQRTPDm
01087   { "SQRTPDr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #950 = SQRTPDr
01088   { "SQRTPSm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo40 },  // Inst #951 = SQRTPSm
01089   { "SQRTPSr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo41 },  // Inst #952 = SQRTPSr
01090   { "SQRTSDm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(11<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo48 },  // Inst #953 = SQRTSDm
01091   { "SQRTSDr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(11<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo66 },  // Inst #954 = SQRTSDr
01092   { "SQRTSSm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(12<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #955 = SQRTSSm
01093   { "SQRTSSr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(12<<7)|(81<<17), EmptyImpList, EmptyImpList, OperandInfo67 },  // Inst #956 = SQRTSSr
01094   { "STMXCSR",  4, -1, 0, false, 0, 0, 0, 0, 0|27|(1<<7)|(174<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #957 = STMXCSR
01095   { "SUB16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #958 = SUB16mi
01096   { "SUB16mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #959 = SUB16mi8
01097   { "SUB16mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(41<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #960 = SUB16mr
01098   { "SUB16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #961 = SUB16ri
01099   { "SUB16ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #962 = SUB16ri8
01100   { "SUB16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(43<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #963 = SUB16rm
01101   { "SUB16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(1<<6)|(41<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #964 = SUB16rr
01102   { "SUB32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|29|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #965 = SUB32mi
01103   { "SUB32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #966 = SUB32mi8
01104   { "SUB32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(41<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #967 = SUB32mr
01105   { "SUB32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #968 = SUB32ri
01106   { "SUB32ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #969 = SUB32ri8
01107   { "SUB32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(43<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #970 = SUB32rm
01108   { "SUB32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(41<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #971 = SUB32rr
01109   { "SUB8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|29|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #972 = SUB8mi
01110   { "SUB8mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(40<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #973 = SUB8mr
01111   { "SUB8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|21|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #974 = SUB8ri
01112   { "SUB8rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(42<<17), EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #975 = SUB8rm
01113   { "SUB8rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|3|(40<<17), EmptyImpList, EmptyImpList, OperandInfo14 },  // Inst #976 = SUB8rr
01114   { "SUBPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #977 = SUBPDrm
01115   { "SUBPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #978 = SUBPDrr
01116   { "SUBPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #979 = SUBPSrm
01117   { "SUBPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #980 = SUBPSrr
01118   { "SUBSDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(11<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #981 = SUBSDrm
01119   { "SUBSDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(11<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo18 },  // Inst #982 = SUBSDrr
01120   { "SUBSSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(12<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #983 = SUBSSrm
01121   { "SUBSSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(12<<7)|(92<<17), EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #984 = SUBSSrr
01122   { "TAILJMPd", 1, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_BRANCH_FLAG|M_BARRIER_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0|1|(233<<17), EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #985 = TAILJMPd
01123   { "TAILJMPm", 4, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0|28|(255<<17), EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #986 = TAILJMPm
01124   { "TAILJMPr", 1, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0|20|(255<<17), EmptyImpList, EmptyImpList, OperandInfo25 },  // Inst #987 = TAILJMPr
01125   { "TEST16mi", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<6)|(2<<11)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #988 = TEST16mi
01126   { "TEST16mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(133<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #989 = TEST16mr
01127   { "TEST16ri", 2, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<6)|(2<<11)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo29 },  // Inst #990 = TEST16ri
01128   { "TEST16rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(133<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #991 = TEST16rm
01129   { "TEST16rr", 2, -1, 0, false, 0, 0, 0, 0|M_COMMUTABLE, 0|3|(1<<6)|(133<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #992 = TEST16rr
01130   { "TEST32mi", 5, -1, 0, false, 0, 0, 0, 0, 0|24|(3<<11)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #993 = TEST32mi
01131   { "TEST32mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(133<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #994 = TEST32mr
01132   { "TEST32ri", 2, -1, 0, false, 0, 0, 0, 0, 0|16|(3<<11)|(247<<17), EmptyImpList, EmptyImpList, OperandInfo32 },  // Inst #995 = TEST32ri
01133   { "TEST32rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(133<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #996 = TEST32rm
01134   { "TEST32rr", 2, -1, 0, false, 0, 0, 0, 0|M_COMMUTABLE, 0|3|(133<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #997 = TEST32rr
01135   { "TEST8mi",  5, -1, 0, false, 0, 0, 0, 0, 0|24|(1<<11)|(246<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #998 = TEST8mi
01136   { "TEST8mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(132<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #999 = TEST8mr
01137   { "TEST8ri",  2, -1, 0, false, 0, 0, 0, 0, 0|16|(1<<11)|(246<<17), EmptyImpList, EmptyImpList, OperandInfo34 },  // Inst #1000 = TEST8ri
01138   { "TEST8rm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(132<<17), EmptyImpList, EmptyImpList, OperandInfo35 },  // Inst #1001 = TEST8rm
01139   { "TEST8rr",  2, -1, 0, false, 0, 0, 0, 0|M_COMMUTABLE, 0|3|(132<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #1002 = TEST8rr
01140   { "UCOMISDrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo48 },  // Inst #1003 = UCOMISDrm
01141   { "UCOMISDrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<6)|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo66 },  // Inst #1004 = UCOMISDrr
01142   { "UCOMISSrm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo46 },  // Inst #1005 = UCOMISSrm
01143   { "UCOMISSrr",  2, -1, 0, false, 0, 0, 0, 0, 0|5|(1<<7)|(46<<17), EmptyImpList, EmptyImpList, OperandInfo67 },  // Inst #1006 = UCOMISSrr
01144   { "UNPCKHPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(21<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #1007 = UNPCKHPDrm
01145   { "UNPCKHPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(21<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #1008 = UNPCKHPDrr
01146   { "UNPCKHPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(21<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #1009 = UNPCKHPSrm
01147   { "UNPCKHPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(21<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #1010 = UNPCKHPSrr
01148   { "UNPCKLPDrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(20<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #1011 = UNPCKLPDrm
01149   { "UNPCKLPDrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<6)|(1<<7)|(20<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #1012 = UNPCKLPDrr
01150   { "UNPCKLPSrm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(20<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #1013 = UNPCKLPSrm
01151   { "UNPCKLPSrr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|5|(1<<7)|(20<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #1014 = UNPCKLPSrr
01152   { "V_SET0_PD",  1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<6)|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo68 },  // Inst #1015 = V_SET0_PD
01153   { "V_SET0_PI",  1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<6)|(1<<7)|(239<<17), EmptyImpList, EmptyImpList, OperandInfo68 },  // Inst #1016 = V_SET0_PI
01154   { "V_SET0_PS",  1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo68 },  // Inst #1017 = V_SET0_PS
01155   { "V_SETALLONES", 1, -1, 0, false, 0, 0, 0, 0, 0|32|(1<<6)|(1<<7)|(118<<17), EmptyImpList, EmptyImpList, OperandInfo68 },  // Inst #1018 = V_SETALLONES
01156   { "XCHG16mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(135<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #1019 = XCHG16mr
01157   { "XCHG16rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(1<<6)|(135<<17), EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #1020 = XCHG16rm
01158   { "XCHG16rr", 2, -1, 0, false, 0, 0, 0, 0, 0|3|(1<<6)|(135<<17), EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #1021 = XCHG16rr
01159   { "XCHG32mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(135<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #1022 = XCHG32mr
01160   { "XCHG32rm", 5, -1, 0, false, 0, 0, 0, 0, 0|6|(135<<17), EmptyImpList, EmptyImpList, OperandInfo33 },  // Inst #1023 = XCHG32rm
01161   { "XCHG32rr", 2, -1, 0, false, 0, 0, 0, 0, 0|3|(135<<17), EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #1024 = XCHG32rr
01162   { "XCHG8mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(134<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #1025 = XCHG8mr
01163   { "XCHG8rm",  5, -1, 0, false, 0, 0, 0, 0, 0|6|(134<<17), EmptyImpList, EmptyImpList, OperandInfo35 },  // Inst #1026 = XCHG8rm
01164   { "XCHG8rr",  2, -1, 0, false, 0, 0, 0, 0, 0|3|(134<<17), EmptyImpList, EmptyImpList, OperandInfo36 },  // Inst #1027 = XCHG8rr
01165   { "XOR16mi",  5, -1, 0, false, 0, 0, 0, 0, 0|30|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #1028 = XOR16mi
01166   { "XOR16mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|30|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #1029 = XOR16mi8
01167   { "XOR16mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(1<<6)|(49<<17), EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #1030 = XOR16mr
01168   { "XOR16ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(2<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #1031 = XOR16ri
01169   { "XOR16ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<6)|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #1032 = XOR16ri8
01170   { "XOR16rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(51<<17), EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #1033 = XOR16rm
01171   { "XOR16rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(1<<6)|(49<<17), EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #1034 = XOR16rr
01172   { "XOR32mi",  5, -1, 0, false, 0, 0, 0, 0, 0|30|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #1035 = XOR32mi
01173   { "XOR32mi8", 5, -1, 0, false, 0, 0, 0, 0, 0|30|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #1036 = XOR32mi8
01174   { "XOR32mr",  5, -1, 0, false, 0, 0, 0, 0, 0|4|(49<<17), EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #1037 = XOR32mr
01175   { "XOR32ri",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|22|(3<<11)|(129<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #1038 = XOR32ri
01176   { "XOR32ri8", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<11)|(131<<17), EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #1039 = XOR32ri8
01177   { "XOR32rm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(51<<17), EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #1040 = XOR32rm
01178   { "XOR32rr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(49<<17), EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #1041 = XOR32rr
01179   { "XOR8mi", 5, -1, 0, false, 0, 0, 0, 0, 0|30|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #1042 = XOR8mi
01180   { "XOR8mr", 5, -1, 0, false, 0, 0, 0, 0, 0|4|(48<<17), EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #1043 = XOR8mr
01181   { "XOR8ri", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|22|(1<<11)|(128<<17), EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #1044 = XOR8ri
01182   { "XOR8rm", 6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(50<<17), EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #1045 = XOR8rm
01183   { "XOR8rr", 3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|3|(48<<17), EmptyImpList, EmptyImpList, OperandInfo14 },  // Inst #1046 = XOR8rr
01184   { "XORPDrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<6)|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #1047 = XORPDrm
01185   { "XORPDrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<6)|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #1048 = XORPDrr
01186   { "XORPSrm",  6, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|6|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #1049 = XORPSrm
01187   { "XORPSrr",  3, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|5|(1<<7)|(87<<17), EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #1050 = XORPSrr
01188 };
01189 } // End llvm namespace