LLVM API Documentation

llvm::ISD Namespace Reference


Enumerations

enum  NodeType {
  EntryToken, TokenFactor, AssertSext, AssertZext,
  STRING, BasicBlock, VALUETYPE, CONDCODE,
  Register, Constant, ConstantFP, GlobalAddress,
  FrameIndex, ConstantPool, ExternalSymbol, TargetConstant,
  TargetConstantFP, TargetGlobalAddress, TargetFrameIndex, TargetConstantPool,
  TargetExternalSymbol, INTRINSIC_WO_CHAIN, INTRINSIC_W_CHAIN, INTRINSIC_VOID,
  CopyToReg, CopyFromReg, UNDEF, FORMAL_ARGUMENTS,
  EXTRACT_ELEMENT, BUILD_PAIR, MERGE_VALUES, ADD,
  SUB, MUL, SDIV, UDIV,
  SREM, UREM, ADDC, SUBC,
  ADDE, SUBE, FADD, FSUB,
  FMUL, FDIV, FREM, FCOPYSIGN,
  VBUILD_VECTOR, BUILD_VECTOR, VINSERT_VECTOR_ELT, INSERT_VECTOR_ELT,
  VEXTRACT_VECTOR_ELT, EXTRACT_VECTOR_ELT, VVECTOR_SHUFFLE, VECTOR_SHUFFLE,
  VBIT_CONVERT, VADD, VSUB, VMUL,
  VSDIV, VUDIV, VAND, VOR,
  VXOR, VSELECT, SCALAR_TO_VECTOR, MULHU,
  MULHS, AND, OR, XOR,
  SHL, SRA, SRL, ROTL,
  ROTR, BSWAP, CTTZ, CTLZ,
  CTPOP, SELECT, SELECT_CC, SETCC,
  SHL_PARTS, SRA_PARTS, SRL_PARTS, SIGN_EXTEND,
  ZERO_EXTEND, ANY_EXTEND, TRUNCATE, SINT_TO_FP,
  UINT_TO_FP, SIGN_EXTEND_INREG, FP_TO_SINT, FP_TO_UINT,
  FP_ROUND, FP_ROUND_INREG, FP_EXTEND, BIT_CONVERT,
  FNEG, FABS, FSQRT, FSIN,
  FCOS, LOAD, STORE, VLOAD,
  EXTLOAD, SEXTLOAD, ZEXTLOAD, TRUNCSTORE,
  DYNAMIC_STACKALLOC, BR, BRCOND, BR_CC,
  RET, INLINEASM, STACKSAVE, STACKRESTORE,
  MEMSET, MEMMOVE, MEMCPY, CALLSEQ_START,
  CALLSEQ_END, VAARG, VACOPY, VAEND,
  VASTART, SRCVALUE, PCMARKER, READCYCLECOUNTER,
  HANDLENODE, LOCATION, DEBUG_LOC, DEBUG_LABEL,
  BUILTIN_OP_END
}
enum  CondCode {
  SETFALSE, SETOEQ, SETOGT, SETOGE,
  SETOLT, SETOLE, SETONE, SETO,
  SETUO, SETUEQ, SETUGT, SETUGE,
  SETULT, SETULE, SETUNE, SETTRUE,
  SETFALSE2, SETEQ, SETGT, SETGE,
  SETLT, SETLE, SETNE, SETTRUE2,
  SETCC_INVALID
}

Functions

bool isBuildVectorAllOnes (const SDNode *N)
 Node predicates.
bool isBuildVectorAllZeros (const SDNode *N)
bool isSignedIntSetCC (CondCode Code)
bool isUnsignedIntSetCC (CondCode Code)
bool isTrueWhenEqual (CondCode Cond)
unsigned getUnorderedFlavor (CondCode Cond)
CondCode getSetCCInverse (CondCode Operation, bool isInteger)
CondCode getSetCCSwappedOperands (CondCode Operation)
CondCode getSetCCOrOperation (CondCode Op1, CondCode Op2, bool isInteger)
CondCode getSetCCAndOperation (CondCode Op1, CondCode Op2, bool isInteger)


Detailed Description

ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types and value types.


Enumeration Type Documentation

enum llvm::ISD::NodeType

ISD::NodeType enum - This enum defines all of the operators valid in a SelectionDAG.

Enumerator:
EntryToken 
TokenFactor 
AssertSext 
AssertZext 
STRING 
BasicBlock 
VALUETYPE 
CONDCODE 
Register 
Constant 
ConstantFP 
GlobalAddress 
FrameIndex 
ConstantPool 
ExternalSymbol 
TargetConstant 
TargetConstantFP 
TargetGlobalAddress 
TargetFrameIndex 
TargetConstantPool 
TargetExternalSymbol 
INTRINSIC_WO_CHAIN  RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic function with no side effects. The first operand is the ID number of the intrinsic from the llvm::Intrinsic namespace. The operands to the intrinsic follow. The node has returns the result of the intrinsic.
INTRINSIC_W_CHAIN  RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target intrinsic function with side effects that returns a result. The first operand is a chain pointer. The second is the ID number of the intrinsic from the llvm::Intrinsic namespace. The operands to the intrinsic follow. The node has two results, the result of the intrinsic and an output chain.
INTRINSIC_VOID  OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic function with side effects that does not return a result. The first operand is a chain pointer. The second is the ID number of the intrinsic from the llvm::Intrinsic namespace. The operands to the intrinsic follow.
CopyToReg 
CopyFromReg 
UNDEF 
FORMAL_ARGUMENTS  FORMAL_ARGUMENTS(CC#, ISVARARG) - This node represents the formal arguments for a function. CC# is a Constant value indicating the calling convention of the function, and ISVARARG is a flag that indicates whether the function is varargs or not. This node has one result value for each incoming argument, and is typically custom legalized.
EXTRACT_ELEMENT 
BUILD_PAIR 
MERGE_VALUES 
ADD 
SUB 
MUL 
SDIV 
UDIV 
SREM 
UREM 
ADDC 
SUBC 
ADDE 
SUBE 
FADD 
FSUB 
FMUL 
FDIV 
FREM 
FCOPYSIGN 
VBUILD_VECTOR  VBUILD_VECTOR(ELT1, ELT2, ELT3, ELT4,..., COUNT,TYPE) - Return a vector with the specified, possibly variable, elements. The number of elements is required to be a power of two.
BUILD_VECTOR  BUILD_VECTOR(ELT1, ELT2, ELT3, ELT4,...) - Return a vector with the specified, possibly variable, elements. The number of elements is required to be a power of two.
VINSERT_VECTOR_ELT  VINSERT_VECTOR_ELT(VECTOR, VAL, IDX, COUNT,TYPE) - Given a vector VECTOR, an element ELEMENT, and a (potentially variable) index IDX, return an vector with the specified element of VECTOR replaced with VAL. COUNT and TYPE specify the type of vector, as is standard for V* nodes.
INSERT_VECTOR_ELT  INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR (a legal packed type) with the element at IDX replaced with VAL.
VEXTRACT_VECTOR_ELT  VEXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR (an MVT::Vector value) identified by the (potentially variable) element number IDX.
EXTRACT_VECTOR_ELT  EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR (a legal packed type vector) identified by the (potentially variable) element number IDX.
VVECTOR_SHUFFLE  VVECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC, COUNT,TYPE) - Returns a vector, of the same type as VEC1/VEC2. SHUFFLEVEC is a VBUILD_VECTOR of constant int values that indicate which value each result element will get. The elements of VEC1/VEC2 are enumerated in order. This is quite similar to the Altivec 'vperm' instruction, except that the indices must be constants and are in terms of the element size of VEC1/VEC2, not in terms of bytes.
VECTOR_SHUFFLE  VECTOR_SHUFFLE(VEC1, VEC2, SHUFFLEVEC) - Returns a vector, of the same type as VEC1/VEC2. SHUFFLEVEC is a BUILD_VECTOR of constant int values (regardless of whether its datatype is legal or not) that indicate which value each result element will get. The elements of VEC1/VEC2 are enumerated in order. This is quite similar to the Altivec 'vperm' instruction, except that the indices must be constants and are in terms of the element size of VEC1/VEC2, not in terms of bytes.
VBIT_CONVERT  X = VBIT_CONVERT(Y) and X = VBIT_CONVERT(Y, COUNT,TYPE) - This node represents a conversion from or to an ISD::Vector type.

This is lowered to a BIT_CONVERT of the appropriate input/output types. The input and output are required to have the same size and at least one is required to be a vector (if neither is a vector, just use BIT_CONVERT).

If the result is a vector, this takes three operands (like any other vector producer) which indicate the size and type of the vector result. Otherwise it takes one input.

VADD  BINOP(LHS, RHS, COUNT,TYPE) Simple abstract vector operators. Unlike the integer and floating point binary operators, these nodes also take two additional operands: a constant element count, and a value type node indicating the type of the elements. The order is count, type, op0, op1. All vector opcodes, including VLOAD and VConstant must currently have count and type as their last two operands.
VSUB 
VMUL 
VSDIV 
VUDIV 
VAND 
VOR 
VXOR 
VSELECT  VSELECT(COND,LHS,RHS, COUNT,TYPE) - Select for MVT::Vector values. COND is a boolean value. This node return LHS if COND is true, RHS if COND is false.
SCALAR_TO_VECTOR  SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into the low element of the resultant vector type. The top elements of the vector are undefined.
MULHU 
MULHS 
AND 
OR 
XOR 
SHL 
SRA 
SRL 
ROTL 
ROTR 
BSWAP 
CTTZ 
CTLZ 
CTPOP 
SELECT 
SELECT_CC 
SETCC 
SHL_PARTS 
SRA_PARTS 
SRL_PARTS 
SIGN_EXTEND 
ZERO_EXTEND 
ANY_EXTEND 
TRUNCATE 
SINT_TO_FP 
UINT_TO_FP 
SIGN_EXTEND_INREG 
FP_TO_SINT 
FP_TO_UINT 
FP_ROUND 
FP_ROUND_INREG 
FP_EXTEND 
BIT_CONVERT 
FNEG 
FABS 
FSQRT 
FSIN 
FCOS 
LOAD 
STORE 
VLOAD 
EXTLOAD 
SEXTLOAD 
ZEXTLOAD 
TRUNCSTORE 
DYNAMIC_STACKALLOC 
BR 
BRCOND 
BR_CC 
RET 
INLINEASM 
STACKSAVE 
STACKRESTORE 
MEMSET 
MEMMOVE 
MEMCPY 
CALLSEQ_START 
CALLSEQ_END 
VAARG 
VACOPY 
VAEND 
VASTART 
SRCVALUE 
PCMARKER 
READCYCLECOUNTER 
HANDLENODE 
LOCATION 
DEBUG_LOC 
DEBUG_LABEL 
BUILTIN_OP_END 

Definition at line 49 of file SelectionDAGNodes.h.

enum llvm::ISD::CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out, when considering SETFALSE (something that never exists dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal to. If the "N" column is 1, the result of the comparison is undefined if the input is a NAN.

All of these (except for the 'always folded ops') should be handled for floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.

Note that these are laid out in a specific order to allow bit-twiddling to transform conditions.

Enumerator:
SETFALSE 
SETOEQ 
SETOGT 
SETOGE 
SETOLT 
SETOLE 
SETONE 
SETO 
SETUO 
SETUEQ 
SETUGT 
SETUGE 
SETULT 
SETULE 
SETUNE 
SETTRUE 
SETFALSE2 
SETEQ 
SETGT 
SETGE 
SETLT 
SETLE 
SETNE 
SETTRUE2 
SETCC_INVALID 

Definition at line 516 of file SelectionDAGNodes.h.


Function Documentation

bool llvm::ISD::isBuildVectorAllOnes ( const SDNode N  ) 

Node predicates.

isBuildVectorAllOnes - Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.

Definition at line 75 of file SelectionDAG.cpp.

References BUILD_VECTOR, llvm::DoubleToBits(), llvm::MVT::f64, llvm::FloatToBits(), llvm::SDNode::getNumOperands(), llvm::SDOperand::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDOperand::getValueType(), and UNDEF.

Referenced by llvm::X86TargetLowering::LowerOperation().

bool llvm::ISD::isBuildVectorAllZeros ( const SDNode N  ) 

isBuildVectorAllZeros - Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.

Definition at line 119 of file SelectionDAG.cpp.

References BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDOperand::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and UNDEF.

bool llvm::ISD::isSignedIntSetCC ( CondCode  Code  )  [inline]

isSignedIntSetCC - Return true if this is a setcc instruction that performs a signed comparison when used with integer operands.

Definition at line 549 of file SelectionDAGNodes.h.

References SETGE, SETGT, SETLE, and SETLT.

bool llvm::ISD::isUnsignedIntSetCC ( CondCode  Code  )  [inline]

isUnsignedIntSetCC - Return true if this is a setcc instruction that performs an unsigned comparison when used with integer operands.

Definition at line 555 of file SelectionDAGNodes.h.

References SETUGE, SETUGT, SETULE, and SETULT.

bool llvm::ISD::isTrueWhenEqual ( CondCode  Cond  )  [inline]

isTrueWhenEqual - Return true if the specified condition returns true if the two operands to the condition are equal. Note that if one of the two operands is a NaN, this value is meaningless.

Definition at line 562 of file SelectionDAGNodes.h.

unsigned llvm::ISD::getUnorderedFlavor ( CondCode  Cond  )  [inline]

getUnorderedFlavor - This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if the condition is undefined if the operand is a NaN.

Definition at line 570 of file SelectionDAGNodes.h.

ISD::CondCode llvm::ISD::getSetCCInverse ( ISD::CondCode  Op,
bool  isInteger 
)

getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.

Definition at line 166 of file SelectionDAG.cpp.

References SETTRUE2.

ISD::CondCode llvm::ISD::getSetCCSwappedOperands ( ISD::CondCode  Operation  ) 

getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for (X op Y).

Definition at line 154 of file SelectionDAG.cpp.

ISD::CondCode llvm::ISD::getSetCCOrOperation ( ISD::CondCode  Op1,
ISD::CondCode  Op2,
bool  isInteger 
)

getSetCCOrOperation - Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function returns SETCC_INVALID if it is not possible to represent the resultant comparison.

Definition at line 201 of file SelectionDAG.cpp.

References isSignedOp(), Op, SETCC_INVALID, and SETTRUE2.

ISD::CondCode llvm::ISD::getSetCCAndOperation ( ISD::CondCode  Op1,
ISD::CondCode  Op2,
bool  isInteger 
)

getSetCCAndOperation - Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This function returns zero if it is not possible to represent the resultant comparison.

Definition at line 220 of file SelectionDAG.cpp.

References isSignedOp(), and SETCC_INVALID.