LLVM API Documentation

TwoAddressInstructionPass.cpp

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00001 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the TwoAddress instruction pass which is used
00011 // by most register allocators. Two-Address instructions are rewritten
00012 // from:
00013 //
00014 //     A = B op C
00015 //
00016 // to:
00017 //
00018 //     A = B
00019 //     A op= C
00020 //
00021 // Note that if a register allocator chooses to use this pass, that it
00022 // has to be capable of handling the non-SSA nature of these rewritten
00023 // virtual registers.
00024 //
00025 // It is also worth noting that the duplicate operand of the two
00026 // address instruction is removed.
00027 //
00028 //===----------------------------------------------------------------------===//
00029 
00030 #define DEBUG_TYPE "twoaddrinstr"
00031 #include "llvm/CodeGen/Passes.h"
00032 #include "llvm/Function.h"
00033 #include "llvm/CodeGen/LiveVariables.h"
00034 #include "llvm/CodeGen/MachineFunctionPass.h"
00035 #include "llvm/CodeGen/MachineInstr.h"
00036 #include "llvm/CodeGen/SSARegMap.h"
00037 #include "llvm/Target/MRegisterInfo.h"
00038 #include "llvm/Target/TargetInstrInfo.h"
00039 #include "llvm/Target/TargetMachine.h"
00040 #include "llvm/Support/Debug.h"
00041 #include "llvm/ADT/Statistic.h"
00042 #include "llvm/ADT/STLExtras.h"
00043 #include <iostream>
00044 using namespace llvm;
00045 
00046 namespace {
00047   Statistic<> NumTwoAddressInstrs("twoaddressinstruction",
00048                                   "Number of two-address instructions");
00049   Statistic<> NumCommuted("twoaddressinstruction",
00050                           "Number of instructions commuted to coalesce");
00051   Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
00052                                 "Number of instructions promoted to 3-address");
00053 
00054   struct TwoAddressInstructionPass : public MachineFunctionPass {
00055     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
00056 
00057     /// runOnMachineFunction - pass entry point
00058     bool runOnMachineFunction(MachineFunction&);
00059   };
00060 
00061   RegisterPass<TwoAddressInstructionPass>
00062   X("twoaddressinstruction", "Two-Address instruction pass");
00063 };
00064 
00065 const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
00066 
00067 void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
00068   AU.addRequired<LiveVariables>();
00069   AU.addPreserved<LiveVariables>();
00070   AU.addPreservedID(PHIEliminationID);
00071   MachineFunctionPass::getAnalysisUsage(AU);
00072 }
00073 
00074 /// runOnMachineFunction - Reduce two-address instructions to two
00075 /// operands.
00076 ///
00077 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
00078   DEBUG(std::cerr << "Machine Function\n");
00079   const TargetMachine &TM = MF.getTarget();
00080   const MRegisterInfo &MRI = *TM.getRegisterInfo();
00081   const TargetInstrInfo &TII = *TM.getInstrInfo();
00082   LiveVariables &LV = getAnalysis<LiveVariables>();
00083 
00084   bool MadeChange = false;
00085 
00086   DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
00087   DEBUG(std::cerr << "********** Function: "
00088                   << MF.getFunction()->getName() << '\n');
00089 
00090   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
00091        mbbi != mbbe; ++mbbi) {
00092     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
00093          mi != me; ++mi) {
00094       unsigned opcode = mi->getOpcode();
00095 
00096       // ignore if it is not a two-address instruction
00097       if (!TII.isTwoAddrInstr(opcode))
00098         continue;
00099 
00100       ++NumTwoAddressInstrs;
00101       DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
00102       assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
00103              mi->getOperand(1).isUse() && "two address instruction invalid");
00104 
00105       // if the two operands are the same we just remove the use
00106       // and mark the def as def&use, otherwise we have to insert a copy.
00107       if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
00108         // rewrite:
00109         //     a = b op c
00110         // to:
00111         //     a = b
00112         //     a = a op c
00113         unsigned regA = mi->getOperand(0).getReg();
00114         unsigned regB = mi->getOperand(1).getReg();
00115 
00116         assert(MRegisterInfo::isVirtualRegister(regA) &&
00117                MRegisterInfo::isVirtualRegister(regB) &&
00118                "cannot update physical register live information");
00119 
00120 #ifndef NDEBUG
00121         // First, verify that we do not have a use of a in the instruction (a =
00122         // b + a for example) because our transformation will not work. This
00123         // should never occur because we are in SSA form.
00124         for (unsigned i = 1; i != mi->getNumOperands(); ++i)
00125           assert(!mi->getOperand(i).isRegister() ||
00126                  mi->getOperand(i).getReg() != regA);
00127 #endif
00128 
00129         // If this instruction is not the killing user of B, see if we can
00130         // rearrange the code to make it so.  Making it the killing user will
00131         // allow us to coalesce A and B together, eliminating the copy we are
00132         // about to insert.
00133         if (!LV.KillsRegister(mi, regB)) {
00134           const TargetInstrDescriptor &TID = TII.get(opcode);
00135 
00136           // If this instruction is commutative, check to see if C dies.  If so,
00137           // swap the B and C operands.  This makes the live ranges of A and C
00138           // joinable.
00139           if (TID.Flags & M_COMMUTABLE) {
00140             assert(mi->getOperand(2).isRegister() &&
00141                    "Not a proper commutative instruction!");
00142             unsigned regC = mi->getOperand(2).getReg();
00143             if (LV.KillsRegister(mi, regC)) {
00144               DEBUG(std::cerr << "2addr: COMMUTING  : " << *mi);
00145               MachineInstr *NewMI = TII.commuteInstruction(mi);
00146               if (NewMI == 0) {
00147                 DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
00148               } else {
00149                 DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
00150                 // If the instruction changed to commute it, update livevar.
00151                 if (NewMI != mi) {
00152                   LV.instructionChanged(mi, NewMI);  // Update live variables
00153                   mbbi->insert(mi, NewMI);           // Insert the new inst
00154                   mbbi->erase(mi);                   // Nuke the old inst.
00155                   mi = NewMI;
00156                 }
00157 
00158                 ++NumCommuted;
00159                 regB = regC;
00160                 goto InstructionRearranged;
00161               }
00162             }
00163           }
00164           // If this instruction is potentially convertible to a true
00165           // three-address instruction,
00166           if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
00167             if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
00168               DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
00169               DEBUG(std::cerr << "2addr:         TO 3-ADDR: " << *New);
00170               LV.instructionChanged(mi, New);  // Update live variables
00171               mbbi->insert(mi, New);           // Insert the new inst
00172               mbbi->erase(mi);                 // Nuke the old inst.
00173               mi = New;
00174               ++NumConvertedTo3Addr;
00175               assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
00176                      "convertToThreeAddress returned a 2-addr instruction??");
00177               // Done with this instruction.
00178               continue;
00179             }
00180         }
00181       InstructionRearranged:
00182         const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
00183         MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
00184 
00185         MachineBasicBlock::iterator prevMi = prior(mi);
00186         DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
00187 
00188         // Update live variables for regA
00189         LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
00190         varInfo.DefInst = prevMi;
00191 
00192         // update live variables for regB
00193         if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
00194           LV.addVirtualRegisterKilled(regB, prevMi);
00195 
00196         if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
00197           LV.addVirtualRegisterDead(regB, prevMi);
00198 
00199         // replace all occurences of regB with regA
00200         for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
00201           if (mi->getOperand(i).isRegister() &&
00202               mi->getOperand(i).getReg() == regB)
00203             mi->SetMachineOperandReg(i, regA);
00204         }
00205       }
00206 
00207       assert(mi->getOperand(0).isDef());
00208       mi->getOperand(0).setUse();
00209       mi->RemoveOperand(1);
00210       MadeChange = true;
00211 
00212       DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
00213     }
00214   }
00215 
00216   return MadeChange;
00217 }