LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Assembly Writer Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 /// printInstruction - This method is automatically generated by tablegen 00010 /// from the instruction set description. This method returns true if the 00011 /// machine instruction was sufficiently described to print it, otherwise 00012 /// it returns false. 00013 bool SparcAsmPrinter::printInstruction(const MachineInstr *MI) { 00014 static const char * const OpStrs[] = { 00015 "PHINODE\n", // PHI 00016 0, // INLINEASM 00017 "addcc ", // ADDCCri 00018 "addcc ", // ADDCCrr 00019 "addx ", // ADDXri 00020 "addx ", // ADDXrr 00021 "add ", // ADDri 00022 "add ", // ADDrr 00023 "!ADJCALLSTACKDOWN ", // ADJCALLSTACKDOWN 00024 "!ADJCALLSTACKUP ", // ADJCALLSTACKUP 00025 "andn ", // ANDNri 00026 "andn ", // ANDNrr 00027 "and ", // ANDri 00028 "and ", // ANDrr 00029 "ba ", // BA 00030 "b", // BCOND 00031 "call ", // CALL 00032 "fabsd ", // FABSD 00033 "fabss ", // FABSS 00034 "faddd ", // FADDD 00035 "fadds ", // FADDS 00036 "fb", // FBCOND 00037 "fcmpd ", // FCMPD 00038 "fcmps ", // FCMPS 00039 "fdivd ", // FDIVD 00040 "fdivs ", // FDIVS 00041 "fdtoi ", // FDTOI 00042 "fdtos ", // FDTOS 00043 "fitod ", // FITOD 00044 "fitos ", // FITOS 00045 "fmovd ", // FMOVD 00046 "fmovd", // FMOVD_FCC 00047 "fmovd", // FMOVD_ICC 00048 "fmovs ", // FMOVS 00049 "fmovs", // FMOVS_FCC 00050 "fmovs", // FMOVS_ICC 00051 "fmuld ", // FMULD 00052 "fmuls ", // FMULS 00053 "fnegd ", // FNEGD 00054 "fnegs ", // FNEGS 00055 "fsmuld ", // FSMULD 00056 "fsqrtd ", // FSQRTD 00057 "fsqrts ", // FSQRTS 00058 "fstod ", // FSTOD 00059 "fstoi ", // FSTOI 00060 "fsubd ", // FSUBD 00061 "fsubs ", // FSUBS 00062 "!FpABSD ", // FpABSD 00063 "!FpMOVD ", // FpMOVD 00064 "!FpNEGD ", // FpNEGD 00065 "!IMPLICIT_DEF ", // IMPLICIT_DEF_DFP 00066 "!IMPLICIT_DEF ", // IMPLICIT_DEF_FP 00067 "!IMPLICIT_DEF ", // IMPLICIT_DEF_Int 00068 "call ", // JMPLri 00069 "call ", // JMPLrr 00070 "ldd [", // LDDFri 00071 "ldd [", // LDDFrr 00072 "ld [", // LDFri 00073 "ld [", // LDFrr 00074 "ldsb [", // LDSBri 00075 "ldsb [", // LDSBrr 00076 "ldsh [", // LDSHri 00077 "ldsh [", // LDSHrr 00078 "ldub [", // LDUBri 00079 "ldub [", // LDUBrr 00080 "lduh [", // LDUHri 00081 "lduh [", // LDUHrr 00082 "ld [", // LDri 00083 "ld [", // LDrr 00084 "add ", // LEA_ADDri 00085 "mov", // MOVFCCri 00086 "mov", // MOVFCCrr 00087 "mov", // MOVICCri 00088 "mov", // MOVICCrr 00089 "nop\n", // NOP 00090 "orn ", // ORNri 00091 "orn ", // ORNrr 00092 "or ", // ORri 00093 "or ", // ORrr 00094 "popc ", // POPCrr 00095 "rd %y, ", // RDY 00096 "restore ", // RESTOREri 00097 "restore ", // RESTORErr 00098 "retl\n", // RETL 00099 "save ", // SAVEri 00100 "save ", // SAVErr 00101 "sdiv ", // SDIVri 00102 "sdiv ", // SDIVrr 00103 "; SELECT_CC_DFP_FCC PSEUDO!\n", // SELECT_CC_DFP_FCC 00104 "; SELECT_CC_DFP_ICC PSEUDO!\n", // SELECT_CC_DFP_ICC 00105 "; SELECT_CC_FP_FCC PSEUDO!\n", // SELECT_CC_FP_FCC 00106 "; SELECT_CC_FP_ICC PSEUDO!\n", // SELECT_CC_FP_ICC 00107 "; SELECT_CC_Int_FCC PSEUDO!\n", // SELECT_CC_Int_FCC 00108 "; SELECT_CC_Int_ICC PSEUDO!\n", // SELECT_CC_Int_ICC 00109 "sethi ", // SETHIi 00110 "sll ", // SLLri 00111 "sll ", // SLLrr 00112 "smul ", // SMULri 00113 "smul ", // SMULrr 00114 "sra ", // SRAri 00115 "sra ", // SRArr 00116 "srl ", // SRLri 00117 "srl ", // SRLrr 00118 "stb ", // STBri 00119 "stb ", // STBrr 00120 "std ", // STDFri 00121 "std ", // STDFrr 00122 "st ", // STFri 00123 "st ", // STFrr 00124 "sth ", // STHri 00125 "sth ", // STHrr 00126 "st ", // STri 00127 "st ", // STrr 00128 "subcc ", // SUBCCri 00129 "subcc ", // SUBCCrr 00130 "subxcc ", // SUBXCCrr 00131 "subx ", // SUBXri 00132 "subx ", // SUBXrr 00133 "sub ", // SUBri 00134 "sub ", // SUBrr 00135 "udiv ", // UDIVri 00136 "udiv ", // UDIVrr 00137 "umul ", // UMULri 00138 "umul ", // UMULrr 00139 "wr ", // WRYri 00140 "wr ", // WRYrr 00141 "xnor ", // XNORri 00142 "xnor ", // XNORrr 00143 "xor ", // XORri 00144 "xor ", // XORrr 00145 }; 00146 00147 // Emit the opcode for the instruction. 00148 if (const char *AsmStr = OpStrs[MI->getOpcode()]) 00149 O << AsmStr; 00150 00151 switch (MI->getOpcode()) { 00152 default: return false; 00153 case SP::INLINEASM: printInlineAsm(MI); break; 00154 case SP::ADDCCri: 00155 case SP::ADDCCrr: 00156 case SP::ADDXri: 00157 case SP::ADDXrr: 00158 case SP::ADDri: 00159 case SP::ADDrr: 00160 case SP::ANDNri: 00161 case SP::ANDNrr: 00162 case SP::ANDri: 00163 case SP::ANDrr: 00164 case SP::FADDD: 00165 case SP::FADDS: 00166 case SP::FDIVD: 00167 case SP::FDIVS: 00168 case SP::FMULD: 00169 case SP::FMULS: 00170 case SP::FSMULD: 00171 case SP::FSUBD: 00172 case SP::FSUBS: 00173 case SP::ORNri: 00174 case SP::ORNrr: 00175 case SP::ORri: 00176 case SP::ORrr: 00177 case SP::RESTOREri: 00178 case SP::RESTORErr: 00179 case SP::SAVEri: 00180 case SP::SAVErr: 00181 case SP::SDIVri: 00182 case SP::SDIVrr: 00183 case SP::SLLri: 00184 case SP::SLLrr: 00185 case SP::SMULri: 00186 case SP::SMULrr: 00187 case SP::SRAri: 00188 case SP::SRArr: 00189 case SP::SRLri: 00190 case SP::SRLrr: 00191 case SP::SUBCCri: 00192 case SP::SUBCCrr: 00193 case SP::SUBXCCrr: 00194 case SP::SUBXri: 00195 case SP::SUBXrr: 00196 case SP::SUBri: 00197 case SP::SUBrr: 00198 case SP::UDIVri: 00199 case SP::UDIVrr: 00200 case SP::UMULri: 00201 case SP::UMULrr: 00202 case SP::XNORri: 00203 case SP::XNORrr: 00204 case SP::XORri: 00205 case SP::XORrr: 00206 printOperand(MI, 1); 00207 O << ", "; 00208 printOperand(MI, 2); 00209 O << ", "; 00210 printOperand(MI, 0); 00211 O << "\n"; 00212 break; 00213 case SP::ADJCALLSTACKDOWN: 00214 case SP::ADJCALLSTACKUP: 00215 case SP::BA: 00216 case SP::CALL: 00217 case SP::IMPLICIT_DEF_DFP: 00218 case SP::IMPLICIT_DEF_FP: 00219 case SP::IMPLICIT_DEF_Int: 00220 case SP::JMPLri: 00221 case SP::JMPLrr: 00222 case SP::RDY: 00223 switch (MI->getOpcode()) { 00224 case SP::ADJCALLSTACKDOWN: 00225 case SP::ADJCALLSTACKUP: 00226 case SP::BA: 00227 case SP::CALL: 00228 case SP::IMPLICIT_DEF_DFP: 00229 case SP::IMPLICIT_DEF_FP: 00230 case SP::IMPLICIT_DEF_Int: 00231 case SP::RDY: printOperand(MI, 0); break; 00232 case SP::JMPLri: 00233 case SP::JMPLrr: printMemOperand(MI, 0); break; 00234 } 00235 O << "\n"; 00236 break; 00237 case SP::BCOND: 00238 case SP::FBCOND: 00239 printCCOperand(MI, 1); 00240 O << " "; 00241 printOperand(MI, 0); 00242 O << "\n"; 00243 break; 00244 case SP::FABSD: 00245 case SP::FABSS: 00246 case SP::FDTOI: 00247 case SP::FDTOS: 00248 case SP::FITOD: 00249 case SP::FITOS: 00250 case SP::FMOVD: 00251 case SP::FMOVS: 00252 case SP::FNEGD: 00253 case SP::FNEGS: 00254 case SP::FSQRTD: 00255 case SP::FSQRTS: 00256 case SP::FSTOD: 00257 case SP::FSTOI: 00258 case SP::FpABSD: 00259 case SP::FpMOVD: 00260 case SP::FpNEGD: 00261 case SP::LEA_ADDri: 00262 case SP::POPCrr: 00263 case SP::SETHIi: 00264 switch (MI->getOpcode()) { 00265 case SP::FABSD: 00266 case SP::FABSS: 00267 case SP::FDTOI: 00268 case SP::FDTOS: 00269 case SP::FITOD: 00270 case SP::FITOS: 00271 case SP::FMOVD: 00272 case SP::FMOVS: 00273 case SP::FNEGD: 00274 case SP::FNEGS: 00275 case SP::FSQRTD: 00276 case SP::FSQRTS: 00277 case SP::FSTOD: 00278 case SP::FSTOI: 00279 case SP::FpABSD: 00280 case SP::FpMOVD: 00281 case SP::FpNEGD: 00282 case SP::POPCrr: 00283 case SP::SETHIi: printOperand(MI, 1); break; 00284 case SP::LEA_ADDri: printMemOperand(MI, 1, "arith"); break; 00285 } 00286 O << ", "; 00287 printOperand(MI, 0); 00288 O << "\n"; 00289 break; 00290 case SP::FCMPD: 00291 case SP::FCMPS: 00292 case SP::WRYri: 00293 case SP::WRYrr: 00294 printOperand(MI, 0); 00295 O << ", "; 00296 printOperand(MI, 1); 00297 switch (MI->getOpcode()) { 00298 case SP::FCMPD: 00299 case SP::FCMPS: O << "\n\tnop\n"; break; 00300 case SP::WRYri: 00301 case SP::WRYrr: O << ", %y\n"; break; 00302 } 00303 break; 00304 case SP::FMOVD_FCC: 00305 case SP::FMOVD_ICC: 00306 case SP::FMOVS_FCC: 00307 case SP::FMOVS_ICC: 00308 case SP::MOVFCCri: 00309 case SP::MOVFCCrr: 00310 case SP::MOVICCri: 00311 case SP::MOVICCrr: 00312 printCCOperand(MI, 2); 00313 switch (MI->getOpcode()) { 00314 case SP::FMOVD_FCC: 00315 case SP::FMOVS_FCC: 00316 case SP::MOVFCCri: 00317 case SP::MOVFCCrr: O << " %fcc0, "; break; 00318 case SP::FMOVD_ICC: 00319 case SP::FMOVS_ICC: 00320 case SP::MOVICCri: 00321 case SP::MOVICCrr: O << " %icc, "; break; 00322 } 00323 printOperand(MI, 1); 00324 O << ", "; 00325 printOperand(MI, 0); 00326 O << "\n"; 00327 break; 00328 case SP::LDDFri: 00329 case SP::LDDFrr: 00330 case SP::LDFri: 00331 case SP::LDFrr: 00332 case SP::LDSBri: 00333 case SP::LDSBrr: 00334 case SP::LDSHri: 00335 case SP::LDSHrr: 00336 case SP::LDUBri: 00337 case SP::LDUBrr: 00338 case SP::LDUHri: 00339 case SP::LDUHrr: 00340 case SP::LDri: 00341 case SP::LDrr: 00342 printMemOperand(MI, 1); 00343 O << "], "; 00344 printOperand(MI, 0); 00345 O << "\n"; 00346 break; 00347 case SP::NOP: 00348 case SP::PHI: 00349 case SP::RETL: 00350 case SP::SELECT_CC_DFP_FCC: 00351 case SP::SELECT_CC_DFP_ICC: 00352 case SP::SELECT_CC_FP_FCC: 00353 case SP::SELECT_CC_FP_ICC: 00354 case SP::SELECT_CC_Int_FCC: 00355 case SP::SELECT_CC_Int_ICC: 00356 break; 00357 case SP::STBri: 00358 case SP::STBrr: 00359 case SP::STDFri: 00360 case SP::STDFrr: 00361 case SP::STFri: 00362 case SP::STFrr: 00363 case SP::STHri: 00364 case SP::STHrr: 00365 case SP::STri: 00366 case SP::STrr: 00367 printOperand(MI, 2); 00368 O << ", ["; 00369 printMemOperand(MI, 0); 00370 O << "]\n"; 00371 break; 00372 } 00373 return true; 00374 }