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PPCISelLowering.cpp

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00001 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Chris Lattner and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the PPCISelLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCISelLowering.h"
00015 #include "PPCTargetMachine.h"
00016 #include "llvm/ADT/VectorExtras.h"
00017 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/SelectionDAG.h"
00022 #include "llvm/CodeGen/SSARegMap.h"
00023 #include "llvm/Constants.h"
00024 #include "llvm/Function.h"
00025 #include "llvm/Intrinsics.h"
00026 #include "llvm/Support/MathExtras.h"
00027 #include "llvm/Target/TargetOptions.h"
00028 using namespace llvm;
00029 
00030 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
00031   : TargetLowering(TM) {
00032     
00033   // Fold away setcc operations if possible.
00034   setSetCCIsExpensive();
00035   setPow2DivIsCheap();
00036   
00037   // Use _setjmp/_longjmp instead of setjmp/longjmp.
00038   setUseUnderscoreSetJmpLongJmp(true);
00039     
00040   // Set up the register classes.
00041   addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
00042   addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
00043   addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
00044   
00045   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
00046   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
00047 
00048   // PowerPC has no intrinsics for these particular operations
00049   setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
00050   setOperationAction(ISD::MEMSET, MVT::Other, Expand);
00051   setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
00052   
00053   // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
00054   setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
00055   setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
00056   
00057   // PowerPC has no SREM/UREM instructions
00058   setOperationAction(ISD::SREM, MVT::i32, Expand);
00059   setOperationAction(ISD::UREM, MVT::i32, Expand);
00060   
00061   // We don't support sin/cos/sqrt/fmod
00062   setOperationAction(ISD::FSIN , MVT::f64, Expand);
00063   setOperationAction(ISD::FCOS , MVT::f64, Expand);
00064   setOperationAction(ISD::FREM , MVT::f64, Expand);
00065   setOperationAction(ISD::FSIN , MVT::f32, Expand);
00066   setOperationAction(ISD::FCOS , MVT::f32, Expand);
00067   setOperationAction(ISD::FREM , MVT::f32, Expand);
00068   
00069   // If we're enabling GP optimizations, use hardware square root
00070   if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
00071     setOperationAction(ISD::FSQRT, MVT::f64, Expand);
00072     setOperationAction(ISD::FSQRT, MVT::f32, Expand);
00073   }
00074   
00075   setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
00076   setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
00077   
00078   // PowerPC does not have BSWAP, CTPOP or CTTZ
00079   setOperationAction(ISD::BSWAP, MVT::i32  , Expand);
00080   setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
00081   setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
00082   
00083   // PowerPC does not have ROTR
00084   setOperationAction(ISD::ROTR, MVT::i32   , Expand);
00085   
00086   // PowerPC does not have Select
00087   setOperationAction(ISD::SELECT, MVT::i32, Expand);
00088   setOperationAction(ISD::SELECT, MVT::f32, Expand);
00089   setOperationAction(ISD::SELECT, MVT::f64, Expand);
00090   setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
00091   setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
00092   setOperationAction(ISD::SELECT, MVT::v8i16, Expand);
00093   setOperationAction(ISD::SELECT, MVT::v16i8, Expand);
00094   
00095   // PowerPC wants to turn select_cc of FP into fsel when possible.
00096   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
00097   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
00098 
00099   // PowerPC wants to optimize integer setcc a bit
00100   setOperationAction(ISD::SETCC, MVT::i32, Custom);
00101   
00102   // PowerPC does not have BRCOND which requires SetCC
00103   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
00104   
00105   // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
00106   setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
00107 
00108   // PowerPC does not have [U|S]INT_TO_FP
00109   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
00110   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
00111 
00112   setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
00113   setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
00114 
00115   // PowerPC does not have truncstore for i1.
00116   setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
00117 
00118   // Support label based line numbers.
00119   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
00120   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
00121   // FIXME - use subtarget debug flags
00122   if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
00123     setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
00124   
00125   // We want to legalize GlobalAddress and ConstantPool nodes into the 
00126   // appropriate instructions to materialize the address.
00127   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
00128   setOperationAction(ISD::ConstantPool,  MVT::i32, Custom);
00129 
00130   // RET must be custom lowered, to meet ABI requirements
00131   setOperationAction(ISD::RET               , MVT::Other, Custom);
00132   
00133   // VASTART needs to be custom lowered to use the VarArgsFrameIndex
00134   setOperationAction(ISD::VASTART           , MVT::Other, Custom);
00135   
00136   // Use the default implementation.
00137   setOperationAction(ISD::VAARG             , MVT::Other, Expand);
00138   setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
00139   setOperationAction(ISD::VAEND             , MVT::Other, Expand);
00140   setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand); 
00141   setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
00142   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
00143   
00144   // We want to custom lower some of our intrinsics.
00145   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
00146   
00147   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
00148     // They also have instructions for converting between i64 and fp.
00149     setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
00150     setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
00151     
00152     // FIXME: disable this lowered code.  This generates 64-bit register values,
00153     // and we don't model the fact that the top part is clobbered by calls.  We
00154     // need to flag these together so that the value isn't live across a call.
00155     //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
00156     
00157     // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
00158     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
00159   } else {
00160     // PowerPC does not have FP_TO_UINT on 32-bit implementations.
00161     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
00162   }
00163 
00164   if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
00165     // 64 bit PowerPC implementations can support i64 types directly
00166     addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
00167     // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
00168     setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
00169   } else {
00170     // 32 bit PowerPC wants to expand i64 shifts itself.
00171     setOperationAction(ISD::SHL, MVT::i64, Custom);
00172     setOperationAction(ISD::SRL, MVT::i64, Custom);
00173     setOperationAction(ISD::SRA, MVT::i64, Custom);
00174   }
00175 
00176   if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
00177     // First set operation action for all vector types to expand. Then we
00178     // will selectively turn on ones that can be effectively codegen'd.
00179     for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
00180          VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
00181       // add/sub/and/or/xor are legal for all supported vector VT's.
00182       setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
00183       setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
00184       setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
00185       setOperationAction(ISD::OR  , (MVT::ValueType)VT, Legal);
00186       setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
00187       
00188       // We promote all shuffles to v16i8.
00189       setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
00190       AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
00191       
00192       setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
00193       setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
00194       setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
00195       setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
00196       setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
00197       setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
00198       setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
00199       setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
00200 
00201       setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
00202     }
00203 
00204     // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
00205     // with merges, splats, etc.
00206     setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
00207 
00208     addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
00209     addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
00210     addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
00211     addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
00212     
00213     setOperationAction(ISD::MUL, MVT::v4f32, Legal);
00214 
00215     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
00216     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
00217     
00218     setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
00219     setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
00220     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
00221     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
00222   }
00223   
00224   setSetCCResultContents(ZeroOrOneSetCCResult);
00225   setStackPointerRegisterToSaveRestore(PPC::R1);
00226   
00227   // We have target-specific dag combine patterns for the following nodes:
00228   setTargetDAGCombine(ISD::SINT_TO_FP);
00229   setTargetDAGCombine(ISD::STORE);
00230   
00231   computeRegisterProperties();
00232 }
00233 
00234 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
00235   switch (Opcode) {
00236   default: return 0;
00237   case PPCISD::FSEL:          return "PPCISD::FSEL";
00238   case PPCISD::FCFID:         return "PPCISD::FCFID";
00239   case PPCISD::FCTIDZ:        return "PPCISD::FCTIDZ";
00240   case PPCISD::FCTIWZ:        return "PPCISD::FCTIWZ";
00241   case PPCISD::STFIWX:        return "PPCISD::STFIWX";
00242   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
00243   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
00244   case PPCISD::VPERM:         return "PPCISD::VPERM";
00245   case PPCISD::Hi:            return "PPCISD::Hi";
00246   case PPCISD::Lo:            return "PPCISD::Lo";
00247   case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
00248   case PPCISD::SRL:           return "PPCISD::SRL";
00249   case PPCISD::SRA:           return "PPCISD::SRA";
00250   case PPCISD::SHL:           return "PPCISD::SHL";
00251   case PPCISD::EXTSW_32:      return "PPCISD::EXTSW_32";
00252   case PPCISD::STD_32:        return "PPCISD::STD_32";
00253   case PPCISD::CALL:          return "PPCISD::CALL";
00254   case PPCISD::RET_FLAG:      return "PPCISD::RET_FLAG";
00255   case PPCISD::MFCR:          return "PPCISD::MFCR";
00256   case PPCISD::VCMP:          return "PPCISD::VCMP";
00257   case PPCISD::VCMPo:         return "PPCISD::VCMPo";
00258   }
00259 }
00260 
00261 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
00262 static bool isFloatingPointZero(SDOperand Op) {
00263   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
00264     return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
00265   else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
00266     // Maybe this has already been legalized into the constant pool?
00267     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
00268       if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
00269         return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
00270   }
00271   return false;
00272 }
00273 
00274 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode.  Return
00275 /// true if Op is undef or if it matches the specified value.
00276 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
00277   return Op.getOpcode() == ISD::UNDEF || 
00278          cast<ConstantSDNode>(Op)->getValue() == Val;
00279 }
00280 
00281 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
00282 /// VPKUHUM instruction.
00283 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
00284   if (!isUnary) {
00285     for (unsigned i = 0; i != 16; ++i)
00286       if (!isConstantOrUndef(N->getOperand(i),  i*2+1))
00287         return false;
00288   } else {
00289     for (unsigned i = 0; i != 8; ++i)
00290       if (!isConstantOrUndef(N->getOperand(i),  i*2+1) ||
00291           !isConstantOrUndef(N->getOperand(i+8),  i*2+1))
00292         return false;
00293   }
00294   return true;
00295 }
00296 
00297 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
00298 /// VPKUWUM instruction.
00299 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
00300   if (!isUnary) {
00301     for (unsigned i = 0; i != 16; i += 2)
00302       if (!isConstantOrUndef(N->getOperand(i  ),  i*2+2) ||
00303           !isConstantOrUndef(N->getOperand(i+1),  i*2+3))
00304         return false;
00305   } else {
00306     for (unsigned i = 0; i != 8; i += 2)
00307       if (!isConstantOrUndef(N->getOperand(i  ),  i*2+2) ||
00308           !isConstantOrUndef(N->getOperand(i+1),  i*2+3) ||
00309           !isConstantOrUndef(N->getOperand(i+8),  i*2+2) ||
00310           !isConstantOrUndef(N->getOperand(i+9),  i*2+3))
00311         return false;
00312   }
00313   return true;
00314 }
00315 
00316 /// isVMerge - Common function, used to match vmrg* shuffles.
00317 ///
00318 static bool isVMerge(SDNode *N, unsigned UnitSize, 
00319                      unsigned LHSStart, unsigned RHSStart) {
00320   assert(N->getOpcode() == ISD::BUILD_VECTOR &&
00321          N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
00322   assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
00323          "Unsupported merge size!");
00324   
00325   for (unsigned i = 0; i != 8/UnitSize; ++i)     // Step over units
00326     for (unsigned j = 0; j != UnitSize; ++j) {   // Step over bytes within unit
00327       if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
00328                              LHSStart+j+i*UnitSize) ||
00329           !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
00330                              RHSStart+j+i*UnitSize))
00331         return false;
00332     }
00333       return true;
00334 }
00335 
00336 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
00337 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
00338 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
00339   if (!isUnary)
00340     return isVMerge(N, UnitSize, 8, 24);
00341   return isVMerge(N, UnitSize, 8, 8);
00342 }
00343 
00344 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
00345 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
00346 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
00347   if (!isUnary)
00348     return isVMerge(N, UnitSize, 0, 16);
00349   return isVMerge(N, UnitSize, 0, 0);
00350 }
00351 
00352 
00353 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
00354 /// amount, otherwise return -1.
00355 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
00356   assert(N->getOpcode() == ISD::BUILD_VECTOR &&
00357          N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
00358   // Find the first non-undef value in the shuffle mask.
00359   unsigned i;
00360   for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
00361     /*search*/;
00362   
00363   if (i == 16) return -1;  // all undef.
00364   
00365   // Otherwise, check to see if the rest of the elements are consequtively
00366   // numbered from this value.
00367   unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
00368   if (ShiftAmt < i) return -1;
00369   ShiftAmt -= i;
00370 
00371   if (!isUnary) {
00372     // Check the rest of the elements to see if they are consequtive.
00373     for (++i; i != 16; ++i)
00374       if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
00375         return -1;
00376   } else {
00377     // Check the rest of the elements to see if they are consequtive.
00378     for (++i; i != 16; ++i)
00379       if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
00380         return -1;
00381   }
00382   
00383   return ShiftAmt;
00384 }
00385 
00386 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
00387 /// specifies a splat of a single element that is suitable for input to
00388 /// VSPLTB/VSPLTH/VSPLTW.
00389 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
00390   assert(N->getOpcode() == ISD::BUILD_VECTOR &&
00391          N->getNumOperands() == 16 &&
00392          (EltSize == 1 || EltSize == 2 || EltSize == 4));
00393   
00394   // This is a splat operation if each element of the permute is the same, and
00395   // if the value doesn't reference the second vector.
00396   unsigned ElementBase = 0;
00397   SDOperand Elt = N->getOperand(0);
00398   if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
00399     ElementBase = EltV->getValue();
00400   else
00401     return false;   // FIXME: Handle UNDEF elements too!
00402 
00403   if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
00404     return false;
00405   
00406   // Check that they are consequtive.
00407   for (unsigned i = 1; i != EltSize; ++i) {
00408     if (!isa<ConstantSDNode>(N->getOperand(i)) ||
00409         cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
00410       return false;
00411   }
00412   
00413   assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
00414   for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
00415     assert(isa<ConstantSDNode>(N->getOperand(i)) &&
00416            "Invalid VECTOR_SHUFFLE mask!");
00417     for (unsigned j = 0; j != EltSize; ++j)
00418       if (N->getOperand(i+j) != N->getOperand(j))
00419         return false;
00420   }
00421 
00422   return true;
00423 }
00424 
00425 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
00426 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
00427 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
00428   assert(isSplatShuffleMask(N, EltSize));
00429   return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
00430 }
00431 
00432 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
00433 /// by using a vspltis[bhw] instruction of the specified element size, return
00434 /// the constant being splatted.  The ByteSize field indicates the number of
00435 /// bytes of each element [124] -> [bhw].
00436 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
00437   SDOperand OpVal(0, 0);
00438 
00439   // If ByteSize of the splat is bigger than the element size of the
00440   // build_vector, then we have a case where we are checking for a splat where
00441   // multiple elements of the buildvector are folded together into a single
00442   // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
00443   unsigned EltSize = 16/N->getNumOperands();
00444   if (EltSize < ByteSize) {
00445     unsigned Multiple = ByteSize/EltSize;   // Number of BV entries per spltval.
00446     SDOperand UniquedVals[4];
00447     assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
00448     
00449     // See if all of the elements in the buildvector agree across.
00450     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
00451       if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
00452       // If the element isn't a constant, bail fully out.
00453       if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
00454 
00455           
00456       if (UniquedVals[i&(Multiple-1)].Val == 0)
00457         UniquedVals[i&(Multiple-1)] = N->getOperand(i);
00458       else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
00459         return SDOperand();  // no match.
00460     }
00461     
00462     // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
00463     // either constant or undef values that are identical for each chunk.  See
00464     // if these chunks can form into a larger vspltis*.
00465     
00466     // Check to see if all of the leading entries are either 0 or -1.  If
00467     // neither, then this won't fit into the immediate field.
00468     bool LeadingZero = true;
00469     bool LeadingOnes = true;
00470     for (unsigned i = 0; i != Multiple-1; ++i) {
00471       if (UniquedVals[i].Val == 0) continue;  // Must have been undefs.
00472       
00473       LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
00474       LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
00475     }
00476     // Finally, check the least significant entry.
00477     if (LeadingZero) {
00478       if (UniquedVals[Multiple-1].Val == 0)
00479         return DAG.getTargetConstant(0, MVT::i32);  // 0,0,0,undef
00480       int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
00481       if (Val < 16)
00482         return DAG.getTargetConstant(Val, MVT::i32);  // 0,0,0,4 -> vspltisw(4)
00483     }
00484     if (LeadingOnes) {
00485       if (UniquedVals[Multiple-1].Val == 0)
00486         return DAG.getTargetConstant(~0U, MVT::i32);  // -1,-1,-1,undef
00487       int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
00488       if (Val >= -16)                            // -1,-1,-1,-2 -> vspltisw(-2)
00489         return DAG.getTargetConstant(Val, MVT::i32);
00490     }
00491     
00492     return SDOperand();
00493   }
00494   
00495   // Check to see if this buildvec has a single non-undef value in its elements.
00496   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
00497     if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
00498     if (OpVal.Val == 0)
00499       OpVal = N->getOperand(i);
00500     else if (OpVal != N->getOperand(i))
00501       return SDOperand();
00502   }
00503   
00504   if (OpVal.Val == 0) return SDOperand();  // All UNDEF: use implicit def.
00505   
00506   unsigned ValSizeInBytes = 0;
00507   uint64_t Value = 0;
00508   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
00509     Value = CN->getValue();
00510     ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
00511   } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
00512     assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
00513     Value = FloatToBits(CN->getValue());
00514     ValSizeInBytes = 4;
00515   }
00516 
00517   // If the splat value is larger than the element value, then we can never do
00518   // this splat.  The only case that we could fit the replicated bits into our
00519   // immediate field for would be zero, and we prefer to use vxor for it.
00520   if (ValSizeInBytes < ByteSize) return SDOperand();
00521   
00522   // If the element value is larger than the splat value, cut it in half and
00523   // check to see if the two halves are equal.  Continue doing this until we
00524   // get to ByteSize.  This allows us to handle 0x01010101 as 0x01.
00525   while (ValSizeInBytes > ByteSize) {
00526     ValSizeInBytes >>= 1;
00527     
00528     // If the top half equals the bottom half, we're still ok.
00529     if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
00530          (Value                        & ((1 << (8*ValSizeInBytes))-1)))
00531       return SDOperand();
00532   }
00533 
00534   // Properly sign extend the value.
00535   int ShAmt = (4-ByteSize)*8;
00536   int MaskVal = ((int)Value << ShAmt) >> ShAmt;
00537   
00538   // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
00539   if (MaskVal == 0) return SDOperand();
00540 
00541   // Finally, if this value fits in a 5 bit sext field, return it
00542   if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
00543     return DAG.getTargetConstant(MaskVal, MVT::i32);
00544   return SDOperand();
00545 }
00546 
00547 // If this is a vector of constants or undefs, get the bits.  A bit in
00548 // UndefBits is set if the corresponding element of the vector is an 
00549 // ISD::UNDEF value.  For undefs, the corresponding VectorBits values are
00550 // zero.   Return true if this is not an array of constants, false if it is.
00551 //
00552 // Note that VectorBits/UndefBits are returned in 'little endian' form, so
00553 // elements 0,1 go in VectorBits[0] and 2,3 go in VectorBits[1] for a v4i32.
00554 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
00555                                        uint64_t UndefBits[2]) {
00556   // Start with zero'd results.
00557   VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
00558   
00559   unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
00560   for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
00561     SDOperand OpVal = BV->getOperand(i);
00562     
00563     unsigned PartNo = i >= e/2;     // In the upper 128 bits?
00564     unsigned SlotNo = i & (e/2-1);  // Which subpiece of the uint64_t it is.
00565 
00566     uint64_t EltBits = 0;
00567     if (OpVal.getOpcode() == ISD::UNDEF) {
00568       uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
00569       UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
00570       continue;
00571     } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
00572       EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
00573     } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
00574       assert(CN->getValueType(0) == MVT::f32 &&
00575              "Only one legal FP vector type!");
00576       EltBits = FloatToBits(CN->getValue());
00577     } else {
00578       // Nonconstant element.
00579       return true;
00580     }
00581     
00582     VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
00583   }
00584   
00585   //printf("%llx %llx  %llx %llx\n", 
00586   //       VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
00587   return false;
00588 }
00589 
00590 /// LowerOperation - Provide custom lowering hooks for some operations.
00591 ///
00592 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
00593   switch (Op.getOpcode()) {
00594   default: assert(0 && "Wasn't expecting to be able to lower this!"); 
00595   case ISD::FP_TO_SINT: {
00596     assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
00597     SDOperand Src = Op.getOperand(0);
00598     if (Src.getValueType() == MVT::f32)
00599       Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
00600     
00601     SDOperand Tmp;
00602     switch (Op.getValueType()) {
00603     default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
00604     case MVT::i32:
00605       Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
00606       break;
00607     case MVT::i64:
00608       Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
00609       break;
00610     }
00611    
00612     // Convert the FP value to an int value through memory.
00613     SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
00614     if (Op.getValueType() == MVT::i32)
00615       Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
00616     return Bits;
00617   }
00618   case ISD::SINT_TO_FP:
00619     if (Op.getOperand(0).getValueType() == MVT::i64) {
00620       SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
00621       SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
00622       if (Op.getValueType() == MVT::f32)
00623         FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
00624       return FP;
00625     } else {
00626       assert(Op.getOperand(0).getValueType() == MVT::i32 &&
00627              "Unhandled SINT_TO_FP type in custom expander!");
00628       // Since we only generate this in 64-bit mode, we can take advantage of
00629       // 64-bit registers.  In particular, sign extend the input value into the
00630       // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
00631       // then lfd it and fcfid it.
00632       MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
00633       int FrameIdx = FrameInfo->CreateStackObject(8, 8);
00634       SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
00635       
00636       SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
00637                                     Op.getOperand(0));
00638 
00639       // STD the extended value into the stack slot.
00640       SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
00641                                     DAG.getEntryNode(), Ext64, FIdx,
00642                                     DAG.getSrcValue(NULL));
00643       // Load the value as a double.
00644       SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
00645       
00646       // FCFID it and return it.
00647       SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
00648       if (Op.getValueType() == MVT::f32)
00649         FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
00650       return FP;
00651     }
00652     break;
00653 
00654   case ISD::SELECT_CC: {
00655     // Turn FP only select_cc's into fsel instructions.
00656     if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
00657         !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
00658       break;
00659     
00660     ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
00661     
00662     // Cannot handle SETEQ/SETNE.
00663     if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
00664     
00665     MVT::ValueType ResVT = Op.getValueType();
00666     MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
00667     SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
00668     SDOperand TV  = Op.getOperand(2), FV  = Op.getOperand(3);
00669 
00670     // If the RHS of the comparison is a 0.0, we don't need to do the
00671     // subtraction at all.
00672     if (isFloatingPointZero(RHS))
00673       switch (CC) {
00674       default: break;       // SETUO etc aren't handled by fsel.
00675       case ISD::SETULT:
00676       case ISD::SETLT:
00677         std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
00678       case ISD::SETUGE:
00679       case ISD::SETGE:
00680         if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
00681           LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
00682         return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
00683       case ISD::SETUGT:
00684       case ISD::SETGT:
00685         std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
00686       case ISD::SETULE:
00687       case ISD::SETLE:
00688         if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
00689           LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
00690         return DAG.getNode(PPCISD::FSEL, ResVT,
00691                            DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
00692       }
00693     
00694     SDOperand Cmp;
00695     switch (CC) {
00696     default: break;       // SETUO etc aren't handled by fsel.
00697     case ISD::SETULT:
00698     case ISD::SETLT:
00699       Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
00700       if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
00701         Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
00702       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
00703     case ISD::SETUGE:
00704     case ISD::SETGE:
00705       Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
00706       if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
00707         Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
00708       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
00709     case ISD::SETUGT:
00710     case ISD::SETGT:
00711       Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
00712       if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
00713         Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
00714       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
00715     case ISD::SETULE:
00716     case ISD::SETLE:
00717       Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
00718       if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
00719         Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
00720       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
00721     }
00722     break;
00723   }
00724   case ISD::SHL: {
00725     assert(Op.getValueType() == MVT::i64 &&
00726            Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
00727     // The generic code does a fine job expanding shift by a constant.
00728     if (isa<ConstantSDNode>(Op.getOperand(1))) break;
00729     
00730     // Otherwise, expand into a bunch of logical ops.  Note that these ops
00731     // depend on the PPC behavior for oversized shift amounts.
00732     SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
00733                                DAG.getConstant(0, MVT::i32));
00734     SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
00735                                DAG.getConstant(1, MVT::i32));
00736     SDOperand Amt = Op.getOperand(1);
00737     
00738     SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
00739                                  DAG.getConstant(32, MVT::i32), Amt);
00740     SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
00741     SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
00742     SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
00743     SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
00744                                  DAG.getConstant(-32U, MVT::i32));
00745     SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
00746     SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
00747     SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
00748     return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
00749   }
00750   case ISD::SRL: {
00751     assert(Op.getValueType() == MVT::i64 &&
00752            Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
00753     // The generic code does a fine job expanding shift by a constant.
00754     if (isa<ConstantSDNode>(Op.getOperand(1))) break;
00755     
00756     // Otherwise, expand into a bunch of logical ops.  Note that these ops
00757     // depend on the PPC behavior for oversized shift amounts.
00758     SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
00759                                DAG.getConstant(0, MVT::i32));
00760     SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
00761                                DAG.getConstant(1, MVT::i32));
00762     SDOperand Amt = Op.getOperand(1);
00763     
00764     SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
00765                                  DAG.getConstant(32, MVT::i32), Amt);
00766     SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
00767     SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
00768     SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
00769     SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
00770                                  DAG.getConstant(-32U, MVT::i32));
00771     SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
00772     SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
00773     SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
00774     return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
00775   }    
00776   case ISD::SRA: {
00777     assert(Op.getValueType() == MVT::i64 &&
00778            Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
00779     // The generic code does a fine job expanding shift by a constant.
00780     if (isa<ConstantSDNode>(Op.getOperand(1))) break;
00781       
00782     // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
00783     SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
00784                                DAG.getConstant(0, MVT::i32));
00785     SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
00786                                DAG.getConstant(1, MVT::i32));
00787     SDOperand Amt = Op.getOperand(1);
00788     
00789     SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
00790                                  DAG.getConstant(32, MVT::i32), Amt);
00791     SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
00792     SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
00793     SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
00794     SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
00795                                  DAG.getConstant(-32U, MVT::i32));
00796     SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
00797     SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
00798     SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
00799                                       Tmp4, Tmp6, ISD::SETLE);
00800     return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
00801   }
00802   case ISD::ConstantPool: {
00803     ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
00804     Constant *C = CP->get();
00805     SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
00806     SDOperand Zero = DAG.getConstant(0, MVT::i32);
00807     
00808     // If this is a non-darwin platform, we don't support non-static relo models
00809     // yet.
00810     if (getTargetMachine().getRelocationModel() == Reloc::Static ||
00811         !getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) {
00812       // Generate non-pic code that has direct accesses to the constant pool.
00813       // The address of the global is just (hi(&g)+lo(&g)).
00814       SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
00815       SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
00816       return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
00817     }
00818     
00819     SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
00820     if (getTargetMachine().getRelocationModel() == Reloc::PIC) {
00821       // With PIC, the first instruction is actually "GR+hi(&G)".
00822       Hi = DAG.getNode(ISD::ADD, MVT::i32,
00823                        DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
00824     }
00825 
00826     SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
00827     Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
00828     return Lo;
00829   }
00830   case ISD::GlobalAddress: {
00831     GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
00832     GlobalValue *GV = GSDN->getGlobal();
00833     SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
00834     SDOperand Zero = DAG.getConstant(0, MVT::i32);
00835 
00836     // If this is a non-darwin platform, we don't support non-static relo models
00837     // yet.
00838     if (getTargetMachine().getRelocationModel() == Reloc::Static ||
00839         !getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) {
00840       // Generate non-pic code that has direct accesses to globals.
00841       // The address of the global is just (hi(&g)+lo(&g)).
00842       SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
00843       SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
00844       return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
00845     }
00846     
00847     SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
00848     if (getTargetMachine().getRelocationModel() == Reloc::PIC) {
00849       // With PIC, the first instruction is actually "GR+hi(&G)".
00850       Hi = DAG.getNode(ISD::ADD, MVT::i32,
00851                        DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
00852     }
00853     
00854     SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
00855     Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
00856                                    
00857     if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
00858         (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
00859       return Lo;
00860 
00861     // If the global is weak or external, we have to go through the lazy
00862     // resolution stub.
00863     return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
00864   }
00865   case ISD::SETCC: {
00866     ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
00867     
00868     // If we're comparing for equality to zero, expose the fact that this is
00869     // implented as a ctlz/srl pair on ppc, so that the dag combiner can
00870     // fold the new nodes.
00871     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
00872       if (C->isNullValue() && CC == ISD::SETEQ) {
00873         MVT::ValueType VT = Op.getOperand(0).getValueType();
00874         SDOperand Zext = Op.getOperand(0);
00875         if (VT < MVT::i32) {
00876           VT = MVT::i32;
00877           Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
00878         } 
00879         unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
00880         SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
00881         SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
00882                                     DAG.getConstant(Log2b, getShiftAmountTy()));
00883         return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc);
00884       }
00885       // Leave comparisons against 0 and -1 alone for now, since they're usually 
00886       // optimized.  FIXME: revisit this when we can custom lower all setcc
00887       // optimizations.
00888       if (C->isAllOnesValue() || C->isNullValue())
00889         break;
00890     }
00891         
00892     // If we have an integer seteq/setne, turn it into a compare against zero
00893     // by subtracting the rhs from the lhs, which is faster than setting a
00894     // condition register, reading it back out, and masking the correct bit.
00895     MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
00896     if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
00897       MVT::ValueType VT = Op.getValueType();
00898       SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 
00899                                   Op.getOperand(1));
00900       return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
00901     }
00902     break;
00903   }
00904   case ISD::VASTART: {
00905     // vastart just stores the address of the VarArgsFrameIndex slot into the
00906     // memory location argument.
00907     // FIXME: Replace MVT::i32 with PointerTy
00908     SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
00909     return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 
00910                        Op.getOperand(1), Op.getOperand(2));
00911   }
00912   case ISD::RET: {
00913     SDOperand Copy;
00914     
00915     switch(Op.getNumOperands()) {
00916     default:
00917       assert(0 && "Do not know how to return this many arguments!");
00918       abort();
00919     case 1: 
00920       return SDOperand(); // ret void is legal
00921     case 2: {
00922       MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
00923       unsigned ArgReg;
00924       if (MVT::isVector(ArgVT))
00925         ArgReg = PPC::V2;
00926       else if (MVT::isInteger(ArgVT))
00927         ArgReg = PPC::R3;
00928       else {
00929         assert(MVT::isFloatingPoint(ArgVT));
00930         ArgReg = PPC::F1;
00931       }
00932       
00933       Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
00934                               SDOperand());
00935       
00936       // If we haven't noted the R3/F1 are live out, do so now.
00937       if (DAG.getMachineFunction().liveout_empty())
00938         DAG.getMachineFunction().addLiveOut(ArgReg);
00939       break;
00940     }
00941     case 3:
00942       Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 
00943                               SDOperand());
00944       Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
00945       // If we haven't noted the R3+R4 are live out, do so now.
00946       if (DAG.getMachineFunction().liveout_empty()) {
00947         DAG.getMachineFunction().addLiveOut(PPC::R3);
00948         DAG.getMachineFunction().addLiveOut(PPC::R4);
00949       }
00950       break;
00951     }
00952     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
00953   }
00954   case ISD::SCALAR_TO_VECTOR: {
00955     // Create a stack slot that is 16-byte aligned.
00956     MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
00957     int FrameIdx = FrameInfo->CreateStackObject(16, 16);
00958     SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
00959     
00960     // Store the input value into Value#0 of the stack slot.
00961     SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
00962                                   Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
00963     // Load it out.
00964     return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
00965   }
00966   case ISD::BUILD_VECTOR: {
00967     // If this is a case we can't handle, return null and let the default
00968     // expansion code take care of it.  If we CAN select this case, return Op
00969     // or something simpler.
00970     
00971     // If this is a vector of constants or undefs, get the bits.  A bit in
00972     // UndefBits is set if the corresponding element of the vector is an 
00973     // ISD::UNDEF value.  For undefs, the corresponding VectorBits values are
00974     // zero. 
00975     uint64_t VectorBits[2];
00976     uint64_t UndefBits[2];
00977     if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
00978       return SDOperand();   // Not a constant vector.
00979 
00980     // See if this is all zeros.
00981     if ((VectorBits[0] | VectorBits[1]) == 0) {
00982       // Canonicalize all zero vectors to be v4i32.
00983       if (Op.getValueType() != MVT::v4i32) {
00984         SDOperand Z = DAG.getConstant(0, MVT::i32);
00985         Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
00986         Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
00987       }
00988       return Op;
00989     }
00990     
00991     // Check to see if this is something we can use VSPLTI* to form.
00992     MVT::ValueType CanonicalVT = MVT::Other;
00993     SDNode *CST = 0;
00994     
00995     if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val))       // vspltisw
00996       CanonicalVT = MVT::v4i32;
00997     else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val))  // vspltish
00998       CanonicalVT = MVT::v8i16;
00999     else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val))  // vspltisb
01000       CanonicalVT = MVT::v16i8;
01001 
01002     // If this matches one of the vsplti* patterns, force it to the canonical
01003     // type for the pattern.
01004     if (CST) {
01005       if (Op.getValueType() != CanonicalVT) {
01006         // Convert the splatted element to the right element type.
01007         SDOperand Elt = DAG.getNode(ISD::TRUNCATE, 
01008                                     MVT::getVectorBaseType(CanonicalVT), 
01009                                     SDOperand(CST, 0));
01010         std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
01011         SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
01012         Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
01013       }
01014       return Op;
01015     }
01016 
01017     // If this is some other splat of 4-byte elements, see if we can handle it
01018     // in another way.
01019     // FIXME: Make this more undef happy and work with other widths (1,2 bytes).
01020     if (VectorBits[0] == VectorBits[1] &&
01021         unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) {
01022       unsigned Bits = unsigned(VectorBits[0]);
01023 
01024       // If this is 0x8000_0000 x 4, turn into vspltisw + vslw.  If it is 
01025       // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000).  These are important
01026       // for fneg/fabs.
01027       if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) {
01028         // Make -1 and vspltisw -1:
01029         SDOperand OnesI = DAG.getConstant(~0U, MVT::i32);
01030         SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
01031                                       OnesI, OnesI, OnesI, OnesI);
01032         
01033         // Make the VSLW intrinsic, computing 0x8000_0000.
01034         SDOperand Res
01035           = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32,
01036                         DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32),
01037                         OnesV, OnesV);
01038         
01039         // If this is 0x7FFF_FFFF, xor by OnesV to invert it.
01040         if (Bits == 0x7FFFFFFF)
01041           Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
01042         
01043         return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
01044       }
01045     }
01046     
01047       
01048     return SDOperand();
01049   }
01050   case ISD::VECTOR_SHUFFLE: {
01051     SDOperand V1 = Op.getOperand(0);
01052     SDOperand V2 = Op.getOperand(1);
01053     SDOperand PermMask = Op.getOperand(2);
01054     
01055     // Cases that are handled by instructions that take permute immediates
01056     // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
01057     // selected by the instruction selector.
01058     if (V2.getOpcode() == ISD::UNDEF) {
01059       if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
01060           PPC::isSplatShuffleMask(PermMask.Val, 2) ||
01061           PPC::isSplatShuffleMask(PermMask.Val, 4) ||
01062           PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
01063           PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
01064           PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
01065           PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
01066           PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
01067           PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
01068           PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
01069           PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
01070           PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
01071         return Op;
01072       }
01073     }
01074     
01075     // Altivec has a variety of "shuffle immediates" that take two vector inputs
01076     // and produce a fixed permutation.  If any of these match, do not lower to
01077     // VPERM.
01078     if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
01079         PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
01080         PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
01081         PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
01082         PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
01083         PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
01084         PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
01085         PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
01086         PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
01087       return Op;
01088     
01089     // TODO: Handle more cases, and also handle cases that are cheaper to do as
01090     // multiple such instructions than as a constant pool load/vperm pair.
01091     
01092     // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
01093     // vector that will get spilled to the constant pool.
01094     if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
01095     
01096     // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
01097     // that it is in input element units, not in bytes.  Convert now.
01098     MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
01099     unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
01100     
01101     std::vector<SDOperand> ResultMask;
01102     for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
01103       unsigned SrcElt =cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
01104       
01105       for (unsigned j = 0; j != BytesPerElement; ++j)
01106         ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
01107                                              MVT::i8));
01108     }
01109     
01110     SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
01111     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
01112   }
01113   case ISD::INTRINSIC_WO_CHAIN: {
01114     unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
01115     
01116     // If this is a lowered altivec predicate compare, CompareOpc is set to the
01117     // opcode number of the comparison.
01118     int CompareOpc = -1;
01119     bool isDot = false;
01120     switch (IntNo) {
01121     default: return SDOperand();    // Don't custom lower most intrinsics.
01122     // Comparison predicates.
01123     case Intrinsic::ppc_altivec_vcmpbfp_p:  CompareOpc = 966; isDot = 1; break;
01124     case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
01125     case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc =   6; isDot = 1; break;
01126     case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc =  70; isDot = 1; break;
01127     case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
01128     case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
01129     case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
01130     case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
01131     case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
01132     case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
01133     case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
01134     case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
01135     case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
01136 
01137     // Normal Comparisons.
01138     case Intrinsic::ppc_altivec_vcmpbfp:    CompareOpc = 966; isDot = 0; break;
01139     case Intrinsic::ppc_altivec_vcmpeqfp:   CompareOpc = 198; isDot = 0; break;
01140     case Intrinsic::ppc_altivec_vcmpequb:   CompareOpc =   6; isDot = 0; break;
01141     case Intrinsic::ppc_altivec_vcmpequh:   CompareOpc =  70; isDot = 0; break;
01142     case Intrinsic::ppc_altivec_vcmpequw:   CompareOpc = 134; isDot = 0; break;
01143     case Intrinsic::ppc_altivec_vcmpgefp:   CompareOpc = 454; isDot = 0; break;
01144     case Intrinsic::ppc_altivec_vcmpgtfp:   CompareOpc = 710; isDot = 0; break;
01145     case Intrinsic::ppc_altivec_vcmpgtsb:   CompareOpc = 774; isDot = 0; break;
01146     case Intrinsic::ppc_altivec_vcmpgtsh:   CompareOpc = 838; isDot = 0; break;
01147     case Intrinsic::ppc_altivec_vcmpgtsw:   CompareOpc = 902; isDot = 0; break;
01148     case Intrinsic::ppc_altivec_vcmpgtub:   CompareOpc = 518; isDot = 0; break;
01149     case Intrinsic::ppc_altivec_vcmpgtuh:   CompareOpc = 582; isDot = 0; break;
01150     case Intrinsic::ppc_altivec_vcmpgtuw:   CompareOpc = 646; isDot = 0; break;
01151     }
01152     
01153     assert(CompareOpc>0 && "We only lower altivec predicate compares so far!");
01154 
01155     // If this is a non-dot comparison, make the VCMP node.
01156     if (!isDot) {
01157       SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
01158                                   Op.getOperand(1), Op.getOperand(2),
01159                                   DAG.getConstant(CompareOpc, MVT::i32));
01160       return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
01161     }
01162     
01163     // Create the PPCISD altivec 'dot' comparison node.
01164     std::vector<SDOperand> Ops;
01165     std::vector<MVT::ValueType> VTs;
01166     Ops.push_back(Op.getOperand(2));  // LHS
01167     Ops.push_back(Op.getOperand(3));  // RHS
01168     Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
01169     VTs.push_back(Op.getOperand(2).getValueType());
01170     VTs.push_back(MVT::Flag);
01171     SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
01172 
01173     // Now that we have the comparison, emit a copy from the CR to a GPR.
01174     // This is flagged to the above dot comparison.
01175     SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
01176                                   DAG.getRegister(PPC::CR6, MVT::i32),
01177                                   CompNode.getValue(1)); 
01178 
01179     // Unpack the result based on how the target uses it.
01180     unsigned BitNo;   // Bit # of CR6.
01181     bool InvertBit;   // Invert result?
01182     switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
01183     default:  // Can't happen, don't crash on invalid number though.
01184     case 0:   // Return the value of the EQ bit of CR6.
01185       BitNo = 0; InvertBit = false;
01186       break;
01187     case 1:   // Return the inverted value of the EQ bit of CR6.
01188       BitNo = 0; InvertBit = true;
01189       break;
01190     case 2:   // Return the value of the LT bit of CR6.
01191       BitNo = 2; InvertBit = false;
01192       break;
01193     case 3:   // Return the inverted value of the LT bit of CR6.
01194       BitNo = 2; InvertBit = true;
01195       break;
01196     }
01197     
01198     // Shift the bit into the low position.
01199     Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
01200                         DAG.getConstant(8-(3-BitNo), MVT::i32));
01201     // Isolate the bit.
01202     Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
01203                         DAG.getConstant(1, MVT::i32));
01204     
01205     // If we are supposed to, toggle the bit.
01206     if (InvertBit)
01207       Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
01208                           DAG.getConstant(1, MVT::i32));
01209     return Flags;
01210   }
01211   }
01212   return SDOperand();
01213 }
01214 
01215 std::vector<SDOperand>
01216 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
01217   //
01218   // add beautiful description of PPC stack frame format, or at least some docs
01219   //
01220   MachineFunction &MF = DAG.getMachineFunction();
01221   MachineFrameInfo *MFI = MF.getFrameInfo();
01222   MachineBasicBlock& BB = MF.front();
01223   SSARegMap *RegMap = MF.getSSARegMap();
01224   std::vector<SDOperand> ArgValues;
01225   
01226   unsigned ArgOffset = 24;
01227   unsigned GPR_remaining = 8;
01228   unsigned FPR_remaining = 13;
01229   unsigned GPR_idx = 0, FPR_idx = 0;
01230   static const unsigned GPR[] = {
01231     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
01232     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
01233   };
01234   static const unsigned FPR[] = {
01235     PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
01236     PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
01237   };
01238   
01239   // Add DAG nodes to load the arguments...  On entry to a function on PPC,
01240   // the arguments start at offset 24, although they are likely to be passed
01241   // in registers.
01242   for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
01243     SDOperand newroot, argt;
01244     unsigned ObjSize;
01245     bool needsLoad = false;
01246     bool ArgLive = !I->use_empty();
01247     MVT::ValueType ObjectVT = getValueType(I->getType());
01248     
01249     switch (ObjectVT) {
01250     default: assert(0 && "Unhandled argument type!");
01251     case MVT::i1:
01252     case MVT::i8:
01253     case MVT::i16:
01254     case MVT::i32:
01255       ObjSize = 4;
01256       if (!ArgLive) break;
01257       if (GPR_remaining > 0) {
01258         unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
01259         MF.addLiveIn(GPR[GPR_idx], VReg);
01260         argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
01261         if (ObjectVT != MVT::i32) {
01262           unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
01263                                                        : ISD::AssertZext;
01264           argt = DAG.getNode(AssertOp, MVT::i32, argt, 
01265                              DAG.getValueType(ObjectVT));
01266           argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
01267         }
01268       } else {
01269         needsLoad = true;
01270       }
01271       break;
01272     case MVT::i64:
01273       ObjSize = 8;
01274       if (!ArgLive) break;
01275       if (GPR_remaining > 0) {
01276         SDOperand argHi, argLo;
01277         unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
01278         MF.addLiveIn(GPR[GPR_idx], VReg);
01279         argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
01280         // If we have two or more remaining argument registers, then both halves
01281         // of the i64 can be sourced from there.  Otherwise, the lower half will
01282         // have to come off the stack.  This can happen when an i64 is preceded
01283         // by 28 bytes of arguments.
01284         if (GPR_remaining > 1) {
01285           unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
01286           MF.addLiveIn(GPR[GPR_idx+1], VReg);
01287           argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
01288         } else {
01289           int FI = MFI->CreateFixedObject(4, ArgOffset+4);
01290           SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
01291           argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
01292                               DAG.getSrcValue(NULL));
01293         }
01294         // Build the outgoing arg thingy
01295         argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
01296         newroot = argLo;
01297       } else {
01298         needsLoad = true;
01299       }
01300       break;
01301     case MVT::f32:
01302     case MVT::f64:
01303       ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
01304       if (!ArgLive) {
01305         if (FPR_remaining > 0) {
01306           --FPR_remaining;
01307           ++FPR_idx;
01308         }        
01309         break;
01310       }
01311       if (FPR_remaining > 0) {
01312         unsigned VReg;
01313         if (ObjectVT == MVT::f32)
01314           VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
01315         else
01316           VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
01317         MF.addLiveIn(FPR[FPR_idx], VReg);
01318         argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
01319         --FPR_remaining;
01320         ++FPR_idx;
01321       } else {
01322         needsLoad = true;
01323       }
01324       break;
01325     }
01326     
01327     // We need to load the argument to a virtual register if we determined above
01328     // that we ran out of physical registers of the appropriate type
01329     if (needsLoad) {
01330       unsigned SubregOffset = 0;
01331       if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
01332       if (ObjectVT == MVT::i16) SubregOffset = 2;
01333       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
01334       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
01335       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
01336                         DAG.getConstant(SubregOffset, MVT::i32));
01337       argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
01338                                    DAG.getSrcValue(NULL));
01339     }
01340     
01341     // Every 4 bytes of argument space consumes one of the GPRs available for
01342     // argument passing.
01343     if (GPR_remaining > 0) {
01344       unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
01345       GPR_remaining -= delta;
01346       GPR_idx += delta;
01347     }
01348     ArgOffset += ObjSize;
01349     if (newroot.Val)
01350       DAG.setRoot(newroot.getValue(1));
01351     
01352     ArgValues.push_back(argt);
01353   }
01354   
01355   // If the function takes variable number of arguments, make a frame index for
01356   // the start of the first vararg value... for expansion of llvm.va_start.
01357   if (F.isVarArg()) {
01358     VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
01359     SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
01360     // If this function is vararg, store any remaining integer argument regs
01361     // to their spots on the stack so that they may be loaded by deferencing the
01362     // result of va_next.
01363     std::vector<SDOperand> MemOps;
01364     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
01365       unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
01366       MF.addLiveIn(GPR[GPR_idx], VReg);
01367       SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
01368       SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
01369                                     Val, FIN, DAG.getSrcValue(NULL));
01370       MemOps.push_back(Store);
01371       // Increment the address by four for the next argument to store
01372       SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
01373       FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
01374     }
01375     if (!MemOps.empty()) {
01376       MemOps.push_back(DAG.getRoot());
01377       DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
01378     }
01379   }
01380   
01381   return ArgValues;
01382 }
01383 
01384 std::pair<SDOperand, SDOperand>
01385 PPCTargetLowering::LowerCallTo(SDOperand Chain,
01386                                const Type *RetTy, bool isVarArg,
01387                                unsigned CallingConv, bool isTailCall,
01388                                SDOperand Callee, ArgListTy &Args,
01389                                SelectionDAG &DAG) {
01390   // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
01391   // SelectExpr to use to put the arguments in the appropriate registers.
01392   std::vector<SDOperand> args_to_use;
01393   
01394   // Count how many bytes are to be pushed on the stack, including the linkage
01395   // area, and parameter passing area.
01396   unsigned NumBytes = 24;
01397   
01398   if (Args.empty()) {
01399     Chain = DAG.getCALLSEQ_START(Chain,
01400                                  DAG.getConstant(NumBytes, getPointerTy()));
01401   } else {
01402     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
01403       switch (getValueType(Args[i].second)) {
01404       default: assert(0 && "Unknown value type!");
01405       case MVT::i1:
01406       case MVT::i8:
01407       case MVT::i16:
01408       case MVT::i32:
01409       case MVT::f32:
01410         NumBytes += 4;
01411         break;
01412       case MVT::i64:
01413       case MVT::f64:
01414         NumBytes += 8;
01415         break;
01416       }
01417     }
01418         
01419     // Just to be safe, we'll always reserve the full 24 bytes of linkage area
01420     // plus 32 bytes of argument space in case any called code gets funky on us.
01421     // (Required by ABI to support var arg)
01422     if (NumBytes < 56) NumBytes = 56;
01423     
01424     // Adjust the stack pointer for the new arguments...
01425     // These operations are automatically eliminated by the prolog/epilog pass
01426     Chain = DAG.getCALLSEQ_START(Chain,
01427                                  DAG.getConstant(NumBytes, getPointerTy()));
01428     
01429     // Set up a copy of the stack pointer for use loading and storing any
01430     // arguments that may not fit in the registers available for argument
01431     // passing.
01432     SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
01433     
01434     // Figure out which arguments are going to go in registers, and which in
01435     // memory.  Also, if this is a vararg function, floating point operations
01436     // must be stored to our stack, and loaded into integer regs as well, if
01437     // any integer regs are available for argument passing.
01438     unsigned ArgOffset = 24;
01439     unsigned GPR_remaining = 8;
01440     unsigned FPR_remaining = 13;
01441     
01442     std::vector<SDOperand> MemOps;
01443     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
01444       // PtrOff will be used to store the current argument to the stack if a
01445       // register cannot be found for it.
01446       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
01447       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
01448       MVT::ValueType ArgVT = getValueType(Args[i].second);
01449       
01450       switch (ArgVT) {
01451       default: assert(0 && "Unexpected ValueType for argument!");
01452       case MVT::i1:
01453       case MVT::i8:
01454       case MVT::i16:
01455         // Promote the integer to 32 bits.  If the input type is signed use a
01456         // sign extend, otherwise use a zero extend.
01457         if (Args[i].second->isSigned())
01458           Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
01459         else
01460           Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
01461         // FALL THROUGH
01462       case MVT::i32:
01463         if (GPR_remaining > 0) {
01464           args_to_use.push_back(Args[i].first);
01465           --GPR_remaining;
01466         } else {
01467           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
01468                                        Args[i].first, PtrOff,
01469                                        DAG.getSrcValue(NULL)));
01470         }
01471         ArgOffset += 4;
01472         break;
01473       case MVT::i64:
01474         // If we have one free GPR left, we can place the upper half of the i64
01475         // in it, and store the other half to the stack.  If we have two or more
01476         // free GPRs, then we can pass both halves of the i64 in registers.
01477         if (GPR_remaining > 0) {
01478           SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
01479                                      Args[i].first, DAG.getConstant(1, MVT::i32));
01480           SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
01481                                      Args[i].first, DAG.getConstant(0, MVT::i32));
01482           args_to_use.push_back(Hi);
01483           --GPR_remaining;
01484           if (GPR_remaining > 0) {
01485             args_to_use.push_back(Lo);
01486             --GPR_remaining;
01487           } else {
01488             SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
01489             PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
01490             MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
01491                                          Lo, PtrOff, DAG.getSrcValue(NULL)));
01492           }
01493         } else {
01494           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
01495                                        Args[i].first, PtrOff,
01496                                        DAG.getSrcValue(NULL)));
01497         }
01498         ArgOffset += 8;
01499         break;
01500       case MVT::f32:
01501       case MVT::f64:
01502         if (FPR_remaining > 0) {
01503           args_to_use.push_back(Args[i].first);
01504           --FPR_remaining;
01505           if (isVarArg) {
01506             SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
01507                                           Args[i].first, PtrOff,
01508                                           DAG.getSrcValue(NULL));
01509             MemOps.push_back(Store);
01510             // Float varargs are always shadowed in available integer registers
01511             if (GPR_remaining > 0) {
01512               SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
01513                                            DAG.getSrcValue(NULL));
01514               MemOps.push_back(Load.getValue(1));
01515               args_to_use.push_back(Load);
01516               --GPR_remaining;
01517             }
01518             if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
01519               SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
01520               PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
01521               SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
01522                                            DAG.getSrcValue(NULL));
01523               MemOps.push_back(Load.getValue(1));
01524               args_to_use.push_back(Load);
01525               --GPR_remaining;
01526             }
01527           } else {
01528             // If we have any FPRs remaining, we may also have GPRs remaining.
01529             // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
01530             // GPRs.
01531             if (GPR_remaining > 0) {
01532               args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
01533               --GPR_remaining;
01534             }
01535             if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
01536               args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
01537               --GPR_remaining;
01538             }
01539           }
01540         } else {
01541           MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
01542                                        Args[i].first, PtrOff,
01543                                        DAG.getSrcValue(NULL)));
01544         }
01545         ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
01546         break;
01547       }
01548     }
01549     if (!MemOps.empty())
01550       Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
01551   }
01552   
01553   std::vector<MVT::ValueType> RetVals;
01554   MVT::ValueType RetTyVT = getValueType(RetTy);
01555   MVT::ValueType ActualRetTyVT = RetTyVT;
01556   if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
01557     ActualRetTyVT = MVT::i32;   // Promote result to i32.
01558     
01559   if (RetTyVT == MVT::i64) {
01560     RetVals.push_back(MVT::i32);
01561     RetVals.push_back(MVT::i32);
01562   } else if (RetTyVT != MVT::isVoid) {
01563     RetVals.push_back(ActualRetTyVT);
01564   }
01565   RetVals.push_back(MVT::Other);
01566   
01567   // If the callee is a GlobalAddress node (quite common, every direct call is)
01568   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
01569   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
01570     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
01571   
01572   std::vector<SDOperand> Ops;
01573   Ops.push_back(Chain);
01574   Ops.push_back(Callee);
01575   Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
01576   SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
01577   Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
01578   Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
01579                       DAG.getConstant(NumBytes, getPointerTy()));
01580   SDOperand RetVal = TheCall;
01581   
01582   // If the result is a small value, add a note so that we keep track of the
01583   // information about whether it is sign or zero extended.
01584   if (RetTyVT != ActualRetTyVT) {
01585     RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
01586                          MVT::i32, RetVal, DAG.getValueType(RetTyVT));
01587     RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
01588   } else if (RetTyVT == MVT::i64) {
01589     RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1));
01590   }
01591   
01592   return std::make_pair(RetVal, Chain);
01593 }
01594 
01595 MachineBasicBlock *
01596 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
01597                                            MachineBasicBlock *BB) {
01598   assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
01599           MI->getOpcode() == PPC::SELECT_CC_F4 ||
01600           MI->getOpcode() == PPC::SELECT_CC_F8 ||
01601           MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
01602          "Unexpected instr type to insert");
01603   
01604   // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
01605   // control-flow pattern.  The incoming instruction knows the destination vreg
01606   // to set, the condition code register to branch on, the true/false values to
01607   // select between, and a branch opcode to use.
01608   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01609   ilist<MachineBasicBlock>::iterator It = BB;
01610   ++It;
01611   
01612   //  thisMBB:
01613   //  ...
01614   //   TrueVal = ...
01615   //   cmpTY ccX, r1, r2
01616   //   bCC copy1MBB
01617   //   fallthrough --> copy0MBB
01618   MachineBasicBlock *thisMBB = BB;
01619   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
01620   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
01621   BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
01622     .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
01623   MachineFunction *F = BB->getParent();
01624   F->getBasicBlockList().insert(It, copy0MBB);
01625   F->getBasicBlockList().insert(It, sinkMBB);
01626   // Update machine-CFG edges by first adding all successors of the current
01627   // block to the new block which will contain the Phi node for the select.
01628   for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 
01629       e = BB->succ_end(); i != e; ++i)
01630     sinkMBB->addSuccessor(*i);
01631   // Next, remove all successors of the current block, and add the true
01632   // and fallthrough blocks as its successors.
01633   while(!BB->succ_empty())
01634     BB->removeSuccessor(BB->succ_begin());
01635   BB->addSuccessor(copy0MBB);
01636   BB->addSuccessor(sinkMBB);
01637   
01638   //  copy0MBB:
01639   //   %FalseValue = ...
01640   //   # fallthrough to sinkMBB
01641   BB = copy0MBB;
01642   
01643   // Update machine-CFG edges
01644   BB->addSuccessor(sinkMBB);
01645   
01646   //  sinkMBB:
01647   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
01648   //  ...
01649   BB = sinkMBB;
01650   BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
01651     .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
01652     .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
01653 
01654   delete MI;   // The pseudo instruction is gone now.
01655   return BB;
01656 }
01657 
01658 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 
01659                                                DAGCombinerInfo &DCI) const {
01660   TargetMachine &TM = getTargetMachine();
01661   SelectionDAG &DAG = DCI.DAG;
01662   switch (N->getOpcode()) {
01663   default: break;
01664   case ISD::SINT_TO_FP:
01665     if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
01666       if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
01667         // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
01668         // We allow the src/dst to be either f32/f64, but the intermediate
01669         // type must be i64.
01670         if (N->getOperand(0).getValueType() == MVT::i64) {
01671           SDOperand Val = N->getOperand(0).getOperand(0);
01672           if (Val.getValueType() == MVT::f32) {
01673             Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
01674             DCI.AddToWorklist(Val.Val);
01675           }
01676             
01677           Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
01678           DCI.AddToWorklist(Val.Val);
01679           Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
01680           DCI.AddToWorklist(Val.Val);
01681           if (N->getValueType(0) == MVT::f32) {
01682             Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
01683             DCI.AddToWorklist(Val.Val);
01684           }
01685           return Val;
01686         } else if (N->getOperand(0).getValueType() == MVT::i32) {
01687           // If the intermediate type is i32, we can avoid the load/store here
01688           // too.
01689         }
01690       }
01691     }
01692     break;
01693   case ISD::STORE:
01694     // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
01695     if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
01696         N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
01697         N->getOperand(1).getValueType() == MVT::i32) {
01698       SDOperand Val = N->getOperand(1).getOperand(0);
01699       if (Val.getValueType() == MVT::f32) {
01700         Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
01701         DCI.AddToWorklist(Val.Val);
01702       }
01703       Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
01704       DCI.AddToWorklist(Val.Val);
01705 
01706       Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
01707                         N->getOperand(2), N->getOperand(3));
01708       DCI.AddToWorklist(Val.Val);
01709       return Val;
01710     }
01711     break;
01712   case PPCISD::VCMP: {
01713     // If a VCMPo node already exists with exactly the same operands as this
01714     // node, use its result instead of this node (VCMPo computes both a CR6 and
01715     // a normal output).
01716     //
01717     if (!N->getOperand(0).hasOneUse() &&
01718         !N->getOperand(1).hasOneUse() &&
01719         !N->getOperand(2).hasOneUse()) {
01720       
01721       // Scan all of the users of the LHS, looking for VCMPo's that match.
01722       SDNode *VCMPoNode = 0;
01723       
01724       SDNode *LHSN = N->getOperand(0).Val;
01725       for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
01726            UI != E; ++UI)
01727         if ((*UI)->getOpcode() == PPCISD::VCMPo &&
01728             (*UI)->getOperand(1) == N->getOperand(1) &&
01729             (*UI)->getOperand(2) == N->getOperand(2) &&
01730             (*UI)->getOperand(0) == N->getOperand(0)) {
01731           VCMPoNode = *UI;
01732           break;
01733         }
01734       
01735       // If there are non-zero uses of the flag value, use the VCMPo node!
01736       if (VCMPoNode && !VCMPoNode->hasNUsesOfValue(0, 1))
01737         return SDOperand(VCMPoNode, 0);
01738     }
01739     break;
01740   }
01741   }
01742   
01743   return SDOperand();
01744 }
01745 
01746 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
01747                                                        uint64_t Mask,
01748                                                        uint64_t &KnownZero, 
01749                                                        uint64_t &KnownOne,
01750                                                        unsigned Depth) const {
01751   KnownZero = 0;
01752   KnownOne = 0;
01753   switch (Op.getOpcode()) {
01754   default: break;
01755   case ISD::INTRINSIC_WO_CHAIN: {
01756     switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
01757     default: break;
01758     case Intrinsic::ppc_altivec_vcmpbfp_p:
01759     case Intrinsic::ppc_altivec_vcmpeqfp_p:
01760     case Intrinsic::ppc_altivec_vcmpequb_p:
01761     case Intrinsic::ppc_altivec_vcmpequh_p:
01762     case Intrinsic::ppc_altivec_vcmpequw_p:
01763     case Intrinsic::ppc_altivec_vcmpgefp_p:
01764     case Intrinsic::ppc_altivec_vcmpgtfp_p:
01765     case Intrinsic::ppc_altivec_vcmpgtsb_p:
01766     case Intrinsic::ppc_altivec_vcmpgtsh_p:
01767     case Intrinsic::ppc_altivec_vcmpgtsw_p:
01768     case Intrinsic::ppc_altivec_vcmpgtub_p:
01769     case Intrinsic::ppc_altivec_vcmpgtuh_p:
01770     case Intrinsic::ppc_altivec_vcmpgtuw_p:
01771       KnownZero = ~1U;  // All bits but the low one are known to be zero.
01772       break;
01773     }        
01774   }
01775   }
01776 }
01777 
01778 
01779 /// getConstraintType - Given a constraint letter, return the type of
01780 /// constraint it is for this target.
01781 PPCTargetLowering::ConstraintType 
01782 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
01783   switch (ConstraintLetter) {
01784   default: break;
01785   case 'b':
01786   case 'r':
01787   case 'f':
01788   case 'v':
01789   case 'y':
01790     return C_RegisterClass;
01791   }  
01792   return TargetLowering::getConstraintType(ConstraintLetter);
01793 }
01794 
01795 
01796 std::vector<unsigned> PPCTargetLowering::
01797 getRegClassForInlineAsmConstraint(const std::string &Constraint,
01798                                   MVT::ValueType VT) const {
01799   if (Constraint.size() == 1) {
01800     switch (Constraint[0]) {      // GCC RS6000 Constraint Letters
01801     default: break;  // Unknown constriant letter
01802     case 'b': 
01803       return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
01804                                    PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
01805                                    PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 
01806                                    PPC::R12, PPC::R13, PPC::R14, PPC::R15, 
01807                                    PPC::R16, PPC::R17, PPC::R18, PPC::R19, 
01808                                    PPC::R20, PPC::R21, PPC::R22, PPC::R23, 
01809                                    PPC::R24, PPC::R25, PPC::R26, PPC::R27, 
01810                                    PPC::R28, PPC::R29, PPC::R30, PPC::R31, 
01811                                    0);
01812     case 'r': 
01813       return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
01814                                    PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
01815                                    PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 
01816                                    PPC::R12, PPC::R13, PPC::R14, PPC::R15, 
01817                                    PPC::R16, PPC::R17, PPC::R18, PPC::R19, 
01818                                    PPC::R20, PPC::R21, PPC::R22, PPC::R23, 
01819                                    PPC::R24, PPC::R25, PPC::R26, PPC::R27, 
01820                                    PPC::R28, PPC::R29, PPC::R30, PPC::R31, 
01821                                    0);
01822     case 'f': 
01823       return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
01824                                    PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
01825                                    PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, 
01826                                    PPC::F12, PPC::F13, PPC::F14, PPC::F15, 
01827                                    PPC::F16, PPC::F17, PPC::F18, PPC::F19, 
01828                                    PPC::F20, PPC::F21, PPC::F22, PPC::F23, 
01829                                    PPC::F24, PPC::F25, PPC::F26, PPC::F27, 
01830                                    PPC::F28, PPC::F29, PPC::F30, PPC::F31, 
01831                                    0);
01832     case 'v': 
01833       return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
01834                                    PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
01835                                    PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, 
01836                                    PPC::V12, PPC::V13, PPC::V14, PPC::V15, 
01837                                    PPC::V16, PPC::V17, PPC::V18, PPC::V19, 
01838                                    PPC::V20, PPC::V21, PPC::V22, PPC::V23, 
01839                                    PPC::V24, PPC::V25, PPC::V26, PPC::V27, 
01840                                    PPC::V28, PPC::V29, PPC::V30, PPC::V31, 
01841                                    0);
01842     case 'y': 
01843       return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
01844                                    PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
01845                                    0);
01846     }
01847   }
01848   
01849   return std::vector<unsigned>();
01850 }
01851 
01852 // isOperandValidForConstraint
01853 bool PPCTargetLowering::
01854 isOperandValidForConstraint(SDOperand Op, char Letter) {
01855   switch (Letter) {
01856   default: break;
01857   case 'I':
01858   case 'J':
01859   case 'K':
01860   case 'L':
01861   case 'M':
01862   case 'N':
01863   case 'O':
01864   case 'P': {
01865     if (!isa<ConstantSDNode>(Op)) return false;  // Must be an immediate.
01866     unsigned Value = cast<ConstantSDNode>(Op)->getValue();
01867     switch (Letter) {
01868     default: assert(0 && "Unknown constraint letter!");
01869     case 'I':  // "I" is a signed 16-bit constant.
01870       return (short)Value == (int)Value;
01871     case 'J':  // "J" is a constant with only the high-order 16 bits nonzero.
01872     case 'L':  // "L" is a signed 16-bit constant shifted left 16 bits.
01873       return (short)Value == 0;
01874     case 'K':  // "K" is a constant with only the low-order 16 bits nonzero.
01875       return (Value >> 16) == 0;
01876     case 'M':  // "M" is a constant that is greater than 31.
01877       return Value > 31;
01878     case 'N':  // "N" is a positive constant that is an exact power of two.
01879       return (int)Value > 0 && isPowerOf2_32(Value);
01880     case 'O':  // "O" is the constant zero. 
01881       return Value == 0;
01882     case 'P':  // "P" is a constant whose negation is a signed 16-bit constant.
01883       return (short)-Value == (int)-Value;
01884     }
01885     break;
01886   }
01887   }
01888   
01889   // Handle standard constraint letters.
01890   return TargetLowering::isOperandValidForConstraint(Op, Letter);
01891 }
01892 
01893 /// isLegalAddressImmediate - Return true if the integer value can be used
01894 /// as the offset of the target addressing mode.
01895 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
01896   // PPC allows a sign-extended 16-bit immediate field.
01897   return (V > -(1 << 16) && V < (1 << 16)-1);
01898 }