LLVM API Documentation

X86RegisterInfo.cpp

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00001 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of the MRegisterInfo class.  This
00011 // file is responsible for the frame pointer elimination optimization on X86.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "X86.h"
00016 #include "X86RegisterInfo.h"
00017 #include "X86InstrBuilder.h"
00018 #include "llvm/Constants.h"
00019 #include "llvm/Type.h"
00020 #include "llvm/CodeGen/ValueTypes.h"
00021 #include "llvm/CodeGen/MachineInstrBuilder.h"
00022 #include "llvm/CodeGen/MachineFunction.h"
00023 #include "llvm/CodeGen/MachineFrameInfo.h"
00024 #include "llvm/CodeGen/MachineLocation.h"
00025 #include "llvm/Target/TargetFrameInfo.h"
00026 #include "llvm/Target/TargetMachine.h"
00027 #include "llvm/Target/TargetOptions.h"
00028 #include "llvm/Support/CommandLine.h"
00029 #include "llvm/ADT/STLExtras.h"
00030 #include <iostream>
00031 
00032 using namespace llvm;
00033 
00034 namespace {
00035   cl::opt<bool>
00036   NoFusing("disable-spill-fusing",
00037            cl::desc("Disable fusing of spill code into instructions"));
00038   cl::opt<bool>
00039   PrintFailedFusing("print-failed-fuse-candidates",
00040                     cl::desc("Print instructions that the allocator wants to"
00041                              " fuse, but the X86 backend currently can't"),
00042                     cl::Hidden);
00043 }
00044 
00045 X86RegisterInfo::X86RegisterInfo()
00046   : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
00047 
00048 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
00049                                           MachineBasicBlock::iterator MI,
00050                                           unsigned SrcReg, int FrameIdx,
00051                                           const TargetRegisterClass *RC) const {
00052   unsigned Opc;
00053   if (RC == &X86::R32RegClass) {
00054     Opc = X86::MOV32mr;
00055   } else if (RC == &X86::R8RegClass) {
00056     Opc = X86::MOV8mr;
00057   } else if (RC == &X86::R16RegClass) {
00058     Opc = X86::MOV16mr;
00059   } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
00060     Opc = X86::FpST64m;
00061   } else if (RC == &X86::FR32RegClass) {
00062     Opc = X86::MOVSSmr;
00063   } else if (RC == &X86::FR64RegClass) {
00064     Opc = X86::MOVSDmr;
00065   } else if (RC == &X86::VR128RegClass) {
00066     Opc = X86::MOVAPDmr;
00067   } else {
00068     assert(0 && "Unknown regclass");
00069     abort();
00070   }
00071   addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
00072 }
00073 
00074 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
00075                                            MachineBasicBlock::iterator MI,
00076                                            unsigned DestReg, int FrameIdx,
00077                                            const TargetRegisterClass *RC) const{
00078   unsigned Opc;
00079   if (RC == &X86::R32RegClass) {
00080     Opc = X86::MOV32rm;
00081   } else if (RC == &X86::R8RegClass) {
00082     Opc = X86::MOV8rm;
00083   } else if (RC == &X86::R16RegClass) {
00084     Opc = X86::MOV16rm;
00085   } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
00086     Opc = X86::FpLD64m;
00087   } else if (RC == &X86::FR32RegClass) {
00088     Opc = X86::MOVSSrm;
00089   } else if (RC == &X86::FR64RegClass) {
00090     Opc = X86::MOVSDrm;
00091   } else if (RC == &X86::VR128RegClass) {
00092     Opc = X86::MOVAPDrm;
00093   } else {
00094     assert(0 && "Unknown regclass");
00095     abort();
00096   }
00097   addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
00098 }
00099 
00100 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
00101                                    MachineBasicBlock::iterator MI,
00102                                    unsigned DestReg, unsigned SrcReg,
00103                                    const TargetRegisterClass *RC) const {
00104   unsigned Opc;
00105   if (RC == &X86::R32RegClass) {
00106     Opc = X86::MOV32rr;
00107   } else if (RC == &X86::R8RegClass) {
00108     Opc = X86::MOV8rr;
00109   } else if (RC == &X86::R16RegClass) {
00110     Opc = X86::MOV16rr;
00111   } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
00112     Opc = X86::FpMOV;
00113   } else if (RC == &X86::FR32RegClass) {
00114     Opc = X86::FsMOVAPSrr;
00115   } else if (RC == &X86::FR64RegClass) {
00116     Opc = X86::FsMOVAPDrr;
00117   } else if (RC == &X86::VR128RegClass) {
00118     Opc = X86::MOVAPSrr;
00119   } else {
00120     assert(0 && "Unknown regclass");
00121     abort();
00122   }
00123   BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
00124 }
00125 
00126 
00127 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
00128                                MachineInstr *MI) {
00129   return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
00130 }
00131 
00132 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
00133                                 MachineInstr *MI) {
00134   return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
00135                  .addReg(MI->getOperand(1).getReg());
00136 }
00137 
00138 static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
00139                                  MachineInstr *MI) {
00140   return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
00141       .addReg(MI->getOperand(1).getReg())
00142       .addZImm(MI->getOperand(2).getImmedValue());
00143 }
00144 
00145 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
00146                                 MachineInstr *MI) {
00147   if (MI->getOperand(1).isImmediate())
00148     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
00149       .addZImm(MI->getOperand(1).getImmedValue());
00150   else if (MI->getOperand(1).isGlobalAddress())
00151     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
00152       .addGlobalAddress(MI->getOperand(1).getGlobal(),
00153                         false, MI->getOperand(1).getOffset());
00154   assert(0 && "Unknown operand for MakeMI!");
00155   return 0;
00156 }
00157 
00158 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
00159                                 MachineInstr *MI) {
00160   return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0);
00161 }
00162 
00163 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
00164                                 MachineInstr *MI) {
00165   const MachineOperand& op = MI->getOperand(0);
00166   return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
00167                            FrameIndex);
00168 }
00169 
00170 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
00171                                  MachineInstr *MI) {
00172   const MachineOperand& op = MI->getOperand(0);
00173   return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
00174                         FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
00175 }
00176 
00177 
00178 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
00179                                                  unsigned i,
00180                                                  int FrameIndex) const {
00181   if (NoFusing) return NULL;
00182 
00183   /// FIXME: This should obviously be autogenerated by tablegen when patterns
00184   /// are available!
00185   MachineBasicBlock& MBB = *MI->getParent();
00186   if (i == 0) {
00187     switch(MI->getOpcode()) {
00188     case X86::XCHG8rr:   return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
00189     case X86::XCHG16rr:  return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
00190     case X86::XCHG32rr:  return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
00191     case X86::MOV8rr:    return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
00192     case X86::MOV16rr:   return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
00193     case X86::MOV32rr:   return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
00194     case X86::MOV8ri:    return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
00195     case X86::MOV16ri:   return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
00196     case X86::MOV32ri:   return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
00197     case X86::MUL8r:     return MakeMInst( X86::MUL8m ,  FrameIndex, MI);
00198     case X86::MUL16r:    return MakeMInst( X86::MUL16m,  FrameIndex, MI);
00199     case X86::MUL32r:    return MakeMInst( X86::MUL32m,  FrameIndex, MI);
00200     case X86::IMUL8r:    return MakeMInst( X86::IMUL8m , FrameIndex, MI);
00201     case X86::IMUL16r:   return MakeMInst( X86::IMUL16m, FrameIndex, MI);
00202     case X86::IMUL32r:   return MakeMInst( X86::IMUL32m, FrameIndex, MI);
00203     case X86::DIV8r:     return MakeMInst( X86::DIV8m ,  FrameIndex, MI);
00204     case X86::DIV16r:    return MakeMInst( X86::DIV16m,  FrameIndex, MI);
00205     case X86::DIV32r:    return MakeMInst( X86::DIV32m,  FrameIndex, MI);
00206     case X86::IDIV8r:    return MakeMInst( X86::IDIV8m , FrameIndex, MI);
00207     case X86::IDIV16r:   return MakeMInst( X86::IDIV16m, FrameIndex, MI);
00208     case X86::IDIV32r:   return MakeMInst( X86::IDIV32m, FrameIndex, MI);
00209     case X86::NEG8r:     return MakeMInst( X86::NEG8m ,  FrameIndex, MI);
00210     case X86::NEG16r:    return MakeMInst( X86::NEG16m,  FrameIndex, MI);
00211     case X86::NEG32r:    return MakeMInst( X86::NEG32m,  FrameIndex, MI);
00212     case X86::NOT8r:     return MakeMInst( X86::NOT8m ,  FrameIndex, MI);
00213     case X86::NOT16r:    return MakeMInst( X86::NOT16m,  FrameIndex, MI);
00214     case X86::NOT32r:    return MakeMInst( X86::NOT32m,  FrameIndex, MI);
00215     case X86::INC8r:     return MakeMInst( X86::INC8m ,  FrameIndex, MI);
00216     case X86::INC16r:    return MakeMInst( X86::INC16m,  FrameIndex, MI);
00217     case X86::INC32r:    return MakeMInst( X86::INC32m,  FrameIndex, MI);
00218     case X86::DEC8r:     return MakeMInst( X86::DEC8m ,  FrameIndex, MI);
00219     case X86::DEC16r:    return MakeMInst( X86::DEC16m,  FrameIndex, MI);
00220     case X86::DEC32r:    return MakeMInst( X86::DEC32m,  FrameIndex, MI);
00221     case X86::ADD8rr:    return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
00222     case X86::ADD16rr:   return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
00223     case X86::ADD32rr:   return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
00224     case X86::ADD8ri:    return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
00225     case X86::ADD16ri:   return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
00226     case X86::ADD32ri:   return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
00227     case X86::ADD16ri8:  return MakeMIInst(X86::ADD16mi8,FrameIndex, MI);
00228     case X86::ADD32ri8:  return MakeMIInst(X86::ADD32mi8,FrameIndex, MI);
00229     case X86::ADC32rr:   return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
00230     case X86::ADC32ri:   return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
00231     case X86::ADC32ri8:  return MakeMIInst(X86::ADC32mi8,FrameIndex, MI);
00232     case X86::SUB8rr:    return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
00233     case X86::SUB16rr:   return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
00234     case X86::SUB32rr:   return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
00235     case X86::SUB8ri:    return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
00236     case X86::SUB16ri:   return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
00237     case X86::SUB32ri:   return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
00238     case X86::SUB16ri8:  return MakeMIInst(X86::SUB16mi8,FrameIndex, MI);
00239     case X86::SUB32ri8:  return MakeMIInst(X86::SUB32mi8,FrameIndex, MI);
00240     case X86::SBB32rr:   return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
00241     case X86::SBB32ri:   return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
00242     case X86::SBB32ri8:  return MakeMIInst(X86::SBB32mi8,FrameIndex, MI);
00243     case X86::AND8rr:    return MakeMRInst(X86::AND8mr , FrameIndex, MI);
00244     case X86::AND16rr:   return MakeMRInst(X86::AND16mr, FrameIndex, MI);
00245     case X86::AND32rr:   return MakeMRInst(X86::AND32mr, FrameIndex, MI);
00246     case X86::AND8ri:    return MakeMIInst(X86::AND8mi , FrameIndex, MI);
00247     case X86::AND16ri:   return MakeMIInst(X86::AND16mi, FrameIndex, MI);
00248     case X86::AND32ri:   return MakeMIInst(X86::AND32mi, FrameIndex, MI);
00249     case X86::AND16ri8:  return MakeMIInst(X86::AND16mi8,FrameIndex, MI);
00250     case X86::AND32ri8:  return MakeMIInst(X86::AND32mi8,FrameIndex, MI);
00251     case X86::OR8rr:     return MakeMRInst(X86::OR8mr ,  FrameIndex, MI);
00252     case X86::OR16rr:    return MakeMRInst(X86::OR16mr,  FrameIndex, MI);
00253     case X86::OR32rr:    return MakeMRInst(X86::OR32mr,  FrameIndex, MI);
00254     case X86::OR8ri:     return MakeMIInst(X86::OR8mi ,  FrameIndex, MI);
00255     case X86::OR16ri:    return MakeMIInst(X86::OR16mi,  FrameIndex, MI);
00256     case X86::OR32ri:    return MakeMIInst(X86::OR32mi,  FrameIndex, MI);
00257     case X86::OR16ri8:   return MakeMIInst(X86::OR16mi8, FrameIndex, MI);
00258     case X86::OR32ri8:   return MakeMIInst(X86::OR32mi8, FrameIndex, MI);
00259     case X86::XOR8rr:    return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
00260     case X86::XOR16rr:   return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
00261     case X86::XOR32rr:   return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
00262     case X86::XOR8ri:    return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
00263     case X86::XOR16ri:   return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
00264     case X86::XOR32ri:   return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
00265     case X86::XOR16ri8:  return MakeMIInst(X86::XOR16mi8,FrameIndex, MI);
00266     case X86::XOR32ri8:  return MakeMIInst(X86::XOR32mi8,FrameIndex, MI);
00267     case X86::SHL8rCL:   return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
00268     case X86::SHL16rCL:  return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
00269     case X86::SHL32rCL:  return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
00270     case X86::SHL8ri:    return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
00271     case X86::SHL16ri:   return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
00272     case X86::SHL32ri:   return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
00273     case X86::SHR8rCL:   return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
00274     case X86::SHR16rCL:  return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
00275     case X86::SHR32rCL:  return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
00276     case X86::SHR8ri:    return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
00277     case X86::SHR16ri:   return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
00278     case X86::SHR32ri:   return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
00279     case X86::SAR8rCL:   return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
00280     case X86::SAR16rCL:  return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
00281     case X86::SAR32rCL:  return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
00282     case X86::SAR8ri:    return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
00283     case X86::SAR16ri:   return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
00284     case X86::SAR32ri:   return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
00285     case X86::ROL8rCL:   return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
00286     case X86::ROL16rCL:  return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
00287     case X86::ROL32rCL:  return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
00288     case X86::ROL8ri:    return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
00289     case X86::ROL16ri:   return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
00290     case X86::ROL32ri:   return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
00291     case X86::ROR8rCL:   return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
00292     case X86::ROR16rCL:  return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
00293     case X86::ROR32rCL:  return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
00294     case X86::ROR8ri:    return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
00295     case X86::ROR16ri:   return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
00296     case X86::ROR32ri:   return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
00297     case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
00298     case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
00299     case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
00300     case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
00301     case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI);
00302     case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI);
00303     case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI);
00304     case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI);
00305     case X86::SETBr:     return MakeMInst( X86::SETBm,   FrameIndex, MI);
00306     case X86::SETAEr:    return MakeMInst( X86::SETAEm,  FrameIndex, MI);
00307     case X86::SETEr:     return MakeMInst( X86::SETEm,   FrameIndex, MI);
00308     case X86::SETNEr:    return MakeMInst( X86::SETNEm,  FrameIndex, MI);
00309     case X86::SETBEr:    return MakeMInst( X86::SETBEm,  FrameIndex, MI);
00310     case X86::SETAr:     return MakeMInst( X86::SETAm,   FrameIndex, MI);
00311     case X86::SETSr:     return MakeMInst( X86::SETSm,   FrameIndex, MI);
00312     case X86::SETNSr:    return MakeMInst( X86::SETNSm,  FrameIndex, MI);
00313     case X86::SETPr:     return MakeMInst( X86::SETPm,   FrameIndex, MI);
00314     case X86::SETNPr:    return MakeMInst( X86::SETNPm,  FrameIndex, MI);
00315     case X86::SETLr:     return MakeMInst( X86::SETLm,   FrameIndex, MI);
00316     case X86::SETGEr:    return MakeMInst( X86::SETGEm,  FrameIndex, MI);
00317     case X86::SETLEr:    return MakeMInst( X86::SETLEm,  FrameIndex, MI);
00318     case X86::SETGr:     return MakeMInst( X86::SETGm,   FrameIndex, MI);
00319     case X86::TEST8rr:   return MakeMRInst(X86::TEST8mr ,FrameIndex, MI);
00320     case X86::TEST16rr:  return MakeMRInst(X86::TEST16mr,FrameIndex, MI);
00321     case X86::TEST32rr:  return MakeMRInst(X86::TEST32mr,FrameIndex, MI);
00322     case X86::TEST8ri:   return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
00323     case X86::TEST16ri:  return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
00324     case X86::TEST32ri:  return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
00325     case X86::CMP8rr:    return MakeMRInst(X86::CMP8mr , FrameIndex, MI);
00326     case X86::CMP16rr:   return MakeMRInst(X86::CMP16mr, FrameIndex, MI);
00327     case X86::CMP32rr:   return MakeMRInst(X86::CMP32mr, FrameIndex, MI);
00328     case X86::CMP8ri:    return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
00329     case X86::CMP16ri:   return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
00330     case X86::CMP32ri:   return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
00331     // Alias instructions
00332     case X86::MOV8r0:    return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
00333     case X86::MOV16r0:   return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
00334     case X86::MOV32r0:   return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
00335     // Alias scalar SSE instructions
00336     case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
00337     case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
00338     // Scalar SSE instructions
00339     case X86::MOVSSrr:   return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
00340     case X86::MOVSDrr:   return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
00341 #if 0
00342     // Packed SSE instructions
00343     // FIXME: Can't use these until we are spilling XMM registers to
00344     // 128-bit locations.
00345     case X86::MOVAPSrr:  return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI);
00346     case X86::MOVAPDrr:  return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI);
00347 #endif
00348     }
00349   } else if (i == 1) {
00350     switch(MI->getOpcode()) {
00351     case X86::XCHG8rr:   return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
00352     case X86::XCHG16rr:  return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
00353     case X86::XCHG32rr:  return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
00354     case X86::MOV8rr:    return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
00355     case X86::MOV16rr:   return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
00356     case X86::MOV32rr:   return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
00357     case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
00358     case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
00359     case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
00360     case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
00361     case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
00362     case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
00363     case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
00364     case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
00365     case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
00366     case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
00367     case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
00368     case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
00369     case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
00370     case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
00371     case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
00372     case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
00373     case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI);
00374     case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI);
00375     case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI);
00376     case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI);
00377     case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
00378     case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
00379     case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
00380     case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
00381     case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
00382     case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
00383     case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
00384     case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
00385     case X86::ADD8rr:    return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
00386     case X86::ADD16rr:   return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
00387     case X86::ADD32rr:   return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
00388     case X86::ADC32rr:   return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
00389     case X86::SUB8rr:    return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
00390     case X86::SUB16rr:   return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
00391     case X86::SUB32rr:   return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
00392     case X86::SBB32rr:   return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
00393     case X86::AND8rr:    return MakeRMInst(X86::AND8rm , FrameIndex, MI);
00394     case X86::AND16rr:   return MakeRMInst(X86::AND16rm, FrameIndex, MI);
00395     case X86::AND32rr:   return MakeRMInst(X86::AND32rm, FrameIndex, MI);
00396     case X86::OR8rr:     return MakeRMInst(X86::OR8rm ,  FrameIndex, MI);
00397     case X86::OR16rr:    return MakeRMInst(X86::OR16rm,  FrameIndex, MI);
00398     case X86::OR32rr:    return MakeRMInst(X86::OR32rm,  FrameIndex, MI);
00399     case X86::XOR8rr:    return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
00400     case X86::XOR16rr:   return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
00401     case X86::XOR32rr:   return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
00402     case X86::TEST8rr:   return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
00403     case X86::TEST16rr:  return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
00404     case X86::TEST32rr:  return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
00405     case X86::IMUL16rr:  return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
00406     case X86::IMUL32rr:  return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
00407     case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
00408     case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
00409     case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI);
00410     case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI);
00411     case X86::CMP8rr:    return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
00412     case X86::CMP16rr:   return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
00413     case X86::CMP32rr:   return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
00414     case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
00415     case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
00416     case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
00417     case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
00418     case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
00419     case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
00420     // Alias scalar SSE instructions
00421     case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
00422     case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
00423     // Scalar SSE instructions
00424     case X86::MOVSSrr:   return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
00425     case X86::MOVSDrr:   return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
00426     case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI);
00427     case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI);
00428     case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI);
00429     case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI);
00430     case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI);
00431     case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI);
00432     case X86::SQRTSSr:  return MakeRMInst(X86::SQRTSSm, FrameIndex, MI);
00433     case X86::SQRTSDr:  return MakeRMInst(X86::SQRTSDm, FrameIndex, MI);
00434     case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI);
00435     case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI);
00436     case X86::ADDSSrr:   return MakeRMInst(X86::ADDSSrm, FrameIndex, MI);
00437     case X86::ADDSDrr:   return MakeRMInst(X86::ADDSDrm, FrameIndex, MI);
00438     case X86::MULSSrr:   return MakeRMInst(X86::MULSSrm, FrameIndex, MI);
00439     case X86::MULSDrr:   return MakeRMInst(X86::MULSDrm, FrameIndex, MI);
00440     case X86::DIVSSrr:   return MakeRMInst(X86::DIVSSrm, FrameIndex, MI);
00441     case X86::DIVSDrr:   return MakeRMInst(X86::DIVSDrm, FrameIndex, MI);
00442     case X86::SUBSSrr:   return MakeRMInst(X86::SUBSSrm, FrameIndex, MI);
00443     case X86::SUBSDrr:   return MakeRMInst(X86::SUBSDrm, FrameIndex, MI);
00444     case X86::CMPSSrr:   return MakeRMInst(X86::CMPSSrm, FrameIndex, MI);
00445     case X86::CMPSDrr:   return MakeRMInst(X86::CMPSDrm, FrameIndex, MI);
00446 #if 0
00447     // Packed SSE instructions
00448     // FIXME: Can't use these until we are spilling XMM registers to
00449     // 128-bit locations.
00450     case X86::ANDPSrr:   return MakeRMInst(X86::ANDPSrm, FrameIndex, MI);
00451     case X86::ANDPDrr:   return MakeRMInst(X86::ANDPDrm, FrameIndex, MI);
00452     case X86::ORPSrr:    return MakeRMInst(X86::ORPSrm, FrameIndex, MI);
00453     case X86::ORPDrr:    return MakeRMInst(X86::ORPDrm, FrameIndex, MI);
00454     case X86::XORPSrr:   return MakeRMInst(X86::XORPSrm, FrameIndex, MI);
00455     case X86::XORPDrr:   return MakeRMInst(X86::XORPDrm, FrameIndex, MI);
00456     case X86::ANDNPSrr:  return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI);
00457     case X86::ANDNPDrr:  return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI);
00458     case X86::MOVAPSrr:  return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI);
00459     case X86::MOVAPDrr:  return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI);
00460 #endif
00461     }
00462   }
00463   if (PrintFailedFusing)
00464     std::cerr << "We failed to fuse: " << *MI;
00465   return NULL;
00466 }
00467 
00468 //===----------------------------------------------------------------------===//
00469 // Stack Frame Processing methods
00470 //===----------------------------------------------------------------------===//
00471 
00472 // hasFP - Return true if the specified function should have a dedicated frame
00473 // pointer register.  This is true if the function has variable sized allocas or
00474 // if frame pointer elimination is disabled.
00475 //
00476 static bool hasFP(MachineFunction &MF) {
00477   return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
00478 }
00479 
00480 void X86RegisterInfo::
00481 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
00482                               MachineBasicBlock::iterator I) const {
00483   if (hasFP(MF)) {
00484     // If we have a frame pointer, turn the adjcallstackup instruction into a
00485     // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
00486     // <amt>'
00487     MachineInstr *Old = I;
00488     unsigned Amount = Old->getOperand(0).getImmedValue();
00489     if (Amount != 0) {
00490       // We need to keep the stack aligned properly.  To do this, we round the
00491       // amount of space needed for the outgoing arguments up to the next
00492       // alignment boundary.
00493       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
00494       Amount = (Amount+Align-1)/Align*Align;
00495 
00496       MachineInstr *New = 0;
00497       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
00498         New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
00499               .addZImm(Amount);
00500       } else {
00501         assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
00502         // factor out the amount the callee already popped.
00503         unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
00504         Amount -= CalleeAmt;
00505         if (Amount) {
00506           unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
00507           New = BuildMI(Opc, 1, X86::ESP,
00508                         MachineOperand::UseAndDef).addZImm(Amount);
00509         }
00510       }
00511 
00512       // Replace the pseudo instruction with a new instruction...
00513       if (New) MBB.insert(I, New);
00514     }
00515   } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
00516     // If we are performing frame pointer elimination and if the callee pops
00517     // something off the stack pointer, add it back.  We do this until we have
00518     // more advanced stack pointer tracking ability.
00519     if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
00520       unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
00521       MachineInstr *New =
00522         BuildMI(Opc, 1, X86::ESP,
00523                 MachineOperand::UseAndDef).addZImm(CalleeAmt);
00524       MBB.insert(I, New);
00525     }
00526   }
00527 
00528   MBB.erase(I);
00529 }
00530 
00531 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
00532   unsigned i = 0;
00533   MachineInstr &MI = *II;
00534   MachineFunction &MF = *MI.getParent()->getParent();
00535   while (!MI.getOperand(i).isFrameIndex()) {
00536     ++i;
00537     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
00538   }
00539 
00540   int FrameIndex = MI.getOperand(i).getFrameIndex();
00541 
00542   // This must be part of a four operand memory reference.  Replace the
00543   // FrameIndex with base register with EBP.  Add add an offset to the offset.
00544   MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
00545 
00546   // Now add the frame object offset to the offset from EBP.
00547   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
00548                MI.getOperand(i+3).getImmedValue()+4;
00549 
00550   if (!hasFP(MF))
00551     Offset += MF.getFrameInfo()->getStackSize();
00552   else
00553     Offset += 4;  // Skip the saved EBP
00554 
00555   MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
00556 }
00557 
00558 void
00559 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
00560   if (hasFP(MF)) {
00561     // Create a frame entry for the EBP register that must be saved.
00562     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
00563     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
00564            "Slot for EBP register must be last in order to be found!");
00565   }
00566 }
00567 
00568 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
00569   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
00570   MachineBasicBlock::iterator MBBI = MBB.begin();
00571   MachineFrameInfo *MFI = MF.getFrameInfo();
00572   MachineInstr *MI;
00573 
00574   // Get the number of bytes to allocate from the FrameInfo
00575   unsigned NumBytes = MFI->getStackSize();
00576   if (hasFP(MF)) {
00577     // Get the offset of the stack slot for the EBP register... which is
00578     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
00579     int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
00580 
00581     if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
00582       unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
00583       MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
00584       MBB.insert(MBBI, MI);
00585     }
00586 
00587     // Save EBP into the appropriate stack slot...
00588     MI = addRegOffset(BuildMI(X86::MOV32mr, 5),    // mov [ESP-<offset>], EBP
00589                       X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
00590     MBB.insert(MBBI, MI);
00591 
00592     // Update EBP with the new base value...
00593     if (NumBytes == 4)    // mov EBP, ESP
00594       MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
00595     else                  // lea EBP, [ESP+StackSize]
00596       MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
00597 
00598     MBB.insert(MBBI, MI);
00599 
00600   } else {
00601     if (MFI->hasCalls()) {
00602       // When we have no frame pointer, we reserve argument space for call sites
00603       // in the function immediately on entry to the current function.  This
00604       // eliminates the need for add/sub ESP brackets around call sites.
00605       //
00606       NumBytes += MFI->getMaxCallFrameSize();
00607 
00608       // Round the size to a multiple of the alignment (don't forget the 4 byte
00609       // offset though).
00610       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
00611       NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
00612     }
00613 
00614     // Update frame info to pretend that this is part of the stack...
00615     MFI->setStackSize(NumBytes);
00616 
00617     if (NumBytes) {
00618       // adjust stack pointer: ESP -= numbytes
00619       unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
00620       MI= BuildMI(Opc, 1, X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes);
00621       MBB.insert(MBBI, MI);
00622     }
00623   }
00624 }
00625 
00626 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
00627                                    MachineBasicBlock &MBB) const {
00628   const MachineFrameInfo *MFI = MF.getFrameInfo();
00629   MachineBasicBlock::iterator MBBI = prior(MBB.end());
00630 
00631   switch (MBBI->getOpcode()) {
00632   case X86::RET:
00633   case X86::RETI:
00634   case X86::TAILJMPd:
00635   case X86::TAILJMPr:
00636   case X86::TAILJMPm: break;  // These are ok
00637   default:
00638     assert(0 && "Can only insert epilog into returning blocks");
00639   }
00640 
00641   if (hasFP(MF)) {
00642     // Get the offset of the stack slot for the EBP register... which is
00643     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
00644     int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
00645 
00646     // mov ESP, EBP
00647     BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
00648 
00649     // pop EBP
00650     BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
00651   } else {
00652     // Get the number of bytes allocated from the FrameInfo...
00653     unsigned NumBytes = MFI->getStackSize();
00654 
00655     if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
00656       // If there is an ADD32ri or SUB32ri of ESP immediately before this
00657       // instruction, merge the two instructions.
00658       if (MBBI != MBB.begin()) {
00659         MachineBasicBlock::iterator PI = prior(MBBI);
00660         if ((PI->getOpcode() == X86::ADD32ri || 
00661              PI->getOpcode() == X86::ADD32ri8) &&
00662             PI->getOperand(0).getReg() == X86::ESP) {
00663           NumBytes += PI->getOperand(1).getImmedValue();
00664           MBB.erase(PI);
00665         } else if ((PI->getOpcode() == X86::SUB32ri ||
00666                     PI->getOpcode() == X86::SUB32ri8) &&
00667                    PI->getOperand(0).getReg() == X86::ESP) {
00668           NumBytes -= PI->getOperand(1).getImmedValue();
00669           MBB.erase(PI);
00670         } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
00671           NumBytes += PI->getOperand(1).getImmedValue();
00672           MBB.erase(PI);
00673         }
00674       }
00675 
00676       if (NumBytes > 0) {
00677         unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
00678         BuildMI(MBB, MBBI, Opc, 2)
00679           .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes);
00680       } else if ((int)NumBytes < 0) {
00681         unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
00682         BuildMI(MBB, MBBI, Opc, 2)
00683           .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes);
00684       }
00685     }
00686   }
00687 }
00688 
00689 unsigned X86RegisterInfo::getRARegister() const {
00690   return X86::ST0;  // use a non-register register
00691 }
00692 
00693 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
00694   return hasFP(MF) ? X86::EBP : X86::ESP;
00695 }
00696 
00697 #include "X86GenRegisterInfo.inc"
00698