LLVM API Documentation
00001 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the X86 implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "X86InstrInfo.h" 00015 #include "X86.h" 00016 #include "X86InstrBuilder.h" 00017 #include "llvm/CodeGen/MachineInstrBuilder.h" 00018 #include "X86GenInstrInfo.inc" 00019 using namespace llvm; 00020 00021 X86InstrInfo::X86InstrInfo() 00022 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) { 00023 } 00024 00025 00026 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 00027 unsigned& sourceReg, 00028 unsigned& destReg) const { 00029 MachineOpCode oc = MI.getOpcode(); 00030 if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr || 00031 oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr || 00032 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || 00033 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || 00034 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || 00035 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || 00036 oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr || 00037 oc == X86::MOVPDI2DIrr) { 00038 assert(MI.getNumOperands() == 2 && 00039 MI.getOperand(0).isRegister() && 00040 MI.getOperand(1).isRegister() && 00041 "invalid register-register move instruction"); 00042 sourceReg = MI.getOperand(1).getReg(); 00043 destReg = MI.getOperand(0).getReg(); 00044 return true; 00045 } 00046 return false; 00047 } 00048 00049 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, 00050 int &FrameIndex) const { 00051 switch (MI->getOpcode()) { 00052 default: break; 00053 case X86::MOV8rm: 00054 case X86::MOV16rm: 00055 case X86::MOV32rm: 00056 case X86::FpLD64m: 00057 case X86::MOVSSrm: 00058 case X86::MOVSDrm: 00059 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && 00060 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && 00061 MI->getOperand(2).getImmedValue() == 1 && 00062 MI->getOperand(3).getReg() == 0 && 00063 MI->getOperand(4).getImmedValue() == 0) { 00064 FrameIndex = MI->getOperand(1).getFrameIndex(); 00065 return MI->getOperand(0).getReg(); 00066 } 00067 break; 00068 } 00069 return 0; 00070 } 00071 00072 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, 00073 int &FrameIndex) const { 00074 switch (MI->getOpcode()) { 00075 default: break; 00076 case X86::MOV8mr: 00077 case X86::MOV16mr: 00078 case X86::MOV32mr: 00079 case X86::FpSTP64m: 00080 case X86::MOVSSmr: 00081 case X86::MOVSDmr: 00082 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && 00083 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && 00084 MI->getOperand(1).getImmedValue() == 1 && 00085 MI->getOperand(2).getReg() == 0 && 00086 MI->getOperand(3).getImmedValue() == 0) { 00087 FrameIndex = MI->getOperand(0).getFrameIndex(); 00088 return MI->getOperand(4).getReg(); 00089 } 00090 break; 00091 } 00092 return 0; 00093 } 00094 00095 00096 00097 /// convertToThreeAddress - This method must be implemented by targets that 00098 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 00099 /// may be able to convert a two-address instruction into a true 00100 /// three-address instruction on demand. This allows the X86 target (for 00101 /// example) to convert ADD and SHL instructions into LEA instructions if they 00102 /// would require register copies due to two-addressness. 00103 /// 00104 /// This method returns a null pointer if the transformation cannot be 00105 /// performed, otherwise it returns the new instruction. 00106 /// 00107 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { 00108 // All instructions input are two-addr instructions. Get the known operands. 00109 unsigned Dest = MI->getOperand(0).getReg(); 00110 unsigned Src = MI->getOperand(1).getReg(); 00111 00112 // FIXME: None of these instructions are promotable to LEAs without 00113 // additional information. In particular, LEA doesn't set the flags that 00114 // add and inc do. :( 00115 return 0; 00116 00117 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 00118 // we have subtarget support, enable the 16-bit LEA generation here. 00119 bool DisableLEA16 = true; 00120 00121 switch (MI->getOpcode()) { 00122 case X86::INC32r: 00123 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); 00124 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1); 00125 case X86::INC16r: 00126 if (DisableLEA16) return 0; 00127 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); 00128 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1); 00129 case X86::DEC32r: 00130 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); 00131 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1); 00132 case X86::DEC16r: 00133 if (DisableLEA16) return 0; 00134 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); 00135 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1); 00136 case X86::ADD32rr: 00137 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 00138 return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src, 00139 MI->getOperand(2).getReg()); 00140 case X86::ADD16rr: 00141 if (DisableLEA16) return 0; 00142 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 00143 return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src, 00144 MI->getOperand(2).getReg()); 00145 case X86::ADD32ri: 00146 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 00147 if (MI->getOperand(2).isImmediate()) 00148 return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 00149 MI->getOperand(2).getImmedValue()); 00150 return 0; 00151 case X86::ADD16ri: 00152 if (DisableLEA16) return 0; 00153 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 00154 if (MI->getOperand(2).isImmediate()) 00155 return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 00156 MI->getOperand(2).getImmedValue()); 00157 break; 00158 00159 case X86::SHL16ri: 00160 if (DisableLEA16) return 0; 00161 case X86::SHL32ri: 00162 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() && 00163 "Unknown shl instruction!"); 00164 unsigned ShAmt = MI->getOperand(2).getImmedValue(); 00165 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 00166 X86AddressMode AM; 00167 AM.Scale = 1 << ShAmt; 00168 AM.IndexReg = Src; 00169 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; 00170 return addFullAddress(BuildMI(Opc, 5, Dest), AM); 00171 } 00172 break; 00173 } 00174 00175 return 0; 00176 } 00177 00178 /// commuteInstruction - We have a few instructions that must be hacked on to 00179 /// commute them. 00180 /// 00181 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { 00182 switch (MI->getOpcode()) { 00183 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 00184 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 00185 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 00186 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 00187 unsigned Opc; 00188 unsigned Size; 00189 switch (MI->getOpcode()) { 00190 default: assert(0 && "Unreachable!"); 00191 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 00192 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 00193 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 00194 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 00195 } 00196 unsigned Amt = MI->getOperand(3).getImmedValue(); 00197 unsigned A = MI->getOperand(0).getReg(); 00198 unsigned B = MI->getOperand(1).getReg(); 00199 unsigned C = MI->getOperand(2).getReg(); 00200 return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt); 00201 } 00202 default: 00203 return TargetInstrInfo::commuteInstruction(MI); 00204 } 00205 } 00206 00207 00208 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB, 00209 MachineBasicBlock& TMBB) const { 00210 BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB); 00211 } 00212 00213 MachineBasicBlock::iterator 00214 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const { 00215 unsigned Opcode = MI->getOpcode(); 00216 assert(isBranch(Opcode) && "MachineInstr must be a branch"); 00217 unsigned ROpcode; 00218 switch (Opcode) { 00219 default: assert(0 && "Cannot reverse unconditional branches!"); 00220 case X86::JB: ROpcode = X86::JAE; break; 00221 case X86::JAE: ROpcode = X86::JB; break; 00222 case X86::JE: ROpcode = X86::JNE; break; 00223 case X86::JNE: ROpcode = X86::JE; break; 00224 case X86::JBE: ROpcode = X86::JA; break; 00225 case X86::JA: ROpcode = X86::JBE; break; 00226 case X86::JS: ROpcode = X86::JNS; break; 00227 case X86::JNS: ROpcode = X86::JS; break; 00228 case X86::JP: ROpcode = X86::JNP; break; 00229 case X86::JNP: ROpcode = X86::JP; break; 00230 case X86::JL: ROpcode = X86::JGE; break; 00231 case X86::JGE: ROpcode = X86::JL; break; 00232 case X86::JLE: ROpcode = X86::JG; break; 00233 case X86::JG: ROpcode = X86::JLE; break; 00234 } 00235 MachineBasicBlock* MBB = MI->getParent(); 00236 MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock(); 00237 return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB); 00238 } 00239