LLVM API Documentation

PPCHazardRecognizers.h

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00001 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Chris Lattner and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines hazard recognizers for scheduling on PowerPC processors.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef PPCHAZRECS_H
00015 #define PPCHAZRECS_H
00016 
00017 #include "llvm/CodeGen/ScheduleDAG.h"
00018 #include "PPCInstrInfo.h"
00019 
00020 namespace llvm {
00021   
00022 /// PPCHazardRecognizer970 - This class defines a finite state automata that
00023 /// models the dispatch logic on the PowerPC 970 (aka G5) processor.  This
00024 /// promotes good dispatch group formation and implements noop insertion to
00025 /// avoid structural hazards that cause significant performance penalties (e.g.
00026 /// setting the CTR register then branching through it within a dispatch group),
00027 /// or storing then loading from the same address within a dispatch group.
00028 class PPCHazardRecognizer970 : public HazardRecognizer {
00029   const TargetInstrInfo &TII;
00030   
00031   unsigned NumIssued;  // Number of insts issued, including advanced cycles.
00032   
00033   // Various things that can cause a structural hazard.
00034   
00035   // HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
00036   bool HasCTRSet;
00037   
00038   // StoredPtr - Keep track of the address of any store.  If we see a load from
00039   // the same address (or one that aliases it), disallow the store.  We can have
00040   // up to four stores in one dispatch group, hence we track up to 4.
00041   //
00042   // This is null if we haven't seen a store yet.  We keep track of both
00043   // operands of the store here, since we support [r+r] and [r+i] addressing.
00044   SDOperand StorePtr1[4], StorePtr2[4];
00045   unsigned  StoreSize[4];
00046   unsigned NumStores;
00047   
00048 public:
00049   PPCHazardRecognizer970(const TargetInstrInfo &TII);
00050   virtual HazardType getHazardType(SDNode *Node);
00051   virtual void EmitInstruction(SDNode *Node);
00052   virtual void AdvanceCycle();
00053   virtual void EmitNoop();
00054   
00055 private:
00056   /// EndDispatchGroup - Called when we are finishing a new dispatch group.
00057   ///
00058   void EndDispatchGroup();
00059   
00060   /// GetInstrType - Classify the specified powerpc opcode according to its
00061   /// pipeline.
00062   PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
00063                                   bool &isFirst, bool &isSingle,bool &isCracked,
00064                                   bool &isLoad, bool &isStore);
00065   
00066   bool isLoadOfStoredAddress(unsigned LoadSize,
00067                              SDOperand Ptr1, SDOperand Ptr2) const;
00068 };
00069 
00070 } // end namespace llvm
00071 
00072 #endif
00073