LLVM API Documentation

SparcGenInstrInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Target Instruction Descriptors
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 static const unsigned EmptyImpList[] = { 0 };
00012 static const unsigned ImplicitList1[] = { SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, 0 };
00013 static const unsigned ImplicitList2[] = { SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O7, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, 0 };
00014 
00015 static const TargetOperandInfo OperandInfo2[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { 0 }, };
00016 static const TargetOperandInfo OperandInfo3[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, };
00017 static const TargetOperandInfo OperandInfo4[] = { { 0 }, };
00018 static const TargetOperandInfo OperandInfo5[] = { { 0 }, { 0 }, };
00019 static const TargetOperandInfo OperandInfo6[] = { { &SP::DFPRegsRegClass }, { &SP::DFPRegsRegClass }, };
00020 static const TargetOperandInfo OperandInfo7[] = { { &SP::FPRegsRegClass }, { &SP::FPRegsRegClass }, };
00021 static const TargetOperandInfo OperandInfo8[] = { { &SP::DFPRegsRegClass }, { &SP::DFPRegsRegClass }, { &SP::DFPRegsRegClass }, };
00022 static const TargetOperandInfo OperandInfo9[] = { { &SP::FPRegsRegClass }, { &SP::FPRegsRegClass }, { &SP::FPRegsRegClass }, };
00023 static const TargetOperandInfo OperandInfo10[] = { { &SP::FPRegsRegClass }, { &SP::DFPRegsRegClass }, };
00024 static const TargetOperandInfo OperandInfo11[] = { { &SP::DFPRegsRegClass }, { &SP::FPRegsRegClass }, };
00025 static const TargetOperandInfo OperandInfo12[] = { { &SP::DFPRegsRegClass }, { &SP::DFPRegsRegClass }, { &SP::DFPRegsRegClass }, { 0 }, };
00026 static const TargetOperandInfo OperandInfo13[] = { { &SP::FPRegsRegClass }, { &SP::FPRegsRegClass }, { &SP::FPRegsRegClass }, { 0 }, };
00027 static const TargetOperandInfo OperandInfo14[] = { { &SP::DFPRegsRegClass }, { &SP::FPRegsRegClass }, { &SP::FPRegsRegClass }, };
00028 static const TargetOperandInfo OperandInfo15[] = { { &SP::DFPRegsRegClass }, };
00029 static const TargetOperandInfo OperandInfo16[] = { { &SP::FPRegsRegClass }, };
00030 static const TargetOperandInfo OperandInfo17[] = { { &SP::IntRegsRegClass }, };
00031 static const TargetOperandInfo OperandInfo18[] = { { &SP::IntRegsRegClass }, { 0 }, };
00032 static const TargetOperandInfo OperandInfo19[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, };
00033 static const TargetOperandInfo OperandInfo20[] = { { &SP::DFPRegsRegClass }, { &SP::IntRegsRegClass }, { 0 }, };
00034 static const TargetOperandInfo OperandInfo21[] = { { &SP::DFPRegsRegClass }, { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, };
00035 static const TargetOperandInfo OperandInfo22[] = { { &SP::FPRegsRegClass }, { &SP::IntRegsRegClass }, { 0 }, };
00036 static const TargetOperandInfo OperandInfo23[] = { { &SP::FPRegsRegClass }, { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, };
00037 static const TargetOperandInfo OperandInfo24[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { 0 }, };
00038 static const TargetOperandInfo OperandInfo25[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { 0 }, { 0 }, };
00039 static const TargetOperandInfo OperandInfo26[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { 0 }, };
00040 static const TargetOperandInfo OperandInfo27[] = { { &SP::IntRegsRegClass }, { 0 }, };
00041 static const TargetOperandInfo OperandInfo28[] = { { &SP::IntRegsRegClass }, { 0 }, { &SP::IntRegsRegClass }, };
00042 static const TargetOperandInfo OperandInfo29[] = { { &SP::IntRegsRegClass }, { 0 }, { &SP::DFPRegsRegClass }, };
00043 static const TargetOperandInfo OperandInfo30[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { &SP::DFPRegsRegClass }, };
00044 static const TargetOperandInfo OperandInfo31[] = { { &SP::IntRegsRegClass }, { 0 }, { &SP::FPRegsRegClass }, };
00045 static const TargetOperandInfo OperandInfo32[] = { { &SP::IntRegsRegClass }, { &SP::IntRegsRegClass }, { &SP::FPRegsRegClass }, };
00046 
00047 static const TargetInstrDescriptor SparcInsts[] = {
00048   { "PHI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #0 = PHI
00049   { "INLINEASM",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #1 = INLINEASM
00050   { "ADDCCri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #2 = ADDCCri
00051   { "ADDCCrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #3 = ADDCCrr
00052   { "ADDXri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #4 = ADDXri
00053   { "ADDXrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #5 = ADDXrr
00054   { "ADDri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #6 = ADDri
00055   { "ADDrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #7 = ADDrr
00056   { "ADJCALLSTACKDOWN", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #8 = ADJCALLSTACKDOWN
00057   { "ADJCALLSTACKUP", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #9 = ADJCALLSTACKUP
00058   { "ANDNri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #10 = ANDNri
00059   { "ANDNrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #11 = ANDNrr
00060   { "ANDri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #12 = ANDri
00061   { "ANDrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #13 = ANDrr
00062   { "BA", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo4 },  // Inst #14 = BA
00063   { "BCOND",  2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #15 = BCOND
00064   { "CALL", 1, -1, 0, false, 0, 0, 0, 0|M_DELAY_SLOT_FLAG|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo4 },  // Inst #16 = CALL
00065   { "FABSD",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #17 = FABSD
00066   { "FABSS",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #18 = FABSS
00067   { "FADDD",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #19 = FADDD
00068   { "FADDS",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #20 = FADDS
00069   { "FBCOND", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo5 },  // Inst #21 = FBCOND
00070   { "FCMPD",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #22 = FCMPD
00071   { "FCMPS",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #23 = FCMPS
00072   { "FDIVD",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #24 = FDIVD
00073   { "FDIVS",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #25 = FDIVS
00074   { "FDTOI",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #26 = FDTOI
00075   { "FDTOS",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo10 },  // Inst #27 = FDTOS
00076   { "FITOD",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #28 = FITOD
00077   { "FITOS",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #29 = FITOS
00078   { "FMOVD",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #30 = FMOVD
00079   { "FMOVD_FCC",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #31 = FMOVD_FCC
00080   { "FMOVD_ICC",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #32 = FMOVD_ICC
00081   { "FMOVS",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #33 = FMOVS
00082   { "FMOVS_FCC",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #34 = FMOVS_FCC
00083   { "FMOVS_ICC",  4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #35 = FMOVS_ICC
00084   { "FMULD",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #36 = FMULD
00085   { "FMULS",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #37 = FMULS
00086   { "FNEGD",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #38 = FNEGD
00087   { "FNEGS",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #39 = FNEGS
00088   { "FSMULD", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo14 },  // Inst #40 = FSMULD
00089   { "FSQRTD", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #41 = FSQRTD
00090   { "FSQRTS", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #42 = FSQRTS
00091   { "FSTOD",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo11 },  // Inst #43 = FSTOD
00092   { "FSTOI",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo7 },  // Inst #44 = FSTOI
00093   { "FSUBD",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo8 },  // Inst #45 = FSUBD
00094   { "FSUBS",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo9 },  // Inst #46 = FSUBS
00095   { "FpABSD", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #47 = FpABSD
00096   { "FpMOVD", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #48 = FpMOVD
00097   { "FpNEGD", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 },  // Inst #49 = FpNEGD
00098   { "IMPLICIT_DEF_DFP", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo15 },  // Inst #50 = IMPLICIT_DEF_DFP
00099   { "IMPLICIT_DEF_FP",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo16 },  // Inst #51 = IMPLICIT_DEF_FP
00100   { "IMPLICIT_DEF_Int", 1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #52 = IMPLICIT_DEF_Int
00101   { "JMPLri", 2, -1, 0, false, 0, 0, 0, 0|M_DELAY_SLOT_FLAG|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo18 },  // Inst #53 = JMPLri
00102   { "JMPLrr", 2, -1, 0, false, 0, 0, 0, 0|M_DELAY_SLOT_FLAG|M_CALL_FLAG, 0, ImplicitList1, ImplicitList2, OperandInfo19 },  // Inst #54 = JMPLrr
00103   { "LDDFri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo20 },  // Inst #55 = LDDFri
00104   { "LDDFrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo21 },  // Inst #56 = LDDFrr
00105   { "LDFri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo22 },  // Inst #57 = LDFri
00106   { "LDFrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo23 },  // Inst #58 = LDFrr
00107   { "LDSBri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #59 = LDSBri
00108   { "LDSBrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #60 = LDSBrr
00109   { "LDSHri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #61 = LDSHri
00110   { "LDSHrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #62 = LDSHrr
00111   { "LDUBri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #63 = LDUBri
00112   { "LDUBrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #64 = LDUBrr
00113   { "LDUHri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #65 = LDUHri
00114   { "LDUHrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #66 = LDUHrr
00115   { "LDri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #67 = LDri
00116   { "LDrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #68 = LDrr
00117   { "LEA_ADDri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo24 },  // Inst #69 = LEA_ADDri
00118   { "MOVFCCri", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo25 },  // Inst #70 = MOVFCCri
00119   { "MOVFCCrr", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo26 },  // Inst #71 = MOVFCCrr
00120   { "MOVICCri", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo25 },  // Inst #72 = MOVICCri
00121   { "MOVICCrr", 4, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpList, EmptyImpList, OperandInfo26 },  // Inst #73 = MOVICCrr
00122   { "NOP",  0, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #74 = NOP
00123   { "ORNri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #75 = ORNri
00124   { "ORNrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #76 = ORNrr
00125   { "ORri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #77 = ORri
00126   { "ORrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #78 = ORrr
00127   { "POPCrr", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #79 = POPCrr
00128   { "RDY",  1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo17 },  // Inst #80 = RDY
00129   { "RESTOREri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #81 = RESTOREri
00130   { "RESTORErr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #82 = RESTORErr
00131   { "RETL", 0, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_DELAY_SLOT_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpList, EmptyImpList, 0 },  // Inst #83 = RETL
00132   { "SAVEri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #84 = SAVEri
00133   { "SAVErr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #85 = SAVErr
00134   { "SDIVri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #86 = SDIVri
00135   { "SDIVrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #87 = SDIVrr
00136   { "SELECT_CC_DFP_FCC",  4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #88 = SELECT_CC_DFP_FCC
00137   { "SELECT_CC_DFP_ICC",  4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo12 },  // Inst #89 = SELECT_CC_DFP_ICC
00138   { "SELECT_CC_FP_FCC", 4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #90 = SELECT_CC_FP_FCC
00139   { "SELECT_CC_FP_ICC", 4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo13 },  // Inst #91 = SELECT_CC_FP_ICC
00140   { "SELECT_CC_Int_FCC",  4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo26 },  // Inst #92 = SELECT_CC_Int_FCC
00141   { "SELECT_CC_Int_ICC",  4, -1, 0, false, 0, 0, 0, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0, EmptyImpList, EmptyImpList, OperandInfo26 },  // Inst #93 = SELECT_CC_Int_ICC
00142   { "SETHIi", 2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo27 },  // Inst #94 = SETHIi
00143   { "SLLri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #95 = SLLri
00144   { "SLLrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #96 = SLLrr
00145   { "SMULri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #97 = SMULri
00146   { "SMULrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #98 = SMULrr
00147   { "SRAri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #99 = SRAri
00148   { "SRArr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #100 = SRArr
00149   { "SRLri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #101 = SRLri
00150   { "SRLrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #102 = SRLrr
00151   { "STBri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #103 = STBri
00152   { "STBrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #104 = STBrr
00153   { "STDFri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo29 },  // Inst #105 = STDFri
00154   { "STDFrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo30 },  // Inst #106 = STDFrr
00155   { "STFri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo31 },  // Inst #107 = STFri
00156   { "STFrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo32 },  // Inst #108 = STFrr
00157   { "STHri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #109 = STHri
00158   { "STHrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #110 = STHrr
00159   { "STri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo28 },  // Inst #111 = STri
00160   { "STrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #112 = STrr
00161   { "SUBCCri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #113 = SUBCCri
00162   { "SUBCCrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #114 = SUBCCrr
00163   { "SUBXCCrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #115 = SUBXCCrr
00164   { "SUBXri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #116 = SUBXri
00165   { "SUBXrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #117 = SUBXrr
00166   { "SUBri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #118 = SUBri
00167   { "SUBrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #119 = SUBrr
00168   { "UDIVri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #120 = UDIVri
00169   { "UDIVrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #121 = UDIVrr
00170   { "UMULri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #122 = UMULri
00171   { "UMULrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #123 = UMULrr
00172   { "WRYri",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo27 },  // Inst #124 = WRYri
00173   { "WRYrr",  2, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo19 },  // Inst #125 = WRYrr
00174   { "XNORri", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #126 = XNORri
00175   { "XNORrr", 3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #127 = XNORrr
00176   { "XORri",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo2 },  // Inst #128 = XORri
00177   { "XORrr",  3, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpList, EmptyImpList, OperandInfo3 },  // Inst #129 = XORrr
00178 };
00179 } // End llvm namespace