LLVM API Documentation
00001 //===-- SparcV9PrologEpilogCodeInserter.cpp - Insert Fn Prolog & Epilog ---===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This is the SparcV9 target's own PrologEpilogInserter. It creates prolog and 00011 // epilog instructions for functions which have not been compiled using "leaf 00012 // function optimizations". These instructions include the SAVE and RESTORE 00013 // instructions used to rotate the SPARC register windows. Prologs are 00014 // attached to the unique function entry, and epilogs are attached to each 00015 // function exit. 00016 // 00017 //===----------------------------------------------------------------------===// 00018 00019 #include "SparcV9Internals.h" 00020 #include "SparcV9RegClassInfo.h" 00021 #include "SparcV9RegisterInfo.h" 00022 #include "SparcV9FrameInfo.h" 00023 #include "MachineFunctionInfo.h" 00024 #include "MachineCodeForInstruction.h" 00025 #include "llvm/CodeGen/MachineFunctionPass.h" 00026 #include "llvm/CodeGen/MachineInstrBuilder.h" 00027 #include "llvm/Pass.h" 00028 #include "llvm/Function.h" 00029 #include "llvm/DerivedTypes.h" 00030 #include "llvm/Intrinsics.h" 00031 00032 namespace llvm { 00033 00034 namespace { 00035 struct InsertPrologEpilogCode : public MachineFunctionPass { 00036 const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; } 00037 00038 bool runOnMachineFunction(MachineFunction &F) { 00039 if (!F.getInfo<SparcV9FunctionInfo>()->isCompiledAsLeafMethod()) { 00040 InsertPrologCode(F); 00041 InsertEpilogCode(F); 00042 } 00043 return false; 00044 } 00045 00046 void InsertPrologCode(MachineFunction &F); 00047 void InsertEpilogCode(MachineFunction &F); 00048 }; 00049 00050 } // End anonymous namespace 00051 00052 static unsigned getStaticStackSize (MachineFunction &MF) { 00053 const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo(); 00054 unsigned staticStackSize = MF.getInfo<SparcV9FunctionInfo>()->getStaticStackSize(); 00055 if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize) 00056 staticStackSize = SparcV9FrameInfo::MinStackFrameSize; 00057 if (unsigned padsz = staticStackSize % 00058 SparcV9FrameInfo::StackFrameSizeAlignment) 00059 staticStackSize += SparcV9FrameInfo::StackFrameSizeAlignment - padsz; 00060 return staticStackSize; 00061 } 00062 00063 void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF) 00064 { 00065 std::vector<MachineInstr*> mvec; 00066 const TargetMachine &TM = MF.getTarget(); 00067 const TargetFrameInfo& frameInfo = *TM.getFrameInfo(); 00068 00069 // The second operand is the stack size. If it does not fit in the 00070 // immediate field, we have to use a free register to hold the size. 00071 // See the comments below for the choice of this register. 00072 unsigned staticStackSize = getStaticStackSize (MF); 00073 int32_t C = - (int) staticStackSize; 00074 int SP = TM.getRegInfo()->getStackPointer(); 00075 if (TM.getInstrInfo()->constantFitsInImmedField(V9::SAVEi,staticStackSize)) { 00076 mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C) 00077 .addMReg(SP, MachineOperand::Def)); 00078 } else { 00079 // We have to put the stack size value into a register before SAVE. 00080 // Use register %g1 since it is volatile across calls. Note that the 00081 // local (%l) and in (%i) registers cannot be used before the SAVE! 00082 // Do this by creating a code sequence equivalent to: 00083 // SETSW -(stackSize), %g1 00084 int uregNum = TM.getRegInfo()->getUnifiedRegNum( 00085 TM.getRegInfo()->getRegClassIDOfType(Type::IntTy), 00086 SparcV9IntRegClass::g1); 00087 00088 MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C) 00089 .addMReg(uregNum, MachineOperand::Def); 00090 M->getOperand(0).markHi32(); 00091 mvec.push_back(M); 00092 00093 M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C) 00094 .addMReg(uregNum, MachineOperand::Def); 00095 M->getOperand(1).markLo32(); 00096 mvec.push_back(M); 00097 00098 M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0) 00099 .addMReg(uregNum, MachineOperand::Def); 00100 mvec.push_back(M); 00101 00102 // Now generate the SAVE using the value in register %g1 00103 M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum) 00104 .addMReg(SP,MachineOperand::Def); 00105 mvec.push_back(M); 00106 } 00107 00108 // For varargs function bodies, insert instructions to copy incoming 00109 // register arguments for the ... list to the stack. 00110 // The first K=6 arguments are always received via int arg regs 00111 // (%i0 ... %i5 if K=6) . 00112 // By copying the varargs arguments to the stack, va_arg() then can 00113 // simply assume that all vararg arguments are in an array on the stack. 00114 if (MF.getFunction()->getFunctionType()->isVarArg()) { 00115 int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams(); 00116 int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs(); 00117 if (numFixedArgs < numArgRegs) { 00118 const TargetFrameInfo &FI = *TM.getFrameInfo(); 00119 int firstArgReg = TM.getRegInfo()->getUnifiedRegNum( 00120 TM.getRegInfo()->getRegClassIDOfType(Type::IntTy), 00121 SparcV9IntRegClass::i0); 00122 int fpReg = SparcV9::i6; 00123 int argSize = 8; 00124 int firstArgOffset= SparcV9FrameInfo::FirstIncomingArgOffsetFromFP; 00125 int nextArgOffset = firstArgOffset + numFixedArgs * argSize; 00126 00127 for (int i=numFixedArgs; i < numArgRegs; ++i) { 00128 mvec.push_back(BuildMI(V9::STXi, 3).addMReg(firstArgReg+i). 00129 addMReg(fpReg).addSImm(nextArgOffset)); 00130 nextArgOffset += argSize; 00131 } 00132 } 00133 } 00134 00135 MF.front().insert(MF.front().begin(), mvec.begin(), mvec.end()); 00136 } 00137 00138 void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF) 00139 { 00140 const TargetMachine &TM = MF.getTarget(); 00141 const TargetInstrInfo &MII = *TM.getInstrInfo(); 00142 00143 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { 00144 MachineBasicBlock &MBB = *I; 00145 const BasicBlock &BB = *I->getBasicBlock(); 00146 const Instruction *TermInst = (Instruction*)BB.getTerminator(); 00147 if (TermInst->getOpcode() == Instruction::Ret) 00148 { 00149 int ZR = TM.getRegInfo()->getZeroRegNum(); 00150 MachineInstr *Restore = 00151 BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0) 00152 .addMReg(ZR, MachineOperand::Def); 00153 00154 MachineCodeForInstruction &termMvec = 00155 MachineCodeForInstruction::get(TermInst); 00156 00157 // Remove the NOPs in the delay slots of the return instruction 00158 unsigned numNOPs = 0; 00159 while (termMvec.back()->getOpcode() == V9::NOP) 00160 { 00161 assert( termMvec.back() == &MBB.back()); 00162 termMvec.pop_back(); 00163 MBB.erase(&MBB.back()); 00164 ++numNOPs; 00165 } 00166 assert(termMvec.back() == &MBB.back()); 00167 00168 // Check that we found the right number of NOPs and have the right 00169 // number of instructions to replace them. 00170 unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode()); 00171 assert(numNOPs == ndelays && "Missing NOPs in delay slots?"); 00172 assert(ndelays == 1 && "Cannot use epilog code for delay slots?"); 00173 00174 // Append the epilog code to the end of the basic block. 00175 MBB.push_back(Restore); 00176 } 00177 } 00178 } 00179 00180 FunctionPass *createPrologEpilogInsertionPass() { 00181 return new InsertPrologEpilogCode(); 00182 } 00183 00184 } // End llvm namespace