LLVM API Documentation

SparcV9BurgISel.cpp

Go to the documentation of this file.
00001 //===- SparcV9BurgISel.cpp - SparcV9 BURG-based Instruction Selector ------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // SparcV9 BURG-based instruction selector. It uses the SSA graph to
00011 // construct a forest of BURG instruction trees (class InstrForest) and then
00012 // uses the BURG-generated tree grammar (BURM) to find the optimal instruction
00013 // sequences for the SparcV9.
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #include "MachineInstrAnnot.h"
00018 #include "SparcV9BurgISel.h"
00019 #include "SparcV9InstrForest.h"
00020 #include "SparcV9Internals.h"
00021 #include "SparcV9TmpInstr.h"
00022 #include "SparcV9FrameInfo.h"
00023 #include "SparcV9RegisterInfo.h"
00024 #include "MachineFunctionInfo.h"
00025 #include "llvm/CodeGen/IntrinsicLowering.h"
00026 #include "llvm/CodeGen/MachineConstantPool.h"
00027 #include "llvm/CodeGen/MachineFunction.h"
00028 #include "llvm/CodeGen/MachineInstr.h"
00029 #include "llvm/CodeGen/MachineInstrBuilder.h"
00030 #include "llvm/Constants.h"
00031 #include "llvm/DerivedTypes.h"
00032 #include "llvm/Instructions.h"
00033 #include "llvm/Intrinsics.h"
00034 #include "llvm/Module.h"
00035 #include "llvm/Pass.h"
00036 #include "llvm/Support/CFG.h"
00037 #include "llvm/Target/TargetInstrInfo.h"
00038 #include "llvm/Target/TargetMachine.h"
00039 #include "llvm/Type.h"
00040 #include "llvm/Config/alloca.h"
00041 #include "llvm/Support/CommandLine.h"
00042 #include "llvm/Support/LeakDetector.h"
00043 #include "llvm/Support/MathExtras.h"
00044 #include "llvm/ADT/STLExtras.h"
00045 #include "llvm/ADT/hash_map"
00046 #include <algorithm>
00047 #include <cmath>
00048 #include <iostream>
00049 using namespace llvm;
00050 
00051 //==------------------------------------------------------------------------==//
00052 //          InstrForest (V9ISel BURG instruction trees) implementation
00053 //==------------------------------------------------------------------------==//
00054 
00055 namespace llvm {
00056 
00057 class InstructionNode : public InstrTreeNode {
00058   bool codeIsFoldedIntoParent;
00059 
00060 public:
00061   InstructionNode(Instruction *_instr);
00062 
00063   Instruction *getInstruction() const {
00064     assert(treeNodeType == NTInstructionNode);
00065     return cast<Instruction>(val);
00066   }
00067 
00068   void markFoldedIntoParent() { codeIsFoldedIntoParent = true; }
00069   bool isFoldedIntoParent()   { return codeIsFoldedIntoParent; }
00070 
00071   // Methods to support type inquiry through isa, cast, and dyn_cast:
00072   static inline bool classof(const InstructionNode *N) { return true; }
00073   static inline bool classof(const InstrTreeNode *N) {
00074     return N->getNodeType() == InstrTreeNode::NTInstructionNode;
00075   }
00076 
00077 protected:
00078   virtual void dumpNode(int indent) const;
00079 };
00080 
00081 class VRegListNode : public InstrTreeNode {
00082 public:
00083   VRegListNode() : InstrTreeNode(NTVRegListNode, 0) { opLabel = VRegListOp; }
00084   // Methods to support type inquiry through isa, cast, and dyn_cast:
00085   static inline bool classof(const VRegListNode  *N) { return true; }
00086   static inline bool classof(const InstrTreeNode *N) {
00087     return N->getNodeType() == InstrTreeNode::NTVRegListNode;
00088   }
00089 protected:
00090   virtual void dumpNode(int indent) const;
00091 };
00092 
00093 class VRegNode : public InstrTreeNode {
00094 public:
00095   VRegNode(Value* _val) : InstrTreeNode(NTVRegNode, _val) {
00096     opLabel = VRegNodeOp;
00097   }
00098   // Methods to support type inquiry through isa, cast, and dyn_cast:
00099   static inline bool classof(const VRegNode  *N) { return true; }
00100   static inline bool classof(const InstrTreeNode *N) {
00101     return N->getNodeType() == InstrTreeNode::NTVRegNode;
00102   }
00103 protected:
00104   virtual void dumpNode(int indent) const;
00105 };
00106 
00107 class ConstantNode : public InstrTreeNode {
00108 public:
00109   ConstantNode(Constant *constVal)
00110     : InstrTreeNode(NTConstNode, (Value*)constVal) {
00111     opLabel = ConstantNodeOp;
00112   }
00113   Constant *getConstVal() const { return (Constant*) val;}
00114   // Methods to support type inquiry through isa, cast, and dyn_cast:
00115   static inline bool classof(const ConstantNode  *N) { return true; }
00116   static inline bool classof(const InstrTreeNode *N) {
00117     return N->getNodeType() == InstrTreeNode::NTConstNode;
00118   }
00119 protected:
00120   virtual void dumpNode(int indent) const;
00121 };
00122 
00123 class LabelNode : public InstrTreeNode {
00124 public:
00125   LabelNode(BasicBlock* BB) : InstrTreeNode(NTLabelNode, (Value*)BB) {
00126     opLabel = LabelNodeOp;
00127   }
00128   BasicBlock *getBasicBlock() const { return (BasicBlock*)val;}
00129   // Methods to support type inquiry through isa, cast, and dyn_cast:
00130   static inline bool classof(const LabelNode     *N) { return true; }
00131   static inline bool classof(const InstrTreeNode *N) {
00132     return N->getNodeType() == InstrTreeNode::NTLabelNode;
00133   }
00134 protected:
00135   virtual void dumpNode(int indent) const;
00136 };
00137 
00138 /// InstrForest -  A forest of instruction trees for a single function.
00139 /// The goal of InstrForest is to group instructions into a single
00140 /// tree if one or more of them might be potentially combined into a
00141 /// single complex instruction in the target machine. We group two
00142 /// instructions O and I if: (1) Instruction O computes an operand used
00143 /// by instruction I, and (2) O and I are part of the same basic block,
00144 /// and (3) O has only a single use, viz., I.
00145 ///
00146 class InstrForest : private hash_map<const Instruction *, InstructionNode*> {
00147 public:
00148   // Use a vector for the root set to get a deterministic iterator
00149   // for stable code generation.  Even though we need to erase nodes
00150   // during forest construction, a vector should still be efficient
00151   // because the elements to erase are nearly always near the end.
00152   typedef std::vector<InstructionNode*> RootSet;
00153   typedef RootSet::      iterator       root_iterator;
00154   typedef RootSet::const_iterator const_root_iterator;
00155 
00156 private:
00157   RootSet treeRoots;
00158 
00159 public:
00160   /*ctor*/      InstrForest     (Function *F);
00161   /*dtor*/      ~InstrForest    ();
00162 
00163   /// getTreeNodeForInstr - Returns the tree node for an Instruction.
00164   ///
00165   inline InstructionNode *getTreeNodeForInstr(Instruction* instr) {
00166     return (*this)[instr];
00167   }
00168 
00169   /// Iterators for the root nodes for all the trees.
00170   ///
00171   const_root_iterator roots_begin() const     { return treeRoots.begin(); }
00172         root_iterator roots_begin()           { return treeRoots.begin(); }
00173   const_root_iterator roots_end  () const     { return treeRoots.end();   }
00174         root_iterator roots_end  ()           { return treeRoots.end();   }
00175 
00176   void dump() const;
00177 
00178 private:
00179   // Methods used to build the instruction forest.
00180   void eraseRoot    (InstructionNode* node);
00181   void setLeftChild (InstrTreeNode* parent, InstrTreeNode* child);
00182   void setRightChild(InstrTreeNode* parent, InstrTreeNode* child);
00183   void setParent    (InstrTreeNode* child,  InstrTreeNode* parent);
00184   void noteTreeNodeForInstr(Instruction* instr, InstructionNode* treeNode);
00185   InstructionNode* buildTreeForInstruction(Instruction* instr);
00186 };
00187 
00188 void InstrTreeNode::dump(int dumpChildren, int indent) const {
00189   dumpNode(indent);
00190 
00191   if (dumpChildren) {
00192     if (LeftChild)
00193       LeftChild->dump(dumpChildren, indent+1);
00194     if (RightChild)
00195       RightChild->dump(dumpChildren, indent+1);
00196   }
00197 }
00198 
00199 InstructionNode::InstructionNode(Instruction* I)
00200   : InstrTreeNode(NTInstructionNode, I), codeIsFoldedIntoParent(false) {
00201   opLabel = I->getOpcode();
00202 
00203   // Distinguish special cases of some instructions such as Ret and Br
00204   //
00205   if (opLabel == Instruction::Ret && cast<ReturnInst>(I)->getReturnValue()) {
00206     opLabel = RetValueOp;                // ret(value) operation
00207   }
00208   else if (opLabel ==Instruction::Br && !cast<BranchInst>(I)->isUnconditional())
00209   {
00210     opLabel = BrCondOp;         // br(cond) operation
00211   } else if (opLabel >= Instruction::SetEQ && opLabel <= Instruction::SetGT) {
00212     opLabel = SetCCOp;          // common label for all SetCC ops
00213   } else if (opLabel == Instruction::Alloca && I->getNumOperands() > 0) {
00214     opLabel = AllocaN;           // Alloca(ptr, N) operation
00215   } else if (opLabel == Instruction::GetElementPtr &&
00216              cast<GetElementPtrInst>(I)->hasIndices()) {
00217     opLabel = opLabel + 100;             // getElem with index vector
00218   } else if (opLabel == Instruction::Xor &&
00219              BinaryOperator::isNot(I)) {
00220     opLabel = (I->getType() == Type::BoolTy)?  NotOp  // boolean Not operator
00221       : BNotOp; // bitwise Not operator
00222   } else if (opLabel == Instruction::And || opLabel == Instruction::Or ||
00223              opLabel == Instruction::Xor) {
00224     // Distinguish bitwise operators from logical operators!
00225     if (I->getType() != Type::BoolTy)
00226       opLabel = opLabel + 100;   // bitwise operator
00227   } else if (opLabel == Instruction::Cast) {
00228     const Type *ITy = I->getType();
00229     switch(ITy->getTypeID())
00230     {
00231     case Type::BoolTyID:    opLabel = ToBoolTy;    break;
00232     case Type::UByteTyID:   opLabel = ToUByteTy;   break;
00233     case Type::SByteTyID:   opLabel = ToSByteTy;   break;
00234     case Type::UShortTyID:  opLabel = ToUShortTy;  break;
00235     case Type::ShortTyID:   opLabel = ToShortTy;   break;
00236     case Type::UIntTyID:    opLabel = ToUIntTy;    break;
00237     case Type::IntTyID:     opLabel = ToIntTy;     break;
00238     case Type::ULongTyID:   opLabel = ToULongTy;   break;
00239     case Type::LongTyID:    opLabel = ToLongTy;    break;
00240     case Type::FloatTyID:   opLabel = ToFloatTy;   break;
00241     case Type::DoubleTyID:  opLabel = ToDoubleTy;  break;
00242     case Type::ArrayTyID:   opLabel = ToArrayTy;   break;
00243     case Type::PointerTyID: opLabel = ToPointerTy; break;
00244     default:
00245       // Just use `Cast' opcode otherwise. It's probably ignored.
00246       break;
00247     }
00248   }
00249 }
00250 
00251 void InstructionNode::dumpNode(int indent) const {
00252   for (int i=0; i < indent; i++)
00253     std::cerr << "    ";
00254   std::cerr << getInstruction()->getOpcodeName()
00255             << " [label " << getOpLabel() << "]" << "\n";
00256 }
00257 
00258 void VRegListNode::dumpNode(int indent) const {
00259   for (int i=0; i < indent; i++)
00260     std::cerr << "    ";
00261 
00262   std::cerr << "List" << "\n";
00263 }
00264 
00265 void VRegNode::dumpNode(int indent) const {
00266   for (int i=0; i < indent; i++)
00267     std::cerr << "    ";
00268     std::cerr << "VReg " << *getValue() << "\n";
00269 }
00270 
00271 void ConstantNode::dumpNode(int indent) const {
00272   for (int i=0; i < indent; i++)
00273     std::cerr << "    ";
00274   std::cerr << "Constant " << *getValue() << "\n";
00275 }
00276 
00277 void LabelNode::dumpNode(int indent) const {
00278   for (int i=0; i < indent; i++)
00279     std::cerr << "    ";
00280 
00281   std::cerr << "Label " << *getValue() << "\n";
00282 }
00283 
00284 /// InstrForest ctor - Create a forest of instruction trees for a
00285 /// single function.
00286 ///
00287 InstrForest::InstrForest(Function *F) {
00288   for (Function::iterator BB = F->begin(), FE = F->end(); BB != FE; ++BB) {
00289     for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
00290       buildTreeForInstruction(I);
00291   }
00292 }
00293 
00294 InstrForest::~InstrForest() {
00295   for_each(treeRoots.begin(), treeRoots.end(), deleter<InstructionNode>);
00296 }
00297 
00298 void InstrForest::dump() const {
00299   for (const_root_iterator I = roots_begin(); I != roots_end(); ++I)
00300     (*I)->dump(/*dumpChildren*/ 1, /*indent*/ 0);
00301 }
00302 
00303 inline void InstrForest::eraseRoot(InstructionNode* node) {
00304   for (RootSet::reverse_iterator RI=treeRoots.rbegin(), RE=treeRoots.rend();
00305        RI != RE; ++RI)
00306     if (*RI == node)
00307       treeRoots.erase(RI.base()-1);
00308 }
00309 
00310 inline void InstrForest::noteTreeNodeForInstr(Instruction *instr,
00311                                               InstructionNode *treeNode) {
00312   (*this)[instr] = treeNode;
00313   treeRoots.push_back(treeNode);        // mark node as root of a new tree
00314 }
00315 
00316 inline void InstrForest::setLeftChild(InstrTreeNode *parent,
00317                                       InstrTreeNode *child) {
00318   parent->LeftChild = child;
00319   child->Parent = parent;
00320   if (InstructionNode* instrNode = dyn_cast<InstructionNode>(child))
00321     eraseRoot(instrNode); // no longer a tree root
00322 }
00323 
00324 inline void InstrForest::setRightChild(InstrTreeNode *parent,
00325                                        InstrTreeNode *child) {
00326   parent->RightChild = child;
00327   child->Parent = parent;
00328   if (InstructionNode* instrNode = dyn_cast<InstructionNode>(child))
00329     eraseRoot(instrNode); // no longer a tree root
00330 }
00331 
00332 InstructionNode* InstrForest::buildTreeForInstruction(Instruction *instr) {
00333   InstructionNode *treeNode = getTreeNodeForInstr(instr);
00334   if (treeNode) {
00335     // treeNode has already been constructed for this instruction
00336     assert(treeNode->getInstruction() == instr);
00337     return treeNode;
00338   }
00339 
00340   // Otherwise, create a new tree node for this instruction.
00341   treeNode = new InstructionNode(instr);
00342   noteTreeNodeForInstr(instr, treeNode);
00343 
00344   if (instr->getOpcode() == Instruction::Call) {
00345     // Operands of call instruction
00346     return treeNode;
00347   }
00348 
00349   // If the instruction has more than 2 instruction operands,
00350   // then we need to create artificial list nodes to hold them.
00351   // (Note that we only count operands that get tree nodes, and not
00352   // others such as branch labels for a branch or switch instruction.)
00353   // To do this efficiently, we'll walk all operands, build treeNodes
00354   // for all appropriate operands and save them in an array.  We then
00355   // insert children at the end, creating list nodes where needed.
00356   // As a performance optimization, allocate a child array only
00357   // if a fixed array is too small.
00358   int numChildren = 0;
00359   InstrTreeNode** childArray = new InstrTreeNode*[instr->getNumOperands()];
00360 
00361   // Walk the operands of the instruction
00362   for (Instruction::op_iterator O = instr->op_begin(); O!=instr->op_end();
00363        ++O) {
00364       Value* operand = *O;
00365 
00366       // Check if the operand is a data value, not an branch label, type,
00367       // method or module.  If the operand is an address type (i.e., label
00368       // or method) that is used in an non-branching operation, e.g., `add'.
00369       // that should be considered a data value.
00370       // Check latter condition here just to simplify the next IF.
00371       bool includeAddressOperand =
00372         (isa<BasicBlock>(operand) || isa<Function>(operand))
00373         && !instr->isTerminator();
00374 
00375       if (includeAddressOperand || isa<Instruction>(operand) ||
00376           isa<Constant>(operand) || isa<Argument>(operand)) {
00377         // This operand is a data value.
00378         // An instruction that computes the incoming value is added as a
00379         // child of the current instruction if:
00380         //   the value has only a single use
00381         //   AND both instructions are in the same basic block.
00382         //   AND the current instruction is not a PHI (because the incoming
00383         //              value is conceptually in a predecessor block,
00384         //              even though it may be in the same static block)
00385         // (Note that if the value has only a single use (viz., `instr'),
00386         //  the def of the value can be safely moved just before instr
00387         //  and therefore it is safe to combine these two instructions.)
00388         // In all other cases, the virtual register holding the value
00389         // is used directly, i.e., made a child of the instruction node.
00390         InstrTreeNode* opTreeNode;
00391         if (isa<Instruction>(operand) && operand->hasOneUse() &&
00392             cast<Instruction>(operand)->getParent() == instr->getParent() &&
00393             instr->getOpcode() != Instruction::PHI &&
00394             instr->getOpcode() != Instruction::Call) {
00395           // Recursively create a treeNode for it.
00396           opTreeNode = buildTreeForInstruction((Instruction*)operand);
00397         } else if (Constant *CPV = dyn_cast<Constant>(operand)) {
00398           if (isa<GlobalValue>(CPV))
00399             opTreeNode = new VRegNode(operand);
00400           else if (isa<UndefValue>(CPV)) {
00401             opTreeNode = new
00402                ConstantNode(Constant::getNullValue(CPV->getType()));
00403           } else {
00404             // Create a leaf node for a constant
00405             opTreeNode = new ConstantNode(CPV);
00406           }
00407         } else {
00408           // Create a leaf node for the virtual register
00409           opTreeNode = new VRegNode(operand);
00410         }
00411 
00412         childArray[numChildren++] = opTreeNode;
00413       }
00414     }
00415 
00416   // Add any selected operands as children in the tree.
00417   // Certain instructions can have more than 2 in some instances (viz.,
00418   // a CALL or a memory access -- LOAD, STORE, and GetElemPtr -- to an
00419   // array or struct). Make the operands of every such instruction into
00420   // a right-leaning binary tree with the operand nodes at the leaves
00421   // and VRegList nodes as internal nodes.
00422   InstrTreeNode *parent = treeNode;
00423 
00424   if (numChildren > 2) {
00425     unsigned instrOpcode = treeNode->getInstruction()->getOpcode();
00426     assert(instrOpcode == Instruction::PHI ||
00427            instrOpcode == Instruction::Call ||
00428            instrOpcode == Instruction::Load ||
00429            instrOpcode == Instruction::Store ||
00430            instrOpcode == Instruction::GetElementPtr);
00431   }
00432 
00433   // Insert the first child as a direct child
00434   if (numChildren >= 1)
00435     setLeftChild(parent, childArray[0]);
00436 
00437   int n;
00438 
00439   // Create a list node for children 2 .. N-1, if any
00440   for (n = numChildren-1; n >= 2; n--) {
00441     // We have more than two children
00442     InstrTreeNode *listNode = new VRegListNode();
00443     setRightChild(parent, listNode);
00444     setLeftChild(listNode, childArray[numChildren - n]);
00445     parent = listNode;
00446   }
00447 
00448   // Now insert the last remaining child (if any).
00449   if (numChildren >= 2) {
00450     assert(n == 1);
00451     setRightChild(parent, childArray[numChildren - 1]);
00452   }
00453 
00454   delete [] childArray;
00455   return treeNode;
00456 }
00457 //==------------------------------------------------------------------------==//
00458 //                V9ISel Command-line options and declarations
00459 //==------------------------------------------------------------------------==//
00460 
00461 namespace {
00462   /// Allow the user to select the amount of debugging information printed
00463   /// out by V9ISel.
00464   ///
00465   enum SelectDebugLevel_t {
00466     Select_NoDebugInfo,
00467     Select_PrintMachineCode,
00468     Select_DebugInstTrees,
00469     Select_DebugBurgTrees,
00470   };
00471   cl::opt<SelectDebugLevel_t>
00472   SelectDebugLevel("dselect", cl::Hidden,
00473                    cl::desc("enable instruction selection debug information"),
00474                    cl::values(
00475      clEnumValN(Select_NoDebugInfo,      "n", "disable debug output"),
00476      clEnumValN(Select_PrintMachineCode, "y", "print generated machine code"),
00477      clEnumValN(Select_DebugInstTrees,   "i",
00478                 "print debugging info for instruction selection"),
00479      clEnumValN(Select_DebugBurgTrees,   "b", "print burg trees"),
00480                               clEnumValEnd));
00481 
00482 
00483   /// V9ISel - This is the FunctionPass that drives the instruction selection
00484   /// process on the SparcV9 target.
00485   ///
00486   class V9ISel : public FunctionPass {
00487     TargetMachine &Target;
00488     void InsertCodeForPhis(Function &F);
00489     void InsertPhiElimInstructions(BasicBlock *BB,
00490                                    const std::vector<MachineInstr*>& CpVec);
00491     void SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt);
00492     void PostprocessMachineCodeForTree(InstructionNode* instrNode,
00493                                        int ruleForNode, short* nts);
00494   public:
00495     V9ISel(TargetMachine &TM) : Target(TM) {}
00496 
00497     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
00498       AU.setPreservesCFG();
00499     }
00500 
00501     bool runOnFunction(Function &F);
00502     virtual const char *getPassName() const {
00503       return "SparcV9 BURG Instruction Selector";
00504     }
00505   };
00506 }
00507 
00508 
00509 //==------------------------------------------------------------------------==//
00510 //                     Various V9ISel helper functions
00511 //==------------------------------------------------------------------------==//
00512 
00513 static const uint32_t MAXLO   = (1 << 10) - 1; // set bits set by %lo(*)
00514 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
00515 
00516 /// ConvertConstantToIntType - Function to get the value of an integral
00517 /// constant in the form that must be put into the machine register.  The
00518 /// specified constant is interpreted as (i.e., converted if necessary to) the
00519 /// specified destination type.  The result is always returned as an uint64_t,
00520 /// since the representation of int64_t and uint64_t are identical.  The
00521 /// argument can be any known const.  isValidConstant is set to true if a valid
00522 /// constant was found.
00523 ///
00524 uint64_t ConvertConstantToIntType(const TargetMachine &target, const Value *V,
00525                                   const Type *destType, bool &isValidConstant) {
00526   isValidConstant = false;
00527   uint64_t C = 0;
00528 
00529   if (! destType->isIntegral() && ! isa<PointerType>(destType))
00530     return C;
00531 
00532   if (! isa<Constant>(V) || isa<GlobalValue>(V))
00533     return C;
00534 
00535   // GlobalValue: no conversions needed: get value and return it
00536   if (const GlobalValue* GV = dyn_cast<GlobalValue>(V)) {
00537     isValidConstant = true;             // may be overwritten by recursive call
00538     return ConvertConstantToIntType(target, GV, destType, isValidConstant);
00539   }
00540 
00541   // ConstantBool: no conversions needed: get value and return it
00542   if (const ConstantBool *CB = dyn_cast<ConstantBool>(V)) {
00543     isValidConstant = true;
00544     return (uint64_t) CB->getValue();
00545   }
00546 
00547   // ConstantPointerNull: it's really just a big, shiny version of zero.
00548   if (isa<ConstantPointerNull>(V)) {
00549     isValidConstant = true;
00550     return 0;
00551   }
00552 
00553   // For other types of constants, some conversion may be needed.
00554   // First, extract the constant operand according to its own type
00555   if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
00556     switch(CE->getOpcode()) {
00557     case Instruction::Cast:             // recursively get the value as cast
00558       C = ConvertConstantToIntType(target, CE->getOperand(0), CE->getType(),
00559                                    isValidConstant);
00560       break;
00561     default:                            // not simplifying other ConstantExprs
00562       break;
00563     }
00564   else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00565     isValidConstant = true;
00566     C = CI->getRawValue();
00567   } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(V)) {
00568     isValidConstant = true;
00569     double fC = CFP->getValue();
00570     C = (destType->isSigned()? (uint64_t) (int64_t) fC
00571                              : (uint64_t)           fC);
00572   } else if (isa<UndefValue>(V)) {
00573     isValidConstant = true;
00574     C = 0;
00575   }
00576 
00577   // Now if a valid value was found, convert it to destType.
00578   if (isValidConstant) {
00579     unsigned opSize   = target.getTargetData().getTypeSize(V->getType());
00580     unsigned destSize = target.getTargetData().getTypeSize(destType);
00581     uint64_t maskHi   = (destSize < 8)? (1U << 8*destSize) - 1 : ~0;
00582     assert(opSize <= 8 && destSize <= 8 && ">8-byte int type unexpected");
00583 
00584     if (destType->isSigned()) {
00585       if (opSize > destSize)            // operand is larger than dest:
00586         C = C & maskHi;                 // mask high bits
00587 
00588       if (opSize > destSize ||
00589           (opSize == destSize && ! V->getType()->isSigned()))
00590         if (C & (1U << (8*destSize - 1)))
00591           C =  C | ~maskHi;             // sign-extend from destSize to 64 bits
00592     }
00593     else {
00594       if (opSize > destSize || (V->getType()->isSigned() && destSize < 8)) {
00595         // operand is larger than dest,
00596         //    OR both are equal but smaller than the full register size
00597         //       AND operand is signed, so it may have extra sign bits:
00598         // mask high bits
00599         C = C & maskHi;
00600       }
00601     }
00602   }
00603 
00604   return C;
00605 }
00606 
00607 /// CreateSETUWConst - Copy a 32-bit unsigned constant into the register
00608 /// `dest', using SETHI, OR in the worst case.  This function correctly emulates
00609 /// the SETUW pseudo-op for SPARC v9 (if argument isSigned == false). The
00610 /// isSigned=true case is used to implement SETSW without duplicating code. It
00611 /// optimizes some common cases:
00612 /// (1) Small value that fits in simm13 field of OR: don't need SETHI.
00613 /// (2) isSigned = true and C is a small negative signed value, i.e.,
00614 ///     high bits are 1, and the remaining bits fit in simm13(OR).
00615 static inline void
00616 CreateSETUWConst(uint32_t C,
00617                  Instruction* dest, std::vector<MachineInstr*>& mvec,
00618                  MachineCodeForInstruction& mcfi, Value* val, bool isSigned = false) {
00619   MachineInstr *miSETHI = NULL, *miOR = NULL;
00620 
00621   // In order to get efficient code, we should not generate the SETHI if
00622   // all high bits are 1 (i.e., this is a small signed value that fits in
00623   // the simm13 field of OR).  So we check for and handle that case specially.
00624   // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
00625   //       In fact, sC == -sC, so we have to check for this explicitly.
00626   int32_t sC = (int32_t) C;
00627   bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
00628 
00629   //Create TmpInstruction for intermediate values
00630   TmpInstruction *tmpReg = 0;
00631 
00632   // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
00633   if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
00634     tmpReg = new TmpInstruction(mcfi, PointerType::get(val->getType()), (Instruction*) val);
00635     miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(tmpReg);
00636     miSETHI->getOperand(0).markHi32();
00637     mvec.push_back(miSETHI);
00638   }
00639 
00640   // Set the low 10 or 12 bits in dest.  This is necessary if no SETHI
00641   // was generated, or if the low 10 bits are non-zero.
00642   if (miSETHI==NULL || C & MAXLO) {
00643     if (miSETHI) {
00644       // unsigned value with high-order bits set using SETHI
00645       miOR = BuildMI(V9::ORi,3).addReg(tmpReg).addZImm(C).addRegDef(dest);
00646       miOR->getOperand(1).markLo32();
00647     } else {
00648       // unsigned or small signed value that fits in simm13 field of OR
00649       assert(smallNegValue || (C & ~MAXSIMM) == 0);
00650       miOR = BuildMI(V9::ORi, 3).addMReg(SparcV9::g0)
00651         .addSImm(sC).addRegDef(dest);
00652     }
00653     mvec.push_back(miOR);
00654   }
00655   else
00656     mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg).addMReg(SparcV9::g0).addRegDef(dest));
00657 
00658   assert((miSETHI || miOR) && "Oops, no code was generated!");
00659 }
00660 
00661 /// CreateSETSWConst - Set a 32-bit signed constant in the register `dest',
00662 /// with sign-extension to 64 bits.  This uses SETHI, OR, SRA in the worst case.
00663 /// This function correctly emulates the SETSW pseudo-op for SPARC v9.  It
00664 /// optimizes the same cases as SETUWConst, plus:
00665 /// (1) SRA is not needed for positive or small negative values.
00666 ///
00667 static inline void
00668 CreateSETSWConst(int32_t C,
00669                  Instruction* dest, std::vector<MachineInstr*>& mvec,
00670                  MachineCodeForInstruction& mcfi, Value* val) {
00671 
00672   //TmpInstruction for intermediate values
00673   TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val);
00674 
00675   // Set the low 32 bits of dest
00676   CreateSETUWConst((uint32_t) C,  tmpReg, mvec, mcfi, val, /*isSigned*/true);
00677 
00678   // Sign-extend to the high 32 bits if needed.
00679   // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
00680   if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
00681     mvec.push_back(BuildMI(V9::SRAi5,3).addReg(tmpReg).addZImm(0).addRegDef(dest));
00682   else
00683     mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg).addMReg(SparcV9::g0).addRegDef(dest));
00684 }
00685 
00686 /// CreateSETXConst - Set a 64-bit signed or unsigned constant in the
00687 /// register `dest'.  Use SETUWConst for each 32 bit word, plus a
00688 /// left-shift-by-32 in between.  This function correctly emulates the SETX
00689 /// pseudo-op for SPARC v9.  It optimizes the same cases as SETUWConst for each
00690 /// 32 bit word.
00691 ///
00692 static inline void
00693 CreateSETXConst(uint64_t C,
00694                 Instruction* tmpReg, Instruction* dest,
00695                 std::vector<MachineInstr*>& mvec,
00696                 MachineCodeForInstruction& mcfi, Value* val) {
00697   assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
00698 
00699   MachineInstr* MI;
00700 
00701   // Code to set the upper 32 bits of the value in register `tmpReg'
00702   CreateSETUWConst((C >> 32), tmpReg, mvec, mcfi, val);
00703 
00704   //TmpInstruction for intermediate values
00705   TmpInstruction *tmpReg2 = new TmpInstruction(mcfi, (Instruction*) val);
00706 
00707   // Shift tmpReg left by 32 bits
00708   mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
00709                  .addRegDef(tmpReg2));
00710 
00711   //TmpInstruction for intermediate values
00712   TmpInstruction *tmpReg3 = new TmpInstruction(mcfi, (Instruction*) val);
00713 
00714   // Code to set the low 32 bits of the value in register `dest'
00715   CreateSETUWConst(C, tmpReg3, mvec, mcfi, val);
00716 
00717   // dest = OR(tmpReg, dest)
00718   mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg3).addReg(tmpReg2).addRegDef(dest));
00719 }
00720 
00721 /// CreateSETUWLabel - Set a 32-bit constant (given by a symbolic label) in
00722 /// the register `dest'.
00723 ///
00724 static inline void
00725 CreateSETUWLabel(Value* val,
00726                  Instruction* dest, std::vector<MachineInstr*>& mvec) {
00727   MachineInstr* MI;
00728 
00729   MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get((Instruction*) val);
00730   TmpInstruction* tmpReg = new TmpInstruction(mcfi, val);
00731 
00732   // Set the high 22 bits in dest
00733   MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(tmpReg);
00734   MI->getOperand(0).markHi32();
00735   mvec.push_back(MI);
00736 
00737   // Set the low 10 bits in dest
00738   MI = BuildMI(V9::ORr, 3).addReg(tmpReg).addReg(val).addRegDef(dest);
00739   MI->getOperand(1).markLo32();
00740   mvec.push_back(MI);
00741 }
00742 
00743 /// CreateSETXLabel - Set a 64-bit constant (given by a symbolic label) in the
00744 /// register `dest'.
00745 ///
00746 static inline void
00747 CreateSETXLabel(Value* val, Instruction* tmpReg,
00748                 Instruction* dest, std::vector<MachineInstr*>& mvec,
00749                 MachineCodeForInstruction& mcfi) {
00750   assert(isa<Constant>(val) &&
00751          "I only know about constant values and global addresses");
00752 
00753   MachineInstr* MI;
00754 
00755   MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
00756   MI->getOperand(0).markHi64();
00757   mvec.push_back(MI);
00758 
00759   TmpInstruction* tmpReg2 =
00760         new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
00761 
00762   MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg2);
00763   MI->getOperand(1).markLo64();
00764   mvec.push_back(MI);
00765 
00766 
00767   TmpInstruction* tmpReg3 =
00768         new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
00769 
00770   mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg2).addZImm(32)
00771                  .addRegDef(tmpReg3));
00772 
00773 
00774   TmpInstruction* tmpReg4 =
00775         new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
00776   MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg4);
00777   MI->getOperand(0).markHi32();
00778   mvec.push_back(MI);
00779 
00780     TmpInstruction* tmpReg5 =
00781         new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
00782   MI = BuildMI(V9::ORr, 3).addReg(tmpReg4).addReg(tmpReg3).addRegDef(tmpReg5);
00783   mvec.push_back(MI);
00784 
00785   MI = BuildMI(V9::ORi, 3).addReg(tmpReg5).addPCDisp(val).addRegDef(dest);
00786   MI->getOperand(1).markLo32();
00787   mvec.push_back(MI);
00788 }
00789 
00790 /// CreateUIntSetInstruction - Create code to Set an unsigned constant in the
00791 /// register `dest'.  Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst
00792 /// as needed.  CreateSETSWConst is an optimization for the case that the
00793 /// unsigned value has all ones in the 33 high bits (so that sign-extension sets
00794 /// them all).
00795 ///
00796 static inline void
00797 CreateUIntSetInstruction(uint64_t C, Instruction* dest,
00798                          std::vector<MachineInstr*>& mvec,
00799                          MachineCodeForInstruction& mcfi, Value* val) {
00800   static const uint64_t lo32 = (uint32_t) ~0;
00801   if (C <= lo32)                        // High 32 bits are 0.  Set low 32 bits.
00802     CreateSETUWConst((uint32_t) C, dest, mvec, mcfi, val);
00803   else if ((C & ~lo32) == ~lo32 && (C & (1U << 31))) {
00804     // All high 33 (not 32) bits are 1s: sign-extension will take care
00805     // of high 32 bits, so use the sequence for signed int
00806     CreateSETSWConst((int32_t) C, dest, mvec, mcfi, val);
00807   } else if (C > lo32) {
00808     // C does not fit in 32 bits
00809     TmpInstruction* tmpReg = new TmpInstruction(mcfi, Type::IntTy);
00810     CreateSETXConst(C, tmpReg, dest, mvec, mcfi, val);
00811   }
00812 }
00813 
00814 /// CreateIntSetInstruction - Create code to Set a signed constant in the
00815 /// register `dest'.  Really the same as CreateUIntSetInstruction.
00816 ///
00817 static inline void
00818 CreateIntSetInstruction(int64_t C, Instruction* dest,
00819                         std::vector<MachineInstr*>& mvec,
00820                         MachineCodeForInstruction& mcfi, Value* val) {
00821   CreateUIntSetInstruction((uint64_t) C, dest, mvec, mcfi, val);
00822 }
00823 
00824 /// MaxConstantsTableTy - Table mapping LLVM opcodes to the max. immediate
00825 /// constant usable for that operation in the SparcV9 backend. Used by
00826 /// ConstantMayNotFitInImmedField().
00827 ///
00828 struct MaxConstantsTableTy {
00829   // Entry == 0 ==> no immediate constant field exists at all.
00830   // Entry >  0 ==> abs(immediate constant) <= Entry
00831   std::vector<int> tbl;
00832 
00833   int getMaxConstantForInstr (unsigned llvmOpCode);
00834   MaxConstantsTableTy ();
00835   unsigned size() const            { return tbl.size (); }
00836   int &operator[] (unsigned index) { return tbl[index];  }
00837 };
00838 
00839 int MaxConstantsTableTy::getMaxConstantForInstr(unsigned llvmOpCode) {
00840   int modelOpCode = -1;
00841 
00842   if (llvmOpCode >= Instruction::BinaryOpsBegin &&
00843       llvmOpCode <  Instruction::BinaryOpsEnd)
00844     modelOpCode = V9::ADDi;
00845   else
00846     switch(llvmOpCode) {
00847     case Instruction::Ret:   modelOpCode = V9::JMPLCALLi; break;
00848 
00849     case Instruction::Malloc:
00850     case Instruction::Alloca:
00851     case Instruction::GetElementPtr:
00852     case Instruction::PHI:
00853     case Instruction::Cast:
00854     case Instruction::Call:  modelOpCode = V9::ADDi; break;
00855 
00856     case Instruction::Shl:
00857     case Instruction::Shr:   modelOpCode = V9::SLLXi6; break;
00858 
00859     default: break;
00860     };
00861 
00862   return (modelOpCode < 0)? 0: SparcV9MachineInstrDesc[modelOpCode].maxImmedConst;
00863 }
00864 
00865 MaxConstantsTableTy::MaxConstantsTableTy () : tbl (Instruction::OtherOpsEnd) {
00866   unsigned op;
00867   assert(tbl.size() == Instruction::OtherOpsEnd &&
00868          "assignments below will be illegal!");
00869   for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
00870     tbl[op] = getMaxConstantForInstr(op);
00871   for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
00872     tbl[op] = getMaxConstantForInstr(op);
00873   for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
00874     tbl[op] = getMaxConstantForInstr(op);
00875   for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
00876     tbl[op] = getMaxConstantForInstr(op);
00877 }
00878 
00879 bool ConstantMayNotFitInImmedField(const Constant* CV, const Instruction* I) {
00880   // The one and only MaxConstantsTable, used only by this function.
00881   static MaxConstantsTableTy MaxConstantsTable;
00882 
00883   if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
00884     return true;
00885 
00886   // can always use %g0
00887   if (isa<ConstantPointerNull>(CV) || isa<UndefValue>(CV))
00888     return false;
00889 
00890   if (isa<SwitchInst>(I)) // Switch instructions will be lowered!
00891     return false;
00892 
00893   if (const ConstantInt* CI = dyn_cast<ConstantInt>(CV))
00894     return labs((int64_t)CI->getRawValue()) > MaxConstantsTable[I->getOpcode()];
00895 
00896   if (isa<ConstantBool>(CV))
00897     return 1 > MaxConstantsTable[I->getOpcode()];
00898 
00899   return true;
00900 }
00901 
00902 /// ChooseLoadInstruction - Return the appropriate load instruction opcode
00903 /// based on the given LLVM value type.
00904 ///
00905 static inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) {
00906   switch (DestTy->getTypeID()) {
00907   case Type::BoolTyID:
00908   case Type::UByteTyID:   return V9::LDUBr;
00909   case Type::SByteTyID:   return V9::LDSBr;
00910   case Type::UShortTyID:  return V9::LDUHr;
00911   case Type::ShortTyID:   return V9::LDSHr;
00912   case Type::UIntTyID:    return V9::LDUWr;
00913   case Type::IntTyID:     return V9::LDSWr;
00914   case Type::PointerTyID:
00915   case Type::ULongTyID:
00916   case Type::LongTyID:    return V9::LDXr;
00917   case Type::FloatTyID:   return V9::LDFr;
00918   case Type::DoubleTyID:  return V9::LDDFr;
00919   default: assert(0 && "Invalid type for Load instruction");
00920   }
00921   return 0;
00922 }
00923 
00924 /// ChooseStoreInstruction - Return the appropriate store instruction opcode
00925 /// based on the given LLVM value type.
00926 ///
00927 static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) {
00928   switch (DestTy->getTypeID()) {
00929   case Type::BoolTyID:
00930   case Type::UByteTyID:
00931   case Type::SByteTyID:   return V9::STBr;
00932   case Type::UShortTyID:
00933   case Type::ShortTyID:   return V9::STHr;
00934   case Type::UIntTyID:
00935   case Type::IntTyID:     return V9::STWr;
00936   case Type::PointerTyID:
00937   case Type::ULongTyID:
00938   case Type::LongTyID:    return V9::STXr;
00939   case Type::FloatTyID:   return V9::STFr;
00940   case Type::DoubleTyID:  return V9::STDFr;
00941   default: assert(0 && "Invalid type for Store instruction");
00942   }
00943   return 0;
00944 }
00945 
00946 static inline MachineOpCode ChooseAddInstructionByType(const Type* resultType) {
00947   MachineOpCode opCode = V9::INVALID_OPCODE;
00948   if (resultType->isIntegral() || isa<PointerType>(resultType)
00949       || isa<FunctionType>(resultType) || resultType == Type::LabelTy) {
00950     opCode = V9::ADDr;
00951   } else
00952     switch(resultType->getTypeID()) {
00953     case Type::FloatTyID:  opCode = V9::FADDS; break;
00954     case Type::DoubleTyID: opCode = V9::FADDD; break;
00955     default: assert(0 && "Invalid type for ADD instruction"); break;
00956     }
00957 
00958   return opCode;
00959 }
00960 
00961 /// convertOpcodeFromRegToImm - Because the SparcV9 instruction selector likes
00962 /// to re-write operands to instructions, making them change from a Value*
00963 /// (virtual register) to a Constant* (making an immediate field), we need to
00964 /// change the opcode from a register-based instruction to an immediate-based
00965 /// instruction, hence this mapping.
00966 ///
00967 static unsigned convertOpcodeFromRegToImm(unsigned Opcode) {
00968   switch (Opcode) {
00969     /* arithmetic */
00970   case V9::ADDr:     return V9::ADDi;
00971   case V9::ADDccr:   return V9::ADDcci;
00972   case V9::ADDCr:    return V9::ADDCi;
00973   case V9::ADDCccr:  return V9::ADDCcci;
00974   case V9::SUBr:     return V9::SUBi;
00975   case V9::SUBccr:   return V9::SUBcci;
00976   case V9::SUBCr:    return V9::SUBCi;
00977   case V9::SUBCccr:  return V9::SUBCcci;
00978   case V9::MULXr:    return V9::MULXi;
00979   case V9::SDIVXr:   return V9::SDIVXi;
00980   case V9::UDIVXr:   return V9::UDIVXi;
00981 
00982     /* logical */
00983   case V9::ANDr:    return V9::ANDi;
00984   case V9::ANDccr:  return V9::ANDcci;
00985   case V9::ANDNr:   return V9::ANDNi;
00986   case V9::ANDNccr: return V9::ANDNcci;
00987   case V9::ORr:     return V9::ORi;
00988   case V9::ORccr:   return V9::ORcci;
00989   case V9::ORNr:    return V9::ORNi;
00990   case V9::ORNccr:  return V9::ORNcci;
00991   case V9::XORr:    return V9::XORi;
00992   case V9::XORccr:  return V9::XORcci;
00993   case V9::XNORr:   return V9::XNORi;
00994   case V9::XNORccr: return V9::XNORcci;
00995 
00996     /* shift */
00997   case V9::SLLr5:   return V9::SLLi5;
00998   case V9::SRLr5:   return V9::SRLi5;
00999   case V9::SRAr5:   return V9::SRAi5;
01000   case V9::SLLXr6:  return V9::SLLXi6;
01001   case V9::SRLXr6:  return V9::SRLXi6;
01002   case V9::SRAXr6:  return V9::SRAXi6;
01003 
01004     /* Conditional move on int comparison with zero */
01005   case V9::MOVRZr:   return V9::MOVRZi;
01006   case V9::MOVRLEZr: return V9::MOVRLEZi;
01007   case V9::MOVRLZr:  return V9::MOVRLZi;
01008   case V9::MOVRNZr:  return V9::MOVRNZi;
01009   case V9::MOVRGZr:  return V9::MOVRGZi;
01010   case V9::MOVRGEZr: return V9::MOVRGEZi;
01011 
01012 
01013     /* Conditional move on int condition code */
01014   case V9::MOVAr:   return V9::MOVAi;
01015   case V9::MOVNr:   return V9::MOVNi;
01016   case V9::MOVNEr:  return V9::MOVNEi;
01017   case V9::MOVEr:   return V9::MOVEi;
01018   case V9::MOVGr:   return V9::MOVGi;
01019   case V9::MOVLEr:  return V9::MOVLEi;
01020   case V9::MOVGEr:  return V9::MOVGEi;
01021   case V9::MOVLr:   return V9::MOVLi;
01022   case V9::MOVGUr:  return V9::MOVGUi;
01023   case V9::MOVLEUr: return V9::MOVLEUi;
01024   case V9::MOVCCr:  return V9::MOVCCi;
01025   case V9::MOVCSr:  return V9::MOVCSi;
01026   case V9::MOVPOSr: return V9::MOVPOSi;
01027   case V9::MOVNEGr: return V9::MOVNEGi;
01028   case V9::MOVVCr:  return V9::MOVVCi;
01029   case V9::MOVVSr:  return V9::MOVVSi;
01030 
01031     /* Conditional move of int reg on fp condition code */
01032   case V9::MOVFAr:   return V9::MOVFAi;
01033   case V9::MOVFNr:   return V9::MOVFNi;
01034   case V9::MOVFUr:   return V9::MOVFUi;
01035   case V9::MOVFGr:   return V9::MOVFGi;
01036   case V9::MOVFUGr:  return V9::MOVFUGi;
01037   case V9::MOVFLr:   return V9::MOVFLi;
01038   case V9::MOVFULr:  return V9::MOVFULi;
01039   case V9::MOVFLGr:  return V9::MOVFLGi;
01040   case V9::MOVFNEr:  return V9::MOVFNEi;
01041   case V9::MOVFEr:   return V9::MOVFEi;
01042   case V9::MOVFUEr:  return V9::MOVFUEi;
01043   case V9::MOVFGEr:  return V9::MOVFGEi;
01044   case V9::MOVFUGEr: return V9::MOVFUGEi;
01045   case V9::MOVFLEr:  return V9::MOVFLEi;
01046   case V9::MOVFULEr: return V9::MOVFULEi;
01047   case V9::MOVFOr:   return V9::MOVFOi;
01048 
01049     /* load */
01050   case V9::LDSBr:   return V9::LDSBi;
01051   case V9::LDSHr:   return V9::LDSHi;
01052   case V9::LDSWr:   return V9::LDSWi;
01053   case V9::LDUBr:   return V9::LDUBi;
01054   case V9::LDUHr:   return V9::LDUHi;
01055   case V9::LDUWr:   return V9::LDUWi;
01056   case V9::LDXr:    return V9::LDXi;
01057   case V9::LDFr:    return V9::LDFi;
01058   case V9::LDDFr:   return V9::LDDFi;
01059   case V9::LDQFr:   return V9::LDQFi;
01060   case V9::LDFSRr:  return V9::LDFSRi;
01061   case V9::LDXFSRr: return V9::LDXFSRi;
01062 
01063     /* store */
01064   case V9::STBr:    return V9::STBi;
01065   case V9::STHr:    return V9::STHi;
01066   case V9::STWr:    return V9::STWi;
01067   case V9::STXr:    return V9::STXi;
01068   case V9::STFr:    return V9::STFi;
01069   case V9::STDFr:   return V9::STDFi;
01070   case V9::STFSRr:  return V9::STFSRi;
01071   case V9::STXFSRr: return V9::STXFSRi;
01072 
01073     /* jump & return */
01074   case V9::JMPLCALLr: return V9::JMPLCALLi;
01075   case V9::JMPLRETr:  return V9::JMPLRETi;
01076 
01077   /* save and restore */
01078   case V9::SAVEr:     return V9::SAVEi;
01079   case V9::RESTOREr:  return V9::RESTOREi;
01080 
01081   default:
01082     // It's already in correct format
01083     // Or, it's just not handled yet, but an assert() would break LLC
01084 #if 0
01085     std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
01086               << "\n";
01087 #endif
01088     return Opcode;
01089   }
01090 }
01091 
01092 /// CreateCodeToLoadConst - Create an instruction sequence to put the
01093 /// constant `val' into the virtual register `dest'.  `val' may be a Constant or
01094 /// a GlobalValue, viz., the constant address of a global variable or function.
01095 /// The generated instructions are returned in `mvec'. Any temp. registers
01096 /// (TmpInstruction) created are recorded in mcfi. Any stack space required is
01097 /// allocated via MachineFunction.
01098 ///
01099 void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
01100                            Value* val, Instruction* dest,
01101                            std::vector<MachineInstr*>& mvec,
01102                            MachineCodeForInstruction& mcfi) {
01103   assert(isa<Constant>(val) &&
01104          "I only know about constant values and global addresses");
01105 
01106   // Use a "set" instruction for known constants or symbolic constants (labels)
01107   // that can go in an integer reg.
01108   // We have to use a "load" instruction for all other constants,
01109   // in particular, floating point constants.
01110   const Type* valType = val->getType();
01111 
01112   if (isa<GlobalValue>(val)) {
01113       TmpInstruction* tmpReg =
01114         new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
01115       CreateSETXLabel(val, tmpReg, dest, mvec, mcfi);
01116       return;
01117   }
01118 
01119   bool isValid;
01120   uint64_t C = ConvertConstantToIntType(target, val, dest->getType(), isValid);
01121   if (isValid) {
01122     if (dest->getType()->isSigned())
01123       CreateUIntSetInstruction(C, dest, mvec, mcfi, val);
01124     else
01125       CreateIntSetInstruction((int64_t) C, dest, mvec, mcfi, val);
01126 
01127   } else {
01128     // Make an instruction sequence to load the constant, viz:
01129     //            SETX <addr-of-constant>, tmpReg, addrReg
01130     //            LOAD  /*addr*/ addrReg, /*offset*/ 0, dest
01131     // First, create a tmp register to be used by the SETX sequence.
01132     TmpInstruction* tmpReg =
01133       new TmpInstruction(mcfi, PointerType::get(val->getType()));
01134 
01135     // Create another TmpInstruction for the address register
01136     TmpInstruction* addrReg =
01137       new TmpInstruction(mcfi, PointerType::get(val->getType()));
01138 
01139     // Get the constant pool index for this constant
01140     MachineConstantPool *CP = MachineFunction::get(F).getConstantPool();
01141     Constant *C = cast<Constant>(val);
01142     unsigned Align = target.getTargetData().getTypeAlignmentShift(C->getType());
01143     unsigned CPI = CP->getConstantPoolIndex(C, Align);
01144 
01145     // Put the address of the constant into a register
01146     MachineInstr* MI;
01147 
01148     MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg);
01149     MI->getOperand(0).markHi64();
01150     mvec.push_back(MI);
01151 
01152     //Create another tmp register for the SETX sequence to preserve SSA
01153     TmpInstruction* tmpReg2 =
01154       new TmpInstruction(mcfi, PointerType::get(val->getType()));
01155 
01156     MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
01157       .addRegDef(tmpReg2);
01158     MI->getOperand(1).markLo64();
01159     mvec.push_back(MI);
01160 
01161     //Create another tmp register for the SETX sequence to preserve SSA
01162     TmpInstruction* tmpReg3 =
01163       new TmpInstruction(mcfi, PointerType::get(val->getType()));
01164 
01165     mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg2).addZImm(32)
01166                    .addRegDef(tmpReg3));
01167     MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
01168     MI->getOperand(0).markHi32();
01169     mvec.push_back(MI);
01170 
01171     // Create another TmpInstruction for the address register
01172     TmpInstruction* addrReg2 =
01173       new TmpInstruction(mcfi, PointerType::get(val->getType()));
01174 
01175 
01176     MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg3).addRegDef(addrReg2);
01177     mvec.push_back(MI);
01178 
01179     // Create another TmpInstruction for the address register
01180     TmpInstruction* addrReg3 =
01181       new TmpInstruction(mcfi, PointerType::get(val->getType()));
01182 
01183     MI = BuildMI(V9::ORi, 3).addReg(addrReg2).addConstantPoolIndex(CPI)
01184       .addRegDef(addrReg3);
01185     MI->getOperand(1).markLo32();
01186     mvec.push_back(MI);
01187 
01188     // Now load the constant from out ConstantPool label
01189     unsigned Opcode = ChooseLoadInstruction(val->getType());
01190     Opcode = convertOpcodeFromRegToImm(Opcode);
01191     mvec.push_back(BuildMI(Opcode, 3)
01192                    .addReg(addrReg3).addSImm((int64_t)0).addRegDef(dest));
01193   }
01194 }
01195 
01196 /// CreateCodeToCopyFloatToInt - Similarly, create an instruction sequence
01197 /// to copy an FP register `val' to an integer register `dest' by copying to
01198 /// memory and back.  The generated instructions are returned in `mvec'.  Any
01199 /// temp. virtual registers (TmpInstruction) created are recorded in mcfi.
01200 /// Temporary stack space required is allocated via MachineFunction.
01201 ///
01202 void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F,
01203                                 Value* val, Instruction* dest,
01204                                 std::vector<MachineInstr*>& mvec,
01205                                 MachineCodeForInstruction& mcfi) {
01206   const Type* opTy   = val->getType();
01207   const Type* destTy = dest->getType();
01208   assert(opTy->isFloatingPoint() && "Source type must be float/double");
01209   assert((destTy->isIntegral() || isa<PointerType>(destTy))
01210          && "Dest type must be integer, bool or pointer");
01211 
01212   // FIXME: For now, we allocate permanent space because the stack frame
01213   // manager does not allow locals to be allocated (e.g., for alloca) after
01214   // a temp is allocated!
01215   int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
01216 
01217   unsigned FPReg = target.getRegInfo()->getFramePointer();
01218 
01219   // Store instruction stores `val' to [%fp+offset].
01220   // The store opCode is based only the source value being copied.
01221   unsigned StoreOpcode = ChooseStoreInstruction(opTy);
01222   StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
01223   mvec.push_back(BuildMI(StoreOpcode, 3)
01224                  .addReg(val).addMReg(FPReg).addSImm(offset));
01225 
01226   // Load instruction loads [%fp+offset] to `dest'.
01227   // The type of the load opCode is the integer type that matches the
01228   // source type in size:
01229   // On SparcV9: int for float, long for double.
01230   // Note that we *must* use signed loads even for unsigned dest types, to
01231   // ensure correct sign-extension for UByte, UShort or UInt:
01232   const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
01233   unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
01234   LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
01235   mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)
01236                  .addSImm(offset).addRegDef(dest));
01237 }
01238 
01239 /// CreateBitExtensionInstructions - Helper function for sign-extension and
01240 /// zero-extension. For SPARC v9, we sign-extend the given operand using SLL;
01241 /// SRA/SRL.
01242 ///
01243 inline void
01244 CreateBitExtensionInstructions(bool signExtend, const TargetMachine& target,
01245                                Function* F, Value* srcVal, Value* destVal,
01246                                unsigned int numLowBits,
01247                                std::vector<MachineInstr*>& mvec,
01248                                MachineCodeForInstruction& mcfi) {
01249   MachineInstr* M;
01250 
01251   assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
01252 
01253   if (numLowBits < 32) {
01254     // SLL is needed since operand size is < 32 bits.
01255     TmpInstruction *tmpI = new TmpInstruction(mcfi, destVal->getType(),
01256                                               srcVal, destVal, "make32");
01257     mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(srcVal)
01258                    .addZImm(32-numLowBits).addRegDef(tmpI));
01259     srcVal = tmpI;
01260   }
01261 
01262   mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
01263                  .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
01264 }
01265 
01266 /// CreateSignExtensionInstructions - Create instruction sequence to produce
01267 /// a sign-extended register value from an arbitrary-sized integer value (sized
01268 /// in bits, not bytes). The generated instructions are returned in `mvec'. Any
01269 /// temp. registers (TmpInstruction) created are recorded in mcfi. Any stack
01270 /// space required is allocated via MachineFunction.
01271 ///
01272 void CreateSignExtensionInstructions(const TargetMachine& target,
01273                                      Function* F, Value* srcVal, Value* destVal,
01274                                      unsigned int numLowBits,
01275                                      std::vector<MachineInstr*>& mvec,
01276                                      MachineCodeForInstruction& mcfi) {
01277   CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
01278                                  destVal, numLowBits, mvec, mcfi);
01279 }
01280 
01281 /// CreateZeroExtensionInstructions - Create instruction sequence to produce
01282 /// a zero-extended register value from an arbitrary-sized integer value (sized
01283 /// in bits, not bytes).  For SPARC v9, we sign-extend the given operand using
01284 /// SLL; SRL.  The generated instructions are returned in `mvec'.  Any temp.
01285 /// registers (TmpInstruction) created are recorded in mcfi.  Any stack space
01286 /// required is allocated via MachineFunction.
01287 ///
01288 void CreateZeroExtensionInstructions(const TargetMachine& target,
01289                                      Function* F, Value* srcVal, Value* destVal,
01290                                      unsigned int numLowBits,
01291                                      std::vector<MachineInstr*>& mvec,
01292                                      MachineCodeForInstruction& mcfi) {
01293   CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
01294                                  destVal, numLowBits, mvec, mcfi);
01295 }
01296 
01297 /// CreateCodeToCopyIntToFloat - Create an instruction sequence to copy an
01298 /// integer register `val' to a floating point register `dest' by copying to
01299 /// memory and back. val must be an integral type.  dest must be a Float or
01300 /// Double. The generated instructions are returned in `mvec'. Any temp.
01301 /// registers (TmpInstruction) created are recorded in mcfi. Any stack space
01302 /// required is allocated via MachineFunction.
01303 ///
01304 void CreateCodeToCopyIntToFloat(const TargetMachine& target,
01305                                 Function* F, Value* val, Instruction* dest,
01306                                 std::vector<MachineInstr*>& mvec,
01307                                 MachineCodeForInstruction& mcfi) {
01308   assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
01309          && "Source type must be integral (integer or bool) or pointer");
01310   assert(dest->getType()->isFloatingPoint()
01311          && "Dest type must be float/double");
01312 
01313   // Get a stack slot to use for the copy
01314   int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
01315 
01316   // Get the size of the source value being copied.
01317   size_t srcSize = target.getTargetData().getTypeSize(val->getType());
01318 
01319   // Store instruction stores `val' to [%fp+offset].
01320   // The store and load opCodes are based on the size of the source value.
01321   // If the value is smaller than 32 bits, we must sign- or zero-extend it
01322   // to 32 bits since the load-float will load 32 bits.
01323   // Note that the store instruction is the same for signed and unsigned ints.
01324   const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
01325   Value* storeVal = val;
01326   if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
01327     // sign- or zero-extend respectively
01328     storeVal = new TmpInstruction(mcfi, storeType, val);
01329     if (val->getType()->isSigned())
01330       CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
01331                                       mvec, mcfi);
01332     else
01333       CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
01334                                       mvec, mcfi);
01335   }
01336 
01337   unsigned FPReg = target.getRegInfo()->getFramePointer();
01338   unsigned StoreOpcode = ChooseStoreInstruction(storeType);
01339   StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
01340   mvec.push_back(BuildMI(StoreOpcode, 3)
01341                  .addReg(storeVal).addMReg(FPReg).addSImm(offset));
01342 
01343   // Load instruction loads [%fp+offset] to `dest'.
01344   // The type of the load opCode is the floating point type that matches the
01345   // stored type in size:
01346   // On SparcV9: float for int or smaller, double for long.
01347   const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
01348   unsigned LoadOpcode = ChooseLoadInstruction(loadType);
01349   LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
01350   mvec.push_back(BuildMI(LoadOpcode, 3)
01351                  .addMReg(FPReg).addSImm(offset).addRegDef(dest));
01352 }
01353 
01354 /// InsertCodeToLoadConstant - Generates code to load the constant
01355 /// into a TmpInstruction (virtual reg) and returns the virtual register.
01356 ///
01357 static TmpInstruction*
01358 InsertCodeToLoadConstant(Function *F, Value* opValue, Instruction* vmInstr,
01359                          std::vector<MachineInstr*>& loadConstVec,
01360                          TargetMachine& target) {
01361   // Create a tmp virtual register to hold the constant.
01362   MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
01363   TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
01364 
01365   CreateCodeToLoadConst(target, F, opValue, tmpReg, loadConstVec, mcfi);
01366 
01367   // Record the mapping from the tmp VM instruction to machine instruction.
01368   // Do this for all machine instructions that were not mapped to any
01369   // other temp values created by
01370   // tmpReg->addMachineInstruction(loadConstVec.back());
01371   return tmpReg;
01372 }
01373 
01374 MachineOperand::MachineOperandType
01375 ChooseRegOrImmed(int64_t intValue, bool isSigned,
01376                  MachineOpCode opCode, const TargetMachine& target,
01377                  bool canUseImmed, unsigned int& getMachineRegNum,
01378                  int64_t& getImmedValue) {
01379   MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
01380   getMachineRegNum = 0;
01381   getImmedValue = 0;
01382 
01383   if (canUseImmed &&
01384       target.getInstrInfo()->constantFitsInImmedField(opCode, intValue)) {
01385       opType = isSigned? MachineOperand::MO_SignExtendedImmed
01386                        : MachineOperand::MO_UnextendedImmed;
01387       getImmedValue = intValue;
01388   } else if (intValue == 0 &&
01389              target.getRegInfo()->getZeroRegNum() != (unsigned)-1) {
01390     opType = MachineOperand::MO_MachineRegister;
01391     getMachineRegNum = target.getRegInfo()->getZeroRegNum();
01392   }
01393 
01394   return opType;
01395 }
01396 
01397 MachineOperand::MachineOperandType
01398 ChooseRegOrImmed(Value* val,
01399                  MachineOpCode opCode, const TargetMachine& target,
01400                  bool canUseImmed, unsigned int& getMachineRegNum,
01401                  int64_t& getImmedValue) {
01402   getMachineRegNum = 0;
01403   getImmedValue = 0;
01404 
01405   // To use reg or immed, constant needs to be integer, bool, or a NULL pointer.
01406   // ConvertConstantToIntType() does the right conversions.
01407   bool isValidConstant;
01408   uint64_t valueToUse =
01409     ConvertConstantToIntType(target, val, val->getType(), isValidConstant);
01410   if (! isValidConstant)
01411     return MachineOperand::MO_VirtualRegister;
01412 
01413   // Now check if the constant value fits in the IMMED field.
01414   return ChooseRegOrImmed((int64_t) valueToUse, val->getType()->isSigned(),
01415                           opCode, target, canUseImmed,
01416                           getMachineRegNum, getImmedValue);
01417 }
01418 
01419 /// CreateCopyInstructionsByType - Create instruction(s) to copy src to dest,
01420 /// for arbitrary types. The generated instructions are returned in `mvec'. Any
01421 /// temp. registers (TmpInstruction) created are recorded in mcfi. Any stack
01422 /// space required is allocated via MachineFunction.
01423 ///
01424 void CreateCopyInstructionsByType(const TargetMachine& target,
01425                                   Function *F, Value* src, Instruction* dest,
01426                                   std::vector<MachineInstr*>& mvec,
01427                                   MachineCodeForInstruction& mcfi) {
01428   bool loadConstantToReg = false;
01429   const Type* resultType = dest->getType();
01430   MachineOpCode opCode = ChooseAddInstructionByType(resultType);
01431   assert (opCode != V9::INVALID_OPCODE
01432           && "Unsupported result type in CreateCopyInstructionsByType()");
01433 
01434   // If `src' is a constant that doesn't fit in the immed field or if it is
01435   // a global variable (i.e., a constant address), generate a load
01436   // instruction instead of an add.
01437   if (isa<GlobalValue>(src))
01438     loadConstantToReg = true;
01439   else if (isa<Constant>(src)) {
01440     unsigned int machineRegNum;
01441     int64_t immedValue;
01442     MachineOperand::MachineOperandType opType =
01443       ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
01444                        machineRegNum, immedValue);
01445 
01446     if (opType == MachineOperand::MO_VirtualRegister)
01447       loadConstantToReg = true;
01448   }
01449 
01450   if (loadConstantToReg) {
01451     // `src' is constant and cannot fit in immed field for the ADD.
01452     // Insert instructions to "load" the constant into a register.
01453     CreateCodeToLoadConst(target, F, src, dest, mvec, mcfi);
01454   } else {
01455     // Create a reg-to-reg copy instruction for the given type:
01456     // -- For FP values, create a FMOVS or FMOVD instruction
01457     // -- For non-FP values, create an add-with-0 instruction (opCode as above)
01458     // Make `src' the second operand, in case it is a small constant!
01459     MachineInstr* MI;
01460     if (resultType->isFloatingPoint())
01461       MI = (BuildMI(resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
01462             .addReg(src).addRegDef(dest));
01463     else {
01464         const Type* Ty =isa<PointerType>(resultType)? Type::ULongTy :resultType;
01465         MI = (BuildMI(opCode, 3)
01466               .addSImm((int64_t) 0).addReg(src).addRegDef(dest));
01467     }
01468     mvec.push_back(MI);
01469   }
01470 }
01471 
01472 /// FixConstantOperandsForInstr - Make a machine instruction use its constant
01473 /// operands more efficiently.  If the constant is 0, then use the hardwired 0
01474 /// register, if any.  Else, if the constant fits in the IMMEDIATE field, then
01475 /// use that field.  Otherwise, else create instructions to put the constant
01476 /// into a register, either directly or by loading explicitly from the constant
01477 /// pool.  In the first 2 cases, the operand of `minstr' is modified in place.
01478 /// Returns a vector of machine instructions generated for operands that fall
01479 /// under case 3; these must be inserted before `minstr'.
01480 ///
01481 std::vector<MachineInstr*>
01482 FixConstantOperandsForInstr(Instruction* vmInstr, MachineInstr* minstr,
01483                             TargetMachine& target) {
01484   std::vector<MachineInstr*> MVec;
01485 
01486   MachineOpCode opCode = minstr->getOpcode();
01487   const TargetInstrInfo& instrInfo = *target.getInstrInfo();
01488   int resultPos = instrInfo.get(opCode).resultPos;
01489   int immedPos = instrInfo.getImmedConstantPos(opCode);
01490 
01491   Function *F = vmInstr->getParent()->getParent();
01492 
01493   for (unsigned op=0; op < minstr->getNumOperands(); op++) {
01494       const MachineOperand& mop = minstr->getOperand(op);
01495 
01496       // Skip the result position, preallocated machine registers, or operands
01497       // that cannot be constants (CC regs or PC-relative displacements)
01498       if (resultPos == (int)op ||
01499           mop.getType() == MachineOperand::MO_MachineRegister ||
01500           mop.getType() == MachineOperand::MO_CCRegister ||
01501           mop.getType() == MachineOperand::MO_PCRelativeDisp)
01502         continue;
01503 
01504       bool constantThatMustBeLoaded = false;
01505       unsigned int machineRegNum = 0;
01506       int64_t immedValue = 0;
01507       Value* opValue = NULL;
01508       MachineOperand::MachineOperandType opType =
01509         MachineOperand::MO_VirtualRegister;
01510 
01511       // Operand may be a virtual register or a compile-time constant
01512       if (mop.getType() == MachineOperand::MO_VirtualRegister) {
01513         assert(mop.getVRegValue() != NULL);
01514         opValue = mop.getVRegValue();
01515         if (Constant *opConst = dyn_cast<Constant>(opValue))
01516           if (!isa<GlobalValue>(opConst)) {
01517             opType = ChooseRegOrImmed(opConst, opCode, target,
01518                                       (immedPos == (int)op), machineRegNum,
01519                                       immedValue);
01520             if (opType == MachineOperand::MO_VirtualRegister)
01521               constantThatMustBeLoaded = true;
01522           }
01523       } else {
01524         // If the operand is from the constant pool, don't try to change it.
01525         if (mop.getType() == MachineOperand::MO_ConstantPoolIndex) {
01526           continue;
01527         }
01528         assert(mop.isImmediate());
01529         bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
01530 
01531         // Bit-selection flags indicate an instruction that is extracting
01532         // bits from its operand so ignore this even if it is a big constant.
01533         if (mop.isHiBits32() || mop.isLoBits32() ||
01534             mop.isHiBits64() || mop.isLoBits64())
01535           continue;
01536 
01537         opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
01538                                   opCode, target, (immedPos == (int)op),
01539                                   machineRegNum, immedValue);
01540 
01541         if (opType == MachineOperand::MO_SignExtendedImmed ||
01542             opType == MachineOperand::MO_UnextendedImmed) {
01543           // The optype is an immediate value
01544           // This means we need to change the opcode, e.g. ADDr -> ADDi
01545           unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
01546           minstr->setOpcode(newOpcode);
01547         }
01548 
01549         if (opType == mop.getType())
01550           continue;           // no change: this is the most common case
01551 
01552         if (opType == MachineOperand::MO_VirtualRegister) {
01553           constantThatMustBeLoaded = true;
01554           opValue = isSigned
01555             ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
01556             : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
01557         }
01558       }
01559 
01560       if (opType == MachineOperand::MO_MachineRegister)
01561         minstr->SetMachineOperandReg(op, machineRegNum);
01562       else if (opType == MachineOperand::MO_SignExtendedImmed ||
01563                opType == MachineOperand::MO_UnextendedImmed) {
01564         minstr->SetMachineOperandConst(op, opType, immedValue);
01565         // The optype is or has become an immediate
01566         // This means we need to change the opcode, e.g. ADDr -> ADDi
01567         unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
01568         minstr->setOpcode(newOpcode);
01569       } else if (constantThatMustBeLoaded ||
01570                (opValue && isa<GlobalValue>(opValue)))
01571         { // opValue is a constant that must be explicitly loaded into a reg
01572           assert(opValue);
01573           TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
01574                                                             MVec, target);
01575           minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
01576                                        tmpReg);
01577         }
01578     }
01579 
01580   // Also, check for implicit operands used by the machine instruction
01581   // (no need to check those defined since they cannot be constants).
01582   // These include:
01583   // -- arguments to a Call
01584   // -- return value of a Return
01585   // Any such operand that is a constant value needs to be fixed also.
01586   // The current instructions with implicit refs (viz., Call and Return)
01587   // have no immediate fields, so the constant always needs to be loaded
01588   // into a register.
01589   bool isCall = instrInfo.isCall(opCode);
01590   unsigned lastCallArgNum = 0;          // unused if not a call
01591   CallArgsDescriptor* argDesc = NULL;   // unused if not a call
01592   if (isCall)
01593     argDesc = CallArgsDescriptor::get(minstr);
01594 
01595   for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
01596     if (isa<Constant>(minstr->getImplicitRef(i))) {
01597         Value* oldVal = minstr->getImplicitRef(i);
01598         TmpInstruction* tmpReg =
01599           InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
01600         minstr->setImplicitRef(i, tmpReg);
01601 
01602         if (isCall) {
01603           // find and replace the argument in the CallArgsDescriptor
01604           unsigned i=lastCallArgNum;
01605           while (argDesc->getArgInfo(i).getArgVal() != oldVal)
01606             ++i;
01607           assert(i < argDesc->getNumArgs() &&
01608                  "Constant operands to a call *must* be in the arg list");
01609           lastCallArgNum = i;
01610           argDesc->getArgInfo(i).replaceArgVal(tmpReg);
01611         }
01612       }
01613 
01614   return MVec;
01615 }
01616 
01617 static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node,
01618                                     std::vector<MachineInstr*>& mvec) {
01619   mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue())
01620                                    .addReg(Node->rightChild()->getValue())
01621                                    .addRegDef(Node->getValue()));
01622 }
01623 
01624 /// IsZero - Check for a constant 0.
01625 ///
01626 static inline bool IsZero(Value* idx) {
01627   return (isa<Constant>(idx) && cast<Constant>(idx)->isNullValue()) ||
01628          isa<UndefValue>(idx);
01629 }
01630 
01631 /// FoldGetElemChain - Fold a chain of GetElementPtr instructions containing
01632 /// only constant offsets into an equivalent (Pointer, IndexVector) pair.
01633 /// Returns the pointer Value, and stores the resulting IndexVector in argument
01634 /// chainIdxVec. This is a helper function for FoldConstantIndices that does the
01635 /// actual folding.
01636 //
01637 static Value*
01638 FoldGetElemChain(InstrTreeNode* ptrNode, std::vector<Value*>& chainIdxVec,
01639                  bool lastInstHasLeadingNonZero) {
01640   InstructionNode* gepNode = dyn_cast<InstructionNode>(ptrNode);
01641   GetElementPtrInst* gepInst =
01642     dyn_cast_or_null<GetElementPtrInst>(gepNode ? gepNode->getInstruction() :0);
01643 
01644   // ptr value is not computed in this tree or ptr value does not come from GEP
01645   // instruction
01646   if (gepInst == NULL)
01647     return NULL;
01648 
01649   // Return NULL if we don't fold any instructions in.
01650   Value* ptrVal = NULL;
01651 
01652   // Now chase the chain of getElementInstr instructions, if any.
01653   // Check for any non-constant indices and stop there.
01654   // Also, stop if the first index of child is a non-zero array index
01655   // and the last index of the current node is a non-array index:
01656   // in that case, a non-array declared type is being accessed as an array
01657   // which is not type-safe, but could be legal.
01658   InstructionNode* ptrChild = gepNode;
01659   while (ptrChild && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
01660                       ptrChild->getOpLabel() == GetElemPtrIdx)) {
01661     // Child is a GetElemPtr instruction
01662     gepInst = cast<GetElementPtrInst>(ptrChild->getValue());
01663     User::op_iterator OI, firstIdx = gepInst->idx_begin();
01664     User::op_iterator lastIdx = gepInst->idx_end();
01665     bool allConstantOffsets = true;
01666 
01667     // The first index of every GEP must be an array index.
01668     assert((*firstIdx)->getType() == Type::LongTy &&
01669            "INTERNAL ERROR: Structure index for a pointer type!");
01670 
01671     // If the last instruction had a leading non-zero index, check if the
01672     // current one references a sequential (i.e., indexable) type.
01673     // If not, the code is not type-safe and we would create an illegal GEP
01674     // by folding them, so don't fold any more instructions.
01675     if (lastInstHasLeadingNonZero)
01676       if (! isa<SequentialType>(gepInst->getType()->getElementType()))
01677         break;   // cannot fold in any preceding getElementPtr instrs.
01678 
01679     // Check that all offsets are constant for this instruction
01680     for (OI = firstIdx; allConstantOffsets && OI != lastIdx; ++OI)
01681       allConstantOffsets = isa<ConstantInt>(*OI);
01682 
01683     if (allConstantOffsets) {
01684       // Get pointer value out of ptrChild.
01685       ptrVal = gepInst->getPointerOperand();
01686 
01687       // Insert its index vector at the start, skipping any leading [0]
01688       // Remember the old size to check if anything was inserted.
01689       unsigned oldSize = chainIdxVec.size();
01690       int firstIsZero = IsZero(*firstIdx);
01691       chainIdxVec.insert(chainIdxVec.begin(), firstIdx + firstIsZero, lastIdx);
01692 
01693       // Remember if it has leading zero index: it will be discarded later.
01694       if (oldSize < chainIdxVec.size())
01695         lastInstHasLeadingNonZero = !firstIsZero;
01696 
01697       // Mark the folded node so no code is generated for it.
01698       ((InstructionNode*) ptrChild)->markFoldedIntoParent();
01699 
01700       // Get the previous GEP instruction and continue trying to fold
01701       ptrChild = dyn_cast<InstructionNode>(ptrChild->leftChild());
01702     } else // cannot fold this getElementPtr instr. or any preceding ones
01703       break;
01704   }
01705 
01706   // If the first getElementPtr instruction had a leading [0], add it back.
01707   // Note that this instruction is the *last* one that was successfully
01708   // folded *and* contributed any indices, in the loop above.
01709   if (ptrVal && ! lastInstHasLeadingNonZero)
01710     chainIdxVec.insert(chainIdxVec.begin(), ConstantSInt::get(Type::LongTy,0));
01711 
01712   return ptrVal;
01713 }
01714 
01715 /// GetGEPInstArgs - Helper function for GetMemInstArgs that handles the
01716 /// final getElementPtr instruction used by (or same as) the memory operation.
01717 /// Extracts the indices of the current instruction and tries to fold in
01718 /// preceding ones if all indices of the current one are constant.
01719 ///
01720 static Value *GetGEPInstArgs(InstructionNode *gepNode,
01721                              std::vector<Value *> &idxVec,
01722                              bool &allConstantIndices) {
01723   allConstantIndices = true;
01724   GetElementPtrInst* gepI = cast<GetElementPtrInst>(gepNode->getInstruction());
01725 
01726   // Default pointer is the one from the current instruction.
01727   Value* ptrVal = gepI->getPointerOperand();
01728   InstrTreeNode* ptrChild = gepNode->leftChild();
01729 
01730   // Extract the index vector of the GEP instruction.
01731   // If all indices are constant and first index is zero, try to fold
01732   // in preceding GEPs with all constant indices.
01733   for (User::op_iterator OI=gepI->idx_begin(),  OE=gepI->idx_end();
01734        allConstantIndices && OI != OE; ++OI)
01735     if (! isa<Constant>(*OI))
01736       allConstantIndices = false;     // note: this also terminates loop!
01737 
01738   // If we have only constant indices, fold chains of constant indices
01739   // in this and any preceding GetElemPtr instructions.
01740   bool foldedGEPs = false;
01741   bool leadingNonZeroIdx = gepI && ! IsZero(*gepI->idx_begin());
01742   if (allConstantIndices && !leadingNonZeroIdx)
01743     if (Value* newPtr = FoldGetElemChain(ptrChild, idxVec, leadingNonZeroIdx)) {
01744       ptrVal = newPtr;
01745       foldedGEPs = true;
01746     }
01747 
01748   // Append the index vector of the current instruction.
01749   // Skip the leading [0] index if preceding GEPs were folded into this.
01750   idxVec.insert(idxVec.end(),
01751                 gepI->idx_begin() + (foldedGEPs && !leadingNonZeroIdx),
01752                 gepI->idx_end());
01753 
01754   return ptrVal;
01755 }
01756 
01757 /// GetMemInstArgs - Get the pointer value and the index vector for a memory
01758 /// operation (GetElementPtr, Load, or Store).  If all indices of the given
01759 /// memory operation are constant, fold in constant indices in a chain of
01760 /// preceding GetElementPtr instructions (if any), and return the pointer value
01761 /// of the first instruction in the chain. All folded instructions are marked so
01762 /// no code is generated for them. Returns the pointer Value to use, and
01763 /// returns the resulting IndexVector in idxVec. Sets allConstantIndices
01764 /// to true/false if all indices are/aren't const.
01765 ///
01766 static Value *GetMemInstArgs(InstructionNode *memInstrNode,
01767                              std::vector<Value*> &idxVec,
01768                              bool& allConstantIndices) {
01769   allConstantIndices = false;
01770   Instruction* memInst = memInstrNode->getInstruction();
01771   assert(idxVec.size() == 0 && "Need empty vector to return indices");
01772 
01773   // If there is a GetElemPtr instruction to fold in to this instr,
01774   // it must be in the left child for Load and GetElemPtr, and in the
01775   // right child for Store instructions.
01776   InstrTreeNode* ptrChild = (memInst->getOpcode() == Instruction::Store
01777                              ? memInstrNode->rightChild()
01778                              : memInstrNode->leftChild());
01779 
01780   // Default pointer is the one from the current instruction.
01781   Value* ptrVal = ptrChild->getValue();
01782 
01783   // Find the "last" GetElemPtr instruction: this one or the immediate child.
01784   // There will be none if this is a load or a store from a scalar pointer.
01785   InstructionNode* gepNode = NULL;
01786   if (isa<GetElementPtrInst>(memInst))
01787     gepNode = memInstrNode;
01788   else if (isa<InstructionNode>(ptrChild) && isa<GetElementPtrInst>(ptrVal)) {
01789     // Child of load/store is a GEP and memInst is its only use.
01790     // Use its indices and mark it as folded.
01791     gepNode = cast<InstructionNode>(ptrChild);
01792     gepNode->markFoldedIntoParent();
01793   }
01794 
01795   // If there are no indices, return the current pointer.
01796   // Else extract the pointer from the GEP and fold the indices.
01797   return gepNode ? GetGEPInstArgs(gepNode, idxVec, allConstantIndices)
01798                  : ptrVal;
01799 }
01800 
01801 static inline MachineOpCode
01802 ChooseBprInstruction(const InstructionNode* instrNode) {
01803   MachineOpCode opCode;
01804 
01805   Instruction* setCCInstr =
01806     ((InstructionNode*) instrNode->leftChild())->getInstruction();
01807 
01808   switch(setCCInstr->getOpcode()) {
01809   case Instruction::SetEQ: opCode = V9::BRZ;   break;
01810   case Instruction::SetNE: opCode = V9::BRNZ;  break;
01811   case Instruction::SetLE: opCode = V9::BRLEZ; break;
01812   case Instruction::SetGE: opCode = V9::BRGEZ; break;
01813   case Instruction::SetLT: opCode = V9::BRLZ;  break;
01814   case Instruction::SetGT: opCode = V9::BRGZ;  break;
01815   default:
01816     assert(0 && "Unrecognized VM instruction!");
01817     opCode = V9::INVALID_OPCODE;
01818     break;
01819   }
01820 
01821   return opCode;
01822 }
01823 
01824 static inline MachineOpCode
01825 ChooseBpccInstruction(const InstructionNode* instrNode,
01826                       const BinaryOperator* setCCInstr) {
01827   MachineOpCode opCode = V9::INVALID_OPCODE;
01828 
01829   bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
01830 
01831   if (isSigned) {
01832     switch(setCCInstr->getOpcode()) {
01833     case Instruction::SetEQ: opCode = V9::BE;  break;
01834     case Instruction::SetNE: opCode = V9::BNE; break;
01835     case Instruction::SetLE: opCode = V9::BLE; break;
01836     case Instruction::SetGE: opCode = V9::BGE; break;
01837     case Instruction::SetLT: opCode = V9::BL;  break;
01838     case Instruction::SetGT: opCode = V9::BG;  break;
01839     default:
01840       assert(0 && "Unrecognized VM instruction!");
01841       break;
01842     }
01843   } else {
01844     switch(setCCInstr->getOpcode()) {
01845     case Instruction::SetEQ: opCode = V9::BE;   break;
01846     case Instruction::SetNE: opCode = V9::BNE;  break;
01847     case Instruction::SetLE: opCode = V9::BLEU; break;
01848     case Instruction::SetGE: opCode = V9::BCC;  break;
01849     case Instruction::SetLT: opCode = V9::BCS;  break;
01850     case Instruction::SetGT: opCode = V9::BGU;  break;
01851     default:
01852       assert(0 && "Unrecognized VM instruction!");
01853       break;
01854     }
01855   }
01856 
01857   return opCode;
01858 }
01859 
01860 static inline MachineOpCode
01861 ChooseBFpccInstruction(const InstructionNode* instrNode,
01862                        const BinaryOperator* setCCInstr) {
01863   MachineOpCode opCode = V9::INVALID_OPCODE;
01864 
01865   switch(setCCInstr->getOpcode()) {
01866   case Instruction::SetEQ: opCode = V9::FBE;  break;
01867   case Instruction::SetNE: opCode = V9::FBNE; break;
01868   case Instruction::SetLE: opCode = V9::FBLE; break;
01869   case Instruction::SetGE: opCode = V9::FBGE; break;
01870   case Instruction::SetLT: opCode = V9::FBL;  break;
01871   case Instruction::SetGT: opCode = V9::FBG;  break;
01872   default:
01873     assert(0 && "Unrecognized VM instruction!");
01874     break;
01875   }
01876 
01877   return opCode;
01878 }
01879 
01880 // GetTmpForCC - Create a unique TmpInstruction for a boolean value,
01881 // representing the CC register used by a branch on that value.
01882 // For now, hack this using a little static cache of TmpInstructions.
01883 // Eventually the entire BURG instruction selection should be put
01884 // into a separate class that can hold such information.
01885 // The static cache is not too bad because the memory for these
01886 // TmpInstructions will be freed along with the rest of the Function anyway.
01887 //
01888 static TmpInstruction *GetTmpForCC (Value* boolVal, const Function *F,
01889                                     const Type* ccType,
01890                                     MachineCodeForInstruction& mcfi) {
01891   typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
01892   static BoolTmpCache boolToTmpCache;     // Map boolVal -> TmpInstruction*
01893   static const Function *lastFunction = 0;// Use to flush cache between funcs
01894 
01895   assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
01896 
01897   if (lastFunction != F) {
01898     lastFunction = F;
01899     boolToTmpCache.clear();
01900   }
01901 
01902   // Look for tmpI and create a new one otherwise.  The new value is
01903   // directly written to map using the ref returned by operator[].
01904   TmpInstruction*& tmpI = boolToTmpCache[boolVal];
01905   if (tmpI == NULL)
01906     tmpI = new TmpInstruction(mcfi, ccType, boolVal);
01907 
01908   return tmpI;
01909 }
01910 
01911 static inline MachineOpCode
01912 ChooseBccInstruction(const InstructionNode* instrNode, const Type*& setCCType) {
01913   InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
01914   assert(setCCNode->getOpLabel() == SetCCOp);
01915   BinaryOperator* setCCInstr =cast<BinaryOperator>(setCCNode->getInstruction());
01916   setCCType = setCCInstr->getOperand(0)->getType();
01917 
01918   if (setCCType->isFloatingPoint())
01919     return ChooseBFpccInstruction(instrNode, setCCInstr);
01920   else
01921     return ChooseBpccInstruction(instrNode, setCCInstr);
01922 }
01923 
01924 /// ChooseMovFpcciInstruction - WARNING: since this function has only one
01925 /// caller, it always returns the opcode that expects an immediate and a
01926 /// register. If this function is ever used in cases where an opcode that takes
01927 /// two registers is required, then modify this function and use
01928 /// convertOpcodeFromRegToImm() where required. It will be necessary to expand
01929 /// convertOpcodeFromRegToImm() to handle the new cases of opcodes.
01930 ///
01931 static inline MachineOpCode
01932 ChooseMovFpcciInstruction(const InstructionNode* instrNode) {
01933   MachineOpCode opCode = V9::INVALID_OPCODE;
01934 
01935   switch(instrNode->getInstruction()->getOpcode()) {
01936   case Instruction::SetEQ: opCode = V9::MOVFEi;  break;
01937   case Instruction::SetNE: opCode = V9::MOVFNEi; break;
01938   case Instruction::SetLE: opCode = V9::MOVFLEi; break;
01939   case Instruction::SetGE: opCode = V9::MOVFGEi; break;
01940   case Instruction::SetLT: opCode = V9::MOVFLi;  break;
01941   case Instruction::SetGT: opCode = V9::MOVFGi;  break;
01942   default:
01943     assert(0 && "Unrecognized VM instruction!");
01944     break;
01945   }
01946 
01947   return opCode;
01948 }
01949 
01950 /// ChooseMovpcciForSetCC -- Choose a conditional-move instruction
01951 /// based on the type of SetCC operation.
01952 ///
01953 /// WARNING: like the previous function, this function always returns
01954 /// the opcode that expects an immediate and a register.  See above.
01955 ///
01956 static MachineOpCode ChooseMovpcciForSetCC(const InstructionNode* instrNode) {
01957   MachineOpCode opCode = V9::INVALID_OPCODE;
01958 
01959   const Type* opType = instrNode->leftChild()->getValue()->getType();
01960   assert(opType->isIntegral() || isa<PointerType>(opType));
01961   bool noSign = opType->isUnsigned() || isa<PointerType>(opType);
01962 
01963   switch(instrNode->getInstruction()->getOpcode()) {
01964   case Instruction::SetEQ: opCode = V9::MOVEi;                        break;
01965   case Instruction::SetLE: opCode = noSign? V9::MOVLEUi : V9::MOVLEi; break;
01966   case Instruction::SetGE: opCode = noSign? V9::MOVCCi  : V9::MOVGEi; break;
01967   case Instruction::SetLT: opCode = noSign? V9::MOVCSi  : V9::MOVLi;  break;
01968   case Instruction::SetGT: opCode = noSign? V9::MOVGUi  : V9::MOVGi;  break;
01969   case Instruction::SetNE: opCode = V9::MOVNEi;                       break;
01970   default: assert(0 && "Unrecognized LLVM instr!"); break;
01971   }
01972 
01973   return opCode;
01974 }
01975 
01976 /// ChooseMovpregiForSetCC -- Choose a conditional-move-on-register-value
01977 /// instruction based on the type of SetCC operation.  These instructions
01978 /// compare a register with 0 and perform the move is the comparison is true.
01979 ///
01980 /// WARNING: like the previous function, this function it always returns
01981 /// the opcode that expects an immediate and a register.  See above.
01982 ///
01983 static MachineOpCode ChooseMovpregiForSetCC(const InstructionNode* instrNode) {
01984   MachineOpCode opCode = V9::INVALID_OPCODE;
01985 
01986   switch(instrNode->getInstruction()->getOpcode()) {
01987   case Instruction::SetEQ: opCode = V9::MOVRZi;  break;
01988   case Instruction::SetLE: opCode = V9::MOVRLEZi; break;
01989   case Instruction::SetGE: opCode = V9::MOVRGEZi; break;
01990   case Instruction::SetLT: opCode = V9::MOVRLZi;  break;
01991   case Instruction::SetGT: opCode = V9::MOVRGZi;  break;
01992   case Instruction::SetNE: opCode = V9::MOVRNZi; break;
01993   default: assert(0 && "Unrecognized VM instr!"); break;
01994   }
01995 
01996   return opCode;
01997 }
01998 
01999 static inline MachineOpCode
02000 ChooseConvertToFloatInstr(const TargetMachine& target,
02001                           OpLabel vopCode, const Type* opType) {
02002   assert((vopCode == ToFloatTy || vopCode == ToDoubleTy) &&
02003          "Unrecognized convert-to-float opcode!");
02004   assert((opType->isIntegral() || opType->isFloatingPoint() ||
02005           isa<PointerType>(opType))
02006          && "Trying to convert a non-scalar type to FLOAT/DOUBLE?");
02007 
02008   MachineOpCode opCode = V9::INVALID_OPCODE;
02009 
02010   unsigned opSize = target.getTargetData().getTypeSize(opType);
02011 
02012   if (opType == Type::FloatTy)
02013     opCode = (vopCode == ToFloatTy? V9::NOP : V9::FSTOD);
02014   else if (opType == Type::DoubleTy)
02015     opCode = (vopCode == ToFloatTy? V9::FDTOS : V9::NOP);
02016   else if (opSize <= 4)
02017     opCode = (vopCode == ToFloatTy? V9::FITOS : V9::FITOD);
02018   else {
02019     assert(opSize == 8 && "Unrecognized type size > 4 and < 8!");
02020     opCode = (vopCode == ToFloatTy? V9::FXTOS : V9::FXTOD);
02021   }
02022 
02023   return opCode;
02024 }
02025 
02026 static inline MachineOpCode
02027 ChooseConvertFPToIntInstr(const TargetMachine& target,
02028                           const Type* destType, const Type* opType) {
02029   assert((opType == Type::FloatTy || opType == Type::DoubleTy)
02030          && "This function should only be called for FLOAT or DOUBLE");
02031   assert((destType->isIntegral() || isa<PointerType>(destType))
02032          && "Trying to convert FLOAT/DOUBLE to a non-scalar type?");
02033 
02034   MachineOpCode opCode = V9::INVALID_OPCODE;
02035 
02036   unsigned destSize = target.getTargetData().getTypeSize(destType);
02037 
02038   if (destType == Type::UIntTy)
02039     assert(destType != Type::UIntTy && "Expand FP-to-uint beforehand.");
02040   else if (destSize <= 4)
02041     opCode = (opType == Type::FloatTy)? V9::FSTOI : V9::FDTOI;
02042   else {
02043     assert(destSize == 8 && "Unrecognized type size > 4 and < 8!");
02044     opCode = (opType == Type::FloatTy)? V9::FSTOX : V9::FDTOX;
02045   }
02046 
02047   return opCode;
02048 }
02049 
02050 static MachineInstr*
02051 CreateConvertFPToIntInstr(const TargetMachine& target, Value* srcVal,
02052                           Value* destVal, const Type* destType) {
02053   MachineOpCode opCode = ChooseConvertFPToIntInstr(target, destType,
02054                                                    srcVal->getType());
02055   assert(opCode != V9::INVALID_OPCODE && "Expected to need conversion!");
02056   return BuildMI(opCode, 2).addReg(srcVal).addRegDef(destVal);
02057 }
02058 
02059 /// CreateCodeToConvertFloatToInt: Convert FP value to signed or unsigned
02060 /// integer.  The FP value must be converted to the dest type in an FP register,
02061 /// and the result is then copied from FP to int register via memory.  SPARC
02062 /// does not have a float-to-uint conversion, only a float-to-int (fdtoi).
02063 /// Since fdtoi converts to signed integers, any FP value V between MAXINT+1 and
02064 /// MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly.
02065 /// Therefore, for converting an FP value to uint32_t, we first need to convert
02066 /// to uint64_t and then to uint32_t.
02067 ///
02068 static void
02069 CreateCodeToConvertFloatToInt(const TargetMachine& target,
02070                               Value* opVal, Instruction* destI,
02071                               std::vector<MachineInstr*>& mvec,
02072                               MachineCodeForInstruction& mcfi) {
02073   Function* F = destI->getParent()->getParent();
02074 
02075   // Create a temporary to represent the FP register into which the
02076   // int value will placed after conversion.  The type of this temporary
02077   // depends on the type of FP register to use: single-prec for a 32-bit
02078   // int or smaller; double-prec for a 64-bit int.
02079   size_t destSize = target.getTargetData().getTypeSize(destI->getType());
02080 
02081   const Type* castDestType = destI->getType(); // type for the cast instr result
02082   const Type* castDestRegType;          // type for cast instruction result reg
02083   TmpInstruction* destForCast;          // dest for cast instruction
02084   Instruction* fpToIntCopyDest = destI; // dest for fp-reg-to-int-reg copy instr
02085 
02086   // For converting an FP value to uint32_t, we first need to convert to
02087   // uint64_t and then to uint32_t, as explained above.
02088   if (destI->getType() == Type::UIntTy) {
02089     castDestType    = Type::ULongTy;       // use this instead of type of destI
02090     castDestRegType = Type::DoubleTy;      // uint64_t needs 64-bit FP register.
02091     destForCast     = new TmpInstruction(mcfi, castDestRegType, opVal);
02092     fpToIntCopyDest = new TmpInstruction(mcfi, castDestType, destForCast);
02093   } else {
02094     castDestRegType = (destSize > 4)? Type::DoubleTy : Type::FloatTy;
02095     destForCast = new TmpInstruction(mcfi, castDestRegType, opVal);
02096   }
02097 
02098   // Create the fp-to-int conversion instruction (src and dest regs are FP regs)
02099   mvec.push_back(CreateConvertFPToIntInstr(target, opVal, destForCast,
02100                                            castDestType));
02101 
02102   // Create the fpreg-to-intreg copy code
02103   CreateCodeToCopyFloatToInt(target, F, destForCast, fpToIntCopyDest, mvec,
02104                              mcfi);
02105 
02106   // Create the uint64_t to uint32_t conversion, if needed
02107   if (destI->getType() == Type::UIntTy)
02108     CreateZeroExtensionInstructions(target, F, fpToIntCopyDest, destI,
02109                                     /*numLowBits*/ 32, mvec, mcfi);
02110 }
02111 
02112 static inline MachineOpCode
02113 ChooseAddInstruction(const InstructionNode* instrNode) {
02114   return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
02115 }
02116 
02117 static inline MachineInstr*
02118 CreateMovFloatInstruction(const InstructionNode* instrNode,
02119                           const Type* resultType) {
02120   return BuildMI((resultType == Type::FloatTy) ? V9::FMOVS : V9::FMOVD, 2)
02121                    .addReg(instrNode->leftChild()->getValue())
02122                    .addRegDef(instrNode->getValue());
02123 }
02124 
02125 static inline MachineInstr*
02126 CreateAddConstInstruction(const InstructionNode* instrNode) {
02127   MachineInstr* minstr = NULL;
02128 
02129   Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
02130   assert(isa<Constant>(constOp));
02131 
02132   // Cases worth optimizing are:
02133   // (1) Add with 0 for float or double: use an FMOV of appropriate type,
02134   //     instead of an FADD (1 vs 3 cycles).  There is no integer MOV.
02135   if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
02136     double dval = FPC->getValue();
02137     if (dval == 0.0)
02138       minstr = CreateMovFloatInstruction(instrNode,
02139                                         instrNode->getInstruction()->getType());
02140   }
02141 
02142   return minstr;
02143 }
02144 
02145 static inline MachineOpCode ChooseSubInstructionByType(const Type* resultType) {
02146   MachineOpCode opCode = V9::INVALID_OPCODE;
02147 
02148   if (resultType->isInteger() || isa<PointerType>(resultType)) {
02149       opCode = V9::SUBr;
02150   } else {
02151     switch(resultType->getTypeID()) {
02152     case Type::FloatTyID:  opCode = V9::FSUBS; break;
02153     case Type::DoubleTyID: opCode = V9::FSUBD; break;
02154     default: assert(0 && "Invalid type for SUB instruction"); break;
02155     }
02156   }
02157 
02158   return opCode;
02159 }
02160 
02161 static inline MachineInstr*
02162 CreateSubConstInstruction(const InstructionNode* instrNode) {
02163   MachineInstr* minstr = NULL;
02164 
02165   Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
02166   assert(isa<Constant>(constOp));
02167 
02168   // Cases worth optimizing are:
02169   // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
02170   //     instead of an FSUB (1 vs 3 cycles).  There is no integer MOV.
02171   if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
02172     double dval = FPC->getValue();
02173     if (dval == 0.0)
02174       minstr = CreateMovFloatInstruction(instrNode,
02175                                         instrNode->getInstruction()->getType());
02176   }
02177 
02178   return minstr;
02179 }
02180 
02181 static inline MachineOpCode
02182 ChooseFcmpInstruction(const InstructionNode* instrNode) {
02183   MachineOpCode opCode = V9::INVALID_OPCODE;
02184 
02185   Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
02186   switch(operand->getType()->getTypeID()) {
02187   case Type::FloatTyID:  opCode = V9::FCMPS; break;
02188   case Type::DoubleTyID: opCode = V9::FCMPD; break;
02189   default: assert(0 && "Invalid type for FCMP instruction"); break;
02190   }
02191 
02192   return opCode;
02193 }
02194 
02195 /// BothFloatToDouble - Assumes that leftArg and rightArg of instrNode are both
02196 /// cast instructions. Returns true if both are floats cast to double.
02197 ///
02198 static inline bool BothFloatToDouble(const InstructionNode* instrNode) {
02199   InstrTreeNode* leftArg = instrNode->leftChild();
02200   InstrTreeNode* rightArg = instrNode->rightChild();
02201   InstrTreeNode* leftArgArg = leftArg->leftChild();
02202   InstrTreeNode* rightArgArg = rightArg->leftChild();
02203   assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
02204   return (leftArg->getValue()->getType() == Type::DoubleTy &&
02205           leftArgArg->getValue()->getType() == Type::FloatTy &&
02206           rightArgArg->getValue()->getType() == Type::FloatTy);
02207 }
02208 
02209 static inline MachineOpCode ChooseMulInstructionByType(const Type* resultType) {
02210   MachineOpCode opCode = V9::INVALID_OPCODE;
02211 
02212   if (resultType->isInteger())
02213     opCode = V9::MULXr;
02214   else
02215     switch(resultType->getTypeID()) {
02216     case Type::FloatTyID:  opCode = V9::FMULS; break;
02217     case Type::DoubleTyID: opCode = V9::FMULD; break;
02218     default: assert(0 && "Invalid type for MUL instruction"); break;
02219     }
02220 
02221   return opCode;
02222 }
02223 
02224 static inline MachineInstr*
02225 CreateIntNegInstruction(const TargetMachine& target, Value* vreg) {
02226   return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo()->getZeroRegNum())
02227     .addReg(vreg).addRegDef(vreg);
02228 }
02229 
02230 static inline MachineInstr*
02231 CreateIntNegInstruction(const TargetMachine& target, Value* vreg, Value *destreg) {
02232   return BuildMI(V9::SUBr, 3).addMReg(target.getRegInfo()->getZeroRegNum())
02233     .addReg(vreg).addRegDef(destreg);
02234 }
02235 
02236 /// CreateShiftInstructions - Create instruction sequence for any shift
02237 /// operation. SLL or SLLX on an operand smaller than the integer reg. size
02238 /// (64bits) requires a second instruction for explicit sign-extension. Note
02239 /// that we only have to worry about a sign-bit appearing in the most
02240 /// significant bit of the operand after shifting (e.g., bit 32 of Int or bit 16
02241 /// of Short), so we do not have to worry about results that are as large as a
02242 /// normal integer register.
02243 ///
02244 static inline void
02245 CreateShiftInstructions(const TargetMachine& target, Function* F,
02246                         MachineOpCode shiftOpCode, Value* argVal1,
02247                         Value* optArgVal2, /* Use optArgVal2 if not NULL */
02248                         unsigned optShiftNum, /* else use optShiftNum */
02249                         Instruction* destVal, std::vector<MachineInstr*>& mvec,
02250                         MachineCodeForInstruction& mcfi) {
02251   assert((optArgVal2 != NULL || optShiftNum <= 64) &&
02252          "Large shift sizes unexpected, but can be handled below: "
02253          "You need to check whether or not it fits in immed field below");
02254 
02255   // If this is a logical left shift of a type smaller than the standard
02256   // integer reg. size, we have to extend the sign-bit into upper bits
02257   // of dest, so we need to put the result of the SLL into a temporary.
02258   Value* shiftDest = destVal;
02259   unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
02260 
02261   if ((shiftOpCode == V9::SLLr5 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
02262     // put SLL result into a temporary
02263     shiftDest = new TmpInstruction(mcfi, argVal1, optArgVal2, "sllTmp");
02264   }
02265 
02266   MachineInstr* M = (optArgVal2 != NULL)
02267     ? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
02268                              .addReg(shiftDest, MachineOperand::Def)
02269     : BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
02270                              .addReg(shiftDest, MachineOperand::Def);
02271   mvec.push_back(M);
02272 
02273   if (shiftDest != destVal) {
02274     // extend the sign-bit of the result into all upper bits of dest
02275     assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
02276     CreateSignExtensionInstructions(target, F, shiftDest, destVal, 8*opSize,
02277                                     mvec, mcfi);
02278   }
02279 }
02280 
02281 /// CreateMulConstInstruction - Does not create any instructions if we
02282 /// cannot exploit constant to create a cheaper instruction. This returns the
02283 /// approximate cost of the instructions generated, which is used to pick the
02284 /// cheapest when both operands are constant.
02285 ///
02286 static unsigned
02287 CreateMulConstInstruction(const TargetMachine &target, Function* F,
02288                           Value* lval, Value* rval, Instruction* destVal,
02289                           std::vector<MachineInstr*>& mvec,
02290                           MachineCodeForInstruction& mcfi) {
02291   // Use max. multiply cost, viz., cost of MULX
02292   unsigned cost = target.getInstrInfo()->minLatency(V9::MULXr);
02293   unsigned firstNewInstr = mvec.size();
02294 
02295   Value* constOp = rval;
02296   if (! isa<Constant>(constOp))
02297     return cost;
02298 
02299   // Cases worth optimizing are:
02300   // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
02301   // (2) Multiply by 2^x for integer types: replace with Shift
02302   const Type* resultType = destVal->getType();
02303 
02304   if (resultType->isInteger() || isa<PointerType>(resultType)) {
02305     bool isValidConst;
02306     int64_t C = (int64_t) ConvertConstantToIntType(target, constOp,
02307                                                    constOp->getType(),
02308                                                    isValidConst);
02309     if (isValidConst) {
02310       bool needNeg = false;
02311       if (C < 0) {
02312         needNeg = true;
02313         C = -C;
02314       }
02315       TmpInstruction *tmpNeg = 0;
02316 
02317       if (C == 0 || C == 1) {
02318         cost = target.getInstrInfo()->minLatency(V9::ADDr);
02319         unsigned Zero = target.getRegInfo()->getZeroRegNum();
02320         MachineInstr* M;
02321         if (C == 0)
02322           M =BuildMI(V9::ADDr,3).addMReg(Zero).addMReg(Zero).addRegDef(destVal);
02323         else
02324           M = BuildMI(V9::ADDr,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
02325         mvec.push_back(M);
02326       } else if (isPowerOf2_64(C)) {
02327         unsigned pow = Log2_64(C);
02328         if(!needNeg) {
02329         unsigned opSize = target.getTargetData().getTypeSize(resultType);
02330         MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
02331         CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
02332                                 destVal, mvec, mcfi);
02333         }
02334         else {
02335           //Create tmp instruction to hold intermeidate value, since we need
02336           //to negate the result
02337           tmpNeg = new TmpInstruction(mcfi, lval);
02338           unsigned opSize = target.getTargetData().getTypeSize(resultType);
02339           MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
02340           CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
02341                                   tmpNeg, mvec, mcfi);
02342         }
02343 
02344       }
02345 
02346       if (mvec.size() > 0 && needNeg) {
02347         MachineInstr* M = 0;
02348         if(tmpNeg)
02349         // insert <reg = SUB 0, reg> after the instr to flip the sign
02350           M = CreateIntNegInstruction(target, tmpNeg, destVal);
02351         else
02352           M = CreateIntNegInstruction(target, destVal);
02353         mvec.push_back(M);
02354       }
02355     }
02356   } else {
02357     if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
02358       double dval = FPC->getValue();
02359       if (fabs(dval) == 1) {
02360         MachineOpCode opCode =  (dval < 0)
02361           ? (resultType == Type::FloatTy? V9::FNEGS : V9::FNEGD)
02362           : (resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD);
02363         mvec.push_back(BuildMI(opCode,2).addReg(lval).addRegDef(destVal));
02364       }
02365     }
02366   }
02367 
02368   if (firstNewInstr < mvec.size()) {
02369     cost = 0;
02370     for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
02371       cost += target.getInstrInfo()->minLatency(mvec[i]->getOpcode());
02372   }
02373 
02374   return cost;
02375 }
02376 
02377 /// CreateCheapestMulConstInstruction - Does not create any instructions
02378 /// if we cannot exploit constant to create a cheaper instruction.
02379 ///
02380 static inline void
02381 CreateCheapestMulConstInstruction(const TargetMachine &target, Function* F,
02382                                   Value* lval, Value* rval,
02383                                   Instruction* destVal,
02384                                   std::vector<MachineInstr*>& mvec,
02385                                   MachineCodeForInstruction& mcfi) {
02386   Value* constOp;
02387   if (isa<Constant>(lval) && isa<Constant>(rval)) {
02388     // both operands are constant: evaluate and "set" in dest
02389     Constant* P = ConstantExpr::get(Instruction::Mul,
02390                                     cast<Constant>(lval),
02391                                     cast<Constant>(rval));
02392     CreateCodeToLoadConst (target, F, P, destVal, mvec, mcfi);
02393   }
02394   else if (isa<Constant>(rval))         // rval is constant, but not lval
02395     CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
02396   else if (isa<Constant>(lval))         // lval is constant, but not rval
02397     CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
02398 
02399   // else neither is constant
02400   return;
02401 }
02402 
02403 /// CreateMulInstruction - Returns NULL if we cannot exploit constant
02404 /// to create a cheaper instruction.
02405 ///
02406 static inline void
02407 CreateMulInstruction(const TargetMachine &target, Function* F,
02408                      Value* lval, Value* rval, Instruction* destVal,
02409                      std::vector<MachineInstr*>& mvec,
02410                      MachineCodeForInstruction& mcfi,
02411                      MachineOpCode forceMulOp = -1) {
02412   unsigned L = mvec.size();
02413   CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
02414   if (mvec.size() == L) {
02415     // no instructions were added so create MUL reg, reg, reg.
02416     // Use FSMULD if both operands are actually floats cast to doubles.
02417     // Otherwise, use the default opcode for the appropriate type.
02418     MachineOpCode mulOp = ((forceMulOp != -1)
02419                            ? forceMulOp
02420                            : ChooseMulInstructionByType(destVal->getType()));
02421     mvec.push_back(BuildMI(mulOp, 3).addReg(lval).addReg(rval)
02422                    .addRegDef(destVal));
02423   }
02424 }
02425 
02426 /// ChooseDivInstruction - Generate a divide instruction for Div or Rem.
02427 /// For Rem, this assumes that the operand type will be signed if the result
02428 /// type is signed.  This is correct because they must have the same sign.
02429 ///
02430 static inline MachineOpCode
02431 ChooseDivInstruction(TargetMachine &target, const InstructionNode* instrNode) {
02432   MachineOpCode opCode = V9::INVALID_OPCODE;
02433 
02434   const Type* resultType = instrNode->getInstruction()->getType();
02435 
02436   if (resultType->isInteger())
02437     opCode = resultType->isSigned()? V9::SDIVXr : V9::UDIVXr;
02438   else
02439     switch(resultType->getTypeID()) {
02440       case Type::FloatTyID:  opCode = V9::FDIVS; break;
02441       case Type::DoubleTyID: opCode = V9::FDIVD; break;
02442       default: assert(0 && "Invalid type for DIV instruction"); break;
02443       }
02444 
02445   return opCode;
02446 }
02447 
02448 /// CreateDivConstInstruction - Return if we cannot exploit constant to create
02449 /// a cheaper instruction.
02450 ///
02451 static void CreateDivConstInstruction(TargetMachine &target,
02452                                       const InstructionNode* instrNode,
02453                                       std::vector<MachineInstr*>& mvec) {
02454   Value* LHS  = instrNode->leftChild()->getValue();
02455   Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
02456   if (!isa<Constant>(constOp))
02457     return;
02458 
02459   Instruction* destVal = instrNode->getInstruction();
02460   unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
02461 
02462   // Cases worth optimizing are:
02463   // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
02464   // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
02465   const Type* resultType = instrNode->getInstruction()->getType();
02466 
02467   if (resultType->isInteger()) {
02468     bool isValidConst;
02469     int64_t C = (int64_t) ConvertConstantToIntType(target, constOp,
02470                                                    constOp->getType(),
02471                                                    isValidConst);
02472     if (isValidConst) {
02473       bool needNeg = false;
02474       if (C < 0) {
02475         needNeg = true;
02476         C = -C;
02477       }
02478 
02479       if (C == 1) {
02480         mvec.push_back(BuildMI(V9::ADDr, 3).addReg(LHS).addMReg(ZeroReg)
02481                        .addRegDef(destVal));
02482       } else if (isPowerOf2_64(C)) {
02483         unsigned pow = Log2_64(C);
02484         unsigned opCode;
02485         Value* shiftOperand;
02486         unsigned opSize = target.getTargetData().getTypeSize(resultType);
02487 
02488         if (resultType->isSigned()) {
02489           // For N / 2^k, if the operand N is negative,
02490           // we need to add (2^k - 1) before right-shifting by k, i.e.,
02491           //
02492           //    (N / 2^k) = N >> k,               if N >= 0;
02493           //                (N + 2^k - 1) >> k,   if N < 0
02494           //
02495           // If N is <= 32 bits, use:
02496           //    sra N, 31, t1           // t1 = ~0,         if N < 0,  0 else
02497           //    srl t1, 32-k, t2        // t2 = 2^k - 1,    if N < 0,  0 else
02498           //    add t2, N, t3           // t3 = N + 2^k -1, if N < 0,  N else
02499           //    sra t3, k, result       // result = N / 2^k
02500           //
02501           // If N is 64 bits, use:
02502           //    srax N,  k-1,  t1       // t1 = sign bit in high k positions
02503           //    srlx t1, 64-k, t2       // t2 = 2^k - 1,    if N < 0,  0 else
02504           //    add t2, N, t3           // t3 = N + 2^k -1, if N < 0,  N else
02505           //    sra t3, k, result       // result = N / 2^k
02506           TmpInstruction *sraTmp, *srlTmp, *addTmp;
02507           MachineCodeForInstruction& mcfi
02508             = MachineCodeForInstruction::get(destVal);
02509           sraTmp = new TmpInstruction(mcfi, resultType, LHS, 0, "getSign");
02510           srlTmp = new TmpInstruction(mcfi, resultType, LHS, 0, "getPlus2km1");
02511           addTmp = new TmpInstruction(mcfi, resultType, LHS, srlTmp,"incIfNeg");
02512 
02513           // Create the SRA or SRAX instruction to get the sign bit
02514           mvec.push_back(BuildMI((opSize > 4)? V9::SRAXi6 : V9::SRAi5, 3)
02515                          .addReg(LHS)
02516                          .addSImm((resultType==Type::LongTy)? pow-1 : 31)
02517                          .addRegDef(sraTmp));
02518 
02519           // Create the SRL or SRLX instruction to get the sign bit
02520           mvec.push_back(BuildMI((opSize > 4)? V9::SRLXi6 : V9::SRLi5, 3)
02521                          .addReg(sraTmp)
02522                          .addSImm((resultType==Type::LongTy)? 64-pow : 32-pow)
02523                          .addRegDef(srlTmp));
02524 
02525           // Create the ADD instruction to add 2^pow-1 for negative values
02526           mvec.push_back(BuildMI(V9::ADDr, 3).addReg(LHS).addReg(srlTmp)
02527                          .addRegDef(addTmp));
02528 
02529           // Get the shift operand and "right-shift" opcode to do the divide
02530           shiftOperand = addTmp;
02531           opCode = (opSize > 4)? V9::SRAXi6 : V9::SRAi5;
02532         } else {
02533           // Get the shift operand and "right-shift" opcode to do the divide
02534           shiftOperand = LHS;
02535           opCode = (opSize > 4)? V9::SRLXi6 : V9::SRLi5;
02536         }
02537 
02538         // Now do the actual shift!
02539         mvec.push_back(BuildMI(opCode, 3).addReg(shiftOperand).addZImm(pow)
02540                        .addRegDef(destVal));
02541       }
02542 
02543       if (needNeg && (C == 1 || isPowerOf2_64(C))) {
02544         // insert <reg = SUB 0, reg> after the instr to flip the sign
02545         mvec.push_back(CreateIntNegInstruction(target, destVal));
02546       }
02547     }
02548   } else {
02549     if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
02550       double dval = FPC->getValue();
02551       if (fabs(dval) == 1) {
02552         unsigned opCode =
02553           (dval < 0) ? (resultType == Type::FloatTy? V9::FNEGS : V9::FNEGD)
02554           : (resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD);
02555 
02556         mvec.push_back(BuildMI(opCode, 2).addReg(LHS).addRegDef(destVal));
02557       }
02558     }
02559   }
02560 }
02561 
02562 static void CreateCodeForVariableSizeAlloca(const TargetMachine& target,
02563                                             Instruction* result, unsigned tsize,
02564                                             Value* numElementsVal,
02565                                             std::vector<MachineInstr*>& getMvec)
02566 {
02567   Value* totalSizeVal;
02568   MachineInstr* M;
02569   MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(result);
02570   Function *F = result->getParent()->getParent();
02571 
02572   // Enforce the alignment constraints on the stack pointer at
02573   // compile time if the total size is a known constant.
02574   if (isa<Constant>(numElementsVal)) {
02575     bool isValid;
02576     int64_t numElem = (int64_t)
02577       ConvertConstantToIntType(target, numElementsVal,
02578                                numElementsVal->getType(), isValid);
02579     assert(isValid && "Unexpectedly large array dimension in alloca!");
02580     int64_t total = numElem * tsize;
02581     if (int extra= total % SparcV9FrameInfo::StackFrameSizeAlignment)
02582       total += SparcV9FrameInfo::StackFrameSizeAlignment - extra;
02583     totalSizeVal = ConstantSInt::get(Type::IntTy, total);
02584   } else {
02585     // The size is not a constant.  Generate code to compute it and
02586     // code to pad the size for stack alignment.
02587     // Create a Value to hold the (constant) element size
02588     Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
02589 
02590     // Create temporary values to hold the result of MUL, SLL, SRL
02591     // To pad `size' to next smallest multiple of 16:
02592     //          size = (size + 15) & (-16 = 0xfffffffffffffff0)
02593     TmpInstruction* tmpProd = new TmpInstruction(mcfi,numElementsVal, tsizeVal);
02594     TmpInstruction* tmpAdd15= new TmpInstruction(mcfi,numElementsVal, tmpProd);
02595     TmpInstruction* tmpAndf0= new TmpInstruction(mcfi,numElementsVal, tmpAdd15);
02596 
02597     // Instruction 1: mul numElements, typeSize -> tmpProd
02598     // This will optimize the MUL as far as possible.
02599     CreateMulInstruction(target, F, numElementsVal, tsizeVal, tmpProd, getMvec,
02600                          mcfi, -1);
02601 
02602     // Instruction 2: andn tmpProd, 0x0f -> tmpAndn
02603     getMvec.push_back(BuildMI(V9::ADDi, 3).addReg(tmpProd).addSImm(15)
02604                       .addReg(tmpAdd15, MachineOperand::Def));
02605 
02606     // Instruction 3: add tmpAndn, 0x10 -> tmpAdd16
02607     getMvec.push_back(BuildMI(V9::ANDi, 3).addReg(tmpAdd15).addSImm(-16)
02608                       .addReg(tmpAndf0, MachineOperand::Def));
02609 
02610     totalSizeVal = tmpAndf0;
02611   }
02612 
02613   // Get the constant offset from SP for dynamically allocated storage
02614   // and create a temporary Value to hold it.
02615   MachineFunction& mcInfo = MachineFunction::get(F);
02616   bool growUp;
02617   ConstantSInt* dynamicAreaOffset =
02618     ConstantSInt::get(Type::IntTy,
02619                     target.getFrameInfo()->getDynamicAreaOffset(mcInfo,growUp));
02620   assert(! growUp && "Has SPARC v9 stack frame convention changed?");
02621 
02622   unsigned SPReg = target.getRegInfo()->getStackPointer();
02623 
02624   // Instruction 2: sub %sp, totalSizeVal -> %sp
02625   getMvec.push_back(BuildMI(V9::SUBr, 3).addMReg(SPReg).addReg(totalSizeVal)
02626                     .addMReg(SPReg,MachineOperand::Def));
02627 
02628   // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
02629   getMvec.push_back(BuildMI(V9::ADDr,3).addMReg(SPReg).addReg(dynamicAreaOffset)
02630                     .addRegDef(result));
02631 }
02632 
02633 static void
02634 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
02635                              Instruction* result, unsigned tsize,
02636                              unsigned numElements,
02637                              std::vector<MachineInstr*>& getMvec) {
02638   assert(result && result->getParent() &&
02639          "Result value is not part of a function?");
02640   Function *F = result->getParent()->getParent();
02641   MachineFunction &mcInfo = MachineFunction::get(F);
02642 
02643   // If the alloca is of zero bytes (which is perfectly legal) we bump it up to
02644   // one byte.  This is unnecessary, but I really don't want to break any
02645   // fragile logic in this code.  FIXME.
02646   if (tsize == 0)
02647     tsize = 1;
02648 
02649   // Put the variable in the dynamically sized area of the frame if either:
02650   // (a) The offset is too large to use as an immediate in load/stores
02651   //     (check LDX because all load/stores have the same-size immed. field).
02652   // (b) The object is "large", so it could cause many other locals,
02653   //     spills, and temporaries to have large offsets.
02654   //     NOTE: We use LARGE = 8 * argSlotSize = 64 bytes.
02655   // You've gotta love having only 13 bits for constant offset values :-|.
02656   //
02657   unsigned paddedSize;
02658   int offsetFromFP = mcInfo.getInfo<SparcV9FunctionInfo>()->computeOffsetforLocalVar(result,
02659                                                                 paddedSize,
02660                                                          tsize * numElements);
02661 
02662   if (((int)paddedSize) > 8 * SparcV9FrameInfo::SizeOfEachArgOnStack ||
02663       !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
02664     CreateCodeForVariableSizeAlloca(target, result, tsize,
02665                                     ConstantSInt::get(Type::IntTy,numElements),
02666                                     getMvec);
02667     return;
02668   }
02669 
02670   // else offset fits in immediate field so go ahead and allocate it.
02671   offsetFromFP = mcInfo.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(result, tsize *numElements);
02672 
02673   // Create a temporary Value to hold the constant offset.
02674   // This is needed because it may not fit in the immediate field.
02675   ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
02676 
02677   // Instruction 1: add %fp, offsetFromFP -> result
02678   unsigned FPReg = target.getRegInfo()->getFramePointer();
02679   getMvec.push_back(BuildMI(V9::ADDr, 3).addMReg(FPReg).addReg(offsetVal)
02680                     .addRegDef(result));
02681 }
02682 
02683 /// SetOperandsForMemInstr - Choose addressing mode for the given load or store
02684 /// instruction.  Use [reg+reg] if it is an indexed reference, and the index
02685 /// offset is not a constant or if it cannot fit in the offset field.  Use
02686 /// [reg+offset] in all other cases.  This assumes that all array refs are
02687 /// "lowered" to one of these forms:
02688 ///    %x = load (subarray*) ptr, constant      ; single constant offset
02689 ///    %x = load (subarray*) ptr, offsetVal     ; single non-constant offset
02690 /// Generally, this should happen via strength reduction + LICM.  Also, strength
02691 /// reduction should take care of using the same register for the loop index
02692 /// variable and an array index, when that is profitable.
02693 ///
02694 static void SetOperandsForMemInstr(unsigned Opcode,
02695                                    std::vector<MachineInstr*>& mvec,
02696                                    InstructionNode* vmInstrNode,
02697                                    const TargetMachine& target) {
02698   Instruction* memInst = vmInstrNode->getInstruction();
02699   // Index vector, ptr value, and flag if all indices are const.
02700   std::vector<Value*> idxVec;
02701   bool allConstantIndices;
02702   Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices);
02703 
02704   // Now create the appropriate operands for the machine instruction.
02705   // First, initialize so we default to storing the offset in a register.
02706   int64_t smallConstOffset = 0;
02707   Value* valueForRegOffset = NULL;
02708   MachineOperand::MachineOperandType offsetOpType =
02709     MachineOperand::MO_VirtualRegister;
02710 
02711   // Check if there is an index vector and if so, compute the
02712   // right offset for structures and for arrays
02713   if (!idxVec.empty()) {
02714     const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
02715 
02716     // If all indices are constant, compute the combined offset directly.
02717     if (allConstantIndices) {
02718       // Compute the offset value using the index vector. Create a
02719       // virtual reg. for it since it may not fit in the immed field.
02720       uint64_t offset = target.getTargetData().getIndexedOffset(ptrType,idxVec);
02721       valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
02722     } else {
02723       // There is at least one non-constant offset.  Therefore, this must
02724       // be an array ref, and must have been lowered to a single non-zero
02725       // offset.  (An extra leading zero offset, if any, can be ignored.)
02726       // Generate code sequence to compute address from index.
02727       bool firstIdxIsZero = IsZero(idxVec[0]);
02728       assert(idxVec.size() == 1U + firstIdxIsZero
02729              && "Array refs must be lowered before Instruction Selection");
02730 
02731       Value* idxVal = idxVec[firstIdxIsZero];
02732 
02733       std::vector<MachineInstr*> mulVec;
02734       Instruction* addr =
02735         new TmpInstruction(MachineCodeForInstruction::get(memInst),
02736                            Type::ULongTy, memInst);
02737 
02738       // Get the array type indexed by idxVal, and compute its element size.
02739       // The call to getTypeSize() will fail if size is not constant.
02740       const Type* vecType = (firstIdxIsZero
02741                              ? GetElementPtrInst::getIndexedType(ptrType,
02742                                            std::vector<Value*>(1U, idxVec[0]),
02743                                            /*AllowCompositeLeaf*/ true)
02744                                  : ptrType);
02745       const Type* eltType = cast<SequentialType>(vecType)->getElementType();
02746       ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy,
02747                                    target.getTargetData().getTypeSize(eltType));
02748 
02749       // CreateMulInstruction() folds constants intelligently enough.
02750       CreateMulInstruction(target, memInst->getParent()->getParent(),
02751                            idxVal,         /* lval, not likely to be const*/
02752                            eltSizeVal,     /* rval, likely to be constant */
02753                            addr,           /* result */
02754                            mulVec, MachineCodeForInstruction::get(memInst),
02755                            -1);
02756 
02757       assert(mulVec.size() > 0 && "No multiply code created?");
02758       mvec.insert(mvec.end(), mulVec.begin(), mulVec.end());
02759 
02760       valueForRegOffset = addr;
02761     }
02762   } else {
02763     offsetOpType = MachineOperand::MO_SignExtendedImmed;
02764     smallConstOffset = 0;
02765   }
02766 
02767   // For STORE:
02768   //   Operand 0 is value, operand 1 is ptr, operand 2 is offset
02769   // For LOAD or GET_ELEMENT_PTR,
02770   //   Operand 0 is ptr, operand 1 is offset, operand 2 is result.
02771   unsigned offsetOpNum, ptrOpNum;
02772   MachineInstr *MI;
02773   if (memInst->getOpcode() == Instruction::Store) {
02774     if (offsetOpType == MachineOperand::MO_VirtualRegister) {
02775       MI = BuildMI(Opcode, 3).addReg(vmInstrNode->leftChild()->getValue())
02776                              .addReg(ptrVal).addReg(valueForRegOffset);
02777     } else {
02778       Opcode = convertOpcodeFromRegToImm(Opcode);
02779       MI = BuildMI(Opcode, 3).addReg(vmInstrNode->leftChild()->getValue())
02780                              .addReg(ptrVal).addSImm(smallConstOffset);
02781     }
02782   } else {
02783     if (offsetOpType == MachineOperand::MO_VirtualRegister) {
02784       MI = BuildMI(Opcode, 3).addReg(ptrVal).addReg(valueForRegOffset)
02785                              .addRegDef(memInst);
02786     } else {
02787       Opcode = convertOpcodeFromRegToImm(Opcode);
02788       MI = BuildMI(Opcode, 3).addReg(ptrVal).addSImm(smallConstOffset)
02789                              .addRegDef(memInst);
02790     }
02791   }
02792   mvec.push_back(MI);
02793 }
02794 
02795 /// ForwardOperand - Substitute operand `operandNum' of the instruction in
02796 /// node `treeNode' in place of the use(s) of that instruction in node `parent'.
02797 /// Check both explicit and implicit operands!  Also make sure to skip over a
02798 /// parent who: (1) is a list node in the Burg tree, or (2) itself had its
02799 /// results forwarded to its parent.
02800 ///
02801 static void ForwardOperand (InstructionNode *treeNode, InstrTreeNode *parent,
02802                             int operandNum) {
02803   assert(treeNode && parent && "Invalid invocation of ForwardOperand");
02804 
02805   Instruction* unusedOp = treeNode->getInstruction();
02806   Value* fwdOp = unusedOp->getOperand(operandNum);
02807 
02808   // The parent itself may be a list node, so find the real parent instruction
02809   while (parent->getNodeType() != InstrTreeNode::NTInstructionNode) {
02810     parent = parent->parent();
02811     assert(parent && "ERROR: Non-instruction node has no parent in tree.");
02812   }
02813   InstructionNode* parentInstrNode = (InstructionNode*) parent;
02814 
02815   Instruction* userInstr = parentInstrNode->getInstruction();
02816   MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
02817 
02818   // The parent's mvec would be empty if it was itself forwarded.
02819   // Recursively call ForwardOperand in that case...
02820   //
02821   if (mvec.size() == 0) {
02822     assert(parent->parent() != NULL &&
02823            "Parent could not have been forwarded, yet has no instructions?");
02824     ForwardOperand(treeNode, parent->parent(), operandNum);
02825   } else {
02826     for (unsigned i=0, N=mvec.size(); i < N; i++) {
02827       MachineInstr* minstr = mvec[i];
02828       for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i) {
02829         const MachineOperand& mop = minstr->getOperand(i);
02830         if (mop.getType() == MachineOperand::MO_VirtualRegister &&
02831             mop.getVRegValue() == unusedOp) {
02832           minstr->SetMachineOperandVal(i, MachineOperand::MO_VirtualRegister,
02833                                        fwdOp);
02834         }
02835       }
02836 
02837       for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
02838         if (minstr->getImplicitRef(i) == unusedOp)
02839           minstr->setImplicitRef(i, fwdOp);
02840     }
02841   }
02842 }
02843 
02844 /// AllUsesAreBranches - Returns true if all the uses of I are
02845 /// Branch instructions, false otherwise.
02846 ///
02847 inline bool AllUsesAreBranches(const Instruction* I) {
02848   for (Value::use_const_iterator UI=I->use_begin(), UE=I->use_end();
02849        UI != UE; ++UI)
02850     if (! isa<TmpInstruction>(*UI)     // ignore tmp instructions here
02851         && cast<Instruction>(*UI)->getOpcode() != Instruction::Br)
02852       return false;
02853   return true;
02854 }
02855 
02856 /// CodeGenIntrinsic - Generate code for any intrinsic that needs a special
02857 /// code sequence instead of a regular call.  If not that kind of intrinsic, do
02858 /// nothing. Returns true if code was generated, otherwise false.
02859 ///
02860 static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr,
02861                              TargetMachine &target,
02862                              std::vector<MachineInstr*>& mvec) {
02863   switch (iid) {
02864   default:
02865     assert(0 && "Unknown intrinsic function call should have been lowered!");
02866   case Intrinsic::vastart: {
02867     // Get the address of the first incoming vararg argument on the stack
02868     Function* func = cast<Function>(callInstr.getParent()->getParent());
02869     int numFixedArgs   = func->getFunctionType()->getNumParams();
02870     int fpReg          = SparcV9::i6;
02871     int firstVarArgOff = numFixedArgs * 8 +
02872                          SparcV9FrameInfo::FirstIncomingArgOffsetFromFP;
02873     //What oh what do we pass to TmpInstruction?
02874     MachineCodeForInstruction& m = MachineCodeForInstruction::get(&callInstr);
02875     TmpInstruction* T = new TmpInstruction(m, callInstr.getOperand(1)->getType());
02876     mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).addRegDef(T));
02877     mvec.push_back(BuildMI(V9::STXr, 3).addReg(T).addReg(callInstr.getOperand(1)).addSImm(0));
02878     return true;
02879   }
02880 
02881   case Intrinsic::vaend:
02882     return true;                        // no-op on SparcV9
02883 
02884   case Intrinsic::vacopy:
02885     {
02886       MachineCodeForInstruction& m1 = MachineCodeForInstruction::get(&callInstr);
02887       TmpInstruction* VReg =
02888         new TmpInstruction(m1, callInstr.getOperand(1)->getType());
02889 
02890       // Simple store of current va_list (arg2) to new va_list (arg1)
02891       mvec.push_back(BuildMI(V9::LDXi, 3).
02892                      addReg(callInstr.getOperand(2)).addSImm(0).addRegDef(VReg));
02893       mvec.push_back(BuildMI(V9::STXi, 3).
02894                      addReg(VReg).addReg(callInstr.getOperand(1)).addSImm(0));
02895       return true;
02896     }
02897   }
02898 }
02899 
02900 /// ThisIsAChainRule - returns true if the given  BURG rule is a chain rule.
02901 ///
02902 extern bool ThisIsAChainRule(int eruleno) {
02903   switch(eruleno) {
02904     case 111:   // stmt:  reg
02905     case 123:
02906     case 124:
02907     case 125:
02908     case 126:
02909     case 127:
02910     case 128:
02911     case 129:
02912     case 130:
02913     case 131:
02914     case 132:
02915     case 133:
02916     case 155:
02917     case 221:
02918     case 222:
02919     case 241:
02920     case 242:
02921     case 243:
02922     case 244:
02923     case 245:
02924     case 321:
02925       return true; break;
02926 
02927     default:
02928       break;
02929     }
02930   return false;
02931 }
02932 
02933 /// GetInstructionsByRule - Choose machine instructions for the
02934 /// SPARC V9 according to the patterns chosen by the BURG-generated parser.
02935 /// This is where most of the work in the V9 instruction selector gets done.
02936 ///
02937 void GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode,
02938                            short* nts, TargetMachine &target,
02939                            std::vector<MachineInstr*>& mvec) {
02940   bool checkCast = false;               // initialize here to use fall-through
02941   bool maskUnsignedResult = false;
02942   int nextRule;
02943   int forwardOperandNum = -1;
02944   unsigned allocaSize = 0;
02945   MachineInstr* M, *M2;
02946   unsigned L;
02947   bool foldCase = false;
02948 
02949   mvec.clear();
02950 
02951   // If the code for this instruction was folded into the parent (user),
02952   // then do nothing!
02953   if (subtreeRoot->isFoldedIntoParent())
02954     return;
02955 
02956   // Let's check for chain rules outside the switch so that we don't have
02957   // to duplicate the list of chain rule production numbers here again
02958   if (ThisIsAChainRule(ruleForNode)) {
02959     // Chain rules have a single nonterminal on the RHS.
02960     // Get the rule that matches the RHS non-terminal and use that instead.
02961     assert(nts[0] && ! nts[1]
02962            && "A chain rule should have only one RHS non-terminal!");
02963     nextRule = burm_rule(subtreeRoot->state, nts[0]);
02964     nts = burm_nts[nextRule];
02965     GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
02966   } else {
02967     switch(ruleForNode) {
02968       case 1:   // stmt:   Ret
02969       case 2:   // stmt:   RetValue(reg)
02970       {         // NOTE: Prepass of register allocation is responsible
02971                 //       for moving return value to appropriate register.
02972                 // Copy the return value to the required return register.
02973                 // Mark the return Value as an implicit ref of the RET instr..
02974                 // Mark the return-address register as a hidden virtual reg.
02975                 // Finally put a NOP in the delay slot.
02976         ReturnInst *returnInstr=cast<ReturnInst>(subtreeRoot->getInstruction());
02977         Value* retVal = returnInstr->getReturnValue();
02978         MachineCodeForInstruction& mcfi =
02979           MachineCodeForInstruction::get(returnInstr);
02980 
02981         // Create a hidden virtual reg to represent the return address register
02982         // used by the machine instruction but not represented in LLVM.
02983         Instruction* returnAddrTmp = new TmpInstruction(mcfi, returnInstr);
02984 
02985         MachineInstr* retMI =
02986           BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
02987           .addMReg(target.getRegInfo()->getZeroRegNum(), MachineOperand::Def);
02988 
02989         // If there is a value to return, we need to:
02990         // (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
02991         // (b) Insert a copy to copy the return value to the appropriate reg.
02992         //     -- For FP values, create a FMOVS or FMOVD instruction
02993         //     -- For non-FP values, create an add-with-0 instruction
02994         if (retVal != NULL) {
02995           const SparcV9RegInfo& regInfo =
02996             (SparcV9RegInfo&) *target.getRegInfo();
02997           const Type* retType = retVal->getType();
02998           unsigned regClassID = regInfo.getRegClassIDOfType(retType);
02999           unsigned retRegNum = (retType->isFloatingPoint()
03000                                 ? (unsigned) SparcV9FloatRegClass::f0
03001                                 : (unsigned) SparcV9IntRegClass::i0);
03002           retRegNum = regInfo.getUnifiedRegNum(regClassID, retRegNum);
03003 
03004           // Insert sign-extension instructions for small signed values.
03005           Value* retValToUse = retVal;
03006           if (retType->isIntegral() && retType->isSigned()) {
03007             unsigned retSize = target.getTargetData().getTypeSize(retType);
03008             if (retSize <= 4) {
03009               // Create a temporary virtual reg. to hold the sign-extension.
03010               retValToUse = new TmpInstruction(mcfi, retVal);
03011 
03012               // Sign-extend retVal and put the result in the temporary reg.
03013               CreateSignExtensionInstructions
03014                 (target, returnInstr->getParent()->getParent(),
03015                  retVal, retValToUse, 8*retSize, mvec, mcfi);
03016             }
03017           }
03018 
03019           // (b) Now, insert a copy to to the appropriate register:
03020           //     -- For FP values, create a FMOVS or FMOVD instruction
03021           //     -- For non-FP values, create an add-with-0 instruction
03022           // First, create a virtual register to represent the register and
03023           // mark this vreg as being an implicit operand of the ret MI.
03024           TmpInstruction* retVReg =
03025             new TmpInstruction(mcfi, retValToUse, NULL, "argReg");
03026 
03027           retMI->addImplicitRef(retVReg);
03028 
03029           if (retType->isFloatingPoint())
03030             M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
03031                  .addReg(retValToUse).addReg(retVReg, MachineOperand::Def));
03032           else
03033             M = (BuildMI(ChooseAddInstructionByType(retType), 3)
03034                  .addReg(retValToUse).addSImm((int64_t) 0)
03035                  .addReg(retVReg, MachineOperand::Def));
03036 
03037           // Mark the operand with the register it should be assigned
03038           M->SetRegForOperand(M->getNumOperands()-1, retRegNum);
03039           retMI->SetRegForImplicitRef(retMI->getNumImplicitRefs()-1, retRegNum);
03040 
03041           mvec.push_back(M);
03042         }
03043 
03044         // Now insert the RET instruction and a NOP for the delay slot
03045         mvec.push_back(retMI);
03046         mvec.push_back(BuildMI(V9::NOP, 0));
03047 
03048         break;
03049       }
03050 
03051       case 3:   // stmt:   Store(reg,reg)
03052       case 4:   // stmt:   Store(reg,ptrreg)
03053         SetOperandsForMemInstr(ChooseStoreInstruction(
03054                         subtreeRoot->leftChild()->getValue()->getType()),
03055                                mvec, subtreeRoot, target);
03056         break;
03057 
03058       case 5:   // stmt:   BrUncond
03059         {
03060           BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
03061           mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(0)));
03062 
03063           // delay slot
03064           mvec.push_back(BuildMI(V9::NOP, 0));
03065           break;
03066         }
03067 
03068       case 206: // stmt:   BrCond(setCCconst)
03069       { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
03070         // If the constant is ZERO, we can use the branch-on-integer-register
03071         // instructions and avoid the SUBcc instruction entirely.
03072         // Otherwise this is just the same as case 5, so just fall through.
03073         //
03074         InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
03075         assert(constNode &&
03076                constNode->getNodeType() ==InstrTreeNode::NTConstNode);
03077         Constant *constVal = cast<Constant>(constNode->getValue());
03078         bool isValidConst;
03079 
03080         if ((constVal->getType()->isInteger()
03081              || isa<PointerType>(constVal->getType()))
03082             && ConvertConstantToIntType(target,
03083                              constVal, constVal->getType(), isValidConst) == 0
03084             && isValidConst)
03085           {
03086             // That constant is a zero after all...
03087             // Use the left child of setCC as the first argument!
03088             // Mark the setCC node so that no code is generated for it.
03089             InstructionNode* setCCNode = (InstructionNode*)
03090                                          subtreeRoot->leftChild();
03091             assert(setCCNode->getOpLabel() == SetCCOp);
03092             setCCNode->markFoldedIntoParent();
03093 
03094             BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
03095 
03096             M = BuildMI(ChooseBprInstruction(subtreeRoot), 2)
03097                                 .addReg(setCCNode->leftChild()->getValue())
03098                                 .addPCDisp(brInst->getSuccessor(0));
03099             mvec.push_back(M);
03100 
03101             // delay slot
03102             mvec.push_back(BuildMI(V9::NOP, 0));
03103 
03104             // false branch
03105             mvec.push_back(BuildMI(V9::BA, 1)
03106                            .addPCDisp(brInst->getSuccessor(1)));
03107 
03108             // delay slot
03109             mvec.push_back(BuildMI(V9::NOP, 0));
03110             break;
03111           }
03112         // ELSE FALL THROUGH
03113       }
03114 
03115       case 6:   // stmt:   BrCond(setCC)
03116       { // bool => boolean was computed with SetCC.
03117         // The branch to use depends on whether it is FP, signed, or unsigned.
03118         // If it is an integer CC, we also need to find the unique
03119         // TmpInstruction representing that CC.
03120         //
03121         BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
03122         const Type* setCCType;
03123         unsigned Opcode = ChooseBccInstruction(subtreeRoot, setCCType);
03124         Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
03125                                      brInst->getParent()->getParent(),
03126                                      setCCType,
03127                                      MachineCodeForInstruction::get(brInst));
03128         M = BuildMI(Opcode, 2).addCCReg(ccValue)
03129                               .addPCDisp(brInst->getSuccessor(0));
03130         mvec.push_back(M);
03131 
03132         // delay slot
03133         mvec.push_back(BuildMI(V9::NOP, 0));
03134 
03135         // false branch
03136         mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(brInst->getSuccessor(1)));
03137 
03138         // delay slot
03139         mvec.push_back(BuildMI(V9::NOP, 0));
03140         break;
03141       }
03142 
03143       case 208: // stmt:   BrCond(boolconst)
03144       {
03145         // boolconst => boolean is a constant; use BA to first or second label
03146         Constant* constVal =
03147           cast<Constant>(subtreeRoot->leftChild()->getValue());
03148         unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
03149 
03150         M = BuildMI(V9::BA, 1).addPCDisp(
03151           cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
03152         mvec.push_back(M);
03153 
03154         // delay slot
03155         mvec.push_back(BuildMI(V9::NOP, 0));
03156         break;
03157       }
03158 
03159       case   8: // stmt:   BrCond(boolreg)
03160       { // boolreg   => boolean is recorded in an integer register.
03161         //              Use branch-on-integer-register instruction.
03162         //
03163         BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
03164         M = BuildMI(V9::BRNZ, 2).addReg(subtreeRoot->leftChild()->getValue())
03165           .addPCDisp(BI->getSuccessor(0));
03166         mvec.push_back(M);
03167 
03168         // delay slot
03169         mvec.push_back(BuildMI(V9::NOP, 0));
03170 
03171         // false branch
03172         mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(1)));
03173 
03174         // delay slot
03175         mvec.push_back(BuildMI(V9::NOP, 0));
03176         break;
03177       }
03178 
03179       case 9:   // stmt:   Switch(reg)
03180         assert(0 && "*** SWITCH instruction is not implemented yet.");
03181         break;
03182 
03183       case 10:  // reg:   VRegList(reg, reg)
03184         assert(0 && "VRegList should never be the topmost non-chain rule");
03185         break;
03186 
03187       case 21:  // bool:  Not(bool,reg): Compute with a conditional-move-on-reg
03188       { // First find the unary operand. It may be left or right, usually right.
03189         Instruction* notI = subtreeRoot->getInstruction();
03190         Value* notArg = BinaryOperator::getNotArgument(
03191                            cast<BinaryOperator>(subtreeRoot->getInstruction()));
03192         unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
03193 
03194         // Unconditionally set register to 0
03195         mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(notI));
03196 
03197         // Now conditionally move 1 into the register.
03198         // Mark the register as a use (as well as a def) because the old
03199         // value will be retained if the condition is false.
03200         mvec.push_back(BuildMI(V9::MOVRZi, 3).addReg(notArg).addZImm(1)
03201                        .addReg(notI, MachineOperand::UseAndDef));
03202 
03203         break;
03204       }
03205 
03206       case 421: // reg:   BNot(reg,reg): Compute as reg = reg XOR-NOT 0
03207       { // First find the unary operand. It may be left or right, usually right.
03208         Value* notArg = BinaryOperator::getNotArgument(
03209                            cast<BinaryOperator>(subtreeRoot->getInstruction()));
03210         unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
03211         mvec.push_back(BuildMI(V9::XNORr, 3).addReg(notArg).addMReg(ZeroReg)
03212                                        .addRegDef(subtreeRoot->getValue()));
03213         break;
03214       }
03215 
03216       case 322: // reg:   Not(tobool, reg):
03217         // Fold CAST-TO-BOOL with NOT by inverting the sense of cast-to-bool
03218         foldCase = true;
03219         // Just fall through!
03220 
03221       case 22:  // reg:   ToBoolTy(reg):
03222       {
03223         Instruction* castI = subtreeRoot->getInstruction();
03224         Value* opVal = subtreeRoot->leftChild()->getValue();
03225         MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
03226         TmpInstruction* tempReg =
03227           new TmpInstruction(mcfi, opVal);
03228 
03229 
03230 
03231         assert(opVal->getType()->isIntegral() ||
03232                isa<PointerType>(opVal->getType()));
03233 
03234         // Unconditionally set register to 0
03235         mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(castI));
03236 
03237         // Now conditionally move 1 into the register.
03238         // Mark the register as a use (as well as a def) because the old
03239         // value will be retained if the condition is false.
03240         MachineOpCode opCode = foldCase? V9::MOVRZi : V9::MOVRNZi;
03241         mvec.push_back(BuildMI(opCode, 3).addReg(opVal).addZImm(1)
03242                        .addReg(castI, MachineOperand::UseAndDef));
03243 
03244         break;
03245       }
03246 
03247       case 23:  // reg:   ToUByteTy(reg)
03248       case 24:  // reg:   ToSByteTy(reg)
03249       case 25:  // reg:   ToUShortTy(reg)
03250       case 26:  // reg:   ToShortTy(reg)
03251       case 27:  // reg:   ToUIntTy(reg)
03252       case 28:  // reg:   ToIntTy(reg)
03253       case 29:  // reg:   ToULongTy(reg)
03254       case 30:  // reg:   ToLongTy(reg)
03255       {
03256         //======================================================================
03257         // Rules for integer conversions:
03258         //
03259         //--------
03260         // From ISO 1998 C++ Standard, Sec. 4.7:
03261         //
03262         // 2. If the destination type is unsigned, the resulting value is
03263         // the least unsigned integer congruent to the source integer
03264         // (modulo 2n where n is the number of bits used to represent the
03265         // unsigned type). [Note: In a two s complement representation,
03266         // this conversion is conceptual and there is no change in the
03267         // bit pattern (if there is no truncation). ]
03268         //
03269         // 3. If the destination type is signed, the value is unchanged if
03270         // it can be represented in the destination type (and bitfield width);
03271         // otherwise, the value is implementation-defined.
03272         //--------
03273         //
03274         // Since we assume 2s complement representations, this implies:
03275         //
03276         // -- If operand is smaller than destination, zero-extend or sign-extend
03277         //    according to the signedness of the *operand*: source decides:
03278         //    (1) If operand is signed, sign-extend it.
03279         //        If dest is unsigned, zero-ext the result!
03280         //    (2) If operand is unsigned, our current invariant is that
03281         //        it's high bits are correct, so zero-extension is not needed.
03282         //
03283         // -- If operand is same size as or larger than destination,
03284         //    zero-extend or sign-extend according to the signedness of
03285         //    the *destination*: destination decides:
03286         //    (1) If destination is signed, sign-extend (truncating if needed)
03287         //        This choice is implementation defined.  We sign-extend the
03288         //        operand, which matches both Sun's cc and gcc3.2.
03289         //    (2) If destination is unsigned, zero-extend (truncating if needed)
03290         //======================================================================
03291 
03292         Instruction* destI =  subtreeRoot->getInstruction();
03293         Function* currentFunc = destI->getParent()->getParent();
03294         MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(destI);
03295 
03296         Value* opVal = subtreeRoot->leftChild()->getValue();
03297         const Type* opType = opVal->getType();
03298         const Type* destType = destI->getType();
03299         unsigned opSize   = target.getTargetData().getTypeSize(opType);
03300         unsigned destSize = target.getTargetData().getTypeSize(destType);
03301 
03302         bool isIntegral = opType->isIntegral() || isa<PointerType>(opType);
03303 
03304         if (opType == Type::BoolTy ||
03305             opType == destType ||
03306             isIntegral && opSize == destSize && opSize == 8) {
03307           // nothing to do in all these cases
03308           forwardOperandNum = 0;          // forward first operand to user
03309 
03310         } else if (opType->isFloatingPoint()) {
03311 
03312           CreateCodeToConvertFloatToInt(target, opVal, destI, mvec, mcfi);
03313           if (destI->getType()->isUnsigned() && destI->getType() !=Type::UIntTy)
03314             maskUnsignedResult = true; // not handled by fp->int code
03315 
03316         } else if (isIntegral) {
03317 
03318           bool opSigned     = opType->isSigned();
03319           bool destSigned   = destType->isSigned();
03320           unsigned extSourceInBits = 8 * std::min<unsigned>(opSize, destSize);
03321 
03322           assert(! (opSize == destSize && opSigned == destSigned) &&
03323                  "How can different int types have same size and signedness?");
03324 
03325           bool signExtend = (opSize <  destSize && opSigned ||
03326                              opSize >= destSize && destSigned);
03327 
03328           bool signAndZeroExtend = (opSize < destSize && destSize < 8u &&
03329                                     opSigned && !destSigned);
03330           assert(!signAndZeroExtend || signExtend);
03331 
03332           bool zeroExtendOnly = opSize >= destSize && !destSigned;
03333           assert(!zeroExtendOnly || !signExtend);
03334 
03335           if (signExtend) {
03336             Value* signExtDest = (signAndZeroExtend
03337                                   ? new TmpInstruction(mcfi, destType, opVal)
03338                                   : destI);
03339 
03340             CreateSignExtensionInstructions
03341               (target, currentFunc,opVal,signExtDest,extSourceInBits,mvec,mcfi);
03342 
03343             if (signAndZeroExtend)
03344               CreateZeroExtensionInstructions
03345               (target, currentFunc, signExtDest, destI, 8*destSize, mvec, mcfi);
03346           }
03347           else if (zeroExtendOnly) {
03348             CreateZeroExtensionInstructions
03349               (target, currentFunc, opVal, destI, extSourceInBits, mvec, mcfi);
03350           }
03351           else
03352             forwardOperandNum = 0;          // forward first operand to user
03353 
03354         } else
03355           assert(0 && "Unrecognized operand type for convert-to-integer");
03356 
03357         break;
03358       }
03359 
03360       case  31: // reg:   ToFloatTy(reg):
03361       case  32: // reg:   ToDoubleTy(reg):
03362       case 232: // reg:   ToDoubleTy(Constant):
03363 
03364         // If this instruction has a parent (a user) in the tree
03365         // and the user is translated as an FsMULd instruction,
03366         // then the cast is unnecessary.  So check that first.
03367         // In the future, we'll want to do the same for the FdMULq instruction,
03368         // so do the check here instead of only for ToFloatTy(reg).
03369         //
03370         if (subtreeRoot->parent() != NULL) {
03371           const MachineCodeForInstruction& mcfi =
03372             MachineCodeForInstruction::get(
03373                 cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
03374           if (mcfi.size() == 0 || mcfi.front()->getOpcode() == V9::FSMULD)
03375             forwardOperandNum = 0;    // forward first operand to user
03376         }
03377 
03378         if (forwardOperandNum != 0) {    // we do need the cast
03379           Value* leftVal = subtreeRoot->leftChild()->getValue();
03380           const Type* opType = leftVal->getType();
03381           MachineOpCode opCode=ChooseConvertToFloatInstr(target,
03382                                        subtreeRoot->getOpLabel(), opType);
03383           if (opCode == V9::NOP) {      // no conversion needed
03384             forwardOperandNum = 0;      // forward first operand to user
03385           } else {
03386             // If the source operand is a non-FP type it must be
03387             // first copied from int to float register via memory!
03388             Instruction *dest = subtreeRoot->getInstruction();
03389             Value* srcForCast;
03390             int n = 0;
03391             if (! opType->isFloatingPoint()) {
03392               // Create a temporary to represent the FP register
03393               // into which the integer will be copied via memory.
03394               // The type of this temporary will determine the FP
03395               // register used: single-prec for a 32-bit int or smaller,
03396               // double-prec for a 64-bit int.
03397               //
03398               uint64_t srcSize =
03399                 target.getTargetData().getTypeSize(leftVal->getType());
03400               Type* tmpTypeToUse =
03401                 (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
03402               MachineCodeForInstruction &destMCFI =
03403                 MachineCodeForInstruction::get(dest);
03404               srcForCast = new TmpInstruction(destMCFI, tmpTypeToUse, dest);
03405 
03406               CreateCodeToCopyIntToFloat(target,
03407                          dest->getParent()->getParent(),
03408                          leftVal, cast<Instruction>(srcForCast),
03409                          mvec, destMCFI);
03410             } else
03411               srcForCast = leftVal;
03412 
03413             M = BuildMI(opCode, 2).addReg(srcForCast).addRegDef(dest);
03414             mvec.push_back(M);
03415           }
03416         }
03417         break;
03418 
03419       case 19:  // reg:   ToArrayTy(reg):
03420       case 20:  // reg:   ToPointerTy(reg):
03421         forwardOperandNum = 0;          // forward first operand to user
03422         break;
03423 
03424       case 233: // reg:   Add(reg, Constant)
03425         maskUnsignedResult = true;
03426         M = CreateAddConstInstruction(subtreeRoot);
03427         if (M != NULL) {
03428           mvec.push_back(M);
03429           break;
03430         }
03431         // ELSE FALL THROUGH
03432 
03433       case 33:  // reg:   Add(reg, reg)
03434         maskUnsignedResult = true;
03435         Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec);
03436         break;
03437 
03438       case 234: // reg:   Sub(reg, Constant)
03439         maskUnsignedResult = true;
03440         M = CreateSubConstInstruction(subtreeRoot);
03441         if (M != NULL) {
03442           mvec.push_back(M);
03443           break;
03444         }
03445         // ELSE FALL THROUGH
03446 
03447       case 34:  // reg:   Sub(reg, reg)
03448         maskUnsignedResult = true;
03449         Add3OperandInstr(ChooseSubInstructionByType(
03450                                    subtreeRoot->getInstruction()->getType()),
03451                          subtreeRoot, mvec);
03452         break;
03453 
03454       case 135: // reg:   Mul(todouble, todouble)
03455         checkCast = true;
03456         // FALL THROUGH
03457 
03458       case 35:  // reg:   Mul(reg, reg)
03459       {
03460         maskUnsignedResult = true;
03461         MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
03462                                  ? (MachineOpCode)V9::FSMULD
03463                                  : -1);
03464         Instruction* mulInstr = subtreeRoot->getInstruction();
03465         CreateMulInstruction(target, mulInstr->getParent()->getParent(),
03466                              subtreeRoot->leftChild()->getValue(),
03467                              subtreeRoot->rightChild()->getValue(),
03468                              mulInstr, mvec,
03469                              MachineCodeForInstruction::get(mulInstr),forceOp);
03470         break;
03471       }
03472       case 335: // reg:   Mul(todouble, todoubleConst)
03473         checkCast = true;
03474         // FALL THROUGH
03475 
03476       case 235: // reg:   Mul(reg, Constant)
03477       {
03478         maskUnsignedResult = true;
03479         MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
03480                                  ? (MachineOpCode)V9::FSMULD
03481                                  : -1);
03482         Instruction* mulInstr = subtreeRoot->getInstruction();
03483         CreateMulInstruction(target, mulInstr->getParent()->getParent(),
03484                              subtreeRoot->leftChild()->getValue(),
03485                              subtreeRoot->rightChild()->getValue(),
03486                              mulInstr, mvec,
03487                              MachineCodeForInstruction::get(mulInstr),
03488                              forceOp);
03489         break;
03490       }
03491       case 236: // reg:   Div(reg, Constant)
03492         maskUnsignedResult = true;
03493         L = mvec.size();
03494         CreateDivConstInstruction(target, subtreeRoot, mvec);
03495         if (mvec.size() > L)
03496           break;
03497         // ELSE FALL THROUGH
03498 
03499       case 36:  // reg:   Div(reg, reg)
03500       {
03501         maskUnsignedResult = true;
03502 
03503         // If either operand of divide is smaller than 64 bits, we have
03504         // to make sure the unused top bits are correct because they affect
03505         // the result.  These bits are already correct for unsigned values.
03506         // They may be incorrect for signed values, so sign extend to fill in.
03507         Instruction* divI = subtreeRoot->getInstruction();
03508         Value* divOp1 = subtreeRoot->leftChild()->getValue();
03509         Value* divOp2 = subtreeRoot->rightChild()->getValue();
03510         Value* divOp1ToUse = divOp1;
03511         Value* divOp2ToUse = divOp2;
03512         if (divI->getType()->isSigned()) {
03513           unsigned opSize=target.getTargetData().getTypeSize(divI->getType());
03514           if (opSize < 8) {
03515             MachineCodeForInstruction& mcfi=MachineCodeForInstruction::get(divI);
03516             divOp1ToUse = new TmpInstruction(mcfi, divOp1);
03517             divOp2ToUse = new TmpInstruction(mcfi, divOp2);
03518             CreateSignExtensionInstructions(target,
03519                                               divI->getParent()->getParent(),
03520                                               divOp1, divOp1ToUse,
03521                                               8*opSize, mvec, mcfi);
03522             CreateSignExtensionInstructions(target,
03523                                               divI->getParent()->getParent(),
03524                                               divOp2, divOp2ToUse,
03525                                               8*opSize, mvec, mcfi);
03526           }
03527         }
03528 
03529         mvec.push_back(BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
03530                        .addReg(divOp1ToUse)
03531                        .addReg(divOp2ToUse)
03532                        .addRegDef(divI));
03533 
03534         break;
03535       }
03536 
03537       case  37: // reg:   Rem(reg, reg)
03538       case 237: // reg:   Rem(reg, Constant)
03539       {
03540         maskUnsignedResult = true;
03541 
03542         Instruction* remI   = subtreeRoot->getInstruction();
03543         Value* divOp1 = subtreeRoot->leftChild()->getValue();
03544         Value* divOp2 = subtreeRoot->rightChild()->getValue();
03545 
03546         MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(remI);
03547 
03548         // If second operand of divide is smaller than 64 bits, we have
03549         // to make sure the unused top bits are correct because they affect
03550         // the result.  These bits are already correct for unsigned values.
03551         // They may be incorrect for signed values, so sign extend to fill in.
03552         //
03553         Value* divOpToUse = divOp2;
03554         if (divOp2->getType()->isSigned()) {
03555           unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
03556           if (opSize < 8) {
03557             divOpToUse = new TmpInstruction(mcfi, divOp2);
03558             CreateSignExtensionInstructions(target,
03559                                               remI->getParent()->getParent(),
03560                                               divOp2, divOpToUse,
03561                                               8*opSize, mvec, mcfi);
03562           }
03563         }
03564 
03565         // Now compute: result = rem V1, V2 as:
03566         //      result = V1 - (V1 / signExtend(V2)) * signExtend(V2)
03567         //
03568         TmpInstruction* quot = new TmpInstruction(mcfi, divOp1, divOpToUse);
03569         TmpInstruction* prod = new TmpInstruction(mcfi, quot, divOpToUse);
03570 
03571         mvec.push_back(BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
03572                        .addReg(divOp1).addReg(divOpToUse).addRegDef(quot));
03573 
03574         mvec.push_back(BuildMI(ChooseMulInstructionByType(remI->getType()), 3)
03575                        .addReg(quot).addReg(divOpToUse).addRegDef(prod));
03576 
03577         mvec.push_back(BuildMI(ChooseSubInstructionByType(remI->getType()), 3)
03578                        .addReg(divOp1).addReg(prod).addRegDef(remI));
03579 
03580         break;
03581       }
03582 
03583       case  38: // bool:   And(bool, bool)
03584       case 138: // bool:   And(bool, not)
03585       case 238: // bool:   And(bool, boolconst)
03586       case 338: // reg :   BAnd(reg, reg)
03587       case 538: // reg :   BAnd(reg, Constant)
03588         Add3OperandInstr(V9::ANDr, subtreeRoot, mvec);
03589         break;
03590 
03591       case 438: // bool:   BAnd(bool, bnot)
03592       { // Use the argument of NOT as the second argument!
03593         // Mark the NOT node so that no code is generated for it.
03594         // If the type is boolean, set 1 or 0 in the result register.
03595         InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
03596         Value* notArg = BinaryOperator::getNotArgument(
03597                            cast<BinaryOperator>(notNode->getInstruction()));
03598         notNode->markFoldedIntoParent();
03599         Value *lhs = subtreeRoot->leftChild()->getValue();
03600         Value *dest = subtreeRoot->getValue();
03601         mvec.push_back(BuildMI(V9::ANDNr, 3).addReg(lhs).addReg(notArg)
03602                                        .addReg(dest, MachineOperand::Def));
03603 
03604         if (notArg->getType() == Type::BoolTy) {
03605           // set 1 in result register if result of above is non-zero
03606           mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
03607                          .addReg(dest, MachineOperand::UseAndDef));
03608         }
03609 
03610         break;
03611       }
03612 
03613       case  39: // bool:   Or(bool, bool)
03614       case 139: // bool:   Or(bool, not)
03615       case 239: // bool:   Or(bool, boolconst)
03616       case 339: // reg :   BOr(reg, reg)
03617       case 539: // reg :   BOr(reg, Constant)
03618         Add3OperandInstr(V9::ORr, subtreeRoot, mvec);
03619         break;
03620 
03621       case 439: // bool:   BOr(bool, bnot)
03622       { // Use the argument of NOT as the second argument!
03623         // Mark the NOT node so that no code is generated for it.
03624         // If the type is boolean, set 1 or 0 in the result register.
03625         InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
03626         Value* notArg = BinaryOperator::getNotArgument(
03627                            cast<BinaryOperator>(notNode->getInstruction()));
03628         notNode->markFoldedIntoParent();
03629         Value *lhs = subtreeRoot->leftChild()->getValue();
03630         Value *dest = subtreeRoot->getValue();
03631 
03632         mvec.push_back(BuildMI(V9::ORNr, 3).addReg(lhs).addReg(notArg)
03633                        .addReg(dest, MachineOperand::Def));
03634 
03635         if (notArg->getType() == Type::BoolTy) {
03636           // set 1 in result register if result of above is non-zero
03637           mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
03638                          .addReg(dest, MachineOperand::UseAndDef));
03639         }
03640 
03641         break;
03642       }
03643 
03644       case  40: // bool:   Xor(bool, bool)
03645       case 140: // bool:   Xor(bool, not)
03646       case 240: // bool:   Xor(bool, boolconst)
03647       case 340: // reg :   BXor(reg, reg)
03648       case 540: // reg :   BXor(reg, Constant)
03649         Add3OperandInstr(V9::XORr, subtreeRoot, mvec);
03650         break;
03651 
03652       case 440: // bool:   BXor(bool, bnot)
03653       { // Use the argument of NOT as the second argument!
03654         // Mark the NOT node so that no code is generated for it.
03655         // If the type is boolean, set 1 or 0 in the result register.
03656         InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
03657         Value* notArg = BinaryOperator::getNotArgument(
03658                            cast<BinaryOperator>(notNode->getInstruction()));
03659         notNode->markFoldedIntoParent();
03660         Value *lhs = subtreeRoot->leftChild()->getValue();
03661         Value *dest = subtreeRoot->getValue();
03662         mvec.push_back(BuildMI(V9::XNORr, 3).addReg(lhs).addReg(notArg)
03663                        .addReg(dest, MachineOperand::Def));
03664 
03665         if (notArg->getType() == Type::BoolTy) {
03666           // set 1 in result register if result of above is non-zero
03667           mvec.push_back(BuildMI(V9::MOVRNZi, 3).addReg(dest).addZImm(1)
03668                          .addReg(dest, MachineOperand::UseAndDef));
03669         }
03670         break;
03671       }
03672 
03673       case 41:  // setCCconst:   SetCC(reg, Constant)
03674       { // Comparison is with a constant:
03675         //
03676         // If the bool result must be computed into a register (see below),
03677         // and the constant is int ZERO, we can use the MOVR[op] instructions
03678         // and avoid the SUBcc instruction entirely.
03679         // Otherwise this is just the same as case 42, so just fall through.
03680         //
03681         // The result of the SetCC must be computed and stored in a register if
03682         // it is used outside the current basic block (so it must be computed
03683         // as a boolreg) or it is used by anything other than a branch.
03684         // We will use a conditional move to do this.
03685         //
03686         Instruction* setCCInstr = subtreeRoot->getInstruction();
03687         bool computeBoolVal = (subtreeRoot->parent() == NULL ||
03688                                ! AllUsesAreBranches(setCCInstr));
03689 
03690         if (computeBoolVal) {
03691           InstrTreeNode* constNode = subtreeRoot->rightChild();
03692           assert(constNode &&
03693                  constNode->getNodeType() ==InstrTreeNode::NTConstNode);
03694           Constant *constVal = cast<Constant>(constNode->getValue());
03695           bool isValidConst;
03696 
03697           if ((constVal->getType()->isInteger()
03698                || isa<PointerType>(constVal->getType()))
03699               && ConvertConstantToIntType(target,
03700                              constVal, constVal->getType(), isValidConst) == 0
03701               && isValidConst)
03702           {
03703             // That constant is an integer zero after all...
03704             // Use a MOVR[op] to compute the boolean result
03705             // Unconditionally set register to 0
03706             mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
03707                            .addRegDef(setCCInstr));
03708 
03709             // Now conditionally move 1 into the register.
03710             // Mark the register as a use (as well as a def) because the old
03711             // value will be retained if the condition is false.
03712             MachineOpCode movOpCode = ChooseMovpregiForSetCC(subtreeRoot);
03713             mvec.push_back(BuildMI(movOpCode, 3)
03714                            .addReg(subtreeRoot->leftChild()->getValue())
03715                            .addZImm(1)
03716                            .addReg(setCCInstr, MachineOperand::UseAndDef));
03717 
03718             break;
03719           }
03720         }
03721         // ELSE FALL THROUGH
03722       }
03723 
03724       case 42:  // bool:   SetCC(reg, reg):
03725       {
03726         // This generates a SUBCC instruction, putting the difference in a
03727         // result reg. if needed, and/or setting a condition code if needed.
03728         //
03729         Instruction* setCCInstr = subtreeRoot->getInstruction();
03730         Value* leftVal  = subtreeRoot->leftChild()->getValue();
03731         Value* rightVal = subtreeRoot->rightChild()->getValue();
03732         const Type* opType = leftVal->getType();
03733         bool isFPCompare = opType->isFloatingPoint();
03734 
03735         // If the boolean result of the SetCC is used outside the current basic
03736         // block (so it must be computed as a boolreg) or is used by anything
03737         // other than a branch, the boolean must be computed and stored
03738         // in a result register.  We will use a conditional move to do this.
03739         //
03740         bool computeBoolVal = (subtreeRoot->parent() == NULL ||
03741                                ! AllUsesAreBranches(setCCInstr));
03742 
03743         // A TmpInstruction is created to represent the CC "result".
03744         // Unlike other instances of TmpInstruction, this one is used
03745         // by machine code of multiple LLVM instructions, viz.,
03746         // the SetCC and the branch.  Make sure to get the same one!
03747         // Note that we do this even for FP CC registers even though they
03748         // are explicit operands, because the type of the operand
03749         // needs to be a floating point condition code, not an integer
03750         // condition code.  Think of this as casting the bool result to
03751         // a FP condition code register.
03752         // Later, we mark the 4th operand as being a CC register, and as a def.
03753         //
03754         TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
03755                                     setCCInstr->getParent()->getParent(),
03756                                     leftVal->getType(),
03757                                     MachineCodeForInstruction::get(setCCInstr));
03758 
03759         // If the operands are signed values smaller than 4 bytes, then they
03760         // must be sign-extended in order to do a valid 32-bit comparison
03761         // and get the right result in the 32-bit CC register (%icc).
03762         //
03763         Value* leftOpToUse  = leftVal;
03764         Value* rightOpToUse = rightVal;
03765         if (opType->isIntegral() && opType->isSigned()) {
03766           unsigned opSize = target.getTargetData().getTypeSize(opType);
03767           if (opSize < 4) {
03768             MachineCodeForInstruction& mcfi =
03769               MachineCodeForInstruction::get(setCCInstr);
03770 
03771             // create temporary virtual regs. to hold the sign-extensions
03772             leftOpToUse  = new TmpInstruction(mcfi, leftVal);
03773             rightOpToUse = new TmpInstruction(mcfi, rightVal);
03774 
03775             // sign-extend each operand and put the result in the temporary reg.
03776             CreateSignExtensionInstructions
03777               (target, setCCInstr->getParent()->getParent(),
03778                leftVal, leftOpToUse, 8*opSize, mvec, mcfi);
03779             CreateSignExtensionInstructions
03780               (target, setCCInstr->getParent()->getParent(),
03781                rightVal, rightOpToUse, 8*opSize, mvec, mcfi);
03782           }
03783         }
03784 
03785         if (! isFPCompare) {
03786           // Integer condition: set CC and discard result.
03787           mvec.push_back(BuildMI(V9::SUBccr, 4)
03788                          .addReg(leftOpToUse)
03789                          .addReg(rightOpToUse)
03790                          .addMReg(target.getRegInfo()->
03791                                    getZeroRegNum(), MachineOperand::Def)
03792                          .addCCReg(tmpForCC, MachineOperand::Def));
03793         } else {
03794           // FP condition: dest of FCMP should be some FCCn register
03795           mvec.push_back(BuildMI(ChooseFcmpInstruction(subtreeRoot), 3)
03796                          .addCCReg(tmpForCC, MachineOperand::Def)
03797                          .addReg(leftOpToUse)
03798                          .addReg(rightOpToUse));
03799         }
03800 
03801         if (computeBoolVal) {
03802           MachineOpCode movOpCode = (isFPCompare
03803                                      ? ChooseMovFpcciInstruction(subtreeRoot)
03804                                      : ChooseMovpcciForSetCC(subtreeRoot));
03805 
03806           // Unconditionally set register to 0
03807           M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
03808           mvec.push_back(M);
03809 
03810           // Now conditionally move 1 into the register.
03811           // Mark the register as a use (as well as a def) because the old
03812           // value will be retained if the condition is false.
03813           M = (BuildMI(movOpCode, 3).addCCReg(tmpForCC).addZImm(1)
03814                .addReg(setCCInstr, MachineOperand::UseAndDef));
03815           mvec.push_back(M);
03816         }
03817         break;
03818       }
03819 
03820       case 51:  // reg:   Load(reg)
03821       case 52:  // reg:   Load(ptrreg)
03822         SetOperandsForMemInstr(ChooseLoadInstruction(
03823                                    subtreeRoot->getValue()->getType()),
03824                                mvec, subtreeRoot, target);
03825         break;
03826 
03827       case 55:  // reg:   GetElemPtr(reg)
03828       case 56:  // reg:   GetElemPtrIdx(reg,reg)
03829         // If the GetElemPtr was folded into the user (parent), it will be
03830         // caught above.  For other cases, we have to compute the address.
03831         SetOperandsForMemInstr(V9::ADDr, mvec, subtreeRoot, target);
03832         break;
03833 
03834       case 57:  // reg:  Alloca: Implement as 1 instruction:
03835       {         //          add %fp, offsetFromFP -> result
03836         AllocationInst* instr =
03837           cast<AllocationInst>(subtreeRoot->getInstruction());
03838         unsigned tsize =
03839           target.getTargetData().getTypeSize(instr->getAllocatedType());
03840         assert(tsize != 0);
03841         CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
03842         break;
03843       }
03844 
03845       case 58:  // reg:   Alloca(reg): Implement as 3 instructions:
03846                 //      mul num, typeSz -> tmp
03847                 //      sub %sp, tmp    -> %sp
03848       {         //      add %sp, frameSizeBelowDynamicArea -> result
03849         AllocationInst* instr =
03850           cast<AllocationInst>(subtreeRoot->getInstruction());
03851         const Type* eltType = instr->getAllocatedType();
03852 
03853         // If #elements is constant, use simpler code for fixed-size allocas
03854         int tsize = (int) target.getTargetData().getTypeSize(eltType);
03855         Value* numElementsVal = NULL;
03856         bool isArray = instr->isArrayAllocation();
03857 
03858         if (!isArray || isa<Constant>(numElementsVal = instr->getArraySize())) {
03859           // total size is constant: generate code for fixed-size alloca
03860           unsigned numElements = isArray?
03861             cast<ConstantUInt>(numElementsVal)->getValue() : 1;
03862           CreateCodeForFixedSizeAlloca(target, instr, tsize,
03863                                        numElements, mvec);
03864         } else {
03865           // total size is not constant.
03866           CreateCodeForVariableSizeAlloca(target, instr, tsize,
03867                                           numElementsVal, mvec);
03868         }
03869         break;
03870       }
03871 
03872       case 61:  // reg:   Call
03873       {         // Generate a direct (CALL) or indirect (JMPL) call.
03874                 // Mark the return-address register, the indirection
03875                 // register (for indirect calls), the operands of the Call,
03876                 // and the return value (if any) as implicit operands
03877                 // of the machine instruction.
03878                 //
03879                 // If this is a varargs function, floating point arguments
03880                 // have to passed in integer registers so insert
03881                 // copy-float-to-int instructions for each float operand.
03882                 //
03883         CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
03884         Value *callee = callInstr->getCalledValue();
03885         Function* calledFunc = dyn_cast<Function>(callee);
03886 
03887         // Check if this is an intrinsic function that needs a special code
03888         // sequence (e.g., va_start).  Indirect calls cannot be special.
03889         //
03890         bool specialIntrinsic = false;
03891         Intrinsic::ID iid;
03892         if (calledFunc && (iid=(Intrinsic::ID)calledFunc->getIntrinsicID()))
03893           specialIntrinsic = CodeGenIntrinsic(iid, *callInstr, target, mvec);
03894 
03895         // If not, generate the normal call sequence for the function.
03896         // This can also handle any intrinsics that are just function calls.
03897         //
03898         if (! specialIntrinsic) {
03899           Function* currentFunc = callInstr->getParent()->getParent();
03900           MachineFunction& MF = MachineFunction::get(currentFunc);
03901           MachineCodeForInstruction& mcfi =
03902             MachineCodeForInstruction::get(callInstr);
03903           const SparcV9RegInfo& regInfo =
03904             (SparcV9RegInfo&) *target.getRegInfo();
03905           const TargetFrameInfo& frameInfo = *target.getFrameInfo();
03906 
03907           // Create hidden virtual register for return address with type void*
03908           TmpInstruction* retAddrReg =
03909             new TmpInstruction(mcfi, PointerType::get(Type::VoidTy), callInstr);
03910 
03911           // Generate the machine instruction and its operands.
03912           // Use CALL for direct function calls; this optimistically assumes
03913           // the PC-relative address fits in the CALL address field (22 bits).
03914           // Use JMPL for indirect calls.
03915           // This will be added to mvec later, after operand copies.
03916           //
03917           MachineInstr* callMI;
03918           if (calledFunc)             // direct function call
03919             callMI = BuildMI(V9::CALL, 1).addPCDisp(callee);
03920           else                        // indirect function call
03921             callMI = (BuildMI(V9::JMPLCALLi,3).addReg(callee)
03922                       .addSImm((int64_t)0).addRegDef(retAddrReg));
03923 
03924           const FunctionType* funcType =
03925             cast<FunctionType>(cast<PointerType>(callee->getType())
03926                                ->getElementType());
03927           bool isVarArgs = funcType->isVarArg();
03928           bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
03929 
03930           // Use a descriptor to pass information about call arguments
03931           // to the register allocator.  This descriptor will be "owned"
03932           // and freed automatically when the MachineCodeForInstruction
03933           // object for the callInstr goes away.
03934           CallArgsDescriptor* argDesc =
03935             new CallArgsDescriptor(callInstr, retAddrReg,isVarArgs,noPrototype);
03936           assert(callInstr->getOperand(0) == callee
03937                  && "This is assumed in the loop below!");
03938 
03939           // Insert sign-extension instructions for small signed values,
03940           // if this is an unknown function (i.e., called via a funcptr)
03941           // or an external one (i.e., which may not be compiled by llc).
03942           //
03943           if (calledFunc == NULL || calledFunc->isExternal()) {
03944             for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
03945               Value* argVal = callInstr->getOperand(i);
03946               const Type* argType = argVal->getType();
03947               if (argType->isIntegral() && argType->isSigned()) {
03948                 unsigned argSize = target.getTargetData().getTypeSize(argType);
03949                 if (argSize <= 4) {
03950                   // create a temporary virtual reg. to hold the sign-extension
03951                   TmpInstruction* argExtend = new TmpInstruction(mcfi, argVal);
03952 
03953                   // sign-extend argVal and put the result in the temporary reg.
03954                   CreateSignExtensionInstructions
03955                     (target, currentFunc, argVal, argExtend,
03956                      8*argSize, mvec, mcfi);
03957 
03958                   // replace argVal with argExtend in CallArgsDescriptor
03959                   argDesc->getArgInfo(i-1).replaceArgVal(argExtend);
03960                 }
03961               }
03962             }
03963           }
03964 
03965           // Insert copy instructions to get all the arguments into
03966           // all the places that they need to be.
03967           //
03968           for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
03969             int argNo = i-1;
03970             CallArgInfo& argInfo = argDesc->getArgInfo(argNo);
03971             Value* argVal = argInfo.getArgVal(); // don't use callInstr arg here
03972             const Type* argType = argVal->getType();
03973             unsigned regType = regInfo.getRegTypeForDataType(argType);
03974             unsigned argSize = target.getTargetData().getTypeSize(argType);
03975             int regNumForArg = SparcV9RegInfo::getInvalidRegNum();
03976             unsigned regClassIDOfArgReg;
03977 
03978             // Check for FP arguments to varargs functions.
03979             // Any such argument in the first $K$ args must be passed in an
03980             // integer register.  If there is no prototype, it must also
03981             // be passed as an FP register.
03982             // K = #integer argument registers.
03983             bool isFPArg = argVal->getType()->isFloatingPoint();
03984             if (isVarArgs && isFPArg) {
03985 
03986               if (noPrototype) {
03987                 // It is a function with no prototype: pass value
03988                 // as an FP value as well as a varargs value.  The FP value
03989                 // may go in a register or on the stack.  The copy instruction
03990                 // to the outgoing reg/stack is created by the normal argument
03991                 // handling code since this is the "normal" passing mode.
03992                 //
03993                 regNumForArg = regInfo.regNumForFPArg(regType,
03994                                                       false, false, argNo,
03995                                                       regClassIDOfArgReg);
03996                 if (regNumForArg == regInfo.getInvalidRegNum())
03997                   argInfo.setUseStackSlot();
03998                 else
03999                   argInfo.setUseFPArgReg();
04000               }
04001 
04002               // If this arg. is in the first $K$ regs, add special copy-
04003               // float-to-int instructions to pass the value as an int.
04004               // To check if it is in the first $K$, get the register
04005               // number for the arg #i.  These copy instructions are
04006               // generated here because they are extra cases and not needed
04007               // for the normal argument handling (some code reuse is
04008               // possible though -- later).
04009               //
04010               int copyRegNum = regInfo.regNumForIntArg(false, false, argNo,
04011                                                        regClassIDOfArgReg);
04012               if (copyRegNum != regInfo.getInvalidRegNum()) {
04013                 // Create a virtual register to represent copyReg. Mark
04014                 // this vreg as being an implicit operand of the call MI
04015                 const Type* loadTy = (argType == Type::FloatTy
04016                                       ? Type::IntTy : Type::LongTy);
04017                 TmpInstruction* argVReg = new TmpInstruction(mcfi, loadTy,
04018                                                              argVal, NULL,
04019                                                              "argRegCopy");
04020                 callMI->addImplicitRef(argVReg);
04021 
04022                 // Get a temp stack location to use to copy
04023                 // float-to-int via the stack.
04024                 //
04025                 // FIXME: For now, we allocate permanent space because
04026                 // the stack frame manager does not allow locals to be
04027                 // allocated (e.g., for alloca) after a temp is
04028                 // allocated!
04029                 //
04030                 // int tmpOffset = MF.getInfo<SparcV9FunctionInfo>()->pushTempValue(argSize);
04031                 int tmpOffset = MF.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(argVReg);
04032 
04033                 // Generate the store from FP reg to stack
04034                 unsigned StoreOpcode = ChooseStoreInstruction(argType);
04035                 M = BuildMI(convertOpcodeFromRegToImm(StoreOpcode), 3)
04036                   .addReg(argVal).addMReg(regInfo.getFramePointer())
04037                   .addSImm(tmpOffset);
04038                 mvec.push_back(M);
04039 
04040                 // Generate the load from stack to int arg reg
04041                 unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
04042                 M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
04043                   .addMReg(regInfo.getFramePointer()).addSImm(tmpOffset)
04044                   .addReg(argVReg, MachineOperand::Def);
04045 
04046                 // Mark operand with register it should be assigned
04047                 // both for copy and for the callMI
04048                 M->SetRegForOperand(M->getNumOperands()-1, copyRegNum);
04049                 callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,
04050                                              copyRegNum);
04051                 mvec.push_back(M);
04052 
04053                 // Add info about the argument to the CallArgsDescriptor
04054                 argInfo.setUseIntArgReg();
04055                 argInfo.setArgCopy(copyRegNum);
04056               } else {
04057                 // Cannot fit in first $K$ regs so pass arg on stack
04058                 argInfo.setUseStackSlot();
04059               }
04060             } else if (isFPArg) {
04061               // Get the outgoing arg reg to see if there is one.
04062               regNumForArg = regInfo.regNumForFPArg(regType, false, false,
04063                                                     argNo, regClassIDOfArgReg);
04064               if (regNumForArg == regInfo.getInvalidRegNum())
04065                 argInfo.setUseStackSlot();
04066               else {
04067                 argInfo.setUseFPArgReg();
04068                 regNumForArg =regInfo.getUnifiedRegNum(regClassIDOfArgReg,
04069                                                        regNumForArg);
04070               }
04071             } else {
04072               // Get the outgoing arg reg to see if there is one.
04073               regNumForArg = regInfo.regNumForIntArg(false,false,
04074                                                      argNo, regClassIDOfArgReg);
04075               if (regNumForArg == regInfo.getInvalidRegNum())
04076                 argInfo.setUseStackSlot();
04077               else {
04078                 argInfo.setUseIntArgReg();
04079                 regNumForArg =regInfo.getUnifiedRegNum(regClassIDOfArgReg,
04080                                                        regNumForArg);
04081               }
04082             }
04083 
04084             //
04085             // Now insert copy instructions to stack slot or arg. register
04086             //
04087             if (argInfo.usesStackSlot()) {
04088               // Get the stack offset for this argument slot.
04089               // FP args on stack are right justified so adjust offset!
04090               // int arguments are also right justified but they are
04091               // always loaded as a full double-word so the offset does
04092               // not need to be adjusted.
04093               int argOffset = frameInfo.getOutgoingArgOffset(MF, argNo);
04094               if (argType->isFloatingPoint()) {
04095                 unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
04096                 assert(argSize <= slotSize && "Insufficient slot size!");
04097                 argOffset += slotSize - argSize;
04098               }
04099 
04100               // Now generate instruction to copy argument to stack
04101               MachineOpCode storeOpCode =
04102                 (argType->isFloatingPoint()
04103                  ? ((argSize == 4)? V9::STFi : V9::STDFi) : V9::STXi);
04104 
04105               M = BuildMI(storeOpCode, 3).addReg(argVal)
04106                 .addMReg(regInfo.getStackPointer()).addSImm(argOffset);
04107               mvec.push_back(M);
04108             }
04109             else if (regNumForArg != regInfo.getInvalidRegNum()) {
04110 
04111               // Create a virtual register to represent the arg reg. Mark
04112               // this vreg as being an implicit operand of the call MI.
04113               TmpInstruction* argVReg =
04114                 new TmpInstruction(mcfi, argVal, NULL, "argReg");
04115 
04116               callMI->addImplicitRef(argVReg);
04117 
04118               // Generate the reg-to-reg copy into the outgoing arg reg.
04119               // -- For FP values, create a FMOVS or FMOVD instruction
04120               // -- For non-FP values, create an add-with-0 instruction
04121               if (argType->isFloatingPoint())
04122                 M=(BuildMI(argType==Type::FloatTy? V9::FMOVS :V9::FMOVD,2)
04123                    .addReg(argVal).addReg(argVReg, MachineOperand::Def));
04124               else
04125                 M = (BuildMI(ChooseAddInstructionByType(argType), 3)
04126                      .addReg(argVal).addSImm((int64_t) 0)
04127                      .addReg(argVReg, MachineOperand::Def));
04128 
04129               // Mark the operand with the register it should be assigned
04130               M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
04131               callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,
04132                                            regNumForArg);
04133 
04134               mvec.push_back(M);
04135             }
04136             else
04137               assert(argInfo.getArgCopy() != regInfo.getInvalidRegNum() &&
04138                      "Arg. not in stack slot, primary or secondary register?");
04139           }
04140 
04141           // add call instruction and delay slot before copying return value
04142           mvec.push_back(callMI);
04143           mvec.push_back(BuildMI(V9::NOP, 0));
04144 
04145           // Add the return value as an implicit ref.  The call operands
04146           // were added above.  Also, add code to copy out the return value.
04147           // This is always register-to-register for int or FP return values.
04148           //
04149           if (callInstr->getType() != Type::VoidTy) {
04150             // Get the return value reg.
04151             const Type* retType = callInstr->getType();
04152 
04153             int regNum = (retType->isFloatingPoint()
04154                           ? (unsigned) SparcV9FloatRegClass::f0
04155                           : (unsigned) SparcV9IntRegClass::o0);
04156             unsigned regClassID = regInfo.getRegClassIDOfType(retType);
04157             regNum = regInfo.getUnifiedRegNum(regClassID, regNum);
04158 
04159             // Create a virtual register to represent it and mark
04160             // this vreg as being an implicit operand of the call MI
04161             TmpInstruction* retVReg =
04162               new TmpInstruction(mcfi, callInstr, NULL, "argReg");
04163 
04164             callMI->addImplicitRef(retVReg, /*isDef*/ true);
04165 
04166             // Generate the reg-to-reg copy from the return value reg.
04167             // -- For FP values, create a FMOVS or FMOVD instruction
04168             // -- For non-FP values, create an add-with-0 instruction
04169             if (retType->isFloatingPoint())
04170               M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
04171                    .addReg(retVReg).addReg(callInstr, MachineOperand::Def));
04172             else
04173               M = (BuildMI(ChooseAddInstructionByType(retType), 3)
04174                    .addReg(retVReg).addSImm((int64_t) 0)
04175                    .addReg(callInstr, MachineOperand::Def));
04176 
04177             // Mark the operand with the register it should be assigned
04178             // Also mark the implicit ref of the call defining this operand
04179             M->SetRegForOperand(0, regNum);
04180             callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,regNum);
04181 
04182             mvec.push_back(M);
04183           }
04184 
04185           // For the CALL instruction, the ret. addr. reg. is also implicit
04186           if (isa<Function>(callee))
04187             callMI->addImplicitRef(retAddrReg, /*isDef*/ true);
04188 
04189           MF.getInfo<SparcV9FunctionInfo>()->popAllTempValues();  // free temps used for this inst
04190         }
04191 
04192         break;
04193       }
04194 
04195       case 62:  // reg:   Shl(reg, reg)
04196       {
04197         Value* argVal1 = subtreeRoot->leftChild()->getValue();
04198         Value* argVal2 = subtreeRoot->rightChild()->getValue();
04199         Instruction* shlInstr = subtreeRoot->getInstruction();
04200 
04201         const Type* opType = argVal1->getType();
04202         assert((opType->isInteger() || isa<PointerType>(opType)) &&
04203                "Shl unsupported for other types");
04204         unsigned opSize = target.getTargetData().getTypeSize(opType);
04205 
04206         CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
04207                                 (opSize > 4)? V9::SLLXr6:V9::SLLr5,
04208                                 argVal1, argVal2, 0, shlInstr, mvec,
04209                                 MachineCodeForInstruction::get(shlInstr));
04210         break;
04211       }
04212 
04213       case 63:  // reg:   Shr(reg, reg)
04214       {
04215         const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
04216         assert((opType->isInteger() || isa<PointerType>(opType)) &&
04217                "Shr unsupported for other types");
04218         unsigned opSize = target.getTargetData().getTypeSize(opType);
04219         Add3OperandInstr(opType->isSigned()
04220                          ? (opSize > 4? V9::SRAXr6 : V9::SRAr5)
04221                          : (opSize > 4? V9::SRLXr6 : V9::SRLr5),
04222                          subtreeRoot, mvec);
04223         break;
04224       }
04225 
04226       case 64:  // reg:   Phi(reg,reg)
04227         break;                          // don't forward the value
04228 
04229       case 66:  // reg:   VAArg (reg): the va_arg instruction
04230       { // Load argument from stack using current va_list pointer value.
04231         // Use 64-bit load for all non-FP args, and LDDF or double for FP.
04232         Instruction* vaArgI = subtreeRoot->getInstruction();
04233         //but first load the va_list pointer
04234         // Create a virtual register to represent it
04235         //What oh what do we pass to TmpInstruction?
04236         MachineCodeForInstruction& m1 = MachineCodeForInstruction::get(vaArgI);
04237         TmpInstruction* VReg = new TmpInstruction(m1, vaArgI->getOperand(0)->getType());
04238         mvec.push_back(BuildMI(V9::LDXi, 3).addReg(vaArgI->getOperand(0))
04239                        .addSImm(0).addRegDef(VReg));
04240         //OK, now do the load
04241         MachineOpCode loadOp = (vaArgI->getType()->isFloatingPoint()
04242                                 ? (vaArgI->getType() == Type::FloatTy
04243                                    ? V9::LDFi : V9::LDDFi)
04244                                 : V9::LDXi);
04245         mvec.push_back(BuildMI(loadOp, 3).addReg(VReg).
04246                        addSImm(0).addRegDef(vaArgI));
04247         //Also increment the pointer
04248         MachineCodeForInstruction& m2 = MachineCodeForInstruction::get(vaArgI);
04249         TmpInstruction* VRegA = new TmpInstruction(m2, vaArgI->getOperand(0)->getType());
04250         unsigned argSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
04251         mvec.push_back(BuildMI(V9::ADDi, 3).addReg(VReg).
04252                        addSImm(argSize).addRegDef(VRegA));
04253         //And store
04254         mvec.push_back(BuildMI(V9::STXr, 3).addReg(VRegA).
04255                        addReg(vaArgI->getOperand(0)).addSImm(0));
04256         break;
04257       }
04258 
04259       case 71:  // reg:     VReg
04260       case 72:  // reg:     Constant
04261         break;                          // don't forward the value
04262 
04263       default:
04264         assert(0 && "Unrecognized BURG rule");
04265         break;
04266       }
04267     }
04268 
04269   if (forwardOperandNum >= 0) {
04270     // We did not generate a machine instruction but need to use operand.
04271     // If user is in the same tree, replace Value in its machine operand.
04272     // If not, insert a copy instruction which should get coalesced away
04273     // by register allocation.
04274     if (subtreeRoot->parent() != NULL)
04275       ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
04276     else {
04277       std::vector<MachineInstr*> minstrVec;
04278       Instruction* instr = subtreeRoot->getInstruction();
04279       CreateCopyInstructionsByType(target,
04280                                      instr->getParent()->getParent(),
04281                                      instr->getOperand(forwardOperandNum),
04282                                      instr, minstrVec,
04283                                      MachineCodeForInstruction::get(instr));
04284       assert(minstrVec.size() > 0);
04285       mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
04286     }
04287   }
04288 
04289   if (maskUnsignedResult) {
04290     // If result is unsigned and smaller than int reg size,
04291     // we need to clear high bits of result value.
04292     assert(forwardOperandNum < 0 && "Need mask but no instruction generated");
04293     Instruction* dest = subtreeRoot->getInstruction();
04294     if (dest->getType()->isUnsigned()) {
04295       unsigned destSize=target.getTargetData().getTypeSize(dest->getType());
04296       if (destSize <= 4) {
04297         // Mask high 64 - N bits, where N = 4*destSize.
04298 
04299         // Use a TmpInstruction to represent the
04300         // intermediate result before masking.  Since those instructions
04301         // have already been generated, go back and substitute tmpI
04302         // for dest in the result position of each one of them.
04303         //
04304         MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(dest);
04305         TmpInstruction *tmpI = new TmpInstruction(mcfi, dest->getType(),
04306                                                   dest, NULL, "maskHi");
04307         Value* srlArgToUse = tmpI;
04308 
04309         unsigned numSubst = 0;
04310         for (unsigned i=0, N=mvec.size(); i < N; ++i) {
04311 
04312           // Make sure we substitute all occurrences of dest in these instrs.
04313           // Otherwise, we will have bogus code.
04314           bool someArgsWereIgnored = false;
04315 
04316           // Make sure not to substitute an upwards-exposed use -- that would
04317           // introduce a use of `tmpI' with no preceding def.  Therefore,
04318           // substitute a use or def-and-use operand only if a previous def
04319           // operand has already been substituted (i.e., numSubst > 0).
04320           //
04321           numSubst += mvec[i]->substituteValue(dest, tmpI,
04322                                                /*defsOnly*/ numSubst == 0,
04323                                                /*notDefsAndUses*/ numSubst > 0,
04324                                                someArgsWereIgnored);
04325           assert(!someArgsWereIgnored &&
04326                  "Operand `dest' exists but not replaced: probably bogus!");
04327         }
04328         assert(numSubst > 0 && "Operand `dest' not replaced: probably bogus!");
04329 
04330         // Left shift 32-N if size (N) is less than 32 bits.
04331         // Use another tmp. virtual register to represent this result.
04332         if (destSize < 4) {
04333           srlArgToUse = new TmpInstruction(mcfi, dest->getType(),
04334                                            tmpI, NULL, "maskHi2");
04335           mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpI)
04336                          .addZImm(8*(4-destSize))
04337                          .addReg(srlArgToUse, MachineOperand::Def));
04338         }
04339 
04340         // Logical right shift 32-N to get zero extension in top 64-N bits.
04341         mvec.push_back(BuildMI(V9::SRLi5, 3).addReg(srlArgToUse)
04342                          .addZImm(8*(4-destSize))
04343                          .addReg(dest, MachineOperand::Def));
04344 
04345       } else if (destSize < 8) {
04346         assert(0 && "Unsupported type size: 32 < size < 64 bits");
04347       }
04348     }
04349   }
04350 }
04351 
04352 } // End llvm namespace
04353 
04354 //==------------------------------------------------------------------------==//
04355 //                     Class V9ISel Implementation
04356 //==------------------------------------------------------------------------==//
04357 
04358 bool V9ISel::runOnFunction(Function &F) {
04359   DefaultIntrinsicLowering IL;
04360   // First pass - Walk the function, lowering any calls to intrinsic functions
04361   // which the instruction selector cannot handle.
04362   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
04363     for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
04364       if (CallInst *CI = dyn_cast<CallInst>(I++))
04365         if (Function *F = CI->getCalledFunction())
04366           switch (F->getIntrinsicID()) {
04367           case Intrinsic::not_intrinsic:
04368           case Intrinsic::vastart:
04369           case Intrinsic::vacopy:
04370           case Intrinsic::vaend:
04371             // We directly implement these intrinsics.  Note that this knowledge
04372             // is incestuously entangled with the code in
04373             // SparcInstrSelection.cpp and must be updated when it is updated.
04374             // Since ALL of the code in this library is incestuously intertwined
04375             // with it already and sparc specific, we will live with this.
04376             break;
04377           default:
04378             // All other intrinsic calls we must lower.
04379             Instruction *Before = CI->getPrev();
04380             IL.LowerIntrinsicCall(CI);
04381             if (Before) {        // Move iterator to instruction after call
04382               I = Before;  ++I;
04383             } else {
04384               I = BB->begin();
04385             }
04386           }
04387 
04388   // Build the instruction trees to be given as inputs to BURG.
04389   InstrForest instrForest(&F);
04390   if (SelectDebugLevel >= Select_DebugInstTrees) {
04391     std::cerr << "\n\n*** Input to instruction selection for function "
04392               << F.getName() << "\n\n" << F
04393               << "\n\n*** Instruction trees for function "
04394               << F.getName() << "\n\n";
04395     instrForest.dump();
04396   }
04397 
04398   // Invoke BURG instruction selection for each tree
04399   for (InstrForest::const_root_iterator RI = instrForest.roots_begin();
04400        RI != instrForest.roots_end(); ++RI) {
04401     InstructionNode* basicNode = *RI;
04402     assert(basicNode->parent() == NULL && "A `root' node has a parent?");
04403 
04404     // Invoke BURM to label each tree node with a state
04405     burm_label(basicNode);
04406     if (SelectDebugLevel >= Select_DebugBurgTrees) {
04407       printcover(basicNode, 1, 0);
04408       std::cerr << "\nCover cost == " << treecost(basicNode, 1, 0) <<"\n\n";
04409       printMatches(basicNode);
04410     }
04411 
04412     // Then recursively walk the tree to select instructions
04413     SelectInstructionsForTree(basicNode, /*goalnt*/1);
04414   }
04415 
04416   // Create the MachineBasicBlocks and add all of the MachineInstrs
04417   // defined in the MachineCodeForInstruction objects to the MachineBasicBlocks.
04418   MachineFunction &MF = MachineFunction::get(&F);
04419   std::map<const BasicBlock *, MachineBasicBlock *> MBBMap;
04420   for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) {
04421     MachineBasicBlock *MBB = new MachineBasicBlock(BI);
04422     MF.getBasicBlockList().push_back(MBB);
04423     MBBMap[BI] = MBB;
04424 
04425     for (BasicBlock::iterator II = BI->begin(); II != BI->end(); ++II) {
04426       MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(II);
04427       MBB->insert(MBB->end(), mvec.begin(), mvec.end());
04428     }
04429   }
04430 
04431   // Initialize Machine-CFG for the function.
04432   for (MachineFunction::iterator i = MF.begin (), e = MF.end (); i != e; ++i) {
04433     MachineBasicBlock &MBB = *i;
04434     const BasicBlock *BB = MBB.getBasicBlock ();
04435     // for each successor S of BB, add MBBMap[S] as a successor of MBB.
04436     for (succ_const_iterator si = succ_begin(BB), se = succ_end(BB); si != se;
04437          ++si) {
04438       MachineBasicBlock *succMBB = MBBMap[*si];
04439       assert (succMBB && "Can't find MachineBasicBlock for this successor");
04440       MBB.addSuccessor (succMBB);
04441     }
04442   }
04443 
04444   // Insert phi elimination code
04445   InsertCodeForPhis(F);
04446 
04447   if (SelectDebugLevel >= Select_PrintMachineCode) {
04448     std::cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
04449     MachineFunction::get(&F).dump();
04450   }
04451 
04452   return true;
04453 }
04454 
04455 /// InsertCodeForPhis - This method inserts Phi elimination code for
04456 /// all Phi nodes in the given function.  After this method is called,
04457 /// the Phi nodes still exist in the LLVM code, but copies are added to the
04458 /// machine code.
04459 ///
04460 void V9ISel::InsertCodeForPhis(Function &F) {
04461   // Iterate over every Phi node PN in F:
04462   MachineFunction &MF = MachineFunction::get(&F);
04463   for (MachineFunction::iterator BB = MF.begin(); BB != MF.end(); ++BB) {
04464     for (BasicBlock::const_iterator IIt = BB->getBasicBlock()->begin();
04465          const PHINode *PN = dyn_cast<PHINode>(IIt); ++IIt) {
04466       // Create a new temporary register to hold the result of the Phi copy.
04467       // The leak detector shouldn't track these nodes.  They are not garbage,
04468       // even though their parent field is never filled in.
04469       Value *PhiCpRes = new PHINode(PN->getType(), PN->getName() + ":PhiCp");
04470       LeakDetector::removeGarbageObject(PhiCpRes);
04471 
04472       // For each of PN's incoming values, insert a copy in the corresponding
04473       // predecessor block.
04474       MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get (PN);
04475       for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) {
04476         std::vector<MachineInstr*> mvec, CpVec;
04477         Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
04478                                            PhiCpRes, mvec);
04479         for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
04480              MI != mvec.end(); ++MI) {
04481           std::vector<MachineInstr*> CpVec2 =
04482             FixConstantOperandsForInstr(const_cast<PHINode*>(PN), *MI, Target);
04483           CpVec2.push_back(*MI);
04484           CpVec.insert(CpVec.end(), CpVec2.begin(), CpVec2.end());
04485         }
04486         // Insert the copy instructions into the predecessor BB.
04487         InsertPhiElimInstructions(PN->getIncomingBlock(i), CpVec);
04488         MCforPN.insert (MCforPN.end (), CpVec.begin (), CpVec.end ());
04489       }
04490       // Insert a copy instruction from PhiCpRes to PN.
04491       std::vector<MachineInstr*> mvec;
04492       Target.getRegInfo()->cpValue2Value(PhiCpRes, const_cast<PHINode*>(PN),
04493                                         mvec);
04494       BB->insert(BB->begin(), mvec.begin(), mvec.end());
04495       MCforPN.insert (MCforPN.end (), mvec.begin (), mvec.end ());
04496     }  // for each Phi Instr in BB
04497   } // for all BBs in function
04498 }
04499 
04500 /// InsertPhiElimInstructions - Inserts the instructions in CpVec into the
04501 /// MachineBasicBlock corresponding to BB, just before its terminator
04502 /// instruction. This is used by InsertCodeForPhis() to insert copies, above.
04503 ///
04504 void V9ISel::InsertPhiElimInstructions(BasicBlock *BB,
04505                                        const std::vector<MachineInstr*>& CpVec)
04506 {
04507   Instruction *TermInst = (Instruction*)BB->getTerminator();
04508   MachineCodeForInstruction &MC4Term = MachineCodeForInstruction::get(TermInst);
04509   MachineInstr *FirstMIOfTerm = MC4Term.front();
04510   assert (FirstMIOfTerm && "No Machine Instrs for terminator");
04511 
04512   MachineBasicBlock *MBB = FirstMIOfTerm->getParent();
04513   assert(MBB && "Machine BB for predecessor's terminator not found");
04514   MachineBasicBlock::iterator MCIt = FirstMIOfTerm;
04515   assert(MCIt != MBB->end() && "Start inst of terminator not found");
04516 
04517   // Insert the copy instructions just before the first machine instruction
04518   // generated for the terminator.
04519   MBB->insert(MCIt, CpVec.begin(), CpVec.end());
04520 }
04521 
04522 /// SelectInstructionsForTree - Recursively walk the tree to select
04523 /// instructions. Do this top-down so that child instructions can exploit
04524 /// decisions made at the child instructions.
04525 ///
04526 /// E.g., if br(setle(reg,const)) decides the constant is 0 and uses
04527 /// a branch-on-integer-register instruction, then the setle node
04528 /// can use that information to avoid generating the SUBcc instruction.
04529 ///
04530 /// Note that this cannot be done bottom-up because setle must do this
04531 /// only if it is a child of the branch (otherwise, the result of setle
04532 /// may be used by multiple instructions).
04533 ///
04534 void V9ISel::SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt) {
04535   // Get the rule that matches this node.
04536   int ruleForNode = burm_rule(treeRoot->state, goalnt);
04537 
04538   if (ruleForNode == 0) {
04539     std::cerr << "Could not match instruction tree for instr selection\n";
04540     abort();
04541   }
04542 
04543   // Get this rule's non-terminals and the corresponding child nodes (if any)
04544   short *nts = burm_nts[ruleForNode];
04545 
04546   // First, select instructions for the current node and rule.
04547   // (If this is a list node, not an instruction, then skip this step).
04548   // This function is specific to the target architecture.
04549   if (treeRoot->opLabel != VRegListOp) {
04550     std::vector<MachineInstr*> minstrVec;
04551     InstructionNode* instrNode = (InstructionNode*)treeRoot;
04552     assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
04553     GetInstructionsByRule(instrNode, ruleForNode, nts, Target, minstrVec);
04554     MachineCodeForInstruction &mvec =
04555       MachineCodeForInstruction::get(instrNode->getInstruction());
04556     mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
04557   }
04558 
04559   // Then, recursively compile the child nodes, if any.
04560   //
04561   if (nts[0]) {
04562     // i.e., there is at least one kid
04563     InstrTreeNode* kids[2];
04564     int currentRule = ruleForNode;
04565     burm_kids(treeRoot, currentRule, kids);
04566 
04567     // First skip over any chain rules so that we don't visit
04568     // the current node again.
04569     while (ThisIsAChainRule(currentRule)) {
04570       currentRule = burm_rule(treeRoot->state, nts[0]);
04571       nts = burm_nts[currentRule];
04572       burm_kids(treeRoot, currentRule, kids);
04573     }
04574 
04575     // Now we have the first non-chain rule so we have found
04576     // the actual child nodes.  Recursively compile them.
04577     for (unsigned i = 0; nts[i]; i++) {
04578       assert(i < 2);
04579       InstrTreeNode::InstrTreeNodeType nodeType = kids[i]->getNodeType();
04580       if (nodeType == InstrTreeNode::NTVRegListNode ||
04581           nodeType == InstrTreeNode::NTInstructionNode)
04582         SelectInstructionsForTree(kids[i], nts[i]);
04583     }
04584   }
04585 
04586   // Finally, do any post-processing on this node after its children
04587   // have been translated.
04588   if (treeRoot->opLabel != VRegListOp)
04589     PostprocessMachineCodeForTree((InstructionNode*)treeRoot, ruleForNode, nts);
04590 }
04591 
04592 /// PostprocessMachineCodeForTree - Apply any final cleanups to
04593 /// machine code for the root of a subtree after selection for all its
04594 /// children has been completed.
04595 ///
04596 void V9ISel::PostprocessMachineCodeForTree(InstructionNode *instrNode,
04597                                            int ruleForNode, short *nts) {
04598   // Fix up any constant operands in the machine instructions to either
04599   // use an immediate field or to load the constant into a register.
04600   // Walk backwards and use direct indexes to allow insertion before current.
04601   Instruction* vmInstr = instrNode->getInstruction();
04602   MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(vmInstr);
04603   for (unsigned i = mvec.size(); i != 0; --i) {
04604     std::vector<MachineInstr*> loadConstVec =
04605       FixConstantOperandsForInstr(vmInstr, mvec[i-1], Target);
04606     mvec.insert(mvec.begin()+i-1, loadConstVec.begin(), loadConstVec.end());
04607   }
04608 }
04609 
04610 /// createSparcV9BurgInstSelector - Creates and returns a new SparcV9
04611 /// BURG-based instruction selection pass.
04612 ///
04613 FunctionPass *llvm::createSparcV9BurgInstSelector(TargetMachine &TM) {
04614   return new V9ISel(TM);
04615 }