LLVM API Documentation

llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

commuteInstruction(MachineInstr *MI) const llvm::PPCInstrInfo [virtual]
constantFitsInImmedField(MachineOpCode Opcode, int64_t intValue) const llvm::TargetInstrInfo [virtual]
convertToThreeAddress(MachineInstr *TA) const llvm::TargetInstrInfo [inline, virtual]
get(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
getImmedConstantPos(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline, virtual]
getImplicitDefs(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
getImplicitUses(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
getName(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
getNumDelaySlots(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
getNumOpcodes() const llvm::TargetInstrInfo [inline]
getNumOperands(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
getRegisterInfo() const llvm::PPCInstrInfo [inline, virtual]
getSchedClass(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
hasDelaySlot(unsigned Opcode) const llvm::TargetInstrInfo [inline]
hasResultInterlock(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline, virtual]
INLINEASM enum valuellvm::TargetInstrInfo
insertGoto(MachineBasicBlock &MBB, MachineBasicBlock &TMBB) const llvm::TargetInstrInfo [inline, virtual]
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const llvm::PPCInstrInfo [virtual]
invertPPCBranchOpcode(unsigned Opcode)llvm::PPCInstrInfo [inline, static]
isBarrier(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isBranch(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isCall(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isCCInstr(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isLoad(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const llvm::PPCInstrInfo [virtual]
isMoveInstr(const MachineInstr &MI, unsigned &sourceReg, unsigned &destReg) const llvm::PPCInstrInfo [virtual]
isNop(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isReturn(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isStore(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const llvm::PPCInstrInfo [virtual]
isTerminatorInstr(unsigned Opcode) const llvm::TargetInstrInfo [inline]
isTwoAddrInstr(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline]
maxImmedConstant(MachineOpCode Opcode, bool &isSignExtended) const llvm::TargetInstrInfo [inline, virtual]
maxLatency(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline, virtual]
minLatency(MachineOpCode Opcode) const llvm::TargetInstrInfo [inline, virtual]
PHI enum valuellvm::TargetInstrInfo
PPCInstrInfo()llvm::PPCInstrInfo
reverseBranchCondition(MachineBasicBlock::iterator MI) const llvm::TargetInstrInfo [inline, virtual]
TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes)llvm::TargetInstrInfo
usesCustomDAGSchedInsertionHook(unsigned Opcode) const llvm::TargetInstrInfo [inline]
~TargetInstrInfo()llvm::TargetInstrInfo [virtual]