LLVM API Documentation
#include <PPCISelLowering.h>
Inheritance diagram for llvm::PPCTargetLowering:
Public Member Functions | |
PPCTargetLowering (TargetMachine &TM) | |
virtual const char * | getTargetNodeName (unsigned Opcode) const |
virtual SDOperand | LowerOperation (SDOperand Op, SelectionDAG &DAG) |
virtual SDOperand | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const |
virtual void | computeMaskedBitsForTargetNode (const SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const |
virtual std::vector< SDOperand > | LowerArguments (Function &F, SelectionDAG &DAG) |
virtual std::pair< SDOperand, SDOperand > | LowerCallTo (SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) |
virtual MachineBasicBlock * | InsertAtEndOfBasicBlock (MachineInstr *MI, MachineBasicBlock *MBB) |
ConstraintType | getConstraintType (char ConstraintLetter) const |
std::vector< unsigned > | getRegClassForInlineAsmConstraint (const std::string &Constraint, MVT::ValueType VT) const |
bool | isOperandValidForConstraint (SDOperand Op, char ConstraintLetter) |
virtual bool | isLegalAddressImmediate (int64_t V) const |
Definition at line 141 of file PPCISelLowering.h.
PPCTargetLowering::PPCTargetLowering | ( | TargetMachine & | TM | ) |
Definition at line 30 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::AddPromotedToType(), llvm::TargetLowering::addRegisterClass(), llvm::ISD::AND, llvm::ISD::BIT_CONVERT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::computeRegisterProperties(), llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::Custom, llvm::ISD::DEBUG_LABEL, llvm::ISD::DEBUG_LOC, llvm::ISD::DYNAMIC_STACKALLOC, llvm::TargetLowering::Expand, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::ISD::FSQRT, llvm::TargetMachine::getSubtarget(), llvm::ISD::GlobalAddress, llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm::TargetLowering::Legal, llvm::ISD::LOCATION, llvm::ISD::MEMCPY, llvm::ISD::MEMMOVE, llvm::ISD::MEMSET, llvm::ISD::MUL, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLowering::Promote, llvm::ISD::RET, llvm::ISD::ROTR, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLowering::setOperationAction(), llvm::TargetLowering::setPow2DivIsCheap(), llvm::TargetLowering::setSetCCIsExpensive(), llvm::TargetLowering::setSetCCResultContents(), llvm::TargetLowering::setStackPointerRegisterToSaveRestore(), llvm::TargetLowering::setTargetDAGCombine(), llvm::TargetLowering::setUseUnderscoreSetJmpLongJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCSTORE, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::MVT::v16i8, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, and llvm::TargetLowering::ZeroOrOneSetCCResult.
void PPCTargetLowering::computeMaskedBitsForTargetNode | ( | const SDOperand | Op, | |
uint64_t | Mask, | |||
uint64_t & | KnownZero, | |||
uint64_t & | KnownOne, | |||
unsigned | Depth = 0 | |||
) | const [virtual] |
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 1746 of file PPCISelLowering.cpp.
References llvm::ISD::INTRINSIC_WO_CHAIN, Op, llvm::Intrinsic::ppc_altivec_vcmpbfp_p, llvm::Intrinsic::ppc_altivec_vcmpeqfp_p, llvm::Intrinsic::ppc_altivec_vcmpequb_p, llvm::Intrinsic::ppc_altivec_vcmpequh_p, llvm::Intrinsic::ppc_altivec_vcmpequw_p, llvm::Intrinsic::ppc_altivec_vcmpgefp_p, llvm::Intrinsic::ppc_altivec_vcmpgtfp_p, llvm::Intrinsic::ppc_altivec_vcmpgtsb_p, llvm::Intrinsic::ppc_altivec_vcmpgtsh_p, llvm::Intrinsic::ppc_altivec_vcmpgtsw_p, llvm::Intrinsic::ppc_altivec_vcmpgtub_p, llvm::Intrinsic::ppc_altivec_vcmpgtuh_p, llvm::Intrinsic::ppc_altivec_vcmpgtuw_p, and U.
PPCTargetLowering::ConstraintType PPCTargetLowering::getConstraintType | ( | char | ConstraintLetter | ) | const [virtual] |
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 1782 of file PPCISelLowering.cpp.
References llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().
std::vector< unsigned > PPCTargetLowering::getRegClassForInlineAsmConstraint | ( | const std::string & | Constraint, | |
MVT::ValueType | VT | |||
) | const |
Definition at line 1797 of file PPCISelLowering.cpp.
const char * PPCTargetLowering::getTargetNodeName | ( | unsigned | Opcode | ) | const [virtual] |
getTargetNodeName() - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 234 of file PPCISelLowering.cpp.
References llvm::PPCISD::CALL, llvm::PPCISD::EXTSW_32, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::PPCISD::FSEL, llvm::PPCISD::GlobalBaseReg, llvm::PPCISD::Hi, llvm::PPCISD::Lo, llvm::PPCISD::MFCR, llvm::PPCISD::RET_FLAG, llvm::PPCISD::SHL, llvm::PPCISD::SRA, llvm::PPCISD::SRL, llvm::PPCISD::STD_32, llvm::PPCISD::STFIWX, llvm::PPCISD::VCMP, llvm::PPCISD::VCMPo, llvm::PPCISD::VMADDFP, llvm::PPCISD::VNMSUBFP, and llvm::PPCISD::VPERM.
MachineBasicBlock * PPCTargetLowering::InsertAtEndOfBasicBlock | ( | MachineInstr * | MI, | |
MachineBasicBlock * | MBB | |||
) | [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 1596 of file PPCISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), BB, llvm::BuildMI(), F, llvm::MachineOperand::getImmedValue(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::BasicBlock::getParent(), llvm::MachineOperand::getReg(), MI, and llvm::PHI.
bool PPCTargetLowering::isLegalAddressImmediate | ( | int64_t | V | ) | const [virtual] |
isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode.
Reimplemented from llvm::TargetLowering.
Definition at line 1895 of file PPCISelLowering.cpp.
bool PPCTargetLowering::isOperandValidForConstraint | ( | SDOperand | Op, | |
char | ConstraintLetter | |||
) | [virtual] |
isOperandValidForConstraint - Return true if the specified SDOperand is valid for the specified target constraint letter.
Reimplemented from llvm::TargetLowering.
Definition at line 1854 of file PPCISelLowering.cpp.
References llvm::TargetLowering::isOperandValidForConstraint(), llvm::isPowerOf2_32(), and Op.
std::vector< SDOperand > PPCTargetLowering::LowerArguments | ( | Function & | F, | |
SelectionDAG & | DAG | |||
) | [virtual] |
LowerArguments - This hook must be implemented to indicate how we should lower the arguments for the specified function, into the specified DAG.
Reimplemented from llvm::TargetLowering.
Definition at line 1216 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, BB, llvm::ISD::BUILD_PAIR, llvm::MachineFrameInfo::CreateFixedObject(), DAG, E, F, llvm::MVT::f32, llvm::MVT::f64, llvm::MachineFunction::front(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getRoot(), llvm::SelectionDAG::getSrcValue(), llvm::MachineFunction::getSSARegMap(), llvm::SDOperand::getValue(), llvm::SelectionDAG::getValueType(), llvm::TargetLowering::getValueType(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, MF, llvm::MVT::Other, RegMap, llvm::SelectionDAG::setRoot(), llvm::ISD::STORE, Store, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, Val, and llvm::SDOperand::Val.
std::pair< SDOperand, SDOperand > PPCTargetLowering::LowerCallTo | ( | SDOperand | Chain, | |
const Type * | RetTy, | |||
bool | isVarArg, | |||
unsigned | CC, | |||
bool | isTailCall, | |||
SDOperand | Callee, | |||
ArgListTy & | Args, | |||
SelectionDAG & | DAG | |||
) | [virtual] |
LowerCallTo - This hook lowers an abstract call to a function into an actual call.
Definition at line 1385 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BUILD_PAIR, llvm::PPCISD::CALL, llvm::ISD::CALLSEQ_END, DAG, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::f32, llvm::MVT::f64, first, G, llvm::SelectionDAG::getCALLSEQ_START(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::TargetLowering::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getSrcValue(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDOperand::getValue(), llvm::SelectionDAG::getValueType(), llvm::TargetLowering::getValueType(), llvm::PPCISD::Hi, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Type::isSigned(), llvm::MVT::isVoid, llvm::PPCISD::Lo, Load, NumBytes, llvm::MVT::Other, RetTy, RetVals, second, llvm::ISD::SIGN_EXTEND, Store, llvm::ISD::STORE, llvm::ISD::TokenFactor, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::SDOperand::Val, and llvm::ISD::ZERO_EXTEND.
SDOperand PPCTargetLowering::LowerOperation | ( | SDOperand | Op, | |
SelectionDAG & | DAG | |||
) | [virtual] |
LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 592 of file PPCISelLowering.cpp.
References abort(), llvm::ISD::ADD, llvm::MachineFunction::addLiveOut(), llvm::ISD::AND, llvm::ISD::BIT_CONVERT, Bits, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::ISD::ConstantPool, Copy, CP, llvm::MachineFrameInfo::CreateStackObject(), llvm::ISD::CTLZ, DAG, llvm::ISD::EXTRACT_ELEMENT, llvm::PPCISD::EXTSW_32, llvm::MVT::f32, llvm::MVT::f64, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::MVT::Flag, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::FR, llvm::PPCISD::FSEL, llvm::ISD::FSUB, llvm::PPC::get_VSPLTI_elt(), llvm::SelectionDAG::getConstant(), GetConstantBuildVectorBits(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDOperand::getOpcode(), llvm::SDOperand::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetCC(), llvm::TargetLowering::getSetCCResultTy(), llvm::TargetLowering::getShiftAmountTy(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSrcValue(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLowering::getTargetMachine(), llvm::SDOperand::getValue(), llvm::SDOperand::getValueType(), llvm::MVT::getVectorBaseType(), llvm::MVT::getVectorNumElements(), llvm::ISD::GlobalAddress, llvm::PPCISD::GlobalBaseReg, GV, llvm::PPCISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isFloatingPoint(), isFloatingPointZero(), llvm::MVT::isInteger(), llvm::PPC::isSplatShuffleMask(), llvm::MVT::isVector(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), llvm::MachineFunction::liveout_empty(), llvm::PPCISD::Lo, llvm::Log2_32(), llvm::PPCISD::MFCR, Op, llvm::ISD::OR, llvm::MVT::Other, llvm::Reloc::PIC, llvm::Intrinsic::ppc_altivec_vcmpbfp, llvm::Intrinsic::ppc_altivec_vcmpbfp_p, llvm::Intrinsic::ppc_altivec_vcmpeqfp, llvm::Intrinsic::ppc_altivec_vcmpeqfp_p, llvm::Intrinsic::ppc_altivec_vcmpequb, llvm::Intrinsic::ppc_altivec_vcmpequb_p, llvm::Intrinsic::ppc_altivec_vcmpequh, llvm::Intrinsic::ppc_altivec_vcmpequh_p, llvm::Intrinsic::ppc_altivec_vcmpequw, llvm::Intrinsic::ppc_altivec_vcmpequw_p, llvm::Intrinsic::ppc_altivec_vcmpgefp, llvm::Intrinsic::ppc_altivec_vcmpgefp_p, llvm::Intrinsic::ppc_altivec_vcmpgtfp, llvm::Intrinsic::ppc_altivec_vcmpgtfp_p, llvm::Intrinsic::ppc_altivec_vcmpgtsb, llvm::Intrinsic::ppc_altivec_vcmpgtsb_p, llvm::Intrinsic::ppc_altivec_vcmpgtsh, llvm::Intrinsic::ppc_altivec_vcmpgtsh_p, llvm::Intrinsic::ppc_altivec_vcmpgtsw, llvm::Intrinsic::ppc_altivec_vcmpgtsw_p, llvm::Intrinsic::ppc_altivec_vcmpgtub, llvm::Intrinsic::ppc_altivec_vcmpgtub_p, llvm::Intrinsic::ppc_altivec_vcmpgtuh, llvm::Intrinsic::ppc_altivec_vcmpgtuh_p, llvm::Intrinsic::ppc_altivec_vcmpgtuw, llvm::Intrinsic::ppc_altivec_vcmpgtuw_p, llvm::Intrinsic::ppc_altivec_vslw, llvm::ISD::RET, llvm::PPCISD::RET_FLAG, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::PPCISD::SHL, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::PPCISD::SRA, llvm::ISD::SRA, Src, llvm::ISD::SRL, llvm::PPCISD::SRL, llvm::Reloc::Static, llvm::PPCISD::STD_32, llvm::ISD::STORE, Store, llvm::ISD::SUB, llvm::ISD::TRUNCATE, U, llvm::ISD::UNDEF, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::SDOperand::Val, llvm::Use::Val, llvm::ISD::VASTART, llvm::PPCISD::VCMP, llvm::PPCISD::VCMPo, llvm::ISD::VECTOR_SHUFFLE, llvm::PPCISD::VPERM, llvm::ISD::XOR, Z, and llvm::ISD::ZERO_EXTEND.
SDOperand PPCTargetLowering::PerformDAGCombine | ( | SDNode * | N, | |
DAGCombinerInfo & | DCI | |||
) | const [virtual] |
Definition at line 1658 of file PPCISelLowering.cpp.
References DAG, E, llvm::MVT::f32, llvm::MVT::f64, llvm::PPCISD::FCFID, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWZ, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getNode(), llvm::SDOperand::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDOperand::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getSubtarget(), llvm::TargetLowering::getTargetMachine(), llvm::SDNode::getValueType(), llvm::Value::getValueType(), llvm::SDOperand::getValueType(), llvm::SDOperand::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::Other, llvm::ISD::SINT_TO_FP, llvm::PPCISD::STFIWX, llvm::ISD::STORE, TM, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::SDOperand::Val, Val, llvm::PPCISD::VCMP, and llvm::PPCISD::VCMPo.