LLVM API Documentation

PPCISelLowering.h

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00001 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Chris Lattner and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the interfaces that PPC uses to lower LLVM code into a
00011 // selection DAG.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
00016 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
00017 
00018 #include "llvm/Target/TargetLowering.h"
00019 #include "llvm/CodeGen/SelectionDAG.h"
00020 #include "PPC.h"
00021 
00022 namespace llvm {
00023   namespace PPCISD {
00024     enum NodeType {
00025       // Start the numbering where the builting ops and target ops leave off.
00026       FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
00027 
00028       /// FSEL - Traditional three-operand fsel node.
00029       ///
00030       FSEL,
00031       
00032       /// FCFID - The FCFID instruction, taking an f64 operand and producing
00033       /// and f64 value containing the FP representation of the integer that
00034       /// was temporarily in the f64 operand.
00035       FCFID,
00036       
00037       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 
00038       /// operand, producing an f64 value containing the integer representation
00039       /// of that FP value.
00040       FCTIDZ, FCTIWZ,
00041       
00042       /// STFIWX - The STFIWX instruction.  The first operand is an input token
00043       /// chain, then an f64 value to store, then an address to store it to,
00044       /// then a SRCVALUE for the address.
00045       STFIWX,
00046       
00047       // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
00048       // three v4f32 operands and producing a v4f32 result.
00049       VMADDFP, VNMSUBFP,
00050       
00051       /// VPERM - The PPC VPERM Instruction.
00052       ///
00053       VPERM,
00054       
00055       /// Hi/Lo - These represent the high and low 16-bit parts of a global
00056       /// address respectively.  These nodes have two operands, the first of
00057       /// which must be a TargetGlobalAddress, and the second of which must be a
00058       /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
00059       /// though these are usually folded into other nodes.
00060       Hi, Lo,
00061       
00062       /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
00063       /// at function entry, used for PIC code.
00064       GlobalBaseReg,
00065       
00066       /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
00067       /// shift amounts.  These nodes are generated by the multi-precision shift
00068       /// code.
00069       SRL, SRA, SHL,
00070       
00071       /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
00072       /// registers.
00073       EXTSW_32,
00074 
00075       /// STD_32 - This is the STD instruction for use with "32-bit" registers.
00076       STD_32,
00077       
00078       /// CALL - A function call.
00079       CALL,
00080       
00081       /// Return with a flag operand, matched by 'blr'
00082       RET_FLAG,
00083       
00084       /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
00085       /// This copies the bits corresponding to the specified CRREG into the
00086       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
00087       MFCR,
00088 
00089       /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
00090       /// instructions.  For lack of better number, we use the opcode number
00091       /// encoding for the OPC field to identify the compare.  For example, 838
00092       /// is VCMPGTSH.
00093       VCMP,
00094       
00095       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
00096       /// altivec VCMP*o instructions.  For lack of better number, we use the 
00097       /// opcode number encoding for the OPC field to identify the compare.  For
00098       /// example, 838 is VCMPGTSH.
00099       VCMPo
00100     };
00101   }
00102 
00103   /// Define some predicates that are used for node matching.
00104   namespace PPC {
00105     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
00106     /// VPKUHUM instruction.
00107     bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
00108     
00109     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
00110     /// VPKUWUM instruction.
00111     bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
00112 
00113     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
00114     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
00115     bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
00116 
00117     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
00118     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
00119     bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
00120     
00121     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
00122     /// amount, otherwise return -1.
00123     int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
00124     
00125     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
00126     /// specifies a splat of a single element that is suitable for input to
00127     /// VSPLTB/VSPLTH/VSPLTW.
00128     bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
00129     
00130     /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
00131     /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
00132     unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
00133     
00134     /// get_VSPLTI_elt - If this is a build_vector of constants which can be
00135     /// formed by using a vspltis[bhw] instruction of the specified element
00136     /// size, return the constant being splatted.  The ByteSize field indicates
00137     /// the number of bytes of each element [124] -> [bhw].
00138     SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
00139   }
00140   
00141   class PPCTargetLowering : public TargetLowering {
00142     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
00143     int ReturnAddrIndex;              // FrameIndex for return slot.
00144   public:
00145     PPCTargetLowering(TargetMachine &TM);
00146     
00147     /// getTargetNodeName() - This method returns the name of a target specific
00148     /// DAG node.
00149     virtual const char *getTargetNodeName(unsigned Opcode) const;
00150     
00151     /// LowerOperation - Provide custom lowering hooks for some operations.
00152     ///
00153     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
00154     
00155     virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
00156 
00157     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
00158                                                 uint64_t Mask,
00159                                                 uint64_t &KnownZero, 
00160                                                 uint64_t &KnownOne,
00161                                                 unsigned Depth = 0) const;
00162     /// LowerArguments - This hook must be implemented to indicate how we should
00163     /// lower the arguments for the specified function, into the specified DAG.
00164     virtual std::vector<SDOperand>
00165       LowerArguments(Function &F, SelectionDAG &DAG);
00166     
00167     /// LowerCallTo - This hook lowers an abstract call to a function into an
00168     /// actual call.
00169     virtual std::pair<SDOperand, SDOperand>
00170       LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
00171                   unsigned CC,
00172                   bool isTailCall, SDOperand Callee, ArgListTy &Args,
00173                   SelectionDAG &DAG);
00174 
00175     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
00176                                                        MachineBasicBlock *MBB);
00177     
00178     ConstraintType getConstraintType(char ConstraintLetter) const;
00179     std::vector<unsigned> 
00180       getRegClassForInlineAsmConstraint(const std::string &Constraint,
00181                                         MVT::ValueType VT) const;
00182     bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
00183 
00184     /// isLegalAddressImmediate - Return true if the integer value can be used
00185     /// as the offset of the target addressing mode.
00186     virtual bool isLegalAddressImmediate(int64_t V) const;
00187   };
00188 }
00189 
00190 #endif   // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H