LLVM API Documentation

X86ISelLowering.cpp File Reference

#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86TargetMachine.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/Intrinsics.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"

Include dependency graph for X86ISelLowering.cpp:

Go to the source code of this file.

Functions

static unsigned AddLiveIn (MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
static unsigned getCondBrOpcodeForX86CC (unsigned X86CC)
static bool translateX86CC (ISD::CondCode SetCCOpcode, bool isFP, unsigned &X86CC, bool &Flip)
static bool translateX86CC (SDOperand CC, bool isFP, unsigned &X86CC, bool &Flip)
static bool hasFPCMov (unsigned X86CC)
static bool DarwinGVRequiresExtraLoad (GlobalValue *GV)
static bool isUndefOrInRange (SDOperand Op, unsigned Low, unsigned Hi)
static bool isUndefOrEqual (SDOperand Op, unsigned Val)
static bool isPSHUFHW_PSHUFLWMask (SDNode *N)
static SDOperand CommuteVectorShuffle (SDOperand Op, SelectionDAG &DAG)
static bool isScalarLoadToVector (SDOperand Op)
static bool ShouldXformedToMOVLP (SDOperand V1, SDOperand V2, SDOperand Mask)
static bool isLowerFromV2UpperFromV1 (SDOperand Op)

Variables

static cl::opt< bool > EnableFastCC ("enable-x86-fastcc", cl::Hidden, cl::desc("Enable fastcc on X86"))
static unsigned FASTCC_NUM_INT_ARGS_INREGS = 0


Function Documentation

static unsigned AddLiveIn ( MachineFunction MF,
unsigned  PReg,
TargetRegisterClass RC 
) [static]

AddLiveIn - This helper function adds the specified physical register to the MachineFunction as a live in value. It also creates a corresponding virtual register for it.

Definition at line 688 of file X86ISelLowering.cpp.

References llvm::MachineFunction::addLiveIn(), llvm::SSARegMap::createVirtualRegister(), llvm::MachineFunction::getSSARegMap(), MF, and RC.

static SDOperand CommuteVectorShuffle ( SDOperand  Op,
SelectionDAG DAG 
) [static]

CommuteVectorShuffle - Swap vector_shuffle operandsas well as values in ther permute mask.

Definition at line 1835 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDOperand::getNumOperands(), llvm::SDOperand::getOperand(), llvm::SDOperand::getValueType(), llvm::MVT::getVectorBaseType(), Op, llvm::ISD::UNDEF, Val, and llvm::ISD::VECTOR_SHUFFLE.

Referenced by llvm::X86TargetLowering::LowerOperation().

static bool DarwinGVRequiresExtraLoad ( GlobalValue GV  )  [static]

DarwinGVRequiresExtraLoad - true if accessing the GV requires an extra load. For Darwin, external and weak symbols are indirect, loading the value at address GV rather then the value of GV itself. This means that the GlobalAddress must be in the base or index register of the address, not the GV offset field.

Definition at line 1425 of file X86ISelLowering.cpp.

References GV, llvm::GlobalValue::hasLinkOnceLinkage(), llvm::GlobalValue::hasNotBeenReadFromBytecode(), llvm::GlobalValue::hasWeakLinkage(), and llvm::GlobalValue::isExternal().

Referenced by llvm::X86TargetLowering::isLegalAddressImmediate(), and llvm::X86TargetLowering::LowerOperation().

static unsigned getCondBrOpcodeForX86CC ( unsigned  X86CC  )  [static]

getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode which corresponds to the condition code.

Definition at line 1186 of file X86ISelLowering.cpp.

References llvm::X86ISD::COND_A, llvm::X86ISD::COND_AE, llvm::X86ISD::COND_B, llvm::X86ISD::COND_BE, llvm::X86ISD::COND_E, llvm::X86ISD::COND_G, llvm::X86ISD::COND_GE, llvm::X86ISD::COND_L, llvm::X86ISD::COND_LE, llvm::X86ISD::COND_NE, llvm::X86ISD::COND_NO, llvm::X86ISD::COND_NP, llvm::X86ISD::COND_NS, llvm::X86ISD::COND_O, llvm::X86ISD::COND_P, and llvm::X86ISD::COND_S.

Referenced by llvm::X86TargetLowering::InsertAtEndOfBasicBlock().

static bool hasFPCMov ( unsigned  X86CC  )  [static]

hasFPCMov - is there a floating point cmov for the specific X86 condition code. Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.

Definition at line 1271 of file X86ISelLowering.cpp.

References llvm::X86ISD::COND_A, llvm::X86ISD::COND_AE, llvm::X86ISD::COND_B, llvm::X86ISD::COND_BE, llvm::X86ISD::COND_E, llvm::X86ISD::COND_NE, llvm::X86ISD::COND_NP, and llvm::X86ISD::COND_P.

Referenced by llvm::X86TargetLowering::LowerOperation().

static bool isLowerFromV2UpperFromV1 ( SDOperand  Op  )  [static]

isLowerFromV2UpperFromV1 - Returns true if the shuffle mask is except the reverse of what x86 shuffles want. x86 shuffles requires the lower half elements to come from vector 1 (which would equal the dest.) and the upper half to come from vector 2.

Definition at line 1895 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, isUndefOrInRange(), and Op.

Referenced by llvm::X86TargetLowering::LowerOperation().

static bool isPSHUFHW_PSHUFLWMask ( SDNode N  )  [static]

isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand specifies a 8 element shuffle that can be broken into a pair of PSHUFHW and PSHUFLW.

Definition at line 1804 of file X86ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::UNDEF, and Val.

Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), and llvm::X86TargetLowering::LowerOperation().

static bool isScalarLoadToVector ( SDOperand  Op  )  [inline, static]

isScalarLoadToVector - Returns true if the node is a scalar load that is promoted to a vector.

Definition at line 1862 of file X86ISelLowering.cpp.

References llvm::ISD::LOAD, Op, and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by ShouldXformedToMOVLP().

static bool isUndefOrEqual ( SDOperand  Op,
unsigned  Val 
) [static]

isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value equal to the specified value.

Definition at line 1442 of file X86ISelLowering.cpp.

References Op, and llvm::ISD::UNDEF.

Referenced by llvm::X86::isMOVHLPSMask(), llvm::X86::isMOVHPMask(), llvm::X86::isMOVLHPSMask(), llvm::X86::isMOVLPMask(), llvm::X86::isMOVSMask(), llvm::X86::isPSHUFLWMask(), llvm::X86::isSHUFPMask(), llvm::X86::isUNPCKHMask(), llvm::X86::isUNPCKL_v_undef_Mask(), llvm::X86::isUNPCKLMask(), and ShouldXformedToMOVLP().

static bool isUndefOrInRange ( SDOperand  Op,
unsigned  Low,
unsigned  Hi 
) [static]

isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return true if Op is undef or if its value falls within the specified range (L, H].

Definition at line 1432 of file X86ISelLowering.cpp.

References Op, llvm::ISD::UNDEF, and Val.

Referenced by isLowerFromV2UpperFromV1(), llvm::X86::isPSHUFLWMask(), and ShouldXformedToMOVLP().

static bool ShouldXformedToMOVLP ( SDOperand  V1,
SDOperand  V2,
SDOperand  Mask 
) [static]

ShouldXformedToMOVLP - Return true if the node should be transformed to match movlp{d|s}. The lower half elements should come from V1 (and in order), and the upper half elements should come from the upper half of V2 (not necessarily in order). And since V1 will become the source of the MOVLP, it must be a scalar load.

Definition at line 1875 of file X86ISelLowering.cpp.

References llvm::SDOperand::getNumOperands(), llvm::SDOperand::getOperand(), isScalarLoadToVector(), isUndefOrEqual(), and isUndefOrInRange().

Referenced by llvm::X86TargetLowering::LowerOperation().

static bool translateX86CC ( SDOperand  CC,
bool  isFP,
unsigned &  X86CC,
bool &  Flip 
) [static]

Definition at line 1263 of file X86ISelLowering.cpp.

References translateX86CC().

static bool translateX86CC ( ISD::CondCode  SetCCOpcode,
bool  isFP,
unsigned &  X86CC,
bool &  Flip 
) [static]

translateX86CC - do a one to one translation of a ISD::CondCode to the X86 specific condition code. It returns a false if it cannot do a direct translation. X86CC is the translated CondCode. Flip is set to true if the the order of comparison operands should be flipped.

Definition at line 1212 of file X86ISelLowering.cpp.

References llvm::X86ISD::COND_A, llvm::X86ISD::COND_AE, llvm::X86ISD::COND_B, llvm::X86ISD::COND_BE, llvm::X86ISD::COND_E, llvm::X86ISD::COND_G, llvm::X86ISD::COND_GE, llvm::X86ISD::COND_INVALID, llvm::X86ISD::COND_L, llvm::X86ISD::COND_LE, llvm::X86ISD::COND_NE, llvm::X86ISD::COND_NP, llvm::X86ISD::COND_P, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.

Referenced by llvm::X86TargetLowering::LowerOperation(), and translateX86CC().


Variable Documentation

cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, cl::desc("Enable fastcc on X86")) [static]

Referenced by llvm::X86TargetLowering::LowerArguments(), and llvm::X86TargetLowering::LowerCallTo().

unsigned FASTCC_NUM_INT_ARGS_INREGS = 0 [static]

Definition at line 713 of file X86ISelLowering.cpp.