LLVM API Documentation

llvm::PPCTargetLowering Member List

This is the complete list of members for llvm::PPCTargetLowering, including all inherited members.

addLegalAddressScale(unsigned Scale)llvm::TargetLowering [inline, protected]
addLegalFPImmediate(double Imm)llvm::TargetLowering [inline, protected]
AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, MVT::ValueType DestVT)llvm::TargetLowering [inline, protected]
addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC)llvm::TargetLowering [inline, protected]
allowsUnalignedMemoryAccesses() const llvm::TargetLowering [inline]
allowUnalignedMemoryAccessesllvm::TargetLowering [protected]
ArgListTy typedefllvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const llvm::TargetLowering
computeMaskedBitsForTargetNode(const SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const llvm::PPCTargetLowering [virtual]
computeRegisterProperties()llvm::TargetLowering [protected]
ConstraintType enum namellvm::TargetLowering
Custom enum valuellvm::TargetLowering
CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG)llvm::TargetLowering [virtual]
Expand enum valuellvm::TargetLowering
Extend enum valuellvm::TargetLowering
getConstraintType(char ConstraintLetter) const llvm::PPCTargetLowering [virtual]
getMaxStoresPerMemcpy() const llvm::TargetLowering [inline]
getMaxStoresPerMemmove() const llvm::TargetLowering [inline]
getMaxStoresPerMemset() const llvm::TargetLowering [inline]
getNumElements(MVT::ValueType VT) const llvm::TargetLowering [inline]
getOperationAction(unsigned Op, MVT::ValueType VT) const llvm::TargetLowering [inline]
getPackedTypeBreakdown(const PackedType *PTy, MVT::ValueType &PTyElementVT, MVT::ValueType &PTyLegalElementVT) const llvm::TargetLowering
getPointerTy() const llvm::TargetLowering [inline]
getRegClassFor(MVT::ValueType VT) const llvm::TargetLowering [inline]
getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const llvm::PPCTargetLowering
llvm::TargetLowering::getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const llvm::TargetLowering [virtual]
getRegForInlineAsmConstraint(const std::string &Constraint, MVT::ValueType VT) const llvm::TargetLowering [virtual]
getSchedulingPreference() const llvm::TargetLowering [inline]
getSetCCResultContents() const llvm::TargetLowering [inline]
getSetCCResultTy() const llvm::TargetLowering [inline]
getShiftAmountFlavor() const llvm::TargetLowering [inline]
getShiftAmountTy() const llvm::TargetLowering [inline]
getStackPointerRegisterToSaveRestore() const llvm::TargetLowering [inline]
getTargetData() const llvm::TargetLowering [inline]
getTargetMachine() const llvm::TargetLowering [inline]
getTargetNodeName(unsigned Opcode) const llvm::PPCTargetLowering [virtual]
getTypeAction(MVT::ValueType VT) const llvm::TargetLowering [inline]
getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const llvm::TargetLowering [inline]
getTypeToTransformTo(MVT::ValueType VT) const llvm::TargetLowering [inline]
getValueType(const Type *Ty) const llvm::TargetLowering [inline]
getValueTypeActions() const llvm::TargetLowering [inline]
hasTargetDAGCombine(ISD::NodeType NT) const llvm::TargetLowering [inline]
InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *MBB)llvm::PPCTargetLowering [virtual]
isIntDivCheap() const llvm::TargetLowering [inline]
isLegalAddressImmediate(int64_t V) const llvm::PPCTargetLowering [virtual]
llvm::TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const llvm::TargetLowering [virtual]
isLittleEndian() const llvm::TargetLowering [inline]
isOperandValidForConstraint(SDOperand Op, char ConstraintLetter)llvm::PPCTargetLowering [virtual]
isOperationLegal(unsigned Op, MVT::ValueType VT) const llvm::TargetLowering [inline]
isPow2DivCheap() const llvm::TargetLowering [inline]
isSetCCExpensive() const llvm::TargetLowering [inline]
isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const llvm::TargetLowering [inline, virtual]
isTypeLegal(MVT::ValueType VT) const llvm::TargetLowering [inline]
Legal enum valuellvm::TargetLowering
legal_am_scale_begin() const llvm::TargetLowering [inline]
legal_am_scale_end() const llvm::TargetLowering [inline]
legal_am_scale_iterator typedefllvm::TargetLowering
legal_fpimm_begin() const llvm::TargetLowering [inline]
legal_fpimm_end() const llvm::TargetLowering [inline]
legal_fpimm_iterator typedefllvm::TargetLowering
LegalizeAction enum namellvm::TargetLowering
LowerArguments(Function &F, SelectionDAG &DAG)llvm::PPCTargetLowering [virtual]
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG)llvm::PPCTargetLowering [virtual]
llvm::TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG)=0llvm::TargetLowering [pure virtual]
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG)llvm::TargetLowering [virtual]
LowerOperation(SDOperand Op, SelectionDAG &DAG)llvm::PPCTargetLowering [virtual]
Mask enum valuellvm::TargetLowering
MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth=0) const llvm::TargetLowering
maxStoresPerMemcpyllvm::TargetLowering [protected]
maxStoresPerMemmovellvm::TargetLowering [protected]
maxStoresPerMemsetllvm::TargetLowering [protected]
OutOfRangeShiftAmount enum namellvm::TargetLowering
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::PPCTargetLowering [virtual]
llvm::TargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::TargetLowering [virtual]
PPCTargetLowering(TargetMachine &TM)llvm::PPCTargetLowering
Promote enum valuellvm::TargetLowering
SchedPreference enum namellvm::TargetLowering
SchedulingForLatency enum valuellvm::TargetLowering
SchedulingForRegPressure enum valuellvm::TargetLowering
SetCCResultValue enum namellvm::TargetLowering
setIntDivIsCheap(bool isCheap=true)llvm::TargetLowering [inline, protected]
setOperationAction(unsigned Op, MVT::ValueType VT, LegalizeAction Action)llvm::TargetLowering [inline, protected]
setPow2DivIsCheap(bool isCheap=true)llvm::TargetLowering [inline, protected]
setSchedulingPreference(SchedPreference Pref)llvm::TargetLowering [inline, protected]
setSetCCIsExpensive()llvm::TargetLowering [inline, protected]
setSetCCResultContents(SetCCResultValue Ty)llvm::TargetLowering [inline, protected]
setSetCCResultType(MVT::ValueType VT)llvm::TargetLowering [inline, protected]
setShiftAmountFlavor(OutOfRangeShiftAmount OORSA)llvm::TargetLowering [inline, protected]
setShiftAmountType(MVT::ValueType VT)llvm::TargetLowering [inline, protected]
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLowering [inline, protected]
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLowering [inline, protected]
setUseUnderscoreSetJmpLongJmp(bool Val)llvm::TargetLowering [inline, protected]
SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, uint64_t &KnownZero, uint64_t &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const llvm::TargetLowering
TargetLowering(TargetMachine &TM)llvm::TargetLowering
Undefined enum valuellvm::TargetLowering
UndefinedSetCCResult enum valuellvm::TargetLowering
usesUnderscoreSetJmpLongJmp() const llvm::TargetLowering [inline]
ZeroOrNegativeOneSetCCResult enum valuellvm::TargetLowering
ZeroOrOneSetCCResult enum valuellvm::TargetLowering
~TargetLowering()llvm::TargetLowering [virtual]