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LegalizeDAG.cpp

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00001 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the SelectionDAG::Legalize method.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "llvm/CodeGen/SelectionDAG.h"
00015 #include "llvm/CodeGen/MachineFunction.h"
00016 #include "llvm/CodeGen/MachineFrameInfo.h"
00017 #include "llvm/Target/TargetLowering.h"
00018 #include "llvm/Target/TargetData.h"
00019 #include "llvm/Target/TargetOptions.h"
00020 #include "llvm/CallingConv.h"
00021 #include "llvm/Constants.h"
00022 #include "llvm/Support/MathExtras.h"
00023 #include "llvm/Support/CommandLine.h"
00024 #include <iostream>
00025 #include <map>
00026 using namespace llvm;
00027 
00028 #ifndef NDEBUG
00029 static cl::opt<bool>
00030 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
00031                  cl::desc("Pop up a window to show dags before legalize"));
00032 #else
00033 static const bool ViewLegalizeDAGs = 0;
00034 #endif
00035 
00036 //===----------------------------------------------------------------------===//
00037 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
00038 /// hacks on it until the target machine can handle it.  This involves
00039 /// eliminating value sizes the machine cannot handle (promoting small sizes to
00040 /// large sizes or splitting up large values into small values) as well as
00041 /// eliminating operations the machine cannot handle.
00042 ///
00043 /// This code also does a small amount of optimization and recognition of idioms
00044 /// as part of its processing.  For example, if a target does not support a
00045 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
00046 /// will attempt merge setcc and brc instructions into brcc's.
00047 ///
00048 namespace {
00049 class SelectionDAGLegalize {
00050   TargetLowering &TLI;
00051   SelectionDAG &DAG;
00052 
00053   // Libcall insertion helpers.
00054   
00055   /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
00056   /// legalized.  We use this to ensure that calls are properly serialized
00057   /// against each other, including inserted libcalls.
00058   SDOperand LastCALLSEQ_END;
00059   
00060   /// IsLegalizingCall - This member is used *only* for purposes of providing
00061   /// helpful assertions that a libcall isn't created while another call is 
00062   /// being legalized (which could lead to non-serialized call sequences).
00063   bool IsLegalizingCall;
00064   
00065   enum LegalizeAction {
00066     Legal,      // The target natively supports this operation.
00067     Promote,    // This operation should be executed in a larger type.
00068     Expand,     // Try to expand this to other ops, otherwise use a libcall.
00069   };
00070   
00071   /// ValueTypeActions - This is a bitvector that contains two bits for each
00072   /// value type, where the two bits correspond to the LegalizeAction enum.
00073   /// This can be queried with "getTypeAction(VT)".
00074   TargetLowering::ValueTypeActionImpl ValueTypeActions;
00075 
00076   /// LegalizedNodes - For nodes that are of legal width, and that have more
00077   /// than one use, this map indicates what regularized operand to use.  This
00078   /// allows us to avoid legalizing the same thing more than once.
00079   std::map<SDOperand, SDOperand> LegalizedNodes;
00080 
00081   /// PromotedNodes - For nodes that are below legal width, and that have more
00082   /// than one use, this map indicates what promoted value to use.  This allows
00083   /// us to avoid promoting the same thing more than once.
00084   std::map<SDOperand, SDOperand> PromotedNodes;
00085 
00086   /// ExpandedNodes - For nodes that need to be expanded this map indicates
00087   /// which which operands are the expanded version of the input.  This allows
00088   /// us to avoid expanding the same node more than once.
00089   std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
00090 
00091   /// SplitNodes - For vector nodes that need to be split, this map indicates
00092   /// which which operands are the split version of the input.  This allows us
00093   /// to avoid splitting the same node more than once.
00094   std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
00095   
00096   /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
00097   /// concrete packed types, this contains the mapping of ones we have already
00098   /// processed to the result.
00099   std::map<SDOperand, SDOperand> PackedNodes;
00100   
00101   void AddLegalizedOperand(SDOperand From, SDOperand To) {
00102     LegalizedNodes.insert(std::make_pair(From, To));
00103     // If someone requests legalization of the new node, return itself.
00104     if (From != To)
00105       LegalizedNodes.insert(std::make_pair(To, To));
00106   }
00107   void AddPromotedOperand(SDOperand From, SDOperand To) {
00108     bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
00109     assert(isNew && "Got into the map somehow?");
00110     // If someone requests legalization of the new node, return itself.
00111     LegalizedNodes.insert(std::make_pair(To, To));
00112   }
00113 
00114 public:
00115 
00116   SelectionDAGLegalize(SelectionDAG &DAG);
00117 
00118   /// getTypeAction - Return how we should legalize values of this type, either
00119   /// it is already legal or we need to expand it into multiple registers of
00120   /// smaller integer type, or we need to promote it to a larger type.
00121   LegalizeAction getTypeAction(MVT::ValueType VT) const {
00122     return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
00123   }
00124 
00125   /// isTypeLegal - Return true if this type is legal on this target.
00126   ///
00127   bool isTypeLegal(MVT::ValueType VT) const {
00128     return getTypeAction(VT) == Legal;
00129   }
00130 
00131   void LegalizeDAG();
00132 
00133 private:
00134   /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
00135   /// appropriate for its type.
00136   void HandleOp(SDOperand Op);
00137     
00138   /// LegalizeOp - We know that the specified value has a legal type.
00139   /// Recursively ensure that the operands have legal types, then return the
00140   /// result.
00141   SDOperand LegalizeOp(SDOperand O);
00142   
00143   /// PromoteOp - Given an operation that produces a value in an invalid type,
00144   /// promote it to compute the value into a larger type.  The produced value
00145   /// will have the correct bits for the low portion of the register, but no
00146   /// guarantee is made about the top bits: it may be zero, sign-extended, or
00147   /// garbage.
00148   SDOperand PromoteOp(SDOperand O);
00149 
00150   /// ExpandOp - Expand the specified SDOperand into its two component pieces
00151   /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this,
00152   /// the LegalizeNodes map is filled in for any results that are not expanded,
00153   /// the ExpandedNodes map is filled in for any results that are expanded, and
00154   /// the Lo/Hi values are returned.   This applies to integer types and Vector
00155   /// types.
00156   void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
00157 
00158   /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
00159   /// two smaller values of MVT::Vector type.
00160   void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
00161   
00162   /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
00163   /// equivalent operation that returns a packed value (e.g. MVT::V4F32).  When
00164   /// this is called, we know that PackedVT is the right type for the result and
00165   /// we know that this type is legal for the target.
00166   SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
00167   
00168   /// isShuffleLegal - Return true if a vector shuffle is legal with the
00169   /// specified mask and type.  Targets can specify exactly which masks they
00170   /// support and the code generator is tasked with not creating illegal masks.
00171   ///
00172   /// Note that this will also return true for shuffles that are promoted to a
00173   /// different type.
00174   ///
00175   /// If this is a legal shuffle, this method returns the (possibly promoted)
00176   /// build_vector Mask.  If it's not a legal shuffle, it returns null.
00177   SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
00178   
00179   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
00180 
00181   void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
00182     
00183   SDOperand CreateStackTemporary(MVT::ValueType VT);
00184 
00185   SDOperand ExpandLibCall(const char *Name, SDNode *Node,
00186                           SDOperand &Hi);
00187   SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
00188                           SDOperand Source);
00189 
00190   SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
00191   SDOperand ExpandBUILD_VECTOR(SDNode *Node);
00192   SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
00193   SDOperand ExpandLegalINT_TO_FP(bool isSigned,
00194                                  SDOperand LegalOp,
00195                                  MVT::ValueType DestVT);
00196   SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
00197                                   bool isSigned);
00198   SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
00199                                   bool isSigned);
00200 
00201   SDOperand ExpandBSWAP(SDOperand Op);
00202   SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
00203   bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
00204                    SDOperand &Lo, SDOperand &Hi);
00205   void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
00206                         SDOperand &Lo, SDOperand &Hi);
00207 
00208   SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
00209   SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
00210   
00211   SDOperand getIntPtrConstant(uint64_t Val) {
00212     return DAG.getConstant(Val, TLI.getPointerTy());
00213   }
00214 };
00215 }
00216 
00217 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
00218 /// specified mask and type.  Targets can specify exactly which masks they
00219 /// support and the code generator is tasked with not creating illegal masks.
00220 ///
00221 /// Note that this will also return true for shuffles that are promoted to a
00222 /// different type.
00223 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 
00224                                              SDOperand Mask) const {
00225   switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
00226   default: return 0;
00227   case TargetLowering::Legal:
00228   case TargetLowering::Custom:
00229     break;
00230   case TargetLowering::Promote: {
00231     // If this is promoted to a different type, convert the shuffle mask and
00232     // ask if it is legal in the promoted type!
00233     MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
00234 
00235     // If we changed # elements, change the shuffle mask.
00236     unsigned NumEltsGrowth =
00237       MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
00238     assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
00239     if (NumEltsGrowth > 1) {
00240       // Renumber the elements.
00241       std::vector<SDOperand> Ops;
00242       for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
00243         SDOperand InOp = Mask.getOperand(i);
00244         for (unsigned j = 0; j != NumEltsGrowth; ++j) {
00245           if (InOp.getOpcode() == ISD::UNDEF)
00246             Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
00247           else {
00248             unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
00249             Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
00250           }
00251         }
00252       }
00253       Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
00254     }
00255     VT = NVT;
00256     break;
00257   }
00258   }
00259   return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
00260 }
00261 
00262 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
00263 /// specified vector opcode.
00264 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
00265   switch (VecOp) {
00266   default: assert(0 && "Don't know how to scalarize this opcode!");
00267   case ISD::VADD:  return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
00268   case ISD::VSUB:  return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
00269   case ISD::VMUL:  return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
00270   case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
00271   case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
00272   case ISD::VAND:  return MVT::isInteger(VT) ? ISD::AND : 0;
00273   case ISD::VOR:   return MVT::isInteger(VT) ? ISD::OR  : 0;
00274   case ISD::VXOR:  return MVT::isInteger(VT) ? ISD::XOR : 0;
00275   }
00276 }
00277 
00278 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
00279   : TLI(dag.getTargetLoweringInfo()), DAG(dag),
00280     ValueTypeActions(TLI.getValueTypeActions()) {
00281   assert(MVT::LAST_VALUETYPE <= 32 &&
00282          "Too many value types for ValueTypeActions to hold!");
00283 }
00284 
00285 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
00286 /// not been visited yet and if all of its operands have already been visited.
00287 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
00288                                    std::map<SDNode*, unsigned> &Visited) {
00289   if (++Visited[N] != N->getNumOperands())
00290     return;  // Haven't visited all operands yet
00291   
00292   Order.push_back(N);
00293   
00294   if (N->hasOneUse()) { // Tail recurse in common case.
00295     ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
00296     return;
00297   }
00298   
00299   // Now that we have N in, add anything that uses it if all of their operands
00300   // are now done.
00301   for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
00302     ComputeTopDownOrdering(*UI, Order, Visited);
00303 }
00304 
00305 
00306 void SelectionDAGLegalize::LegalizeDAG() {
00307   LastCALLSEQ_END = DAG.getEntryNode();
00308   IsLegalizingCall = false;
00309   
00310   // The legalize process is inherently a bottom-up recursive process (users
00311   // legalize their uses before themselves).  Given infinite stack space, we
00312   // could just start legalizing on the root and traverse the whole graph.  In
00313   // practice however, this causes us to run out of stack space on large basic
00314   // blocks.  To avoid this problem, compute an ordering of the nodes where each
00315   // node is only legalized after all of its operands are legalized.
00316   std::map<SDNode*, unsigned> Visited;
00317   std::vector<SDNode*> Order;
00318   
00319   // Compute ordering from all of the leaves in the graphs, those (like the
00320   // entry node) that have no operands.
00321   for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
00322        E = DAG.allnodes_end(); I != E; ++I) {
00323     if (I->getNumOperands() == 0) {
00324       Visited[I] = 0 - 1U;
00325       ComputeTopDownOrdering(I, Order, Visited);
00326     }
00327   }
00328   
00329   assert(Order.size() == Visited.size() &&
00330          Order.size() == 
00331             (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
00332          "Error: DAG is cyclic!");
00333   Visited.clear();
00334   
00335   for (unsigned i = 0, e = Order.size(); i != e; ++i)
00336     HandleOp(SDOperand(Order[i], 0));
00337 
00338   // Finally, it's possible the root changed.  Get the new root.
00339   SDOperand OldRoot = DAG.getRoot();
00340   assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
00341   DAG.setRoot(LegalizedNodes[OldRoot]);
00342 
00343   ExpandedNodes.clear();
00344   LegalizedNodes.clear();
00345   PromotedNodes.clear();
00346   SplitNodes.clear();
00347   PackedNodes.clear();
00348 
00349   // Remove dead nodes now.
00350   DAG.RemoveDeadNodes(OldRoot.Val);
00351 }
00352 
00353 
00354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
00355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
00356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
00357   if (Node->getOpcode() == ISD::CALLSEQ_END)
00358     return Node;
00359   if (Node->use_empty())
00360     return 0;   // No CallSeqEnd
00361   
00362   // The chain is usually at the end.
00363   SDOperand TheChain(Node, Node->getNumValues()-1);
00364   if (TheChain.getValueType() != MVT::Other) {
00365     // Sometimes it's at the beginning.
00366     TheChain = SDOperand(Node, 0);
00367     if (TheChain.getValueType() != MVT::Other) {
00368       // Otherwise, hunt for it.
00369       for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
00370         if (Node->getValueType(i) == MVT::Other) {
00371           TheChain = SDOperand(Node, i);
00372           break;
00373         }
00374           
00375       // Otherwise, we walked into a node without a chain.  
00376       if (TheChain.getValueType() != MVT::Other)
00377         return 0;
00378     }
00379   }
00380   
00381   for (SDNode::use_iterator UI = Node->use_begin(),
00382        E = Node->use_end(); UI != E; ++UI) {
00383     
00384     // Make sure to only follow users of our token chain.
00385     SDNode *User = *UI;
00386     for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
00387       if (User->getOperand(i) == TheChain)
00388         if (SDNode *Result = FindCallEndFromCallStart(User))
00389           return Result;
00390   }
00391   return 0;
00392 }
00393 
00394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call 
00395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
00396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
00397   assert(Node && "Didn't find callseq_start for a call??");
00398   if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
00399   
00400   assert(Node->getOperand(0).getValueType() == MVT::Other &&
00401          "Node doesn't have a token chain argument!");
00402   return FindCallStartFromCallEnd(Node->getOperand(0).Val);
00403 }
00404 
00405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
00406 /// see if any uses can reach Dest.  If no dest operands can get to dest, 
00407 /// legalize them, legalize ourself, and return false, otherwise, return true.
00408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, 
00409                                                         SDNode *Dest) {
00410   if (N == Dest) return true;  // N certainly leads to Dest :)
00411   
00412   // If the first result of this node has been already legalized, then it cannot
00413   // reach N.
00414   switch (getTypeAction(N->getValueType(0))) {
00415   case Legal: 
00416     if (LegalizedNodes.count(SDOperand(N, 0))) return false;
00417     break;
00418   case Promote:
00419     if (PromotedNodes.count(SDOperand(N, 0))) return false;
00420     break;
00421   case Expand:
00422     if (ExpandedNodes.count(SDOperand(N, 0))) return false;
00423     break;
00424   }
00425   
00426   // Okay, this node has not already been legalized.  Check and legalize all
00427   // operands.  If none lead to Dest, then we can legalize this node.
00428   bool OperandsLeadToDest = false;
00429   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
00430     OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
00431       LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
00432 
00433   if (OperandsLeadToDest) return true;
00434 
00435   // Okay, this node looks safe, legalize it and return false.
00436   switch (getTypeAction(N->getValueType(0))) {
00437   case Legal:
00438     LegalizeOp(SDOperand(N, 0));
00439     break;
00440   case Promote:
00441     PromoteOp(SDOperand(N, 0));
00442     break;
00443   case Expand: {
00444     SDOperand X, Y;
00445     ExpandOp(SDOperand(N, 0), X, Y);
00446     break;
00447   }
00448   }
00449   return false;
00450 }
00451 
00452 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
00453 /// appropriate for its type.
00454 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
00455   switch (getTypeAction(Op.getValueType())) {
00456   default: assert(0 && "Bad type action!");
00457   case Legal:   LegalizeOp(Op); break;
00458   case Promote: PromoteOp(Op);  break;
00459   case Expand:
00460     if (Op.getValueType() != MVT::Vector) {
00461       SDOperand X, Y;
00462       ExpandOp(Op, X, Y);
00463     } else {
00464       SDNode *N = Op.Val;
00465       unsigned NumOps = N->getNumOperands();
00466       unsigned NumElements =
00467         cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
00468       MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
00469       MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
00470       if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
00471         // In the common case, this is a legal vector type, convert it to the
00472         // packed operation and type now.
00473         PackVectorOp(Op, PackedVT);
00474       } else if (NumElements == 1) {
00475         // Otherwise, if this is a single element vector, convert it to a
00476         // scalar operation.
00477         PackVectorOp(Op, EVT);
00478       } else {
00479         // Otherwise, this is a multiple element vector that isn't supported.
00480         // Split it in half and legalize both parts.
00481         SDOperand X, Y;
00482         SplitVectorOp(Op, X, Y);
00483       }
00484     }
00485     break;
00486   }
00487 }
00488 
00489 
00490 /// LegalizeOp - We know that the specified value has a legal type.
00491 /// Recursively ensure that the operands have legal types, then return the
00492 /// result.
00493 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
00494   assert(isTypeLegal(Op.getValueType()) &&
00495          "Caller should expand or promote operands that are not legal!");
00496   SDNode *Node = Op.Val;
00497 
00498   // If this operation defines any values that cannot be represented in a
00499   // register on this target, make sure to expand or promote them.
00500   if (Node->getNumValues() > 1) {
00501     for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
00502       if (getTypeAction(Node->getValueType(i)) != Legal) {
00503         HandleOp(Op.getValue(i));
00504         assert(LegalizedNodes.count(Op) &&
00505                "Handling didn't add legal operands!");
00506         return LegalizedNodes[Op];
00507       }
00508   }
00509 
00510   // Note that LegalizeOp may be reentered even from single-use nodes, which
00511   // means that we always must cache transformed nodes.
00512   std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
00513   if (I != LegalizedNodes.end()) return I->second;
00514 
00515   SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
00516   SDOperand Result = Op;
00517   bool isCustom = false;
00518   
00519   switch (Node->getOpcode()) {
00520   case ISD::FrameIndex:
00521   case ISD::EntryToken:
00522   case ISD::Register:
00523   case ISD::BasicBlock:
00524   case ISD::TargetFrameIndex:
00525   case ISD::TargetConstant:
00526   case ISD::TargetConstantFP:
00527   case ISD::TargetConstantPool:
00528   case ISD::TargetGlobalAddress:
00529   case ISD::TargetExternalSymbol:
00530   case ISD::VALUETYPE:
00531   case ISD::SRCVALUE:
00532   case ISD::STRING:
00533   case ISD::CONDCODE:
00534     // Primitives must all be legal.
00535     assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
00536            "This must be legal!");
00537     break;
00538   default:
00539     if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
00540       // If this is a target node, legalize it by legalizing the operands then
00541       // passing it through.
00542       std::vector<SDOperand> Ops;
00543       bool Changed = false;
00544       for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
00545         Ops.push_back(LegalizeOp(Node->getOperand(i)));
00546         Changed = Changed || Node->getOperand(i) != Ops.back();
00547       }
00548       if (Changed)
00549         if (Node->getNumValues() == 1)
00550           Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
00551         else {
00552           std::vector<MVT::ValueType> VTs(Node->value_begin(),
00553                                           Node->value_end());
00554           Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
00555         }
00556 
00557       for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
00558         AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
00559       return Result.getValue(Op.ResNo);
00560     }
00561     // Otherwise this is an unhandled builtin node.  splat.
00562     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
00563     assert(0 && "Do not know how to legalize this operator!");
00564     abort();
00565   case ISD::GlobalAddress:
00566   case ISD::ExternalSymbol:
00567   case ISD::ConstantPool:           // Nothing to do.
00568     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
00569     default: assert(0 && "This action is not supported yet!");
00570     case TargetLowering::Custom:
00571       Tmp1 = TLI.LowerOperation(Op, DAG);
00572       if (Tmp1.Val) Result = Tmp1;
00573       // FALLTHROUGH if the target doesn't want to lower this op after all.
00574     case TargetLowering::Legal:
00575       break;
00576     }
00577     break;
00578   case ISD::AssertSext:
00579   case ISD::AssertZext:
00580     Tmp1 = LegalizeOp(Node->getOperand(0));
00581     Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
00582     break;
00583   case ISD::MERGE_VALUES:
00584     // Legalize eliminates MERGE_VALUES nodes.
00585     Result = Node->getOperand(Op.ResNo);
00586     break;
00587   case ISD::CopyFromReg:
00588     Tmp1 = LegalizeOp(Node->getOperand(0));
00589     Result = Op.getValue(0);
00590     if (Node->getNumValues() == 2) {
00591       Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
00592     } else {
00593       assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
00594       if (Node->getNumOperands() == 3) {
00595         Tmp2 = LegalizeOp(Node->getOperand(2));
00596         Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
00597       } else {
00598         Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
00599       }
00600       AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
00601     }
00602     // Since CopyFromReg produces two values, make sure to remember that we
00603     // legalized both of them.
00604     AddLegalizedOperand(Op.getValue(0), Result);
00605     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
00606     return Result.getValue(Op.ResNo);
00607   case ISD::UNDEF: {
00608     MVT::ValueType VT = Op.getValueType();
00609     switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
00610     default: assert(0 && "This action is not supported yet!");
00611     case TargetLowering::Expand:
00612       if (MVT::isInteger(VT))
00613         Result = DAG.getConstant(0, VT);
00614       else if (MVT::isFloatingPoint(VT))
00615         Result = DAG.getConstantFP(0, VT);
00616       else
00617         assert(0 && "Unknown value type!");
00618       break;
00619     case TargetLowering::Legal:
00620       break;
00621     }
00622     break;
00623   }
00624     
00625   case ISD::INTRINSIC_W_CHAIN:
00626   case ISD::INTRINSIC_WO_CHAIN:
00627   case ISD::INTRINSIC_VOID: {
00628     std::vector<SDOperand> Ops;
00629     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
00630       Ops.push_back(LegalizeOp(Node->getOperand(i)));
00631     Result = DAG.UpdateNodeOperands(Result, Ops);
00632     
00633     // Allow the target to custom lower its intrinsics if it wants to.
00634     if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 
00635         TargetLowering::Custom) {
00636       Tmp3 = TLI.LowerOperation(Result, DAG);
00637       if (Tmp3.Val) Result = Tmp3;
00638     }
00639 
00640     if (Result.Val->getNumValues() == 1) break;
00641 
00642     // Must have return value and chain result.
00643     assert(Result.Val->getNumValues() == 2 &&
00644            "Cannot return more than two values!");
00645 
00646     // Since loads produce two values, make sure to remember that we 
00647     // legalized both of them.
00648     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
00649     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
00650     return Result.getValue(Op.ResNo);
00651   }    
00652 
00653   case ISD::LOCATION:
00654     assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
00655     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the input chain.
00656     
00657     switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
00658     case TargetLowering::Promote:
00659     default: assert(0 && "This action is not supported yet!");
00660     case TargetLowering::Expand: {
00661       MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
00662       bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
00663       bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
00664       
00665       if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
00666         const std::string &FName =
00667           cast<StringSDNode>(Node->getOperand(3))->getValue();
00668         const std::string &DirName = 
00669           cast<StringSDNode>(Node->getOperand(4))->getValue();
00670         unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
00671 
00672         std::vector<SDOperand> Ops;
00673         Ops.push_back(Tmp1);  // chain
00674         SDOperand LineOp = Node->getOperand(1);
00675         SDOperand ColOp = Node->getOperand(2);
00676         
00677         if (useDEBUG_LOC) {
00678           Ops.push_back(LineOp);  // line #
00679           Ops.push_back(ColOp);  // col #
00680           Ops.push_back(DAG.getConstant(SrcFile, MVT::i32));  // source file id
00681           Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
00682         } else {
00683           unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
00684           unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
00685           unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
00686           Ops.push_back(DAG.getConstant(ID, MVT::i32));
00687           Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
00688         }
00689       } else {
00690         Result = Tmp1;  // chain
00691       }
00692       break;
00693     }
00694     case TargetLowering::Legal:
00695       if (Tmp1 != Node->getOperand(0) ||
00696           getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
00697         std::vector<SDOperand> Ops;
00698         Ops.push_back(Tmp1);
00699         if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
00700           Ops.push_back(Node->getOperand(1));  // line # must be legal.
00701           Ops.push_back(Node->getOperand(2));  // col # must be legal.
00702         } else {
00703           // Otherwise promote them.
00704           Ops.push_back(PromoteOp(Node->getOperand(1)));
00705           Ops.push_back(PromoteOp(Node->getOperand(2)));
00706         }
00707         Ops.push_back(Node->getOperand(3));  // filename must be legal.
00708         Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
00709         Result = DAG.UpdateNodeOperands(Result, Ops);
00710       }
00711       break;
00712     }
00713     break;
00714     
00715   case ISD::DEBUG_LOC:
00716     assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
00717     switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
00718     default: assert(0 && "This action is not supported yet!");
00719     case TargetLowering::Legal:
00720       Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
00721       Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the line #.
00722       Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the col #.
00723       Tmp4 = LegalizeOp(Node->getOperand(3));  // Legalize the source file id.
00724       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
00725       break;
00726     }
00727     break;    
00728 
00729   case ISD::DEBUG_LABEL:
00730     assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
00731     switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
00732     default: assert(0 && "This action is not supported yet!");
00733     case TargetLowering::Legal:
00734       Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
00735       Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the label id.
00736       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
00737       break;
00738     }
00739     break;
00740 
00741   case ISD::Constant:
00742     // We know we don't need to expand constants here, constants only have one
00743     // value and we check that it is fine above.
00744 
00745     // FIXME: Maybe we should handle things like targets that don't support full
00746     // 32-bit immediates?
00747     break;
00748   case ISD::ConstantFP: {
00749     // Spill FP immediates to the constant pool if the target cannot directly
00750     // codegen them.  Targets often have some immediate values that can be
00751     // efficiently generated into an FP register without a load.  We explicitly
00752     // leave these constants as ConstantFP nodes for the target to deal with.
00753     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
00754 
00755     // Check to see if this FP immediate is already legal.
00756     bool isLegal = false;
00757     for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
00758            E = TLI.legal_fpimm_end(); I != E; ++I)
00759       if (CFP->isExactlyValue(*I)) {
00760         isLegal = true;
00761         break;
00762       }
00763 
00764     // If this is a legal constant, turn it into a TargetConstantFP node.
00765     if (isLegal) {
00766       Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
00767       break;
00768     }
00769 
00770     switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
00771     default: assert(0 && "This action is not supported yet!");
00772     case TargetLowering::Custom:
00773       Tmp3 = TLI.LowerOperation(Result, DAG);
00774       if (Tmp3.Val) {
00775         Result = Tmp3;
00776         break;
00777       }
00778       // FALLTHROUGH
00779     case TargetLowering::Expand:
00780       // Otherwise we need to spill the constant to memory.
00781       bool Extend = false;
00782 
00783       // If a FP immediate is precise when represented as a float and if the
00784       // target can do an extending load from float to double, we put it into
00785       // the constant pool as a float, even if it's is statically typed as a
00786       // double.
00787       MVT::ValueType VT = CFP->getValueType(0);
00788       bool isDouble = VT == MVT::f64;
00789       ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
00790                                              Type::FloatTy, CFP->getValue());
00791       if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
00792           // Only do this if the target has a native EXTLOAD instruction from
00793           // f32.
00794           TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
00795         LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
00796         VT = MVT::f32;
00797         Extend = true;
00798       }
00799 
00800       SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
00801       if (Extend) {
00802         Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
00803                                 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
00804       } else {
00805         Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
00806                              DAG.getSrcValue(NULL));
00807       }
00808     }
00809     break;
00810   }
00811   case ISD::TokenFactor:
00812     if (Node->getNumOperands() == 2) {
00813       Tmp1 = LegalizeOp(Node->getOperand(0));
00814       Tmp2 = LegalizeOp(Node->getOperand(1));
00815       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
00816     } else if (Node->getNumOperands() == 3) {
00817       Tmp1 = LegalizeOp(Node->getOperand(0));
00818       Tmp2 = LegalizeOp(Node->getOperand(1));
00819       Tmp3 = LegalizeOp(Node->getOperand(2));
00820       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
00821     } else {
00822       std::vector<SDOperand> Ops;
00823       // Legalize the operands.
00824       for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
00825         Ops.push_back(LegalizeOp(Node->getOperand(i)));
00826       Result = DAG.UpdateNodeOperands(Result, Ops);
00827     }
00828     break;
00829     
00830   case ISD::FORMAL_ARGUMENTS:
00831     // The only option for this is to custom lower it.
00832     Result = TLI.LowerOperation(Result, DAG);
00833     assert(Result.Val && "Target didn't custom lower ISD::FORMAL_ARGUMENTS!");
00834     break;
00835         
00836   case ISD::BUILD_VECTOR:
00837     switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
00838     default: assert(0 && "This action is not supported yet!");
00839     case TargetLowering::Custom:
00840       Tmp3 = TLI.LowerOperation(Result, DAG);
00841       if (Tmp3.Val) {
00842         Result = Tmp3;
00843         break;
00844       }
00845       // FALLTHROUGH
00846     case TargetLowering::Expand:
00847       Result = ExpandBUILD_VECTOR(Result.Val);
00848       break;
00849     }
00850     break;
00851   case ISD::INSERT_VECTOR_ELT:
00852     Tmp1 = LegalizeOp(Node->getOperand(0));  // InVec
00853     Tmp2 = LegalizeOp(Node->getOperand(1));  // InVal
00854     Tmp3 = LegalizeOp(Node->getOperand(2));  // InEltNo
00855     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
00856     
00857     switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
00858                                    Node->getValueType(0))) {
00859     default: assert(0 && "This action is not supported yet!");
00860     case TargetLowering::Legal:
00861       break;
00862     case TargetLowering::Custom:
00863       Tmp3 = TLI.LowerOperation(Result, DAG);
00864       if (Tmp3.Val) {
00865         Result = Tmp3;
00866         break;
00867       }
00868       // FALLTHROUGH
00869     case TargetLowering::Expand: {
00870       // If the target doesn't support this, we have to spill the input vector
00871       // to a temporary stack slot, update the element, then reload it.  This is
00872       // badness.  We could also load the value into a vector register (either
00873       // with a "move to register" or "extload into register" instruction, then
00874       // permute it into place, if the idx is a constant and if the idx is
00875       // supported by the target.
00876       MVT::ValueType VT    = Tmp1.getValueType();
00877       MVT::ValueType EltVT = Tmp2.getValueType();
00878       MVT::ValueType IdxVT = Tmp3.getValueType();
00879       MVT::ValueType PtrVT = TLI.getPointerTy();
00880       SDOperand StackPtr = CreateStackTemporary(VT);
00881       // Store the vector.
00882       SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
00883                                  Tmp1, StackPtr, DAG.getSrcValue(NULL));
00884 
00885       // Truncate or zero extend offset to target pointer type.
00886       unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
00887       Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
00888       // Add the offset to the index.
00889       unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
00890       Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
00891       SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
00892       // Store the scalar value.
00893       Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
00894                        Tmp2, StackPtr2, DAG.getSrcValue(NULL));
00895       // Load the updated vector.
00896       Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
00897       break;
00898     }
00899     }
00900     break;
00901   case ISD::SCALAR_TO_VECTOR:
00902     if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
00903       Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
00904       break;
00905     }
00906     
00907     Tmp1 = LegalizeOp(Node->getOperand(0));  // InVal
00908     Result = DAG.UpdateNodeOperands(Result, Tmp1);
00909     switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
00910                                    Node->getValueType(0))) {
00911     default: assert(0 && "This action is not supported yet!");
00912     case TargetLowering::Legal:
00913       break;
00914     case TargetLowering::Custom:
00915       Tmp3 = TLI.LowerOperation(Result, DAG);
00916       if (Tmp3.Val) {
00917         Result = Tmp3;
00918         break;
00919       }
00920       // FALLTHROUGH
00921     case TargetLowering::Expand:
00922       Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
00923       break;
00924     }
00925     break;
00926   case ISD::VECTOR_SHUFFLE:
00927     Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize the input vectors,
00928     Tmp2 = LegalizeOp(Node->getOperand(1));   // but not the shuffle mask.
00929     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
00930 
00931     // Allow targets to custom lower the SHUFFLEs they support.
00932     switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
00933     default: assert(0 && "Unknown operation action!");
00934     case TargetLowering::Legal:
00935       assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
00936              "vector shuffle should not be created if not legal!");
00937       break;
00938     case TargetLowering::Custom:
00939       Tmp3 = TLI.LowerOperation(Result, DAG);
00940       if (Tmp3.Val) {
00941         Result = Tmp3;
00942         break;
00943       }
00944       // FALLTHROUGH
00945     case TargetLowering::Expand: {
00946       MVT::ValueType VT = Node->getValueType(0);
00947       MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
00948       MVT::ValueType PtrVT = TLI.getPointerTy();
00949       SDOperand Mask = Node->getOperand(2);
00950       unsigned NumElems = Mask.getNumOperands();
00951       std::vector<SDOperand> Ops;
00952       for (unsigned i = 0; i != NumElems; ++i) {
00953         SDOperand Arg = Mask.getOperand(i);
00954         if (Arg.getOpcode() == ISD::UNDEF) {
00955           Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
00956         } else {
00957           assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
00958           unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
00959           if (Idx < NumElems)
00960             Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
00961                                       DAG.getConstant(Idx, PtrVT)));
00962           else
00963             Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
00964                                       DAG.getConstant(Idx - NumElems, PtrVT)));
00965         }
00966       }
00967       Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
00968       break;
00969     }
00970     case TargetLowering::Promote: {
00971       // Change base type to a different vector type.
00972       MVT::ValueType OVT = Node->getValueType(0);
00973       MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
00974 
00975       // Cast the two input vectors.
00976       Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
00977       Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
00978       
00979       // Convert the shuffle mask to the right # elements.
00980       Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
00981       assert(Tmp3.Val && "Shuffle not legal?");
00982       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
00983       Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
00984       break;
00985     }
00986     }
00987     break;
00988   
00989   case ISD::EXTRACT_VECTOR_ELT:
00990     Tmp1 = LegalizeOp(Node->getOperand(0));
00991     Tmp2 = LegalizeOp(Node->getOperand(1));
00992     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
00993     
00994     switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
00995                                    Tmp1.getValueType())) {
00996     default: assert(0 && "This action is not supported yet!");
00997     case TargetLowering::Legal:
00998       break;
00999     case TargetLowering::Custom:
01000       Tmp3 = TLI.LowerOperation(Result, DAG);
01001       if (Tmp3.Val) {
01002         Result = Tmp3;
01003         break;
01004       }
01005       // FALLTHROUGH
01006     case TargetLowering::Expand:
01007       Result = ExpandEXTRACT_VECTOR_ELT(Result);
01008       break;
01009     }
01010     break;
01011 
01012   case ISD::VEXTRACT_VECTOR_ELT: 
01013     Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
01014     break;
01015     
01016   case ISD::CALLSEQ_START: {
01017     SDNode *CallEnd = FindCallEndFromCallStart(Node);
01018     
01019     // Recursively Legalize all of the inputs of the call end that do not lead
01020     // to this call start.  This ensures that any libcalls that need be inserted
01021     // are inserted *before* the CALLSEQ_START.
01022     for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
01023       LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
01024 
01025     // Now that we legalized all of the inputs (which may have inserted
01026     // libcalls) create the new CALLSEQ_START node.
01027     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01028 
01029     // Merge in the last call, to ensure that this call start after the last
01030     // call ended.
01031     Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
01032     Tmp1 = LegalizeOp(Tmp1);
01033       
01034     // Do not try to legalize the target-specific arguments (#1+).
01035     if (Tmp1 != Node->getOperand(0)) {
01036       std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
01037       Ops[0] = Tmp1;
01038       Result = DAG.UpdateNodeOperands(Result, Ops);
01039     }
01040     
01041     // Remember that the CALLSEQ_START is legalized.
01042     AddLegalizedOperand(Op.getValue(0), Result);
01043     if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
01044       AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
01045     
01046     // Now that the callseq_start and all of the non-call nodes above this call
01047     // sequence have been legalized, legalize the call itself.  During this 
01048     // process, no libcalls can/will be inserted, guaranteeing that no calls
01049     // can overlap.
01050     assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
01051     SDOperand InCallSEQ = LastCALLSEQ_END;
01052     // Note that we are selecting this call!
01053     LastCALLSEQ_END = SDOperand(CallEnd, 0);
01054     IsLegalizingCall = true;
01055     
01056     // Legalize the call, starting from the CALLSEQ_END.
01057     LegalizeOp(LastCALLSEQ_END);
01058     assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
01059     return Result;
01060   }
01061   case ISD::CALLSEQ_END:
01062     // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
01063     // will cause this node to be legalized as well as handling libcalls right.
01064     if (LastCALLSEQ_END.Val != Node) {
01065       LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
01066       std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
01067       assert(I != LegalizedNodes.end() &&
01068              "Legalizing the call start should have legalized this node!");
01069       return I->second;
01070     }
01071     
01072     // Otherwise, the call start has been legalized and everything is going 
01073     // according to plan.  Just legalize ourselves normally here.
01074     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01075     // Do not try to legalize the target-specific arguments (#1+), except for
01076     // an optional flag input.
01077     if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
01078       if (Tmp1 != Node->getOperand(0)) {
01079         std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
01080         Ops[0] = Tmp1;
01081         Result = DAG.UpdateNodeOperands(Result, Ops);
01082       }
01083     } else {
01084       Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
01085       if (Tmp1 != Node->getOperand(0) ||
01086           Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
01087         std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
01088         Ops[0] = Tmp1;
01089         Ops.back() = Tmp2;
01090         Result = DAG.UpdateNodeOperands(Result, Ops);
01091       }
01092     }
01093     assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
01094     // This finishes up call legalization.
01095     IsLegalizingCall = false;
01096     
01097     // If the CALLSEQ_END node has a flag, remember that we legalized it.
01098     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
01099     if (Node->getNumValues() == 2)
01100       AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
01101     return Result.getValue(Op.ResNo);
01102   case ISD::DYNAMIC_STACKALLOC: {
01103     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01104     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the size.
01105     Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the alignment.
01106     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
01107 
01108     Tmp1 = Result.getValue(0);
01109     Tmp2 = Result.getValue(1);
01110     switch (TLI.getOperationAction(Node->getOpcode(),
01111                                    Node->getValueType(0))) {
01112     default: assert(0 && "This action is not supported yet!");
01113     case TargetLowering::Expand: {
01114       unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
01115       assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
01116              " not tell us which reg is the stack pointer!");
01117       SDOperand Chain = Tmp1.getOperand(0);
01118       SDOperand Size  = Tmp2.getOperand(1);
01119       SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
01120       Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size);    // Value
01121       Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1);      // Output chain
01122       Tmp1 = LegalizeOp(Tmp1);
01123       Tmp2 = LegalizeOp(Tmp2);
01124       break;
01125     }
01126     case TargetLowering::Custom:
01127       Tmp3 = TLI.LowerOperation(Tmp1, DAG);
01128       if (Tmp3.Val) {
01129         Tmp1 = LegalizeOp(Tmp3);
01130         Tmp2 = LegalizeOp(Tmp3.getValue(1));
01131       }
01132       break;
01133     case TargetLowering::Legal:
01134       break;
01135     }
01136     // Since this op produce two values, make sure to remember that we
01137     // legalized both of them.
01138     AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
01139     AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
01140     return Op.ResNo ? Tmp2 : Tmp1;
01141   }
01142   case ISD::INLINEASM:
01143     Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize Chain.
01144     Tmp2 = Node->getOperand(Node->getNumOperands()-1);
01145     if (Tmp2.getValueType() == MVT::Flag)     // Legalize Flag if it exists.
01146       Tmp2 = Tmp3 = SDOperand(0, 0);
01147     else
01148       Tmp3 = LegalizeOp(Tmp2);
01149     
01150     if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
01151       std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
01152       Ops[0] = Tmp1;
01153       if (Tmp3.Val) Ops.back() = Tmp3;
01154       Result = DAG.UpdateNodeOperands(Result, Ops);
01155     }
01156       
01157     // INLINE asm returns a chain and flag, make sure to add both to the map.
01158     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
01159     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
01160     return Result.getValue(Op.ResNo);
01161   case ISD::BR:
01162     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01163     // Ensure that libcalls are emitted before a branch.
01164     Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
01165     Tmp1 = LegalizeOp(Tmp1);
01166     LastCALLSEQ_END = DAG.getEntryNode();
01167     
01168     Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
01169     break;
01170 
01171   case ISD::BRCOND:
01172     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01173     // Ensure that libcalls are emitted before a return.
01174     Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
01175     Tmp1 = LegalizeOp(Tmp1);
01176     LastCALLSEQ_END = DAG.getEntryNode();
01177 
01178     switch (getTypeAction(Node->getOperand(1).getValueType())) {
01179     case Expand: assert(0 && "It's impossible to expand bools");
01180     case Legal:
01181       Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
01182       break;
01183     case Promote:
01184       Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the condition.
01185       break;
01186     }
01187 
01188     // Basic block destination (Op#2) is always legal.
01189     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
01190       
01191     switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {  
01192     default: assert(0 && "This action is not supported yet!");
01193     case TargetLowering::Legal: break;
01194     case TargetLowering::Custom:
01195       Tmp1 = TLI.LowerOperation(Result, DAG);
01196       if (Tmp1.Val) Result = Tmp1;
01197       break;
01198     case TargetLowering::Expand:
01199       // Expand brcond's setcc into its constituent parts and create a BR_CC
01200       // Node.
01201       if (Tmp2.getOpcode() == ISD::SETCC) {
01202         Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
01203                              Tmp2.getOperand(0), Tmp2.getOperand(1),
01204                              Node->getOperand(2));
01205       } else {
01206         // Make sure the condition is either zero or one.  It may have been
01207         // promoted from something else.
01208         unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
01209         if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
01210           Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
01211         
01212         Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 
01213                              DAG.getCondCode(ISD::SETNE), Tmp2,
01214                              DAG.getConstant(0, Tmp2.getValueType()),
01215                              Node->getOperand(2));
01216       }
01217       break;
01218     }
01219     break;
01220   case ISD::BR_CC:
01221     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01222     // Ensure that libcalls are emitted before a branch.
01223     Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
01224     Tmp1 = LegalizeOp(Tmp1);
01225     LastCALLSEQ_END = DAG.getEntryNode();
01226     
01227     Tmp2 = Node->getOperand(2);              // LHS 
01228     Tmp3 = Node->getOperand(3);              // RHS
01229     Tmp4 = Node->getOperand(1);              // CC
01230 
01231     LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
01232     
01233     // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
01234     // the LHS is a legal SETCC itself.  In this case, we need to compare
01235     // the result against zero to select between true and false values.
01236     if (Tmp3.Val == 0) {
01237       Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
01238       Tmp4 = DAG.getCondCode(ISD::SETNE);
01239     }
01240     
01241     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 
01242                                     Node->getOperand(4));
01243       
01244     switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
01245     default: assert(0 && "Unexpected action for BR_CC!");
01246     case TargetLowering::Legal: break;
01247     case TargetLowering::Custom:
01248       Tmp4 = TLI.LowerOperation(Result, DAG);
01249       if (Tmp4.Val) Result = Tmp4;
01250       break;
01251     }
01252     break;
01253   case ISD::LOAD: {
01254     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01255     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
01256 
01257     MVT::ValueType VT = Node->getValueType(0);
01258     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
01259     Tmp3 = Result.getValue(0);
01260     Tmp4 = Result.getValue(1);
01261     
01262     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
01263     default: assert(0 && "This action is not supported yet!");
01264     case TargetLowering::Legal: break;
01265     case TargetLowering::Custom:
01266       Tmp1 = TLI.LowerOperation(Tmp3, DAG);
01267       if (Tmp1.Val) {
01268         Tmp3 = LegalizeOp(Tmp1);
01269         Tmp4 = LegalizeOp(Tmp1.getValue(1));
01270       }
01271       break;
01272     case TargetLowering::Promote: {
01273       // Only promote a load of vector type to another.
01274       assert(MVT::isVector(VT) && "Cannot promote this load!");
01275       // Change base type to a different vector type.
01276       MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
01277 
01278       Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
01279       Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
01280       Tmp4 = LegalizeOp(Tmp1.getValue(1));
01281       break;
01282     }
01283     }
01284     // Since loads produce two values, make sure to remember that we 
01285     // legalized both of them.
01286     AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
01287     AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
01288     return Op.ResNo ? Tmp4 : Tmp3;
01289   }
01290   case ISD::EXTLOAD:
01291   case ISD::SEXTLOAD:
01292   case ISD::ZEXTLOAD: {
01293     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01294     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
01295 
01296     MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
01297     switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
01298     default: assert(0 && "This action is not supported yet!");
01299     case TargetLowering::Promote:
01300       assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
01301       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
01302                                       DAG.getValueType(MVT::i8));
01303       Tmp1 = Result.getValue(0);
01304       Tmp2 = Result.getValue(1);
01305       break;
01306     case TargetLowering::Custom:
01307       isCustom = true;
01308       // FALLTHROUGH
01309     case TargetLowering::Legal:
01310       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
01311                                       Node->getOperand(3));
01312       Tmp1 = Result.getValue(0);
01313       Tmp2 = Result.getValue(1);
01314       
01315       if (isCustom) {
01316         Tmp3 = TLI.LowerOperation(Tmp3, DAG);
01317         if (Tmp3.Val) {
01318           Tmp1 = LegalizeOp(Tmp3);
01319           Tmp2 = LegalizeOp(Tmp3.getValue(1));
01320         }
01321       }
01322       break;
01323     case TargetLowering::Expand:
01324       // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
01325       if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
01326         SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
01327         Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
01328         Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
01329         Tmp2 = LegalizeOp(Load.getValue(1));
01330         break;
01331       }
01332       assert(Node->getOpcode() != ISD::EXTLOAD &&
01333              "EXTLOAD should always be supported!");
01334       // Turn the unsupported load into an EXTLOAD followed by an explicit
01335       // zero/sign extend inreg.
01336       Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
01337                               Tmp1, Tmp2, Node->getOperand(2), SrcVT);
01338       SDOperand ValRes;
01339       if (Node->getOpcode() == ISD::SEXTLOAD)
01340         ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
01341                              Result, DAG.getValueType(SrcVT));
01342       else
01343         ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
01344       Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
01345       Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
01346       break;
01347     }
01348     // Since loads produce two values, make sure to remember that we legalized
01349     // both of them.
01350     AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
01351     AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
01352     return Op.ResNo ? Tmp2 : Tmp1;
01353   }
01354   case ISD::EXTRACT_ELEMENT: {
01355     MVT::ValueType OpTy = Node->getOperand(0).getValueType();
01356     switch (getTypeAction(OpTy)) {
01357     default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
01358     case Legal:
01359       if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
01360         // 1 -> Hi
01361         Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
01362                              DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 
01363                                              TLI.getShiftAmountTy()));
01364         Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
01365       } else {
01366         // 0 -> Lo
01367         Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 
01368                              Node->getOperand(0));
01369       }
01370       break;
01371     case Expand:
01372       // Get both the low and high parts.
01373       ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
01374       if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
01375         Result = Tmp2;  // 1 -> Hi
01376       else
01377         Result = Tmp1;  // 0 -> Lo
01378       break;
01379     }
01380     break;
01381   }
01382 
01383   case ISD::CopyToReg:
01384     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01385 
01386     assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
01387            "Register type must be legal!");
01388     // Legalize the incoming value (must be a legal type).
01389     Tmp2 = LegalizeOp(Node->getOperand(2));
01390     if (Node->getNumValues() == 1) {
01391       Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
01392     } else {
01393       assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
01394       if (Node->getNumOperands() == 4) {
01395         Tmp3 = LegalizeOp(Node->getOperand(3));
01396         Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
01397                                         Tmp3);
01398       } else {
01399         Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
01400       }
01401       
01402       // Since this produces two values, make sure to remember that we legalized
01403       // both of them.
01404       AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
01405       AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
01406       return Result;
01407     }
01408     break;
01409 
01410   case ISD::RET:
01411     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01412 
01413     // Ensure that libcalls are emitted before a return.
01414     Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
01415     Tmp1 = LegalizeOp(Tmp1);
01416     LastCALLSEQ_END = DAG.getEntryNode();
01417       
01418     switch (Node->getNumOperands()) {
01419     case 2:  // ret val
01420       Tmp2 = Node->getOperand(1);
01421       switch (getTypeAction(Tmp2.getValueType())) {
01422       case Legal:
01423         Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2));
01424         break;
01425       case Expand:
01426         if (Tmp2.getValueType() != MVT::Vector) {
01427           SDOperand Lo, Hi;
01428           ExpandOp(Tmp2, Lo, Hi);
01429           Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
01430         } else {
01431           SDNode *InVal = Tmp2.Val;
01432           unsigned NumElems =
01433             cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
01434           MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
01435           
01436           // Figure out if there is a Packed type corresponding to this Vector
01437           // type.  If so, convert to the packed type.
01438           MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
01439           if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
01440             // Turn this into a return of the packed type.
01441             Tmp2 = PackVectorOp(Tmp2, TVT);
01442             Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
01443           } else if (NumElems == 1) {
01444             // Turn this into a return of the scalar type.
01445             Tmp2 = PackVectorOp(Tmp2, EVT);
01446             Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
01447             
01448             // FIXME: Returns of gcc generic vectors smaller than a legal type
01449             // should be returned in integer registers!
01450             
01451             // The scalarized value type may not be legal, e.g. it might require
01452             // promotion or expansion.  Relegalize the return.
01453             Result = LegalizeOp(Result);
01454           } else {
01455             // FIXME: Returns of gcc generic vectors larger than a legal vector
01456             // type should be returned by reference!
01457             SDOperand Lo, Hi;
01458             SplitVectorOp(Tmp2, Lo, Hi);
01459             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
01460             Result = LegalizeOp(Result);
01461           }
01462         }
01463         break;
01464       case Promote:
01465         Tmp2 = PromoteOp(Node->getOperand(1));
01466         Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
01467         Result = LegalizeOp(Result);
01468         break;
01469       }
01470       break;
01471     case 1:  // ret void
01472       Result = DAG.UpdateNodeOperands(Result, Tmp1);
01473       break;
01474     default: { // ret <values>
01475       std::vector<SDOperand> NewValues;
01476       NewValues.push_back(Tmp1);
01477       for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
01478         switch (getTypeAction(Node->getOperand(i).getValueType())) {
01479         case Legal:
01480           NewValues.push_back(LegalizeOp(Node->getOperand(i)));
01481           break;
01482         case Expand: {
01483           SDOperand Lo, Hi;
01484           assert(Node->getOperand(i).getValueType() != MVT::Vector &&
01485                  "FIXME: TODO: implement returning non-legal vector types!");
01486           ExpandOp(Node->getOperand(i), Lo, Hi);
01487           NewValues.push_back(Lo);
01488           NewValues.push_back(Hi);
01489           break;
01490         }
01491         case Promote:
01492           assert(0 && "Can't promote multiple return value yet!");
01493         }
01494           
01495       if (NewValues.size() == Node->getNumOperands())
01496         Result = DAG.UpdateNodeOperands(Result, NewValues);
01497       else
01498         Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
01499       break;
01500     }
01501     }
01502 
01503     if (Result.getOpcode() == ISD::RET) {
01504       switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
01505       default: assert(0 && "This action is not supported yet!");
01506       case TargetLowering::Legal: break;
01507       case TargetLowering::Custom:
01508         Tmp1 = TLI.LowerOperation(Result, DAG);
01509         if (Tmp1.Val) Result = Tmp1;
01510         break;
01511       }
01512     }
01513     break;
01514   case ISD::STORE: {
01515     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01516     Tmp2 = LegalizeOp(Node->getOperand(2));  // Legalize the pointer.
01517 
01518     // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
01519     // FIXME: We shouldn't do this for TargetConstantFP's.
01520     // FIXME: move this to the DAG Combiner!
01521     if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
01522       if (CFP->getValueType(0) == MVT::f32) {
01523         Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
01524       } else {
01525         assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
01526         Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
01527       }
01528       Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 
01529                            Node->getOperand(3));
01530       break;
01531     }
01532 
01533     switch (getTypeAction(Node->getOperand(1).getValueType())) {
01534     case Legal: {
01535       Tmp3 = LegalizeOp(Node->getOperand(1));
01536       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
01537                                       Node->getOperand(3));
01538 
01539       MVT::ValueType VT = Tmp3.getValueType();
01540       switch (TLI.getOperationAction(ISD::STORE, VT)) {
01541       default: assert(0 && "This action is not supported yet!");
01542       case TargetLowering::Legal:  break;
01543       case TargetLowering::Custom:
01544         Tmp1 = TLI.LowerOperation(Result, DAG);
01545         if (Tmp1.Val) Result = Tmp1;
01546         break;
01547       }
01548       break;
01549     }
01550     case Promote:
01551       // Truncate the value and store the result.
01552       Tmp3 = PromoteOp(Node->getOperand(1));
01553       Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
01554                            Node->getOperand(3),
01555                           DAG.getValueType(Node->getOperand(1).getValueType()));
01556       break;
01557 
01558     case Expand:
01559       unsigned IncrementSize = 0;
01560       SDOperand Lo, Hi;
01561       
01562       // If this is a vector type, then we have to calculate the increment as
01563       // the product of the element size in bytes, and the number of elements
01564       // in the high half of the vector.
01565       if (Node->getOperand(1).getValueType() == MVT::Vector) {
01566         SDNode *InVal = Node->getOperand(1).Val;
01567         unsigned NumElems =
01568           cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
01569         MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
01570 
01571         // Figure out if there is a Packed type corresponding to this Vector
01572         // type.  If so, convert to the packed type.
01573         MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
01574         if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
01575           // Turn this into a normal store of the packed type.
01576           Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
01577           Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
01578                                           Node->getOperand(3));
01579           break;
01580         } else if (NumElems == 1) {
01581           // Turn this into a normal store of the scalar type.
01582           Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
01583           Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
01584                                           Node->getOperand(3));
01585           // The scalarized value type may not be legal, e.g. it might require
01586           // promotion or expansion.  Relegalize the scalar store.
01587           Result = LegalizeOp(Result);
01588           break;
01589         } else {
01590           SplitVectorOp(Node->getOperand(1), Lo, Hi);
01591           IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
01592         }
01593       } else {
01594         ExpandOp(Node->getOperand(1), Lo, Hi);
01595         IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
01596 
01597         if (!TLI.isLittleEndian())
01598           std::swap(Lo, Hi);
01599       }
01600 
01601       Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
01602                        Node->getOperand(3));
01603       Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
01604                          getIntPtrConstant(IncrementSize));
01605       assert(isTypeLegal(Tmp2.getValueType()) &&
01606              "Pointers must be legal!");
01607       // FIXME: This sets the srcvalue of both halves to be the same, which is
01608       // wrong.
01609       Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
01610                        Node->getOperand(3));
01611       Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
01612       break;
01613     }
01614     break;
01615   }
01616   case ISD::PCMARKER:
01617     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01618     Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
01619     break;
01620   case ISD::STACKSAVE:
01621     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01622     Result = DAG.UpdateNodeOperands(Result, Tmp1);
01623     Tmp1 = Result.getValue(0);
01624     Tmp2 = Result.getValue(1);
01625     
01626     switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
01627     default: assert(0 && "This action is not supported yet!");
01628     case TargetLowering::Legal: break;
01629     case TargetLowering::Custom:
01630       Tmp3 = TLI.LowerOperation(Result, DAG);
01631       if (Tmp3.Val) {
01632         Tmp1 = LegalizeOp(Tmp3);
01633         Tmp2 = LegalizeOp(Tmp3.getValue(1));
01634       }
01635       break;
01636     case TargetLowering::Expand:
01637       // Expand to CopyFromReg if the target set 
01638       // StackPointerRegisterToSaveRestore.
01639       if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
01640         Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
01641                                   Node->getValueType(0));
01642         Tmp2 = Tmp1.getValue(1);
01643       } else {
01644         Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
01645         Tmp2 = Node->getOperand(0);
01646       }
01647       break;
01648     }
01649 
01650     // Since stacksave produce two values, make sure to remember that we
01651     // legalized both of them.
01652     AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
01653     AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
01654     return Op.ResNo ? Tmp2 : Tmp1;
01655 
01656   case ISD::STACKRESTORE:
01657     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01658     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
01659     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
01660       
01661     switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
01662     default: assert(0 && "This action is not supported yet!");
01663     case TargetLowering::Legal: break;
01664     case TargetLowering::Custom:
01665       Tmp1 = TLI.LowerOperation(Result, DAG);
01666       if (Tmp1.Val) Result = Tmp1;
01667       break;
01668     case TargetLowering::Expand:
01669       // Expand to CopyToReg if the target set 
01670       // StackPointerRegisterToSaveRestore.
01671       if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
01672         Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
01673       } else {
01674         Result = Tmp1;
01675       }
01676       break;
01677     }
01678     break;
01679 
01680   case ISD::READCYCLECOUNTER:
01681     Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
01682     Result = DAG.UpdateNodeOperands(Result, Tmp1);
01683 
01684     // Since rdcc produce two values, make sure to remember that we legalized
01685     // both of them.
01686     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
01687     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
01688     return Result;
01689 
01690   case ISD::TRUNCSTORE: {
01691     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
01692     Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the pointer.
01693 
01694     assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
01695            "Cannot handle illegal TRUNCSTORE yet!");
01696     Tmp2 = LegalizeOp(Node->getOperand(1));
01697     
01698     // The only promote case we handle is TRUNCSTORE:i1 X into
01699     //   -> TRUNCSTORE:i8 (and X, 1)
01700     if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
01701         TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 
01702               TargetLowering::Promote) {
01703       // Promote the bool to a mask then store.
01704       Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
01705                          DAG.getConstant(1, Tmp2.getValueType()));
01706       Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
01707                            Node->getOperand(3), DAG.getValueType(MVT::i8));
01708 
01709     } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
01710                Tmp3 != Node->getOperand(2)) {
01711       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
01712                                       Node->getOperand(3), Node->getOperand(4));
01713     }
01714 
01715     MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
01716     switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
01717     default: assert(0 && "This action is not supported yet!");
01718     case TargetLowering::Legal: break;
01719     case TargetLowering::Custom:
01720       Tmp1 = TLI.LowerOperation(Result, DAG);
01721       if (Tmp1.Val) Result = Tmp1;
01722       break;
01723     }
01724     break;
01725   }
01726   case ISD::SELECT:
01727     switch (getTypeAction(Node->getOperand(0).getValueType())) {
01728     case Expand: assert(0 && "It's impossible to expand bools");
01729     case Legal:
01730       Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
01731       break;
01732     case Promote:
01733       Tmp1 = PromoteOp(Node->getOperand(0));  // Promote the condition.
01734       break;
01735     }
01736     Tmp2 = LegalizeOp(Node->getOperand(1));   // TrueVal
01737     Tmp3 = LegalizeOp(Node->getOperand(2));   // FalseVal
01738 
01739     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
01740       
01741     switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
01742     default: assert(0 && "This action is not supported yet!");
01743     case TargetLowering::Legal: break;
01744     case TargetLowering::Custom: {
01745       Tmp1 = TLI.LowerOperation(Result, DAG);
01746       if (Tmp1.Val) Result = Tmp1;
01747       break;
01748     }
01749     case TargetLowering::Expand:
01750       if (Tmp1.getOpcode() == ISD::SETCC) {
01751         Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 
01752                               Tmp2, Tmp3,
01753                               cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
01754       } else {
01755         // Make sure the condition is either zero or one.  It may have been
01756         // promoted from something else.
01757         unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
01758         if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
01759           Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
01760         Result = DAG.getSelectCC(Tmp1, 
01761                                  DAG.getConstant(0, Tmp1.getValueType()),
01762                                  Tmp2, Tmp3, ISD::SETNE);
01763       }
01764       break;
01765     case TargetLowering::Promote: {
01766       MVT::ValueType NVT =
01767         TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
01768       unsigned ExtOp, TruncOp;
01769       if (MVT::isVector(Tmp2.getValueType())) {
01770         ExtOp   = ISD::BIT_CONVERT;
01771         TruncOp = ISD::BIT_CONVERT;
01772       } else if (MVT::isInteger(Tmp2.getValueType())) {
01773         ExtOp   = ISD::ANY_EXTEND;
01774         TruncOp = ISD::TRUNCATE;
01775       } else {
01776         ExtOp   = ISD::FP_EXTEND;
01777         TruncOp = ISD::FP_ROUND;
01778       }
01779       // Promote each of the values to the new type.
01780       Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
01781       Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
01782       // Perform the larger operation, then round down.
01783       Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
01784       Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
01785       break;
01786     }
01787     }
01788     break;
01789   case ISD::SELECT_CC: {
01790     Tmp1 = Node->getOperand(0);               // LHS
01791     Tmp2 = Node->getOperand(1);               // RHS
01792     Tmp3 = LegalizeOp(Node->getOperand(2));   // True
01793     Tmp4 = LegalizeOp(Node->getOperand(3));   // False
01794     SDOperand CC = Node->getOperand(4);
01795     
01796     LegalizeSetCCOperands(Tmp1, Tmp2, CC);
01797     
01798     // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
01799     // the LHS is a legal SETCC itself.  In this case, we need to compare
01800     // the result against zero to select between true and false values.
01801     if (Tmp2.Val == 0) {
01802       Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
01803       CC = DAG.getCondCode(ISD::SETNE);
01804     }
01805     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
01806 
01807     // Everything is legal, see if we should expand this op or something.
01808     switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
01809     default: assert(0 && "This action is not supported yet!");
01810     case TargetLowering::Legal: break;
01811     case TargetLowering::Custom:
01812       Tmp1 = TLI.LowerOperation(Result, DAG);
01813       if (Tmp1.Val) Result = Tmp1;
01814       break;
01815     }
01816     break;
01817   }
01818   case ISD::SETCC:
01819     Tmp1 = Node->getOperand(0);
01820     Tmp2 = Node->getOperand(1);
01821     Tmp3 = Node->getOperand(2);
01822     LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
01823     
01824     // If we had to Expand the SetCC operands into a SELECT node, then it may 
01825     // not always be possible to return a true LHS & RHS.  In this case, just 
01826     // return the value we legalized, returned in the LHS
01827     if (Tmp2.Val == 0) {
01828       Result = Tmp1;
01829       break;
01830     }
01831 
01832     switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
01833     default: assert(0 && "Cannot handle this action for SETCC yet!");
01834     case TargetLowering::Custom:
01835       isCustom = true;
01836       // FALLTHROUGH.
01837     case TargetLowering::Legal:
01838       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
01839       if (isCustom) {
01840         Tmp3 = TLI.LowerOperation(Result, DAG);
01841         if (Tmp3.Val) Result = Tmp3;
01842       }
01843       break;
01844     case TargetLowering::Promote: {
01845       // First step, figure out the appropriate operation to use.
01846       // Allow SETCC to not be supported for all legal data types
01847       // Mostly this targets FP
01848       MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
01849       MVT::ValueType OldVT = NewInTy;
01850 
01851       // Scan for the appropriate larger type to use.
01852       while (1) {
01853         NewInTy = (MVT::ValueType)(NewInTy+1);
01854 
01855         assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
01856                "Fell off of the edge of the integer world");
01857         assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
01858                "Fell off of the edge of the floating point world");
01859           
01860         // If the target supports SETCC of this type, use it.
01861         if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
01862           break;
01863       }
01864       if (MVT::isInteger(NewInTy))
01865         assert(0 && "Cannot promote Legal Integer SETCC yet");
01866       else {
01867         Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
01868         Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
01869       }
01870       Tmp1 = LegalizeOp(Tmp1);
01871       Tmp2 = LegalizeOp(Tmp2);
01872       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
01873       Result = LegalizeOp(Result);
01874       break;
01875     }
01876     case TargetLowering::Expand:
01877       // Expand a setcc node into a select_cc of the same condition, lhs, and
01878       // rhs that selects between const 1 (true) and const 0 (false).
01879       MVT::ValueType VT = Node->getValueType(0);
01880       Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 
01881                            DAG.getConstant(1, VT), DAG.getConstant(0, VT),
01882                            Node->getOperand(2));
01883       break;
01884     }
01885     break;
01886   case ISD::MEMSET:
01887   case ISD::MEMCPY:
01888   case ISD::MEMMOVE: {
01889     Tmp1 = LegalizeOp(Node->getOperand(0));      // Chain
01890     Tmp2 = LegalizeOp(Node->getOperand(1));      // Pointer
01891 
01892     if (Node->getOpcode() == ISD::MEMSET) {      // memset = ubyte
01893       switch (getTypeAction(Node->getOperand(2).getValueType())) {
01894       case Expand: assert(0 && "Cannot expand a byte!");
01895       case Legal:
01896         Tmp3 = LegalizeOp(Node->getOperand(2));
01897         break;
01898       case Promote:
01899         Tmp3 = PromoteOp(Node->getOperand(2));
01900         break;
01901       }
01902     } else {
01903       Tmp3 = LegalizeOp(Node->getOperand(2));    // memcpy/move = pointer,
01904     }
01905 
01906     SDOperand Tmp4;
01907     switch (getTypeAction(Node->getOperand(3).getValueType())) {
01908     case Expand: {
01909       // Length is too big, just take the lo-part of the length.
01910       SDOperand HiPart;
01911       ExpandOp(Node->getOperand(3), HiPart, Tmp4);
01912       break;
01913     }
01914     case Legal:
01915       Tmp4 = LegalizeOp(Node->getOperand(3));
01916       break;
01917     case Promote:
01918       Tmp4 = PromoteOp(Node->getOperand(3));
01919       break;
01920     }
01921 
01922     SDOperand Tmp5;
01923     switch (getTypeAction(Node->getOperand(4).getValueType())) {  // uint
01924     case Expand: assert(0 && "Cannot expand this yet!");
01925     case Legal:
01926       Tmp5 = LegalizeOp(Node->getOperand(4));
01927       break;
01928     case Promote:
01929       Tmp5 = PromoteOp(Node->getOperand(4));
01930       break;
01931     }
01932 
01933     switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
01934     default: assert(0 && "This action not implemented for this operation!");
01935     case TargetLowering::Custom:
01936       isCustom = true;
01937       // FALLTHROUGH
01938     case TargetLowering::Legal:
01939       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
01940       if (isCustom) {
01941         Tmp1 = TLI.LowerOperation(Result, DAG);
01942         if (Tmp1.Val) Result = Tmp1;
01943       }
01944       break;
01945     case TargetLowering::Expand: {
01946       // Otherwise, the target does not support this operation.  Lower the
01947       // operation to an explicit libcall as appropriate.
01948       MVT::ValueType IntPtr = TLI.getPointerTy();
01949       const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
01950       std::vector<std::pair<SDOperand, const Type*> > Args;
01951 
01952       const char *FnName = 0;
01953       if (Node->getOpcode() == ISD::MEMSET) {
01954         Args.push_back(std::make_pair(Tmp2, IntPtrTy));
01955         // Extend the (previously legalized) ubyte argument to be an int value
01956         // for the call.
01957         if (Tmp3.getValueType() > MVT::i32)
01958           Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
01959         else
01960           Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
01961         Args.push_back(std::make_pair(Tmp3, Type::IntTy));
01962         Args.push_back(std::make_pair(Tmp4, IntPtrTy));
01963 
01964         FnName = "memset";
01965       } else if (Node->getOpcode() == ISD::MEMCPY ||
01966                  Node->getOpcode() == ISD::MEMMOVE) {
01967         Args.push_back(std::make_pair(Tmp2, IntPtrTy));
01968         Args.push_back(std::make_pair(Tmp3, IntPtrTy));
01969         Args.push_back(std::make_pair(Tmp4, IntPtrTy));
01970         FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
01971       } else {
01972         assert(0 && "Unknown op!");
01973       }
01974 
01975       std::pair<SDOperand,SDOperand> CallResult =
01976         TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
01977                         DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
01978       Result = CallResult.second;
01979       break;
01980     }
01981     }
01982     break;
01983   }
01984 
01985   case ISD::SHL_PARTS:
01986   case ISD::SRA_PARTS:
01987   case ISD::SRL_PARTS: {
01988     std::vector<SDOperand> Ops;
01989     bool Changed = false;
01990     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
01991       Ops.push_back(LegalizeOp(Node->getOperand(i)));
01992       Changed |= Ops.back() != Node->getOperand(i);
01993     }
01994     if (Changed)
01995       Result = DAG.UpdateNodeOperands(Result, Ops);
01996 
01997     switch (TLI.getOperationAction(Node->getOpcode(),
01998                                    Node->getValueType(0))) {
01999     default: assert(0 && "This action is not supported yet!");
02000     case TargetLowering::Legal: break;
02001     case TargetLowering::Custom:
02002       Tmp1 = TLI.LowerOperation(Result, DAG);
02003       if (Tmp1.Val) {
02004         SDOperand Tmp2, RetVal(0, 0);
02005         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
02006           Tmp2 = LegalizeOp(Tmp1.getValue(i));
02007           AddLegalizedOperand(SDOperand(Node, i), Tmp2);
02008           if (i == Op.ResNo)
02009             RetVal = Tmp2;
02010         }
02011         assert(RetVal.Val && "Illegal result number");
02012         return RetVal;
02013       }
02014       break;
02015     }
02016 
02017     // Since these produce multiple values, make sure to remember that we
02018     // legalized all of them.
02019     for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
02020       AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
02021     return Result.getValue(Op.ResNo);
02022   }
02023 
02024     // Binary operators
02025   case ISD::ADD:
02026   case ISD::SUB:
02027   case ISD::MUL:
02028   case ISD::MULHS:
02029   case ISD::MULHU:
02030   case ISD::UDIV:
02031   case ISD::SDIV:
02032   case ISD::AND:
02033   case ISD::OR:
02034   case ISD::XOR:
02035   case ISD::SHL:
02036   case ISD::SRL:
02037   case ISD::SRA:
02038   case ISD::FADD:
02039   case ISD::FSUB:
02040   case ISD::FMUL:
02041   case ISD::FDIV:
02042     Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
02043     switch (getTypeAction(Node->getOperand(1).getValueType())) {
02044     case Expand: assert(0 && "Not possible");
02045     case Legal:
02046       Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
02047       break;
02048     case Promote:
02049       Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the RHS.
02050       break;
02051     }
02052     
02053     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
02054       
02055     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
02056     default: assert(0 && "BinOp legalize operation not supported");
02057     case TargetLowering::Legal: break;
02058     case TargetLowering::Custom:
02059       Tmp1 = TLI.LowerOperation(Result, DAG);
02060       if (Tmp1.Val) Result = Tmp1;
02061       break;
02062     case TargetLowering::Expand: {
02063       assert(MVT::isVector(Node->getValueType(0)) &&
02064              "Cannot expand this binary operator!");
02065       // Expand the operation into a bunch of nasty scalar code.
02066       std::vector<SDOperand> Ops;
02067       MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
02068       MVT::ValueType PtrVT = TLI.getPointerTy();
02069       for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
02070            i != e; ++i) {
02071         SDOperand Idx = DAG.getConstant(i, PtrVT);
02072         SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
02073         SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
02074         Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
02075       }
02076       Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
02077       break;
02078     }
02079     case TargetLowering::Promote: {
02080       switch (Node->getOpcode()) {
02081       default:  assert(0 && "Do not know how to promote this BinOp!");
02082       case ISD::AND:
02083       case ISD::OR:
02084       case ISD::XOR: {
02085         MVT::ValueType OVT = Node->getValueType(0);
02086         MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
02087         assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
02088         // Bit convert each of the values to the new type.
02089         Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
02090         Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
02091         Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
02092         // Bit convert the result back the original type.
02093         Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
02094         break;
02095       }
02096       }
02097     }
02098     }
02099     break;
02100     
02101   case ISD::FCOPYSIGN:  // FCOPYSIGN does not require LHS/RHS to match type!
02102     Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
02103     switch (getTypeAction(Node->getOperand(1).getValueType())) {
02104       case Expand: assert(0 && "Not possible");
02105       case Legal:
02106         Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
02107         break;
02108       case Promote:
02109         Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the RHS.
02110         break;
02111     }
02112       
02113     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
02114     
02115     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
02116     default: assert(0 && "Operation not supported");
02117     case TargetLowering::Custom:
02118       Tmp1 = TLI.LowerOperation(Result, DAG);
02119       if (Tmp1.Val) Result = Tmp1;
02120       break;
02121     case TargetLowering::Legal: break;
02122     case TargetLowering::Expand:
02123       // If this target supports fabs/fneg natively, do this efficiently.
02124       if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
02125           TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
02126         // Get the sign bit of the RHS.
02127         MVT::ValueType IVT = 
02128           Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
02129         SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
02130         SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
02131                                SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
02132         // Get the absolute value of the result.
02133         SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
02134         // Select between the nabs and abs value based on the sign bit of
02135         // the input.
02136         Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
02137                              DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 
02138                                          AbsVal),
02139                              AbsVal);
02140         Result = LegalizeOp(Result);
02141         break;
02142       }
02143       
02144       // Otherwise, do bitwise ops!
02145       
02146       // copysign -> copysignf/copysign libcall.
02147       const char *FnName;
02148       if (Node->getValueType(0) == MVT::f32) {
02149         FnName = "copysignf";
02150         if (Tmp2.getValueType() != MVT::f32)  // Force operands to match type.
02151           Result = DAG.UpdateNodeOperands(Result, Tmp1, 
02152                                     DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
02153       } else {
02154         FnName = "copysign";
02155         if (Tmp2.getValueType() != MVT::f64)  // Force operands to match type.
02156           Result = DAG.UpdateNodeOperands(Result, Tmp1, 
02157                                    DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
02158       }
02159       SDOperand Dummy;
02160       Result = ExpandLibCall(FnName, Node, Dummy);
02161       break;
02162     }
02163     break;
02164     
02165   case ISD::ADDC:
02166   case ISD::SUBC:
02167     Tmp1 = LegalizeOp(Node->getOperand(0));
02168     Tmp2 = LegalizeOp(Node->getOperand(1));
02169     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
02170     // Since this produces two values, make sure to remember that we legalized
02171     // both of them.
02172     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
02173     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
02174     return Result;
02175 
02176   case ISD::ADDE:
02177   case ISD::SUBE:
02178     Tmp1 = LegalizeOp(Node->getOperand(0));
02179     Tmp2 = LegalizeOp(Node->getOperand(1));
02180     Tmp3 = LegalizeOp(Node->getOperand(2));
02181     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
02182     // Since this produces two values, make sure to remember that we legalized
02183     // both of them.
02184     AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
02185     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
02186     return Result;
02187     
02188   case ISD::BUILD_PAIR: {
02189     MVT::ValueType PairTy = Node->getValueType(0);
02190     // TODO: handle the case where the Lo and Hi operands are not of legal type
02191     Tmp1 = LegalizeOp(Node->getOperand(0));   // Lo
02192     Tmp2 = LegalizeOp(Node->getOperand(1));   // Hi
02193     switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
02194     case TargetLowering::Promote:
02195     case TargetLowering::Custom:
02196       assert(0 && "Cannot promote/custom this yet!");
02197     case TargetLowering::Legal:
02198       if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
02199         Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
02200       break;
02201     case TargetLowering::Expand:
02202       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
02203       Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
02204       Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
02205                          DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 
02206                                          TLI.getShiftAmountTy()));
02207       Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
02208       break;
02209     }
02210     break;
02211   }
02212 
02213   case ISD::UREM:
02214   case ISD::SREM:
02215   case ISD::FREM:
02216     Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
02217     Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
02218 
02219     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
02220     case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
02221     case TargetLowering::Custom:
02222       isCustom = true;
02223       // FALLTHROUGH
02224     case TargetLowering::Legal:
02225       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
02226       if (isCustom) {
02227         Tmp1 = TLI.LowerOperation(Result, DAG);
02228         if (Tmp1.Val) Result = Tmp1;
02229       }
02230       break;
02231     case TargetLowering::Expand:
02232       if (MVT::isInteger(Node->getValueType(0))) {
02233         // X % Y -> X-X/Y*Y
02234         MVT::ValueType VT = Node->getValueType(0);
02235         unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
02236         Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
02237         Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
02238         Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
02239       } else {
02240         // Floating point mod -> fmod libcall.
02241         const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
02242         SDOperand Dummy;
02243         Result = ExpandLibCall(FnName, Node, Dummy);
02244       }
02245       break;
02246     }
02247     break;
02248   case ISD::VAARG: {
02249     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
02250     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
02251 
02252     MVT::ValueType VT = Node->getValueType(0);
02253     switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
02254     default: assert(0 && "This action is not supported yet!");
02255     case TargetLowering::Custom:
02256       isCustom = true;
02257       // FALLTHROUGH
02258     case TargetLowering::Legal:
02259       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
02260       Result = Result.getValue(0);
02261       Tmp1 = Result.getValue(1);
02262 
02263       if (isCustom) {
02264         Tmp2 = TLI.LowerOperation(Result, DAG);
02265         if (Tmp2.Val) {
02266           Result = LegalizeOp(Tmp2);
02267           Tmp1 = LegalizeOp(Tmp2.getValue(1));
02268         }
02269       }
02270       break;
02271     case TargetLowering::Expand: {
02272       SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
02273                                      Node->getOperand(2));
02274       // Increment the pointer, VAList, to the next vaarg
02275       Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 
02276                          DAG.getConstant(MVT::getSizeInBits(VT)/8, 
02277                                          TLI.getPointerTy()));
02278       // Store the incremented VAList to the legalized pointer
02279       Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 
02280                          Node->getOperand(2));
02281       // Load the actual argument out of the pointer VAList
02282       Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
02283       Tmp1 = LegalizeOp(Result.getValue(1));
02284       Result = LegalizeOp(Result);
02285       break;
02286     }
02287     }
02288     // Since VAARG produces two values, make sure to remember that we 
02289     // legalized both of them.
02290     AddLegalizedOperand(SDOperand(Node, 0), Result);
02291     AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
02292     return Op.ResNo ? Tmp1 : Result;
02293   }
02294     
02295   case ISD::VACOPY: 
02296     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
02297     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the dest pointer.
02298     Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the source pointer.
02299 
02300     switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
02301     default: assert(0 && "This action is not supported yet!");
02302     case TargetLowering::Custom:
02303       isCustom = true;
02304       // FALLTHROUGH
02305     case TargetLowering::Legal:
02306       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
02307                                       Node->getOperand(3), Node->getOperand(4));
02308       if (isCustom) {
02309         Tmp1 = TLI.LowerOperation(Result, DAG);
02310         if (Tmp1.Val) Result = Tmp1;
02311       }
02312       break;
02313     case TargetLowering::Expand:
02314       // This defaults to loading a pointer from the input and storing it to the
02315       // output, returning the chain.
02316       Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
02317       Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
02318                            Node->getOperand(4));
02319       break;
02320     }
02321     break;
02322 
02323   case ISD::VAEND: 
02324     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
02325     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
02326 
02327     switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
02328     default: assert(0 && "This action is not supported yet!");
02329     case TargetLowering::Custom:
02330       isCustom = true;
02331       // FALLTHROUGH
02332     case TargetLowering::Legal:
02333       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
02334       if (isCustom) {
02335         Tmp1 = TLI.LowerOperation(Tmp1, DAG);
02336         if (Tmp1.Val) Result = Tmp1;
02337       }
02338       break;
02339     case TargetLowering::Expand:
02340       Result = Tmp1; // Default to a no-op, return the chain
02341       break;
02342     }
02343     break;
02344     
02345   case ISD::VASTART: 
02346     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
02347     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
02348 
02349     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
02350     
02351     switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
02352     default: assert(0 && "This action is not supported yet!");
02353     case TargetLowering::Legal: break;
02354     case TargetLowering::Custom:
02355       Tmp1 = TLI.LowerOperation(Result, DAG);
02356       if (Tmp1.Val) Result = Tmp1;
02357       break;
02358     }
02359     break;
02360     
02361   case ISD::ROTL:
02362   case ISD::ROTR:
02363     Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
02364     Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
02365     
02366     assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
02367            "Cannot handle this yet!");
02368     Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
02369     break;
02370     
02371   case ISD::BSWAP:
02372     Tmp1 = LegalizeOp(Node->getOperand(0));   // Op
02373     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
02374     case TargetLowering::Custom:
02375       assert(0 && "Cannot custom legalize this yet!");
02376     case TargetLowering::Legal:
02377       Result = DAG.UpdateNodeOperands(Result, Tmp1);
02378       break;
02379     case TargetLowering::Promote: {
02380       MVT::ValueType OVT = Tmp1.getValueType();
02381       MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
02382       unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
02383 
02384       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
02385       Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
02386       Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
02387                            DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
02388       break;
02389     }
02390     case TargetLowering::Expand:
02391       Result = ExpandBSWAP(Tmp1);
02392       break;
02393     }
02394     break;
02395     
02396   case ISD::CTPOP:
02397   case ISD::CTTZ:
02398   case ISD::CTLZ:
02399     Tmp1 = LegalizeOp(Node->getOperand(0));   // Op
02400     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
02401     case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
02402     case TargetLowering::Legal:
02403       Result = DAG.UpdateNodeOperands(Result, Tmp1);
02404       break;
02405     case TargetLowering::Promote: {
02406       MVT::ValueType OVT = Tmp1.getValueType();
02407       MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
02408 
02409       // Zero extend the argument.
02410       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
02411       // Perform the larger operation, then subtract if needed.
02412       Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
02413       switch (Node->getOpcode()) {
02414       case ISD::CTPOP:
02415         Result = Tmp1;
02416         break;
02417       case ISD::CTTZ:
02418         //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
02419         Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
02420                             DAG.getConstant(getSizeInBits(NVT), NVT),
02421                             ISD::SETEQ);
02422         Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
02423                            DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
02424         break;
02425       case ISD::CTLZ:
02426         // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
02427         Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
02428                              DAG.getConstant(getSizeInBits(NVT) -
02429                                              getSizeInBits(OVT), NVT));
02430         break;
02431       }
02432       break;
02433     }
02434     case TargetLowering::Expand:
02435       Result = ExpandBitCount(Node->getOpcode(), Tmp1);
02436       break;
02437     }
02438     break;
02439 
02440     // Unary operators
02441   case ISD::FABS:
02442   case ISD::FNEG:
02443   case ISD::FSQRT:
02444   case ISD::FSIN:
02445   case ISD::FCOS:
02446     Tmp1 = LegalizeOp(Node->getOperand(0));
02447     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
02448     case TargetLowering::Promote:
02449     case TargetLowering::Custom:
02450      isCustom = true;
02451      // FALLTHROUGH
02452     case TargetLowering::Legal:
02453       Result = DAG.UpdateNodeOperands(Result, Tmp1);
02454       if (isCustom) {
02455         Tmp1 = TLI.LowerOperation(Result, DAG);
02456         if (Tmp1.Val) Result = Tmp1;
02457       }
02458       break;
02459     case TargetLowering::Expand:
02460       switch (Node->getOpcode()) {
02461       default: assert(0 && "Unreachable!");
02462       case ISD::FNEG:
02463         // Expand Y = FNEG(X) ->  Y = SUB -0.0, X
02464         Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
02465         Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
02466         break;
02467       case ISD::FABS: {
02468         // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
02469         MVT::ValueType VT = Node->getValueType(0);
02470         Tmp2 = DAG.getConstantFP(0.0, VT);
02471         Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
02472         Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
02473         Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
02474         break;
02475       }
02476       case ISD::FSQRT:
02477       case ISD::FSIN:
02478       case ISD::FCOS: {
02479         MVT::ValueType VT = Node->getValueType(0);
02480         const char *FnName = 0;
02481         switch(Node->getOpcode()) {
02482         case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
02483         case ISD::FSIN:  FnName = VT == MVT::f32 ? "sinf"  : "sin"; break;
02484         case ISD::FCOS:  FnName = VT == MVT::f32 ? "cosf"  : "cos"; break;
02485         default: assert(0 && "Unreachable!");
02486         }
02487         SDOperand Dummy;
02488         Result = ExpandLibCall(FnName, Node, Dummy);
02489         break;
02490       }
02491       }
02492       break;
02493     }
02494     break;
02495     
02496   case ISD::BIT_CONVERT:
02497     if (!isTypeLegal(Node->getOperand(0).getValueType())) {
02498       Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
02499     } else {
02500       switch (TLI.getOperationAction(ISD::BIT_CONVERT,
02501                                      Node->getOperand(0).getValueType())) {
02502       default: assert(0 && "Unknown operation action!");
02503       case TargetLowering::Expand:
02504         Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
02505         break;
02506       case TargetLowering::Legal:
02507         Tmp1 = LegalizeOp(Node->getOperand(0));
02508         Result = DAG.UpdateNodeOperands(Result, Tmp1);
02509         break;
02510       }
02511     }
02512     break;
02513   case ISD::VBIT_CONVERT: {
02514     assert(Op.getOperand(0).getValueType() == MVT::Vector &&
02515            "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
02516     
02517     // The input has to be a vector type, we have to either scalarize it, pack
02518     // it, or convert it based on whether the input vector type is legal.
02519     SDNode *InVal = Node->getOperand(0).Val;
02520     unsigned NumElems =
02521       cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
02522     MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
02523     
02524     // Figure out if there is a Packed type corresponding to this Vector
02525     // type.  If so, convert to the packed type.
02526     MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
02527     if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
02528       // Turn this into a bit convert of the packed input.
02529       Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 
02530                            PackVectorOp(Node->getOperand(0), TVT));
02531       break;
02532     } else if (NumElems == 1) {
02533       // Turn this into a bit convert of the scalar input.
02534       Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 
02535                            PackVectorOp(Node->getOperand(0), EVT));
02536       break;
02537     } else {
02538       // FIXME: UNIMP!  Store then reload
02539       assert(0 && "Cast from unsupported vector type not implemented yet!");
02540     }
02541   }
02542       
02543     // Conversion operators.  The source and destination have different types.
02544   case ISD::SINT_TO_FP:
02545   case ISD::UINT_TO_FP: {
02546     bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
02547     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02548     case Legal:
02549       switch (TLI.getOperationAction(Node->getOpcode(),
02550                                      Node->getOperand(0).getValueType())) {
02551       default: assert(0 && "Unknown operation action!");
02552       case TargetLowering::Custom:
02553         isCustom = true;
02554         // FALLTHROUGH
02555       case TargetLowering::Legal:
02556         Tmp1 = LegalizeOp(Node->getOperand(0));
02557         Result = DAG.UpdateNodeOperands(Result, Tmp1);
02558         if (isCustom) {
02559           Tmp1 = TLI.LowerOperation(Result, DAG);
02560           if (Tmp1.Val) Result = Tmp1;
02561         }
02562         break;
02563       case TargetLowering::Expand:
02564         Result = ExpandLegalINT_TO_FP(isSigned,
02565                                       LegalizeOp(Node->getOperand(0)),
02566                                       Node->getValueType(0));
02567         break;
02568       case TargetLowering::Promote:
02569         Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
02570                                        Node->getValueType(0),
02571                                        isSigned);
02572         break;
02573       }
02574       break;
02575     case Expand:
02576       Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
02577                              Node->getValueType(0), Node->getOperand(0));
02578       break;
02579     case Promote:
02580       Tmp1 = PromoteOp(Node->getOperand(0));
02581       if (isSigned) {
02582         Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
02583                  Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
02584       } else {
02585         Tmp1 = DAG.getZeroExtendInReg(Tmp1,
02586                                       Node->getOperand(0).getValueType());
02587       }
02588       Result = DAG.UpdateNodeOperands(Result, Tmp1);
02589       Result = LegalizeOp(Result);  // The 'op' is not necessarily legal!
02590       break;
02591     }
02592     break;
02593   }
02594   case ISD::TRUNCATE:
02595     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02596     case Legal:
02597       Tmp1 = LegalizeOp(Node->getOperand(0));
02598       Result = DAG.UpdateNodeOperands(Result, Tmp1);
02599       break;
02600     case Expand:
02601       ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
02602 
02603       // Since the result is legal, we should just be able to truncate the low
02604       // part of the source.
02605       Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
02606       break;
02607     case Promote:
02608       Result = PromoteOp(Node->getOperand(0));
02609       Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
02610       break;
02611     }
02612     break;
02613 
02614   case ISD::FP_TO_SINT:
02615   case ISD::FP_TO_UINT:
02616     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02617     case Legal:
02618       Tmp1 = LegalizeOp(Node->getOperand(0));
02619 
02620       switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
02621       default: assert(0 && "Unknown operation action!");
02622       case TargetLowering::Custom:
02623         isCustom = true;
02624         // FALLTHROUGH
02625       case TargetLowering::Legal:
02626         Result = DAG.UpdateNodeOperands(Result, Tmp1);
02627         if (isCustom) {
02628           Tmp1 = TLI.LowerOperation(Result, DAG);
02629           if (Tmp1.Val) Result = Tmp1;
02630         }
02631         break;
02632       case TargetLowering::Promote:
02633         Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
02634                                        Node->getOpcode() == ISD::FP_TO_SINT);
02635         break;
02636       case TargetLowering::Expand:
02637         if (Node->getOpcode() == ISD::FP_TO_UINT) {
02638           SDOperand True, False;
02639           MVT::ValueType VT =  Node->getOperand(0).getValueType();
02640           MVT::ValueType NVT = Node->getValueType(0);
02641           unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
02642           Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
02643           Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
02644                             Node->getOperand(0), Tmp2, ISD::SETLT);
02645           True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
02646           False = DAG.getNode(ISD::FP_TO_SINT, NVT,
02647                               DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
02648                                           Tmp2));
02649           False = DAG.getNode(ISD::XOR, NVT, False, 
02650                               DAG.getConstant(1ULL << ShiftAmt, NVT));
02651           Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
02652           break;
02653         } else {
02654           assert(0 && "Do not know how to expand FP_TO_SINT yet!");
02655         }
02656         break;
02657       }
02658       break;
02659     case Expand:
02660       assert(0 && "Shouldn't need to expand other operators here!");
02661     case Promote:
02662       Tmp1 = PromoteOp(Node->getOperand(0));
02663       Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
02664       Result = LegalizeOp(Result);
02665       break;
02666     }
02667     break;
02668 
02669   case ISD::ANY_EXTEND:
02670   case ISD::ZERO_EXTEND:
02671   case ISD::SIGN_EXTEND:
02672   case ISD::FP_EXTEND:
02673   case ISD::FP_ROUND:
02674     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02675     case Expand: assert(0 && "Shouldn't need to expand other operators here!");
02676     case Legal:
02677       Tmp1 = LegalizeOp(Node->getOperand(0));
02678       Result = DAG.UpdateNodeOperands(Result, Tmp1);
02679       break;
02680     case Promote:
02681       switch (Node->getOpcode()) {
02682       case ISD::ANY_EXTEND:
02683         Tmp1 = PromoteOp(Node->getOperand(0));
02684         Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
02685         break;
02686       case ISD::ZERO_EXTEND:
02687         Result = PromoteOp(Node->getOperand(0));
02688         Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
02689         Result = DAG.getZeroExtendInReg(Result,
02690                                         Node->getOperand(0).getValueType());
02691         break;
02692       case ISD::SIGN_EXTEND:
02693         Result = PromoteOp(Node->getOperand(0));
02694         Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
02695         Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
02696                              Result,
02697                           DAG.getValueType(Node->getOperand(0).getValueType()));
02698         break;
02699       case ISD::FP_EXTEND:
02700         Result = PromoteOp(Node->getOperand(0));
02701         if (Result.getValueType() != Op.getValueType())
02702           // Dynamically dead while we have only 2 FP types.
02703           Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
02704         break;
02705       case ISD::FP_ROUND:
02706         Result = PromoteOp(Node->getOperand(0));
02707         Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
02708         break;
02709       }
02710     }
02711     break;
02712   case ISD::FP_ROUND_INREG:
02713   case ISD::SIGN_EXTEND_INREG: {
02714     Tmp1 = LegalizeOp(Node->getOperand(0));
02715     MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
02716 
02717     // If this operation is not supported, convert it to a shl/shr or load/store
02718     // pair.
02719     switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
02720     default: assert(0 && "This action not supported for this op yet!");
02721     case TargetLowering::Legal:
02722       Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
02723       break;
02724     case TargetLowering::Expand:
02725       // If this is an integer extend and shifts are supported, do that.
02726       if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
02727         // NOTE: we could fall back on load/store here too for targets without
02728         // SAR.  However, it is doubtful that any exist.
02729         unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
02730                             MVT::getSizeInBits(ExtraVT);
02731         SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
02732         Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
02733                              Node->getOperand(0), ShiftCst);
02734         Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
02735                              Result, ShiftCst);
02736       } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
02737         // The only way we can lower this is to turn it into a STORETRUNC,
02738         // EXTLOAD pair, targetting a temporary location (a stack slot).
02739 
02740         // NOTE: there is a choice here between constantly creating new stack
02741         // slots and always reusing the same one.  We currently always create
02742         // new ones, as reuse may inhibit scheduling.
02743         const Type *Ty = MVT::getTypeForValueType(ExtraVT);
02744         unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
02745         unsigned Align  = TLI.getTargetData().getTypeAlignment(Ty);
02746         MachineFunction &MF = DAG.getMachineFunction();
02747         int SSFI =
02748           MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
02749         SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
02750         Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
02751                              Node->getOperand(0), StackSlot,
02752                              DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
02753         Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
02754                                 Result, StackSlot, DAG.getSrcValue(NULL),
02755                                 ExtraVT);
02756       } else {
02757         assert(0 && "Unknown op");
02758       }
02759       break;
02760     }
02761     break;
02762   }
02763   }
02764   
02765   assert(Result.getValueType() == Op.getValueType() &&
02766          "Bad legalization!");
02767   
02768   // Make sure that the generated code is itself legal.
02769   if (Result != Op)
02770     Result = LegalizeOp(Result);
02771 
02772   // Note that LegalizeOp may be reentered even from single-use nodes, which
02773   // means that we always must cache transformed nodes.
02774   AddLegalizedOperand(Op, Result);
02775   return Result;
02776 }
02777 
02778 /// PromoteOp - Given an operation that produces a value in an invalid type,
02779 /// promote it to compute the value into a larger type.  The produced value will
02780 /// have the correct bits for the low portion of the register, but no guarantee
02781 /// is made about the top bits: it may be zero, sign-extended, or garbage.
02782 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
02783   MVT::ValueType VT = Op.getValueType();
02784   MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
02785   assert(getTypeAction(VT) == Promote &&
02786          "Caller should expand or legalize operands that are not promotable!");
02787   assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
02788          "Cannot promote to smaller type!");
02789 
02790   SDOperand Tmp1, Tmp2, Tmp3;
02791   SDOperand Result;
02792   SDNode *Node = Op.Val;
02793 
02794   std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
02795   if (I != PromotedNodes.end()) return I->second;
02796 
02797   switch (Node->getOpcode()) {
02798   case ISD::CopyFromReg:
02799     assert(0 && "CopyFromReg must be legal!");
02800   default:
02801     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
02802     assert(0 && "Do not know how to promote this operator!");
02803     abort();
02804   case ISD::UNDEF:
02805     Result = DAG.getNode(ISD::UNDEF, NVT);
02806     break;
02807   case ISD::Constant:
02808     if (VT != MVT::i1)
02809       Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
02810     else
02811       Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
02812     assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
02813     break;
02814   case ISD::ConstantFP:
02815     Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
02816     assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
02817     break;
02818 
02819   case ISD::SETCC:
02820     assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
02821     Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
02822                          Node->getOperand(1), Node->getOperand(2));
02823     break;
02824     
02825   case ISD::TRUNCATE:
02826     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02827     case Legal:
02828       Result = LegalizeOp(Node->getOperand(0));
02829       assert(Result.getValueType() >= NVT &&
02830              "This truncation doesn't make sense!");
02831       if (Result.getValueType() > NVT)    // Truncate to NVT instead of VT
02832         Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
02833       break;
02834     case Promote:
02835       // The truncation is not required, because we don't guarantee anything
02836       // about high bits anyway.
02837       Result = PromoteOp(Node->getOperand(0));
02838       break;
02839     case Expand:
02840       ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
02841       // Truncate the low part of the expanded value to the result type
02842       Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
02843     }
02844     break;
02845   case ISD::SIGN_EXTEND:
02846   case ISD::ZERO_EXTEND:
02847   case ISD::ANY_EXTEND:
02848     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02849     case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
02850     case Legal:
02851       // Input is legal?  Just do extend all the way to the larger type.
02852       Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
02853       break;
02854     case Promote:
02855       // Promote the reg if it's smaller.
02856       Result = PromoteOp(Node->getOperand(0));
02857       // The high bits are not guaranteed to be anything.  Insert an extend.
02858       if (Node->getOpcode() == ISD::SIGN_EXTEND)
02859         Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
02860                          DAG.getValueType(Node->getOperand(0).getValueType()));
02861       else if (Node->getOpcode() == ISD::ZERO_EXTEND)
02862         Result = DAG.getZeroExtendInReg(Result,
02863                                         Node->getOperand(0).getValueType());
02864       break;
02865     }
02866     break;
02867   case ISD::BIT_CONVERT:
02868     Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
02869     Result = PromoteOp(Result);
02870     break;
02871     
02872   case ISD::FP_EXTEND:
02873     assert(0 && "Case not implemented.  Dynamically dead with 2 FP types!");
02874   case ISD::FP_ROUND:
02875     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02876     case Expand: assert(0 && "BUG: Cannot expand FP regs!");
02877     case Promote:  assert(0 && "Unreachable with 2 FP types!");
02878     case Legal:
02879       // Input is legal?  Do an FP_ROUND_INREG.
02880       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
02881                            DAG.getValueType(VT));
02882       break;
02883     }
02884     break;
02885 
02886   case ISD::SINT_TO_FP:
02887   case ISD::UINT_TO_FP:
02888     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02889     case Legal:
02890       // No extra round required here.
02891       Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
02892       break;
02893 
02894     case Promote:
02895       Result = PromoteOp(Node->getOperand(0));
02896       if (Node->getOpcode() == ISD::SINT_TO_FP)
02897         Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
02898                              Result,
02899                          DAG.getValueType(Node->getOperand(0).getValueType()));
02900       else
02901         Result = DAG.getZeroExtendInReg(Result,
02902                                         Node->getOperand(0).getValueType());
02903       // No extra round required here.
02904       Result = DAG.getNode(Node->getOpcode(), NVT, Result);
02905       break;
02906     case Expand:
02907       Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
02908                              Node->getOperand(0));
02909       // Round if we cannot tolerate excess precision.
02910       if (NoExcessFPPrecision)
02911         Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
02912                              DAG.getValueType(VT));
02913       break;
02914     }
02915     break;
02916 
02917   case ISD::SIGN_EXTEND_INREG:
02918     Result = PromoteOp(Node->getOperand(0));
02919     Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 
02920                          Node->getOperand(1));
02921     break;
02922   case ISD::FP_TO_SINT:
02923   case ISD::FP_TO_UINT:
02924     switch (getTypeAction(Node->getOperand(0).getValueType())) {
02925     case Legal:
02926       Tmp1 = Node->getOperand(0);
02927       break;
02928     case Promote:
02929       // The input result is prerounded, so we don't have to do anything
02930       // special.
02931       Tmp1 = PromoteOp(Node->getOperand(0));
02932       break;
02933     case Expand:
02934       assert(0 && "not implemented");
02935     }
02936     // If we're promoting a UINT to a larger size, check to see if the new node
02937     // will be legal.  If it isn't, check to see if FP_TO_SINT is legal, since
02938     // we can use that instead.  This allows us to generate better code for
02939     // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
02940     // legal, such as PowerPC.
02941     if (Node->getOpcode() == ISD::FP_TO_UINT && 
02942         !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
02943         (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
02944          TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
02945       Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
02946     } else {
02947       Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
02948     }
02949     break;
02950 
02951   case ISD::FABS:
02952   case ISD::FNEG:
02953     Tmp1 = PromoteOp(Node->getOperand(0));
02954     assert(Tmp1.getValueType() == NVT);
02955     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
02956     // NOTE: we do not have to do any extra rounding here for
02957     // NoExcessFPPrecision, because we know the input will have the appropriate
02958     // precision, and these operations don't modify precision at all.
02959     break;
02960 
02961   case ISD::FSQRT:
02962   case ISD::FSIN:
02963   case ISD::FCOS:
02964     Tmp1 = PromoteOp(Node->getOperand(0));
02965     assert(Tmp1.getValueType() == NVT);
02966     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
02967     if (NoExcessFPPrecision)
02968       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
02969                            DAG.getValueType(VT));
02970     break;
02971 
02972   case ISD::AND:
02973   case ISD::OR:
02974   case ISD::XOR:
02975     // The input may have strange things in the top bits of the registers, but
02976     // these operations don't care.  They may have weird bits going out, but
02977     // that too is okay if they are integer operations.
02978     Tmp1 = PromoteOp(Node->getOperand(0));
02979     Tmp2 = PromoteOp(Node->getOperand(1));
02980     assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
02981     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
02982     break;
02983   case ISD::ADD:
02984   case ISD::SUB:
02985   case ISD::MUL:
02986     // The input may have strange things in the top bits of the registers, but
02987     // these operations don't care.  They may have weird bits going out, but
02988     // that too is okay if they are integer operations.
02989     Tmp1 = PromoteOp(Node->getOperand(0));
02990     Tmp2 = PromoteOp(Node->getOperand(1));
02991     assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
02992     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
02993     break;
02994   case ISD::FADD:
02995   case ISD::FSUB:
02996   case ISD::FMUL:
02997     Tmp1 = PromoteOp(Node->getOperand(0));
02998     Tmp2 = PromoteOp(Node->getOperand(1));
02999     assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
03000     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
03001     
03002     // Floating point operations will give excess precision that we may not be
03003     // able to tolerate.  If we DO allow excess precision, just leave it,
03004     // otherwise excise it.
03005     // FIXME: Why would we need to round FP ops more than integer ones?
03006     //     Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
03007     if (NoExcessFPPrecision)
03008       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
03009                            DAG.getValueType(VT));
03010     break;
03011 
03012   case ISD::SDIV:
03013   case ISD::SREM:
03014     // These operators require that their input be sign extended.
03015     Tmp1 = PromoteOp(Node->getOperand(0));
03016     Tmp2 = PromoteOp(Node->getOperand(1));
03017     if (MVT::isInteger(NVT)) {
03018       Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
03019                          DAG.getValueType(VT));
03020       Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
03021                          DAG.getValueType(VT));
03022     }
03023     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
03024 
03025     // Perform FP_ROUND: this is probably overly pessimistic.
03026     if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
03027       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
03028                            DAG.getValueType(VT));
03029     break;
03030   case ISD::FDIV:
03031   case ISD::FREM:
03032   case ISD::FCOPYSIGN:
03033     // These operators require that their input be fp extended.
03034     Tmp1 = PromoteOp(Node->getOperand(0));
03035     Tmp2 = PromoteOp(Node->getOperand(1));
03036     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
03037     
03038     // Perform FP_ROUND: this is probably overly pessimistic.
03039     if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
03040       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
03041                            DAG.getValueType(VT));
03042     break;
03043 
03044   case ISD::UDIV:
03045   case ISD::UREM:
03046     // These operators require that their input be zero extended.
03047     Tmp1 = PromoteOp(Node->getOperand(0));
03048     Tmp2 = PromoteOp(Node->getOperand(1));
03049     assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
03050     Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
03051     Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
03052     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
03053     break;
03054 
03055   case ISD::SHL:
03056     Tmp1 = PromoteOp(Node->getOperand(0));
03057     Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
03058     break;
03059   case ISD::SRA:
03060     // The input value must be properly sign extended.
03061     Tmp1 = PromoteOp(Node->getOperand(0));
03062     Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
03063                        DAG.getValueType(VT));
03064     Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
03065     break;
03066   case ISD::SRL:
03067     // The input value must be properly zero extended.
03068     Tmp1 = PromoteOp(Node->getOperand(0));
03069     Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
03070     Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
03071     break;
03072 
03073   case ISD::VAARG:
03074     Tmp1 = Node->getOperand(0);   // Get the chain.
03075     Tmp2 = Node->getOperand(1);   // Get the pointer.
03076     if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
03077       Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
03078       Result = TLI.CustomPromoteOperation(Tmp3, DAG);
03079     } else {
03080       SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
03081                                      Node->getOperand(2));
03082       // Increment the pointer, VAList, to the next vaarg
03083       Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 
03084                          DAG.getConstant(MVT::getSizeInBits(VT)/8, 
03085                                          TLI.getPointerTy()));
03086       // Store the incremented VAList to the legalized pointer
03087       Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 
03088                          Node->getOperand(2));
03089       // Load the actual argument out of the pointer VAList
03090       Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
03091                               DAG.getSrcValue(0), VT);
03092     }
03093     // Remember that we legalized the chain.
03094     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
03095     break;
03096 
03097   case ISD::LOAD:
03098     Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
03099                             Node->getOperand(1), Node->getOperand(2), VT);
03100     // Remember that we legalized the chain.
03101     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
03102     break;
03103   case ISD::SEXTLOAD:
03104   case ISD::ZEXTLOAD:
03105   case ISD::EXTLOAD:
03106     Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
03107                             Node->getOperand(1), Node->getOperand(2),
03108                             cast<VTSDNode>(Node->getOperand(3))->getVT());
03109     // Remember that we legalized the chain.
03110     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
03111     break;
03112   case ISD::SELECT:
03113     Tmp2 = PromoteOp(Node->getOperand(1));   // Legalize the op0
03114     Tmp3 = PromoteOp(Node->getOperand(2));   // Legalize the op1
03115     Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
03116     break;
03117   case ISD::SELECT_CC:
03118     Tmp2 = PromoteOp(Node->getOperand(2));   // True
03119     Tmp3 = PromoteOp(Node->getOperand(3));   // False
03120     Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
03121                          Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
03122     break;
03123   case ISD::BSWAP:
03124     Tmp1 = Node->getOperand(0);
03125     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
03126     Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
03127     Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
03128                          DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
03129                                          TLI.getShiftAmountTy()));
03130     break;
03131   case ISD::CTPOP:
03132   case ISD::CTTZ:
03133   case ISD::CTLZ:
03134     // Zero extend the argument
03135     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
03136     // Perform the larger operation, then subtract if needed.
03137     Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
03138     switch(Node->getOpcode()) {
03139     case ISD::CTPOP:
03140       Result = Tmp1;
03141       break;
03142     case ISD::CTTZ:
03143       // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
03144       Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
03145                           DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
03146       Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
03147                            DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
03148       break;
03149     case ISD::CTLZ:
03150       //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
03151       Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
03152                            DAG.getConstant(getSizeInBits(NVT) -
03153                                            getSizeInBits(VT), NVT));
03154       break;
03155     }
03156     break;
03157   case ISD::VEXTRACT_VECTOR_ELT:
03158     Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
03159     break;
03160   case ISD::EXTRACT_VECTOR_ELT:
03161     Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
03162     break;
03163   }
03164 
03165   assert(Result.Val && "Didn't set a result!");
03166 
03167   // Make sure the result is itself legal.
03168   Result = LegalizeOp(Result);
03169   
03170   // Remember that we promoted this!
03171   AddPromotedOperand(Op, Result);
03172   return Result;
03173 }
03174 
03175 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
03176 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
03177 /// on the vector type.  The return type of this matches the element type of the
03178 /// vector, which may not be legal for the target.
03179 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
03180   // We know that operand #0 is the Vec vector.  If the index is a constant
03181   // or if the invec is a supported hardware type, we can use it.  Otherwise,
03182   // lower to a store then an indexed load.
03183   SDOperand Vec = Op.getOperand(0);
03184   SDOperand Idx = LegalizeOp(Op.getOperand(1));
03185   
03186   SDNode *InVal = Vec.Val;
03187   unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
03188   MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
03189   
03190   // Figure out if there is a Packed type corresponding to this Vector
03191   // type.  If so, convert to the packed type.
03192   MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
03193   if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
03194     // Turn this into a packed extract_vector_elt operation.
03195     Vec = PackVectorOp(Vec, TVT);
03196     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
03197   } else if (NumElems == 1) {
03198     // This must be an access of the only element.  Return it.
03199     return PackVectorOp(Vec, EVT);
03200   } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
03201     SDOperand Lo, Hi;
03202     SplitVectorOp(Vec, Lo, Hi);
03203     if (CIdx->getValue() < NumElems/2) {
03204       Vec = Lo;
03205     } else {
03206       Vec = Hi;
03207       Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
03208     }
03209     
03210     // It's now an extract from the appropriate high or low part.  Recurse.
03211     Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
03212     return LowerVEXTRACT_VECTOR_ELT(Op);
03213   } else {
03214     // Variable index case for extract element.
03215     // FIXME: IMPLEMENT STORE/LOAD lowering.  Need alignment of stack slot!!
03216     assert(0 && "unimp!");
03217     return SDOperand();
03218   }
03219 }
03220 
03221 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
03222 /// memory traffic.
03223 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
03224   SDOperand Vector = Op.getOperand(0);
03225   SDOperand Idx    = Op.getOperand(1);
03226   
03227   // If the target doesn't support this, store the value to a temporary
03228   // stack slot, then LOAD the scalar element back out.
03229   SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
03230   SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
03231                              Vector, StackPtr, DAG.getSrcValue(NULL));
03232   
03233   // Add the offset to the index.
03234   unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
03235   Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
03236                     DAG.getConstant(EltSize, Idx.getValueType()));
03237   StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
03238   
03239   return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
03240 }
03241 
03242 
03243 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
03244 /// with condition CC on the current target.  This usually involves legalizing
03245 /// or promoting the arguments.  In the case where LHS and RHS must be expanded,
03246 /// there may be no choice but to create a new SetCC node to represent the
03247 /// legalized value of setcc lhs, rhs.  In this case, the value is returned in
03248 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
03249 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
03250                                                  SDOperand &RHS,
03251                                                  SDOperand &CC) {
03252   SDOperand Tmp1, Tmp2, Result;    
03253   
03254   switch (getTypeAction(LHS.getValueType())) {
03255   case Legal:
03256     Tmp1 = LegalizeOp(LHS);   // LHS
03257     Tmp2 = LegalizeOp(RHS);   // RHS
03258     break;
03259   case Promote:
03260     Tmp1 = PromoteOp(LHS);   // LHS
03261     Tmp2 = PromoteOp(RHS);   // RHS
03262 
03263     // If this is an FP compare, the operands have already been extended.
03264     if (MVT::isInteger(LHS.getValueType())) {
03265       MVT::ValueType VT = LHS.getValueType();
03266       MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
03267 
03268       // Otherwise, we have to insert explicit sign or zero extends.  Note
03269       // that we could insert sign extends for ALL conditions, but zero extend
03270       // is cheaper on many machines (an AND instead of two shifts), so prefer
03271       // it.
03272       switch (cast<CondCodeSDNode>(CC)->get()) {
03273       default: assert(0 && "Unknown integer comparison!");
03274       case ISD::SETEQ:
03275       case ISD::SETNE:
03276       case ISD::SETUGE:
03277       case ISD::SETUGT:
03278       case ISD::SETULE:
03279       case ISD::SETULT:
03280         // ALL of these operations will work if we either sign or zero extend
03281         // the operands (including the unsigned comparisons!).  Zero extend is
03282         // usually a simpler/cheaper operation, so prefer it.
03283         Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
03284         Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
03285         break;
03286       case ISD::SETGE:
03287       case ISD::SETGT:
03288       case ISD::SETLT:
03289       case ISD::SETLE:
03290         Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
03291                            DAG.getValueType(VT));
03292         Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
03293                            DAG.getValueType(VT));
03294         break;
03295       }
03296     }
03297     break;
03298   case Expand:
03299     SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
03300     ExpandOp(LHS, LHSLo, LHSHi);
03301     ExpandOp(RHS, RHSLo, RHSHi);
03302     switch (cast<CondCodeSDNode>(CC)->get()) {
03303     case ISD::SETEQ:
03304     case ISD::SETNE:
03305       if (RHSLo == RHSHi)
03306         if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
03307           if (RHSCST->isAllOnesValue()) {
03308             // Comparison to -1.
03309             Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
03310             Tmp2 = RHSLo;
03311             break;
03312           }
03313 
03314       Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
03315       Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
03316       Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
03317       Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
03318       break;
03319     default:
03320       // If this is a comparison of the sign bit, just look at the top part.
03321       // X > -1,  x < 0
03322       if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
03323         if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 
03324              CST->getValue() == 0) ||             // X < 0
03325             (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
03326              CST->isAllOnesValue())) {            // X > -1
03327           Tmp1 = LHSHi;
03328           Tmp2 = RHSHi;
03329           break;
03330         }
03331 
03332       // FIXME: This generated code sucks.
03333       ISD::CondCode LowCC;
03334       switch (cast<CondCodeSDNode>(CC)->get()) {
03335       default: assert(0 && "Unknown integer setcc!");
03336       case ISD::SETLT:
03337       case ISD::SETULT: LowCC = ISD::SETULT; break;
03338       case ISD::SETGT:
03339       case ISD::SETUGT: LowCC = ISD::SETUGT; break;
03340       case ISD::SETLE:
03341       case ISD::SETULE: LowCC = ISD::SETULE; break;
03342       case ISD::SETGE:
03343       case ISD::SETUGE: LowCC = ISD::SETUGE; break;
03344       }
03345 
03346       // Tmp1 = lo(op1) < lo(op2)   // Always unsigned comparison
03347       // Tmp2 = hi(op1) < hi(op2)   // Signedness depends on operands
03348       // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
03349 
03350       // NOTE: on targets without efficient SELECT of bools, we can always use
03351       // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
03352       Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
03353       Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
03354       Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
03355       Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
03356                                       Result, Tmp1, Tmp2));
03357       Tmp1 = Result;
03358       Tmp2 = SDOperand();
03359     }
03360   }
03361   LHS = Tmp1;
03362   RHS = Tmp2;
03363 }
03364 
03365 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
03366 /// The resultant code need not be legal.  Note that SrcOp is the input operand
03367 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
03368 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 
03369                                                   SDOperand SrcOp) {
03370   // Create the stack frame object.
03371   SDOperand FIPtr = CreateStackTemporary(DestVT);
03372   
03373   // Emit a store to the stack slot.
03374   SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
03375                                 SrcOp, FIPtr, DAG.getSrcValue(NULL));
03376   // Result is a load from the stack slot.
03377   return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
03378 }
03379 
03380 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
03381   // Create a vector sized/aligned stack slot, store the value to element #0,
03382   // then load the whole vector back out.
03383   SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
03384   SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
03385                              Node->getOperand(0), StackPtr,
03386                              DAG.getSrcValue(NULL));
03387   return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
03388 }
03389 
03390 
03391 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
03392 /// support the operation, but do support the resultant packed vector type.
03393 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
03394   
03395   // If the only non-undef value is the low element, turn this into a 
03396   // SCALAR_TO_VECTOR node.  If this is { X, X, X, X }, determine X.
03397   unsigned NumElems = Node->getNumOperands();
03398   bool isOnlyLowElement = true;
03399   SDOperand SplatValue = Node->getOperand(0);
03400   std::map<SDOperand, std::vector<unsigned> > Values;
03401   Values[SplatValue].push_back(0);
03402   bool isConstant = true;
03403   if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
03404       SplatValue.getOpcode() != ISD::UNDEF)
03405     isConstant = false;
03406   
03407   for (unsigned i = 1; i < NumElems; ++i) {
03408     SDOperand V = Node->getOperand(i);
03409     std::map<SDOperand, std::vector<unsigned> >::iterator I = Values.find(V);
03410     if (I != Values.end())
03411       I->second.push_back(i);
03412     else
03413       Values[V].push_back(i);
03414     if (V.getOpcode() != ISD::UNDEF)
03415       isOnlyLowElement = false;
03416     if (SplatValue != V)
03417       SplatValue = SDOperand(0,0);
03418 
03419     // If this isn't a constant element or an undef, we can't use a constant
03420     // pool load.
03421     if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
03422         V.getOpcode() != ISD::UNDEF)
03423       isConstant = false;
03424   }
03425   
03426   if (isOnlyLowElement) {
03427     // If the low element is an undef too, then this whole things is an undef.
03428     if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
03429       return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
03430     // Otherwise, turn this into a scalar_to_vector node.
03431     return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
03432                        Node->getOperand(0));
03433   }
03434   
03435   // If all elements are constants, create a load from the constant pool.
03436   if (isConstant) {
03437     MVT::ValueType VT = Node->getValueType(0);
03438     const Type *OpNTy = 
03439       MVT::getTypeForValueType(Node->getOperand(0).getValueType());
03440     std::vector<Constant*> CV;
03441     for (unsigned i = 0, e = NumElems; i != e; ++i) {
03442       if (ConstantFPSDNode *V = 
03443           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
03444         CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
03445       } else if (ConstantSDNode *V = 
03446                  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
03447         CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
03448       } else {
03449         assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
03450         CV.push_back(UndefValue::get(OpNTy));
03451       }
03452     }
03453     Constant *CP = ConstantPacked::get(CV);
03454     SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
03455     return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
03456                        DAG.getSrcValue(NULL));
03457   }
03458   
03459   if (SplatValue.Val) {   // Splat of one value?
03460     // Build the shuffle constant vector: <0, 0, 0, 0>
03461     MVT::ValueType MaskVT = 
03462       MVT::getIntVectorWithNumElements(NumElems);
03463     SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
03464     std::vector<SDOperand> ZeroVec(NumElems, Zero);
03465     SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
03466 
03467     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
03468     if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
03469       // Get the splatted value into the low element of a vector register.
03470       SDOperand LowValVec = 
03471         DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
03472     
03473       // Return shuffle(LowValVec, undef, <0,0,0,0>)
03474       return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
03475                          DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
03476                          SplatMask);
03477     }
03478   }
03479   
03480   // If there are only two unique elements, we may be able to turn this into a
03481   // vector shuffle.
03482   if (Values.size() == 2) {
03483     // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
03484     MVT::ValueType MaskVT = 
03485       MVT::getIntVectorWithNumElements(NumElems);
03486     std::vector<SDOperand> MaskVec(NumElems);
03487     unsigned i = 0;
03488     for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
03489            E = Values.end(); I != E; ++I) {
03490       for (std::vector<unsigned>::iterator II = I->second.begin(),
03491              EE = I->second.end(); II != EE; ++II)
03492         MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
03493       i += NumElems;
03494     }
03495     SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
03496 
03497     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
03498     if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
03499         isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
03500       std::vector<SDOperand> Ops;
03501       for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
03502             E = Values.end(); I != E; ++I) {
03503         SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
03504                                    I->first);
03505         Ops.push_back(Op);
03506       }
03507       Ops.push_back(ShuffleMask);
03508 
03509       // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
03510       return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
03511     }
03512   }
03513   
03514   // Otherwise, we can't handle this case efficiently.  Allocate a sufficiently
03515   // aligned object on the stack, store each element into it, then load
03516   // the result as a vector.
03517   MVT::ValueType VT = Node->getValueType(0);
03518   // Create the stack frame object.
03519   SDOperand FIPtr = CreateStackTemporary(VT);
03520   
03521   // Emit a store of each element to the stack slot.
03522   std::vector<SDOperand> Stores;
03523   unsigned TypeByteSize = 
03524     MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
03525   unsigned VectorSize = MVT::getSizeInBits(VT)/8;
03526   // Store (in the right endianness) the elements to memory.
03527   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
03528     // Ignore undef elements.
03529     if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
03530     
03531     unsigned Offset = TypeByteSize*i;
03532     
03533     SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
03534     Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
03535     
03536     Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
03537                                  Node->getOperand(i), Idx, 
03538                                  DAG.getSrcValue(NULL)));
03539   }
03540   
03541   SDOperand StoreChain;
03542   if (!Stores.empty())    // Not all undef elements?
03543     StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
03544   else
03545     StoreChain = DAG.getEntryNode();
03546   
03547   // Result is a load from the stack slot.
03548   return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
03549 }
03550 
03551 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
03552 /// specified value type.
03553 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
03554   MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
03555   unsigned ByteSize = MVT::getSizeInBits(VT)/8;
03556   int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
03557   return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
03558 }
03559 
03560 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
03561                                             SDOperand Op, SDOperand Amt,
03562                                             SDOperand &Lo, SDOperand &Hi) {
03563   // Expand the subcomponents.
03564   SDOperand LHSL, LHSH;
03565   ExpandOp(Op, LHSL, LHSH);
03566 
03567   std::vector<SDOperand> Ops;
03568   Ops.push_back(LHSL);
03569   Ops.push_back(LHSH);
03570   Ops.push_back(Amt);
03571   std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
03572   Lo = DAG.getNode(NodeOp, VTs, Ops);
03573   Hi = Lo.getValue(1);
03574 }
03575 
03576 
03577 /// ExpandShift - Try to find a clever way to expand this shift operation out to
03578 /// smaller elements.  If we can't find a way that is more efficient than a
03579 /// libcall on this target, return false.  Otherwise, return true with the
03580 /// low-parts expanded into Lo and Hi.
03581 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
03582                                        SDOperand &Lo, SDOperand &Hi) {
03583   assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
03584          "This is not a shift!");
03585 
03586   MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
03587   SDOperand ShAmt = LegalizeOp(Amt);
03588   MVT::ValueType ShTy = ShAmt.getValueType();
03589   unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
03590   unsigned NVTBits = MVT::getSizeInBits(NVT);
03591 
03592   // Handle the case when Amt is an immediate.  Other cases are currently broken
03593   // and are disabled.
03594   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
03595     unsigned Cst = CN->getValue();
03596     // Expand the incoming operand to be shifted, so that we have its parts
03597     SDOperand InL, InH;
03598     ExpandOp(Op, InL, InH);
03599     switch(Opc) {
03600     case ISD::SHL:
03601       if (Cst > VTBits) {
03602         Lo = DAG.getConstant(0, NVT);
03603         Hi = DAG.getConstant(0, NVT);
03604       } else if (Cst > NVTBits) {
03605         Lo = DAG.getConstant(0, NVT);
03606         Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
03607       } else if (Cst == NVTBits) {
03608         Lo = DAG.getConstant(0, NVT);
03609         Hi = InL;
03610       } else {
03611         Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
03612         Hi = DAG.getNode(ISD::OR, NVT,
03613            DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
03614            DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
03615       }
03616       return true;
03617     case ISD::SRL:
03618       if (Cst > VTBits) {
03619         Lo = DAG.getConstant(0, NVT);
03620         Hi = DAG.getConstant(0, NVT);
03621       } else if (Cst > NVTBits) {
03622         Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
03623         Hi = DAG.getConstant(0, NVT);
03624       } else if (Cst == NVTBits) {
03625         Lo = InH;
03626         Hi = DAG.getConstant(0, NVT);
03627       } else {
03628         Lo = DAG.getNode(ISD::OR, NVT,
03629            DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
03630            DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
03631         Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
03632       }
03633       return true;
03634     case ISD::SRA:
03635       if (Cst > VTBits) {
03636         Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
03637                               DAG.getConstant(NVTBits-1, ShTy));
03638       } else if (Cst > NVTBits) {
03639         Lo = DAG.getNode(ISD::SRA, NVT, InH,
03640                            DAG.getConstant(Cst-NVTBits, ShTy));
03641         Hi = DAG.getNode(ISD::SRA, NVT, InH,
03642                               DAG.getConstant(NVTBits-1, ShTy));
03643       } else if (Cst == NVTBits) {
03644         Lo = InH;
03645         Hi = DAG.getNode(ISD::SRA, NVT, InH,
03646                               DAG.getConstant(NVTBits-1, ShTy));
03647       } else {
03648         Lo = DAG.getNode(ISD::OR, NVT,
03649            DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
03650            DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
03651         Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
03652       }
03653       return true;
03654     }
03655   }
03656   return false;
03657 }
03658 
03659 
03660 // ExpandLibCall - Expand a node into a call to a libcall.  If the result value
03661 // does not fit into a register, return the lo part and set the hi part to the
03662 // by-reg argument.  If it does fit into a single register, return the result
03663 // and leave the Hi part unset.
03664 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
03665                                               SDOperand &Hi) {
03666   assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
03667   // The input chain to this libcall is the entry node of the function. 
03668   // Legalizing the call will automatically add the previous call to the
03669   // dependence.
03670   SDOperand InChain = DAG.getEntryNode();
03671   
03672   TargetLowering::ArgListTy Args;
03673   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
03674     MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
03675     const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
03676     Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
03677   }
03678   SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
03679 
03680   // Splice the libcall in wherever FindInputOutputChains tells us to.
03681   const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
03682   std::pair<SDOperand,SDOperand> CallInfo =
03683     TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
03684                     Callee, Args, DAG);
03685 
03686   // Legalize the call sequence, starting with the chain.  This will advance
03687   // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
03688   // was added by LowerCallTo (guaranteeing proper serialization of calls).
03689   LegalizeOp(CallInfo.second);
03690   SDOperand Result;
03691   switch (getTypeAction(CallInfo.first.getValueType())) {
03692   default: assert(0 && "Unknown thing");
03693   case Legal:
03694     Result = CallInfo.first;
03695     break;
03696   case Expand:
03697     ExpandOp(CallInfo.first, Result, Hi);
03698     break;
03699   }
03700   return Result;
03701 }
03702 
03703 
03704 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
03705 /// destination type is legal.
03706 SDOperand SelectionDAGLegalize::
03707 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
03708   assert(isTypeLegal(DestTy) && "Destination type is not legal!");
03709   assert(getTypeAction(Source.getValueType()) == Expand &&
03710          "This is not an expansion!");
03711   assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
03712 
03713   if (!isSigned) {
03714     assert(Source.getValueType() == MVT::i64 &&
03715            "This only works for 64-bit -> FP");
03716     // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
03717     // incoming integer is set.  To handle this, we dynamically test to see if
03718     // it is set, and, if so, add a fudge factor.
03719     SDOperand Lo, Hi;
03720     ExpandOp(Source, Lo, Hi);
03721 
03722     // If this is unsigned, and not supported, first perform the conversion to
03723     // signed, then adjust the result if the sign bit is set.
03724     SDOperand SignedConv = ExpandIntToFP(true, DestTy,
03725                    DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
03726 
03727     SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
03728                                      DAG.getConstant(0, Hi.getValueType()),
03729                                      ISD::SETLT);
03730     SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
03731     SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
03732                                       SignSet, Four, Zero);
03733     uint64_t FF = 0x5f800000ULL;
03734     if (TLI.isLittleEndian()) FF <<= 32;
03735     static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
03736 
03737     SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
03738     CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
03739     SDOperand FudgeInReg;
03740     if (DestTy == MVT::f32)
03741       FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
03742                                DAG.getSrcValue(NULL));
03743     else {
03744       assert(DestTy == MVT::f64 && "Unexpected conversion");
03745       FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
03746                                   CPIdx, DAG.getSrcValue(NULL), MVT::f32);
03747     }
03748     return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
03749   }
03750 
03751   // Check to see if the target has a custom way to lower this.  If so, use it.
03752   switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
03753   default: assert(0 && "This action not implemented for this operation!");
03754   case TargetLowering::Legal:
03755   case TargetLowering::Expand:
03756     break;   // This case is handled below.
03757   case TargetLowering::Custom: {
03758     SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
03759                                                   Source), DAG);
03760     if (NV.Val)
03761       return LegalizeOp(NV);
03762     break;   // The target decided this was legal after all
03763   }
03764   }
03765 
03766   // Expand the source, then glue it back together for the call.  We must expand
03767   // the source in case it is shared (this pass of legalize must traverse it).
03768   SDOperand SrcLo, SrcHi;
03769   ExpandOp(Source, SrcLo, SrcHi);
03770   Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
03771 
03772   const char *FnName = 0;
03773   if (DestTy == MVT::f32)
03774     FnName = "__floatdisf";
03775   else {
03776     assert(DestTy == MVT::f64 && "Unknown fp value type!");
03777     FnName = "__floatdidf";
03778   }
03779   
03780   Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
03781   SDOperand UnusedHiPart;
03782   return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
03783 }
03784 
03785 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
03786 /// INT_TO_FP operation of the specified operand when the target requests that
03787 /// we expand it.  At this point, we know that the result and operand types are
03788 /// legal for the target.
03789 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
03790                                                      SDOperand Op0,
03791                                                      MVT::ValueType DestVT) {
03792   if (Op0.getValueType() == MVT::i32) {
03793     // simple 32-bit [signed|unsigned] integer to float/double expansion
03794     
03795     // get the stack frame index of a 8 byte buffer
03796     MachineFunction &MF = DAG.getMachineFunction();
03797     int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
03798     // get address of 8 byte buffer
03799     SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
03800     // word offset constant for Hi/Lo address computation
03801     SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
03802     // set up Hi and Lo (into buffer) address based on endian
03803     SDOperand Hi = StackSlot;
03804     SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
03805     if (TLI.isLittleEndian())
03806       std::swap(Hi, Lo);
03807     
03808     // if signed map to unsigned space
03809     SDOperand Op0Mapped;
03810     if (isSigned) {
03811       // constant used to invert sign bit (signed to unsigned mapping)
03812       SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
03813       Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
03814     } else {
03815       Op0Mapped = Op0;
03816     }
03817     // store the lo of the constructed double - based on integer input
03818     SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
03819                                    Op0Mapped, Lo, DAG.getSrcValue(NULL));
03820     // initial hi portion of constructed double
03821     SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
03822     // store the hi of the constructed double - biased exponent
03823     SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
03824                                    InitialHi, Hi, DAG.getSrcValue(NULL));
03825     // load the constructed double
03826     SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
03827                                DAG.getSrcValue(NULL));
03828     // FP constant to bias correct the final result
03829     SDOperand Bias = DAG.getConstantFP(isSigned ?
03830                                             BitsToDouble(0x4330000080000000ULL)
03831                                           : BitsToDouble(0x4330000000000000ULL),
03832                                      MVT::f64);
03833     // subtract the bias
03834     SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
03835     // final result
03836     SDOperand Result;
03837     // handle final rounding
03838     if (DestVT == MVT::f64) {
03839       // do nothing
03840       Result = Sub;
03841     } else {
03842      // if f32 then cast to f32
03843       Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
03844     }
03845     return Result;
03846   }
03847   assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
03848   SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
03849 
03850   SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
03851                                    DAG.getConstant(0, Op0.getValueType()),
03852                                    ISD::SETLT);
03853   SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
03854   SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
03855                                     SignSet, Four, Zero);
03856 
03857   // If the sign bit of the integer is set, the large number will be treated
03858   // as a negative number.  To counteract this, the dynamic code adds an
03859   // offset depending on the data type.
03860   uint64_t FF;
03861   switch (Op0.getValueType()) {
03862   default: assert(0 && "Unsupported integer type!");
03863   case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
03864   case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
03865   case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
03866   case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
03867   }
03868   if (TLI.isLittleEndian()) FF <<= 32;
03869   static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
03870 
03871   SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
03872   CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
03873   SDOperand FudgeInReg;
03874   if (DestVT == MVT::f32)
03875     FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
03876                              DAG.getSrcValue(NULL));
03877   else {
03878     assert(DestVT == MVT::f64 && "Unexpected conversion");
03879     FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
03880                                            DAG.getEntryNode(), CPIdx,
03881                                            DAG.getSrcValue(NULL), MVT::f32));
03882   }
03883 
03884   return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
03885 }
03886 
03887 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
03888 /// *INT_TO_FP operation of the specified operand when the target requests that
03889 /// we promote it.  At this point, we know that the result and operand types are
03890 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
03891 /// operation that takes a larger input.
03892 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
03893                                                       MVT::ValueType DestVT,
03894                                                       bool isSigned) {
03895   // First step, figure out the appropriate *INT_TO_FP operation to use.
03896   MVT::ValueType NewInTy = LegalOp.getValueType();
03897 
03898   unsigned OpToUse = 0;
03899 
03900   // Scan for the appropriate larger type to use.
03901   while (1) {
03902     NewInTy = (MVT::ValueType)(NewInTy+1);
03903     assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
03904 
03905     // If the target supports SINT_TO_FP of this type, use it.
03906     switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
03907       default: break;
03908       case TargetLowering::Legal:
03909         if (!TLI.isTypeLegal(NewInTy))
03910           break;  // Can't use this datatype.
03911         // FALL THROUGH.
03912       case TargetLowering::Custom:
03913         OpToUse = ISD::SINT_TO_FP;
03914         break;
03915     }
03916     if (OpToUse) break;
03917     if (isSigned) continue;
03918 
03919     // If the target supports UINT_TO_FP of this type, use it.
03920     switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
03921       default: break;
03922       case TargetLowering::Legal:
03923         if (!TLI.isTypeLegal(NewInTy))
03924           break;  // Can't use this datatype.
03925         // FALL THROUGH.
03926       case TargetLowering::Custom:
03927         OpToUse = ISD::UINT_TO_FP;
03928         break;
03929     }
03930     if (OpToUse) break;
03931 
03932     // Otherwise, try a larger type.
03933   }
03934 
03935   // Okay, we found the operation and type to use.  Zero extend our input to the
03936   // desired type then run the operation on it.
03937   return DAG.getNode(OpToUse, DestVT,
03938                      DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
03939                                  NewInTy, LegalOp));
03940 }
03941 
03942 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
03943 /// FP_TO_*INT operation of the specified operand when the target requests that
03944 /// we promote it.  At this point, we know that the result and operand types are
03945 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
03946 /// operation that returns a larger result.
03947 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
03948                                                       MVT::ValueType DestVT,
03949                                                       bool isSigned) {
03950   // First step, figure out the appropriate FP_TO*INT operation to use.
03951   MVT::ValueType NewOutTy = DestVT;
03952 
03953   unsigned OpToUse = 0;
03954 
03955   // Scan for the appropriate larger type to use.
03956   while (1) {
03957     NewOutTy = (MVT::ValueType)(NewOutTy+1);
03958     assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
03959 
03960     // If the target supports FP_TO_SINT returning this type, use it.
03961     switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
03962     default: break;
03963     case TargetLowering::Legal:
03964       if (!TLI.isTypeLegal(NewOutTy))
03965         break;  // Can't use this datatype.
03966       // FALL THROUGH.
03967     case TargetLowering::Custom:
03968       OpToUse = ISD::FP_TO_SINT;
03969       break;
03970     }
03971     if (OpToUse) break;
03972 
03973     // If the target supports FP_TO_UINT of this type, use it.
03974     switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
03975     default: break;
03976     case TargetLowering::Legal:
03977       if (!TLI.isTypeLegal(NewOutTy))
03978         break;  // Can't use this datatype.
03979       // FALL THROUGH.
03980     case TargetLowering::Custom:
03981       OpToUse = ISD::FP_TO_UINT;
03982       break;
03983     }
03984     if (OpToUse) break;
03985 
03986     // Otherwise, try a larger type.
03987   }
03988 
03989   // Okay, we found the operation and type to use.  Truncate the result of the
03990   // extended FP_TO_*INT operation to the desired size.
03991   return DAG.getNode(ISD::TRUNCATE, DestVT,
03992                      DAG.getNode(OpToUse, NewOutTy, LegalOp));
03993 }
03994 
03995 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
03996 ///
03997 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
03998   MVT::ValueType VT = Op.getValueType();
03999   MVT::ValueType SHVT = TLI.getShiftAmountTy();
04000   SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
04001   switch (VT) {
04002   default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
04003   case MVT::i16:
04004     Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
04005     Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
04006     return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
04007   case MVT::i32:
04008     Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
04009     Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
04010     Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
04011     Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
04012     Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
04013     Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
04014     Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
04015     Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
04016     return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
04017   case MVT::i64:
04018     Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
04019     Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
04020     Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
04021     Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
04022     Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
04023     Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
04024     Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
04025     Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
04026     Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
04027     Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
04028     Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
04029     Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
04030     Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
04031     Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
04032     Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
04033     Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
04034     Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
04035     Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
04036     Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
04037     Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
04038     return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
04039   }
04040 }
04041 
04042 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
04043 ///
04044 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
04045   switch (Opc) {
04046   default: assert(0 && "Cannot expand this yet!");
04047   case ISD::CTPOP: {
04048     static const uint64_t mask[6] = {
04049       0x5555555555555555ULL, 0x3333333333333333ULL,
04050       0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
04051       0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
04052     };
04053     MVT::ValueType VT = Op.getValueType();
04054     MVT::ValueType ShVT = TLI.getShiftAmountTy();
04055     unsigned len = getSizeInBits(VT);
04056     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
04057       //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
04058       SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
04059       SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
04060       Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
04061                        DAG.getNode(ISD::AND, VT,
04062                                    DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
04063     }
04064     return Op;
04065   }
04066   case ISD::CTLZ: {
04067     // for now, we do this:
04068     // x = x | (x >> 1);
04069     // x = x | (x >> 2);
04070     // ...
04071     // x = x | (x >>16);
04072     // x = x | (x >>32); // for 64-bit input
04073     // return popcount(~x);
04074     //
04075     // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
04076     MVT::ValueType VT = Op.getValueType();
04077     MVT::ValueType ShVT = TLI.getShiftAmountTy();
04078     unsigned len = getSizeInBits(VT);
04079     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
04080       SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
04081       Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
04082     }
04083     Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
04084     return DAG.getNode(ISD::CTPOP, VT, Op);
04085   }
04086   case ISD::CTTZ: {
04087     // for now, we use: { return popcount(~x & (x - 1)); }
04088     // unless the target has ctlz but not ctpop, in which case we use:
04089     // { return 32 - nlz(~x & (x-1)); }
04090     // see also http://www.hackersdelight.org/HDcode/ntz.cc
04091     MVT::ValueType VT = Op.getValueType();
04092     SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
04093     SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
04094                        DAG.getNode(ISD::XOR, VT, Op, Tmp2),
04095                        DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
04096     // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
04097     if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
04098         TLI.isOperationLegal(ISD::CTLZ, VT))
04099       return DAG.getNode(ISD::SUB, VT,
04100                          DAG.getConstant(getSizeInBits(VT), VT),
04101                          DAG.getNode(ISD::CTLZ, VT, Tmp3));
04102     return DAG.getNode(ISD::CTPOP, VT, Tmp3);
04103   }
04104   }
04105 }
04106 
04107 /// ExpandOp - Expand the specified SDOperand into its two component pieces
04108 /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this, the
04109 /// LegalizeNodes map is filled in for any results that are not expanded, the
04110 /// ExpandedNodes map is filled in for any results that are expanded, and the
04111 /// Lo/Hi values are returned.
04112 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
04113   MVT::ValueType VT = Op.getValueType();
04114   MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
04115   SDNode *Node = Op.Val;
04116   assert(getTypeAction(VT) == Expand && "Not an expanded type!");
04117   assert((MVT::isInteger(VT) || VT == MVT::Vector) && 
04118          "Cannot expand FP values!");
04119   assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
04120          "Cannot expand to FP value or to larger int value!");
04121 
04122   // See if we already expanded it.
04123   std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
04124     = ExpandedNodes.find(Op);
04125   if (I != ExpandedNodes.end()) {
04126     Lo = I->second.first;
04127     Hi = I->second.second;
04128     return;
04129   }
04130 
04131   switch (Node->getOpcode()) {
04132   case ISD::CopyFromReg:
04133     assert(0 && "CopyFromReg must be legal!");
04134   default:
04135     std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
04136     assert(0 && "Do not know how to expand this operator!");
04137     abort();
04138   case ISD::UNDEF:
04139     Lo = DAG.getNode(ISD::UNDEF, NVT);
04140     Hi = DAG.getNode(ISD::UNDEF, NVT);
04141     break;
04142   case ISD::Constant: {
04143     uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
04144     Lo = DAG.getConstant(Cst, NVT);
04145     Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
04146     break;
04147   }
04148   case ISD::BUILD_PAIR:
04149     // Return the operands.
04150     Lo = Node->getOperand(0);
04151     Hi = Node->getOperand(1);
04152     break;
04153     
04154   case ISD::SIGN_EXTEND_INREG:
04155     ExpandOp(Node->getOperand(0), Lo, Hi);
04156     // Sign extend the lo-part.
04157     Hi = DAG.getNode(ISD::SRA, NVT, Lo,
04158                      DAG.getConstant(MVT::getSizeInBits(NVT)-1,
04159                                      TLI.getShiftAmountTy()));
04160     // sext_inreg the low part if needed.
04161     Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
04162     break;
04163 
04164   case ISD::BSWAP: {
04165     ExpandOp(Node->getOperand(0), Lo, Hi);
04166     SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
04167     Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
04168     Lo = TempLo;
04169     break;
04170   }
04171     
04172   case ISD::CTPOP:
04173     ExpandOp(Node->getOperand(0), Lo, Hi);
04174     Lo = DAG.getNode(ISD::ADD, NVT,          // ctpop(HL) -> ctpop(H)+ctpop(L)
04175                      DAG.getNode(ISD::CTPOP, NVT, Lo),
04176                      DAG.getNode(ISD::CTPOP, NVT, Hi));
04177     Hi = DAG.getConstant(0, NVT);
04178     break;
04179 
04180   case ISD::CTLZ: {
04181     // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
04182     ExpandOp(Node->getOperand(0), Lo, Hi);
04183     SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
04184     SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
04185     SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
04186                                         ISD::SETNE);
04187     SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
04188     LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
04189 
04190     Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
04191     Hi = DAG.getConstant(0, NVT);
04192     break;
04193   }
04194 
04195   case ISD::CTTZ: {
04196     // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
04197     ExpandOp(Node->getOperand(0), Lo, Hi);
04198     SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
04199     SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
04200     SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
04201                                         ISD::SETNE);
04202     SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
04203     HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
04204 
04205     Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
04206     Hi = DAG.getConstant(0, NVT);
04207     break;
04208   }
04209 
04210   case ISD::VAARG: {
04211     SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
04212     SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
04213     Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
04214     Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
04215 
04216     // Remember that we legalized the chain.
04217     Hi = LegalizeOp(Hi);
04218     AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
04219     if (!TLI.isLittleEndian())
04220       std::swap(Lo, Hi);
04221     break;
04222   }
04223     
04224   case ISD::LOAD: {
04225     SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
04226     SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
04227     Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
04228 
04229     // Increment the pointer to the other half.
04230     unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
04231     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
04232                       getIntPtrConstant(IncrementSize));
04233     // FIXME: This creates a bogus srcvalue!
04234     Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
04235 
04236     // Build a factor node to remember that this load is independent of the
04237     // other one.
04238     SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
04239                                Hi.getValue(1));
04240 
04241     // Remember that we legalized the chain.
04242     AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
04243     if (!TLI.isLittleEndian())
04244       std::swap(Lo, Hi);
04245     break;
04246   }
04247   case ISD::AND:
04248   case ISD::OR:
04249   case ISD::XOR: {   // Simple logical operators -> two trivial pieces.
04250     SDOperand LL, LH, RL, RH;
04251     ExpandOp(Node->getOperand(0), LL, LH);
04252     ExpandOp(Node->getOperand(1), RL, RH);
04253     Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
04254     Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
04255     break;
04256   }
04257   case ISD::SELECT: {
04258     SDOperand LL, LH, RL, RH;
04259     ExpandOp(Node->getOperand(1), LL, LH);
04260     ExpandOp(Node->getOperand(2), RL, RH);
04261     Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
04262     Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
04263     break;
04264   }
04265   case ISD::SELECT_CC: {
04266     SDOperand TL, TH, FL, FH;
04267     ExpandOp(Node->getOperand(2), TL, TH);
04268     ExpandOp(Node->getOperand(3), FL, FH);
04269     Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
04270                      Node->getOperand(1), TL, FL, Node->getOperand(4));
04271     Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
04272                      Node->getOperand(1), TH, FH, Node->getOperand(4));
04273     break;
04274   }
04275   case ISD::SEXTLOAD: {
04276     SDOperand Chain = Node->getOperand(0);
04277     SDOperand Ptr   = Node->getOperand(1);
04278     MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
04279     
04280     if (EVT == NVT)
04281       Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
04282     else
04283       Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
04284                           EVT);
04285     
04286     // Remember that we legalized the chain.
04287     AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
04288     
04289     // The high part is obtained by SRA'ing all but one of the bits of the lo
04290     // part.
04291     unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
04292     Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
04293                                                        TLI.getShiftAmountTy()));
04294     break;
04295   }
04296   case ISD::ZEXTLOAD: {
04297     SDOperand Chain = Node->getOperand(0);
04298     SDOperand Ptr   = Node->getOperand(1);
04299     MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
04300     
04301     if (EVT == NVT)
04302       Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
04303     else
04304       Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
04305                           EVT);
04306     
04307     // Remember that we legalized the chain.
04308     AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
04309 
04310     // The high part is just a zero.
04311     Hi = DAG.getConstant(0, NVT);
04312     break;
04313   }
04314   case ISD::EXTLOAD: {
04315     SDOperand Chain = Node->getOperand(0);
04316     SDOperand Ptr   = Node->getOperand(1);
04317     MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
04318     
04319     if (EVT == NVT)
04320       Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
04321     else
04322       Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
04323                           EVT);
04324     
04325     // Remember that we legalized the chain.
04326     AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
04327     
04328     // The high part is undefined.
04329     Hi = DAG.getNode(ISD::UNDEF, NVT);
04330     break;
04331   }
04332   case ISD::ANY_EXTEND:
04333     // The low part is any extension of the input (which degenerates to a copy).
04334     Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
04335     // The high part is undefined.
04336     Hi = DAG.getNode(ISD::UNDEF, NVT);
04337     break;
04338   case ISD::SIGN_EXTEND: {
04339     // The low part is just a sign extension of the input (which degenerates to
04340     // a copy).
04341     Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
04342 
04343     // The high part is obtained by SRA'ing all but one of the bits of the lo
04344     // part.
04345     unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
04346     Hi = DAG.getNode(ISD::SRA, NVT, Lo,
04347                      DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
04348     break;
04349   }
04350   case ISD::ZERO_EXTEND:
04351     // The low part is just a zero extension of the input (which degenerates to
04352     // a copy).
04353     Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
04354 
04355     // The high part is just a zero.
04356     Hi = DAG.getConstant(0, NVT);
04357     break;
04358     
04359   case ISD::BIT_CONVERT: {
04360     SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 
04361                                       Node->getOperand(0));
04362     ExpandOp(Tmp, Lo, Hi);
04363     break;
04364   }
04365 
04366   case ISD::READCYCLECOUNTER:
04367     assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 
04368                  TargetLowering::Custom &&
04369            "Must custom expand ReadCycleCounter");
04370     Lo = TLI.LowerOperation(Op, DAG);
04371     assert(Lo.Val && "Node must be custom expanded!");
04372     Hi = Lo.getValue(1);
04373     AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
04374                         LegalizeOp(Lo.getValue(2)));
04375     break;
04376 
04377     // These operators cannot be expanded directly, emit them as calls to
04378     // library functions.
04379   case ISD::FP_TO_SINT:
04380     if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
04381       SDOperand Op;
04382       switch (getTypeAction(Node->getOperand(0).getValueType())) {
04383       case Expand: assert(0 && "cannot expand FP!");
04384       case Legal:   Op = LegalizeOp(Node->getOperand(0)); break;
04385       case Promote: Op = PromoteOp (Node->getOperand(0)); break;
04386       }
04387 
04388       Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
04389 
04390       // Now that the custom expander is done, expand the result, which is still
04391       // VT.
04392       if (Op.Val) {
04393         ExpandOp(Op, Lo, Hi);
04394         break;
04395       }
04396     }
04397 
04398     if (Node->getOperand(0).getValueType() == MVT::f32)
04399       Lo = ExpandLibCall("__fixsfdi", Node, Hi);
04400     else
04401       Lo = ExpandLibCall("__fixdfdi", Node, Hi);
04402     break;
04403 
04404   case ISD::FP_TO_UINT:
04405     if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
04406       SDOperand Op;
04407       switch (getTypeAction(Node->getOperand(0).getValueType())) {
04408         case Expand: assert(0 && "cannot expand FP!");
04409         case Legal:   Op = LegalizeOp(Node->getOperand(0)); break;
04410         case Promote: Op = PromoteOp (Node->getOperand(0)); break;
04411       }
04412         
04413       Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
04414 
04415       // Now that the custom expander is done, expand the result.
04416       if (Op.Val) {
04417         ExpandOp(Op, Lo, Hi);
04418         break;
04419       }
04420     }
04421 
04422     if (Node->getOperand(0).getValueType() == MVT::f32)
04423       Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
04424     else
04425       Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
04426     break;
04427 
04428   case ISD::SHL: {
04429     // If the target wants custom lowering, do so.
04430     SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
04431     if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
04432       SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
04433       Op = TLI.LowerOperation(Op, DAG);
04434       if (Op.Val) {
04435         // Now that the custom expander is done, expand the result, which is
04436         // still VT.
04437         ExpandOp(Op, Lo, Hi);
04438         break;
04439       }
04440     }
04441     
04442     // If we can emit an efficient shift operation, do so now.
04443     if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
04444       break;
04445 
04446     // If this target supports SHL_PARTS, use it.
04447     TargetLowering::LegalizeAction Action =
04448       TLI.getOperationAction(ISD::SHL_PARTS, NVT);
04449     if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
04450         Action == TargetLowering::Custom) {
04451       ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
04452       break;
04453     }
04454 
04455     // Otherwise, emit a libcall.
04456     Lo = ExpandLibCall("__ashldi3", Node, Hi);
04457     break;
04458   }
04459 
04460   case ISD::SRA: {
04461     // If the target wants custom lowering, do so.
04462     SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
04463     if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
04464       SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
04465       Op = TLI.LowerOperation(Op, DAG);
04466       if (Op.Val) {
04467         // Now that the custom expander is done, expand the result, which is
04468         // still VT.
04469         ExpandOp(Op, Lo, Hi);
04470         break;
04471       }
04472     }
04473     
04474     // If we can emit an efficient shift operation, do so now.
04475     if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
04476       break;
04477 
04478     // If this target supports SRA_PARTS, use it.
04479     TargetLowering::LegalizeAction Action =
04480       TLI.getOperationAction(ISD::SRA_PARTS, NVT);
04481     if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
04482         Action == TargetLowering::Custom) {
04483       ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
04484       break;
04485     }
04486 
04487     // Otherwise, emit a libcall.
04488     Lo = ExpandLibCall("__ashrdi3", Node, Hi);
04489     break;
04490   }
04491 
04492   case ISD::SRL: {
04493     // If the target wants custom lowering, do so.
04494     SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
04495     if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
04496       SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
04497       Op = TLI.LowerOperation(Op, DAG);
04498       if (Op.Val) {
04499         // Now that the custom expander is done, expand the result, which is
04500         // still VT.
04501         ExpandOp(Op, Lo, Hi);
04502         break;
04503       }
04504     }
04505 
04506     // If we can emit an efficient shift operation, do so now.
04507     if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
04508       break;
04509 
04510     // If this target supports SRL_PARTS, use it.
04511     TargetLowering::LegalizeAction Action =
04512       TLI.getOperationAction(ISD::SRL_PARTS, NVT);
04513     if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
04514         Action == TargetLowering::Custom) {
04515       ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
04516       break;
04517     }
04518 
04519     // Otherwise, emit a libcall.
04520     Lo = ExpandLibCall("__lshrdi3", Node, Hi);
04521     break;
04522   }
04523 
04524   case ISD::ADD:
04525   case ISD::SUB: {
04526     // If the target wants to custom expand this, let them.
04527     if (TLI.getOperationAction(Node->getOpcode(), VT) ==
04528             TargetLowering::Custom) {
04529       Op = TLI.LowerOperation(Op, DAG);
04530       if (Op.Val) {
04531         ExpandOp(Op, Lo, Hi);
04532         break;
04533       }
04534     }
04535     
04536     // Expand the subcomponents.
04537     SDOperand LHSL, LHSH, RHSL, RHSH;
04538     ExpandOp(Node->getOperand(0), LHSL, LHSH);
04539     ExpandOp(Node->getOperand(1), RHSL, RHSH);
04540     std::vector<MVT::ValueType> VTs;
04541     std::vector<SDOperand> LoOps, HiOps;
04542     VTs.push_back(LHSL.getValueType());
04543     VTs.push_back(MVT::Flag);
04544     LoOps.push_back(LHSL);
04545     LoOps.push_back(RHSL);
04546     HiOps.push_back(LHSH);
04547     HiOps.push_back(RHSH);
04548     if (Node->getOpcode() == ISD::ADD) {
04549       Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
04550       HiOps.push_back(Lo.getValue(1));
04551       Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
04552     } else {
04553       Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
04554       HiOps.push_back(Lo.getValue(1));
04555       Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
04556     }
04557     break;
04558   }
04559   case ISD::MUL: {
04560     if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
04561       SDOperand LL, LH, RL, RH;
04562       ExpandOp(Node->getOperand(0), LL, LH);
04563       ExpandOp(Node->getOperand(1), RL, RH);
04564       unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
04565       // MULHS implicitly sign extends its inputs.  Check to see if ExpandOp
04566       // extended the sign bit of the low half through the upper half, and if so
04567       // emit a MULHS instead of the alternate sequence that is valid for any
04568       // i64 x i64 multiply.
04569       if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
04570           // is RH an extension of the sign bit of RL?
04571           RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
04572           RH.getOperand(1).getOpcode() == ISD::Constant &&
04573           cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
04574           // is LH an extension of the sign bit of LL?
04575           LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
04576           LH.getOperand(1).getOpcode() == ISD::Constant &&
04577           cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
04578         Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
04579       } else {
04580         Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
04581         RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
04582         LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
04583         Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
04584         Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
04585       }
04586       Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
04587     } else {
04588       Lo = ExpandLibCall("__muldi3" , Node, Hi);
04589     }
04590     break;
04591   }
04592   case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
04593   case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
04594   case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
04595   case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
04596   }
04597 
04598   // Make sure the resultant values have been legalized themselves, unless this
04599   // is a type that requires multi-step expansion.
04600   if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
04601     Lo = LegalizeOp(Lo);
04602     Hi = LegalizeOp(Hi);
04603   }
04604 
04605   // Remember in a map if the values will be reused later.
04606   bool isNew =
04607     ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
04608   assert(isNew && "Value already expanded?!?");
04609 }
04610 
04611 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
04612 /// two smaller values of MVT::Vector type.
04613 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
04614                                          SDOperand &Hi) {
04615   assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
04616   SDNode *Node = Op.Val;
04617   unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
04618   assert(NumElements > 1 && "Cannot split a single element vector!");
04619   unsigned NewNumElts = NumElements/2;
04620   SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
04621   SDOperand TypeNode = *(Node->op_end()-1);
04622   
04623   // See if we already split it.
04624   std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
04625     = SplitNodes.find(Op);
04626   if (I != SplitNodes.end()) {
04627     Lo = I->second.first;
04628     Hi = I->second.second;
04629     return;
04630   }
04631   
04632   switch (Node->getOpcode()) {
04633   default: Node->dump(); assert(0 && "Unknown vector operation!");
04634   case ISD::VBUILD_VECTOR: {
04635     std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
04636     LoOps.push_back(NewNumEltsNode);
04637     LoOps.push_back(TypeNode);
04638     Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
04639 
04640     std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
04641     HiOps.push_back(NewNumEltsNode);
04642     HiOps.push_back(TypeNode);
04643     Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
04644     break;
04645   }
04646   case ISD::VADD:
04647   case ISD::VSUB:
04648   case ISD::VMUL:
04649   case ISD::VSDIV:
04650   case ISD::VUDIV:
04651   case ISD::VAND:
04652   case ISD::VOR:
04653   case ISD::VXOR: {
04654     SDOperand LL, LH, RL, RH;
04655     SplitVectorOp(Node->getOperand(0), LL, LH);
04656     SplitVectorOp(Node->getOperand(1), RL, RH);
04657     
04658     Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
04659                      NewNumEltsNode, TypeNode);
04660     Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
04661                      NewNumEltsNode, TypeNode);
04662     break;
04663   }
04664   case ISD::VLOAD: {
04665     SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
04666     SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
04667     MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
04668     
04669     Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
04670     unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
04671     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
04672                       getIntPtrConstant(IncrementSize));
04673     // FIXME: This creates a bogus srcvalue!
04674     Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
04675     
04676     // Build a factor node to remember that this load is independent of the
04677     // other one.
04678     SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
04679                                Hi.getValue(1));
04680     
04681     // Remember that we legalized the chain.
04682     AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
04683     break;
04684   }
04685   case ISD::VBIT_CONVERT: {
04686     // We know the result is a vector.  The input may be either a vector or a
04687     // scalar value.
04688     if (Op.getOperand(0).getValueType() != MVT::Vector) {
04689       // Lower to a store/load.  FIXME: this could be improved probably.
04690       SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
04691 
04692       SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
04693                                  Op.getOperand(0), Ptr, DAG.getSrcValue(0));
04694       MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
04695       St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
04696       SplitVectorOp(St, Lo, Hi);
04697     } else {
04698       // If the input is a vector type, we have to either scalarize it, pack it
04699       // or convert it based on whether the input vector type is legal.
04700       SDNode *InVal = Node->getOperand(0).Val;
04701       unsigned NumElems =
04702         cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
04703       MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
04704 
04705       // If the input is from a single element vector, scalarize the vector,
04706       // then treat like a scalar.
04707       if (NumElems == 1) {
04708         SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
04709         Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
04710                              Op.getOperand(1), Op.getOperand(2));
04711         SplitVectorOp(Scalar, Lo, Hi);
04712       } else {
04713         // Split the input vector.
04714         SplitVectorOp(Op.getOperand(0), Lo, Hi);
04715 
04716         // Convert each of the pieces now.
04717         Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
04718                          NewNumEltsNode, TypeNode);
04719         Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
04720                          NewNumEltsNode, TypeNode);
04721       }
04722       break;
04723     }
04724   }
04725   }
04726       
04727   // Remember in a map if the values will be reused later.
04728   bool isNew =
04729     SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
04730   assert(isNew && "Value already expanded?!?");
04731 }
04732 
04733 
04734 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
04735 /// equivalent operation that returns a scalar (e.g. F32) or packed value
04736 /// (e.g. MVT::V4F32).  When this is called, we know that PackedVT is the right
04737 /// type for the result.
04738 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 
04739                                              MVT::ValueType NewVT) {
04740   assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
04741   SDNode *Node = Op.Val;
04742   
04743   // See if we already packed it.
04744   std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
04745   if (I != PackedNodes.end()) return I->second;
04746   
04747   SDOperand Result;
04748   switch (Node->getOpcode()) {
04749   default: 
04750     Node->dump(); std::cerr << "\n";
04751     assert(0 && "Unknown vector operation in PackVectorOp!");
04752   case ISD::VADD:
04753   case ISD::VSUB:
04754   case ISD::VMUL:
04755   case ISD::VSDIV:
04756   case ISD::VUDIV:
04757   case ISD::VAND:
04758   case ISD::VOR:
04759   case ISD::VXOR:
04760     Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
04761                          NewVT, 
04762                          PackVectorOp(Node->getOperand(0), NewVT),
04763                          PackVectorOp(Node->getOperand(1), NewVT));
04764     break;
04765   case ISD::VLOAD: {
04766     SDOperand Ch = LegalizeOp(Node->getOperand(0));   // Legalize the chain.
04767     SDOperand Ptr = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
04768     
04769     Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
04770     
04771     // Remember that we legalized the chain.
04772     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
04773     break;
04774   }
04775   case ISD::VBUILD_VECTOR:
04776     if (Node->getOperand(0).getValueType() == NewVT) {
04777       // Returning a scalar?
04778       Result = Node->getOperand(0);
04779     } else {
04780       // Returning a BUILD_VECTOR?
04781       
04782       // If all elements of the build_vector are undefs, return an undef.
04783       bool AllUndef = true;
04784       for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
04785         if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
04786           AllUndef = false;
04787           break;
04788         }
04789       if (AllUndef) {
04790         Result = DAG.getNode(ISD::UNDEF, NewVT);
04791       } else {
04792         std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
04793         Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
04794       }
04795     }
04796     break;
04797   case ISD::VINSERT_VECTOR_ELT:
04798     if (!MVT::isVector(NewVT)) {
04799       // Returning a scalar?  Must be the inserted element.
04800       Result = Node->getOperand(1);
04801     } else {
04802       Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
04803                            PackVectorOp(Node->getOperand(0), NewVT),
04804                            Node->getOperand(1), Node->getOperand(2));
04805     }
04806     break;
04807   case ISD::VVECTOR_SHUFFLE:
04808     if (!MVT::isVector(NewVT)) {
04809       // Returning a scalar?  Figure out if it is the LHS or RHS and return it.
04810       SDOperand EltNum = Node->getOperand(2).getOperand(0);
04811       if (cast<ConstantSDNode>(EltNum)->getValue())
04812         Result = PackVectorOp(Node->getOperand(1), NewVT);
04813       else
04814         Result = PackVectorOp(Node->getOperand(0), NewVT);
04815     } else {
04816       // Otherwise, return a VECTOR_SHUFFLE node.  First convert the index
04817       // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
04818       std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
04819                                          Node->getOperand(2).Val->op_end()-2);
04820       MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
04821       SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
04822       
04823       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
04824                            PackVectorOp(Node->getOperand(0), NewVT),
04825                            PackVectorOp(Node->getOperand(1), NewVT), BV);
04826     }
04827     break;
04828   case ISD::VBIT_CONVERT:
04829     if (Op.getOperand(0).getValueType() != MVT::Vector)
04830       Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
04831     else {
04832       // If the input is a vector type, we have to either scalarize it, pack it
04833       // or convert it based on whether the input vector type is legal.
04834       SDNode *InVal = Node->getOperand(0).Val;
04835       unsigned NumElems =
04836         cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
04837       MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
04838         
04839       // Figure out if there is a Packed type corresponding to this Vector
04840       // type.  If so, convert to the packed type.
04841       MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
04842       if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
04843         // Turn this into a bit convert of the packed input.
04844         Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 
04845                              PackVectorOp(Node->getOperand(0), TVT));
04846         break;
04847       } else if (NumElems == 1) {
04848         // Turn this into a bit convert of the scalar input.
04849         Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 
04850                              PackVectorOp(Node->getOperand(0), EVT));
04851         break;
04852       } else {
04853         // FIXME: UNIMP!
04854         assert(0 && "Cast from unsupported vector type not implemented yet!");
04855       }
04856     }
04857     break;
04858   case ISD::VSELECT:
04859     Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
04860                          PackVectorOp(Op.getOperand(1), NewVT),
04861                          PackVectorOp(Op.getOperand(2), NewVT));
04862     break;
04863   }
04864 
04865   if (TLI.isTypeLegal(NewVT))
04866     Result = LegalizeOp(Result);
04867   bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
04868   assert(isNew && "Value already packed?");
04869   return Result;
04870 }
04871 
04872 
04873 // SelectionDAG::Legalize - This is the entry point for the file.
04874 //
04875 void SelectionDAG::Legalize() {
04876   if (ViewLegalizeDAGs) viewGraph();
04877 
04878   /// run - This is the main entry point to this class.
04879   ///
04880   SelectionDAGLegalize(*this).LegalizeDAG();
04881 }
04882