LLVM API Documentation
00001 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the PowerPC implementation of the MRegisterInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #define DEBUG_TYPE "reginfo" 00015 #include "PPC.h" 00016 #include "PPCInstrBuilder.h" 00017 #include "PPCRegisterInfo.h" 00018 #include "llvm/Constants.h" 00019 #include "llvm/Type.h" 00020 #include "llvm/CodeGen/ValueTypes.h" 00021 #include "llvm/CodeGen/MachineInstrBuilder.h" 00022 #include "llvm/CodeGen/MachineDebugInfo.h" 00023 #include "llvm/CodeGen/MachineFunction.h" 00024 #include "llvm/CodeGen/MachineFrameInfo.h" 00025 #include "llvm/CodeGen/MachineLocation.h" 00026 #include "llvm/CodeGen/SelectionDAGNodes.h" 00027 #include "llvm/Target/TargetFrameInfo.h" 00028 #include "llvm/Target/TargetMachine.h" 00029 #include "llvm/Target/TargetOptions.h" 00030 #include "llvm/Support/CommandLine.h" 00031 #include "llvm/Support/Debug.h" 00032 #include "llvm/Support/MathExtras.h" 00033 #include "llvm/ADT/STLExtras.h" 00034 #include <cstdlib> 00035 #include <iostream> 00036 using namespace llvm; 00037 00038 PPCRegisterInfo::PPCRegisterInfo() 00039 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 00040 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 00041 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 00042 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 00043 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 00044 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 00045 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 00046 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 00047 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 00048 } 00049 00050 void 00051 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 00052 MachineBasicBlock::iterator MI, 00053 unsigned SrcReg, int FrameIdx, 00054 const TargetRegisterClass *RC) const { 00055 if (SrcReg == PPC::LR) { 00056 // FIXME: this spills LR immediately to memory in one step. To do this, we 00057 // use R11, which we know cannot be used in the prolog/epilog. This is a 00058 // hack. 00059 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 00060 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 00061 } else if (RC == PPC::CRRCRegisterClass) { 00062 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 00063 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 00064 } else if (RC == PPC::GPRCRegisterClass) { 00065 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 00066 } else if (RC == PPC::G8RCRegisterClass) { 00067 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 00068 } else if (RC == PPC::F8RCRegisterClass) { 00069 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 00070 } else if (RC == PPC::F4RCRegisterClass) { 00071 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 00072 } else if (RC == PPC::VRRCRegisterClass) { 00073 // We don't have indexed addressing for vector loads. Emit: 00074 // R11 = ADDI FI# 00075 // Dest = LVX R0, R11 00076 // 00077 // FIXME: We use R0 here, because it isn't available for RA. 00078 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 00079 BuildMI(MBB, MI, PPC::STVX, 3) 00080 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 00081 } else { 00082 assert(0 && "Unknown regclass!"); 00083 abort(); 00084 } 00085 } 00086 00087 void 00088 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 00089 MachineBasicBlock::iterator MI, 00090 unsigned DestReg, int FrameIdx, 00091 const TargetRegisterClass *RC) const { 00092 if (DestReg == PPC::LR) { 00093 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 00094 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 00095 } else if (RC == PPC::CRRCRegisterClass) { 00096 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 00097 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 00098 } else if (RC == PPC::GPRCRegisterClass) { 00099 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 00100 } else if (RC == PPC::G8RCRegisterClass) { 00101 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 00102 } else if (RC == PPC::F8RCRegisterClass) { 00103 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 00104 } else if (RC == PPC::F4RCRegisterClass) { 00105 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 00106 } else if (RC == PPC::VRRCRegisterClass) { 00107 // We don't have indexed addressing for vector loads. Emit: 00108 // R11 = ADDI FI# 00109 // Dest = LVX R0, R11 00110 // 00111 // FIXME: We use R0 here, because it isn't available for RA. 00112 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 00113 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 00114 } else { 00115 assert(0 && "Unknown regclass!"); 00116 abort(); 00117 } 00118 } 00119 00120 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 00121 MachineBasicBlock::iterator MI, 00122 unsigned DestReg, unsigned SrcReg, 00123 const TargetRegisterClass *RC) const { 00124 if (RC == PPC::GPRCRegisterClass) { 00125 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 00126 } else if (RC == PPC::G8RCRegisterClass) { 00127 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 00128 } else if (RC == PPC::F4RCRegisterClass) { 00129 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 00130 } else if (RC == PPC::F8RCRegisterClass) { 00131 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 00132 } else if (RC == PPC::CRRCRegisterClass) { 00133 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 00134 } else if (RC == PPC::VRRCRegisterClass) { 00135 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 00136 } else { 00137 std::cerr << "Attempt to copy register that is not GPR or FPR"; 00138 abort(); 00139 } 00140 } 00141 00142 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 00143 /// copy instructions, turning them into load/store instructions. 00144 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 00145 unsigned OpNum, 00146 int FrameIndex) const { 00147 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 00148 // it takes more than one instruction to store it. 00149 unsigned Opc = MI->getOpcode(); 00150 00151 if ((Opc == PPC::OR4 && 00152 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 00153 if (OpNum == 0) { // move -> store 00154 unsigned InReg = MI->getOperand(1).getReg(); 00155 return addFrameReference(BuildMI(PPC::STW, 00156 3).addReg(InReg), FrameIndex); 00157 } else { // move -> load 00158 unsigned OutReg = MI->getOperand(0).getReg(); 00159 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 00160 } 00161 } else if ((Opc == PPC::OR8 && 00162 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 00163 if (OpNum == 0) { // move -> store 00164 unsigned InReg = MI->getOperand(1).getReg(); 00165 return addFrameReference(BuildMI(PPC::STD, 00166 3).addReg(InReg), FrameIndex); 00167 } else { // move -> load 00168 unsigned OutReg = MI->getOperand(0).getReg(); 00169 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 00170 } 00171 } else if (Opc == PPC::FMRD) { 00172 if (OpNum == 0) { // move -> store 00173 unsigned InReg = MI->getOperand(1).getReg(); 00174 return addFrameReference(BuildMI(PPC::STFD, 00175 3).addReg(InReg), FrameIndex); 00176 } else { // move -> load 00177 unsigned OutReg = MI->getOperand(0).getReg(); 00178 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 00179 } 00180 } else if (Opc == PPC::FMRS) { 00181 if (OpNum == 0) { // move -> store 00182 unsigned InReg = MI->getOperand(1).getReg(); 00183 return addFrameReference(BuildMI(PPC::STFS, 00184 3).addReg(InReg), FrameIndex); 00185 } else { // move -> load 00186 unsigned OutReg = MI->getOperand(0).getReg(); 00187 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 00188 } 00189 } 00190 return 0; 00191 } 00192 00193 //===----------------------------------------------------------------------===// 00194 // Stack Frame Processing methods 00195 //===----------------------------------------------------------------------===// 00196 00197 // hasFP - Return true if the specified function should have a dedicated frame 00198 // pointer register. This is true if the function has variable sized allocas or 00199 // if frame pointer elimination is disabled. 00200 // 00201 static bool hasFP(const MachineFunction &MF) { 00202 const MachineFrameInfo *MFI = MF.getFrameInfo(); 00203 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 00204 00205 // If frame pointers are forced, or if there are variable sized stack objects, 00206 // use a frame pointer. 00207 // 00208 return NoFramePointerElim || MFI->hasVarSizedObjects(); 00209 } 00210 00211 void PPCRegisterInfo:: 00212 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 00213 MachineBasicBlock::iterator I) const { 00214 if (hasFP(MF)) { 00215 // If we have a frame pointer, convert as follows: 00216 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 00217 // ADJCALLSTACKUP -> addi, r1, r1, amount 00218 MachineInstr *Old = I; 00219 unsigned Amount = Old->getOperand(0).getImmedValue(); 00220 if (Amount != 0) { 00221 // We need to keep the stack aligned properly. To do this, we round the 00222 // amount of space needed for the outgoing arguments up to the next 00223 // alignment boundary. 00224 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 00225 Amount = (Amount+Align-1)/Align*Align; 00226 00227 // Replace the pseudo instruction with a new instruction... 00228 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 00229 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); 00230 } else { 00231 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 00232 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); 00233 } 00234 } 00235 } 00236 MBB.erase(I); 00237 } 00238 00239 void 00240 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 00241 unsigned i = 0; 00242 MachineInstr &MI = *II; 00243 MachineBasicBlock &MBB = *MI.getParent(); 00244 MachineFunction &MF = *MBB.getParent(); 00245 00246 while (!MI.getOperand(i).isFrameIndex()) { 00247 ++i; 00248 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 00249 } 00250 00251 int FrameIndex = MI.getOperand(i).getFrameIndex(); 00252 00253 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 00254 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 00255 00256 // Take into account whether it's an add or mem instruction 00257 unsigned OffIdx = (i == 2) ? 1 : 2; 00258 00259 // Now add the frame object offset to the offset from r1. 00260 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 00261 MI.getOperand(OffIdx).getImmedValue(); 00262 00263 // If we're not using a Frame Pointer that has been set to the value of the 00264 // SP before having the stack size subtracted from it, then add the stack size 00265 // to Offset to get the correct offset. 00266 Offset += MF.getFrameInfo()->getStackSize(); 00267 00268 if (Offset > 32767 || Offset < -32768) { 00269 // Insert a set of r0 with the full offset value before the ld, st, or add 00270 MachineBasicBlock *MBB = MI.getParent(); 00271 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); 00272 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 00273 00274 // convert into indexed form of the instruction 00275 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 00276 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 00277 assert(ImmToIdxMap.count(MI.getOpcode()) && 00278 "No indexed form of load or store available!"); 00279 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 00280 MI.setOpcode(NewOpcode); 00281 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 00282 MI.SetMachineOperandReg(2, PPC::R0); 00283 } else { 00284 switch (MI.getOpcode()) { 00285 case PPC::LWA: 00286 case PPC::LD: 00287 case PPC::STD: 00288 case PPC::STD_32: 00289 assert((Offset & 3) == 0 && "Invalid frame offset!"); 00290 Offset >>= 2; // The actual encoded value has the low two bits zero. 00291 break; 00292 } 00293 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 00294 Offset); 00295 } 00296 } 00297 00298 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 00299 // instruction selector. Based on the vector registers that have been used, 00300 // transform this into the appropriate ORI instruction. 00301 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 00302 unsigned UsedRegMask = 0; 00303 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N) 00304 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3); 00305 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7); 00306 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11); 00307 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15); 00308 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19); 00309 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23); 00310 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27); 00311 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31); 00312 #undef HANDLEREG 00313 unsigned SrcReg = MI->getOperand(1).getReg(); 00314 unsigned DstReg = MI->getOperand(0).getReg(); 00315 // If no registers are used, turn this into a copy. 00316 if (UsedRegMask == 0) { 00317 if (SrcReg != DstReg) 00318 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) 00319 .addReg(SrcReg).addReg(SrcReg); 00320 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 00321 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 00322 .addReg(SrcReg).addImm(UsedRegMask); 00323 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 00324 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 00325 .addReg(SrcReg).addImm(UsedRegMask >> 16); 00326 } else { 00327 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 00328 .addReg(SrcReg).addImm(UsedRegMask >> 16); 00329 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 00330 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 00331 } 00332 00333 // Remove the old UPDATE_VRSAVE instruction. 00334 MI->getParent()->erase(MI); 00335 } 00336 00337 00338 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 00339 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 00340 MachineBasicBlock::iterator MBBI = MBB.begin(); 00341 MachineFrameInfo *MFI = MF.getFrameInfo(); 00342 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 00343 00344 // Do we have a frame pointer for this function? 00345 bool HasFP = hasFP(MF); 00346 00347 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 00348 // process it. 00349 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 00350 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 00351 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 00352 break; 00353 } 00354 } 00355 00356 // Move MBBI back to the beginning of the function. 00357 MBBI = MBB.begin(); 00358 00359 // Get the number of bytes to allocate from the FrameInfo 00360 unsigned NumBytes = MFI->getStackSize(); 00361 00362 // Get the alignments provided by the target, and the maximum alignment 00363 // (if any) of the fixed frame objects. 00364 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 00365 unsigned MaxAlign = MFI->getMaxAlignment(); 00366 00367 // If we have calls, we cannot use the red zone to store callee save registers 00368 // and we must set up a stack frame, so calculate the necessary size here. 00369 if (MFI->hasCalls()) { 00370 // We reserve argument space for call sites in the function immediately on 00371 // entry to the current function. This eliminates the need for add/sub 00372 // brackets around call sites. 00373 NumBytes += MFI->getMaxCallFrameSize(); 00374 } 00375 00376 // If we are a leaf function, and use up to 224 bytes of stack space, 00377 // and don't have a frame pointer, then we do not need to adjust the stack 00378 // pointer (we fit in the Red Zone). 00379 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && 00380 MaxAlign <= TargetAlign)) { 00381 MFI->setStackSize(0); 00382 return; 00383 } 00384 00385 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 00386 // of the stack and round the size to a multiple of the alignment. 00387 unsigned Align = std::max(TargetAlign, MaxAlign); 00388 unsigned GPRSize = 4; 00389 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; 00390 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 00391 00392 // Update frame info to pretend that this is part of the stack... 00393 MFI->setStackSize(NumBytes); 00394 int NegNumbytes = -NumBytes; 00395 00396 // Adjust stack pointer: r1 -= numbytes. 00397 // If there is a preferred stack alignment, align R1 now 00398 if (MaxAlign > TargetAlign) { 00399 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 00400 assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!"); 00401 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 00402 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 00403 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) 00404 .addSImm(MaxAlign-NumBytes); 00405 BuildMI(MBB, MBBI, PPC::STWUX, 3) 00406 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 00407 } else if (NumBytes <= 32768) { 00408 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes) 00409 .addReg(PPC::R1); 00410 } else { 00411 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 00412 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 00413 .addImm(NegNumbytes & 0xFFFF); 00414 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) 00415 .addReg(PPC::R0); 00416 } 00417 00418 if (DebugInfo && DebugInfo->hasInfo()) { 00419 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); 00420 unsigned LabelID = DebugInfo->NextLabelID(); 00421 00422 // Show update of SP. 00423 MachineLocation Dst(MachineLocation::VirtualFP); 00424 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); 00425 Moves.push_back(new MachineMove(LabelID, Dst, Src)); 00426 00427 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); 00428 } 00429 00430 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 00431 if (HasFP) { 00432 BuildMI(MBB, MBBI, PPC::STW, 3) 00433 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 00434 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 00435 } 00436 } 00437 00438 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 00439 MachineBasicBlock &MBB) const { 00440 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 00441 assert(MBBI->getOpcode() == PPC::BLR && 00442 "Can only insert epilog into returning blocks"); 00443 00444 // Get alignment info so we know how to restore r1 00445 const MachineFrameInfo *MFI = MF.getFrameInfo(); 00446 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 00447 00448 // Get the number of bytes allocated from the FrameInfo. 00449 unsigned NumBytes = MFI->getStackSize(); 00450 unsigned GPRSize = 4; 00451 00452 if (NumBytes != 0) { 00453 // If this function has a frame pointer, load the saved stack pointer from 00454 // its stack slot. 00455 if (hasFP(MF)) { 00456 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 00457 .addSImm(GPRSize).addReg(PPC::R31); 00458 } 00459 00460 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 00461 // on entry to the function. Add this offset back now. 00462 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { 00463 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 00464 .addReg(PPC::R1).addSImm(NumBytes); 00465 } else { 00466 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); 00467 } 00468 } 00469 } 00470 00471 unsigned PPCRegisterInfo::getRARegister() const { 00472 return PPC::LR; 00473 } 00474 00475 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 00476 return hasFP(MF) ? PPC::R31 : PPC::R1; 00477 } 00478 00479 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) 00480 const { 00481 // Initial state is the frame pointer is R1. 00482 MachineLocation Dst(MachineLocation::VirtualFP); 00483 MachineLocation Src(PPC::R1, 0); 00484 Moves.push_back(new MachineMove(0, Dst, Src)); 00485 } 00486 00487 #include "PPCGenRegisterInfo.inc" 00488