LLVM API Documentation

llvm::TargetInstrInfo Class Reference

#include <TargetInstrInfo.h>

Inheritance diagram for llvm::TargetInstrInfo:

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Collaboration diagram for llvm::TargetInstrInfo:

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List of all members.

Public Types

 PHI = 0
 INLINEASM = 1
enum  { PHI = 0, INLINEASM = 1 }

Public Member Functions

 TargetInstrInfo (const TargetInstrDescriptor *desc, unsigned NumOpcodes)
virtual ~TargetInstrInfo ()
unsigned getNumOpcodes () const
const TargetInstrDescriptorget (MachineOpCode Opcode) const
const char * getName (MachineOpCode Opcode) const
int getNumOperands (MachineOpCode Opcode) const
InstrSchedClass getSchedClass (MachineOpCode Opcode) const
const unsigned * getImplicitUses (MachineOpCode Opcode) const
const unsigned * getImplicitDefs (MachineOpCode Opcode) const
bool isReturn (MachineOpCode Opcode) const
bool isTwoAddrInstr (MachineOpCode Opcode) const
bool isTerminatorInstr (unsigned Opcode) const
bool isBranch (MachineOpCode Opcode) const
bool isBarrier (MachineOpCode Opcode) const
bool isCall (MachineOpCode Opcode) const
bool isLoad (MachineOpCode Opcode) const
bool isStore (MachineOpCode Opcode) const
bool usesCustomDAGSchedInsertionHook (unsigned Opcode) const
virtual bool isMoveInstr (const MachineInstr &MI, unsigned &sourceReg, unsigned &destReg) const
virtual unsigned isLoadFromStackSlot (MachineInstr *MI, int &FrameIndex) const
virtual unsigned isStoreToStackSlot (MachineInstr *MI, int &FrameIndex) const
virtual MachineInstrconvertToThreeAddress (MachineInstr *TA) const
virtual MachineInstrcommuteInstruction (MachineInstr *MI) const
virtual void insertGoto (MachineBasicBlock &MBB, MachineBasicBlock &TMBB) const
virtual MachineBasicBlock::iterator reverseBranchCondition (MachineBasicBlock::iterator MI) const
virtual void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
unsigned getNumDelaySlots (MachineOpCode Opcode) const
bool isCCInstr (MachineOpCode Opcode) const
bool isNop (MachineOpCode Opcode) const
bool hasDelaySlot (unsigned Opcode) const
virtual bool hasResultInterlock (MachineOpCode Opcode) const
virtual int minLatency (MachineOpCode Opcode) const
virtual int maxLatency (MachineOpCode Opcode) const
virtual int getImmedConstantPos (MachineOpCode Opcode) const
virtual bool constantFitsInImmedField (MachineOpCode Opcode, int64_t intValue) const
virtual uint64_t maxImmedConstant (MachineOpCode Opcode, bool &isSignExtended) const

Detailed Description

TargetInstrInfo - Interface to description of machine instructions

Definition at line 117 of file TargetInstrInfo.h.


Member Enumeration Documentation

anonymous enum

Enumerator:
PHI 
INLINEASM 

Definition at line 129 of file TargetInstrInfo.h.


Constructor & Destructor Documentation

TargetInstrInfo::TargetInstrInfo ( const TargetInstrDescriptor desc,
unsigned  NumOpcodes 
)

Definition at line 28 of file TargetInstrInfo.cpp.

References llvm::TargetInstrDescriptors.

TargetInstrInfo::~TargetInstrInfo (  )  [virtual]

Definition at line 37 of file TargetInstrInfo.cpp.

References llvm::TargetInstrDescriptors.


Member Function Documentation

MachineInstr * TargetInstrInfo::commuteInstruction ( MachineInstr MI  )  const [virtual]

commuteInstruction - If a target has any instructions that are commutable, but require converting to a different instruction or making non-trivial changes to commute them, this method can overloaded to do this. The default implementation of this method simply swaps the first two operands of MI and returns it.

If a target wants to make more aggressive changes, they can construct and return a new machine instruction. If an instruction cannot commute, it can also return null.

Reimplemented in llvm::PPCInstrInfo, and llvm::X86InstrInfo.

Definition at line 64 of file TargetInstrInfo.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isRegister(), MI, and llvm::MachineInstr::SetMachineOperandReg().

Referenced by llvm::X86InstrInfo::commuteInstruction(), and llvm::PPCInstrInfo::commuteInstruction().

bool TargetInstrInfo::constantFitsInImmedField ( MachineOpCode  Opcode,
int64_t  intValue 
) const [virtual]

Definition at line 42 of file TargetInstrInfo.cpp.

References maxImmedConstant().

Referenced by llvm::SparcV9RegInfo::cpMem2RegMI(), and llvm::SparcV9RegInfo::cpReg2MemMI().

virtual MachineInstr* llvm::TargetInstrInfo::convertToThreeAddress ( MachineInstr TA  )  const [inline, virtual]

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

Reimplemented in llvm::X86InstrInfo.

Definition at line 244 of file TargetInstrInfo.h.

const TargetInstrDescriptor& llvm::TargetInstrInfo::get ( MachineOpCode  Opcode  )  const [inline]

get - Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Definition at line 139 of file TargetInstrInfo.h.

Referenced by llvm::ScheduleDAG::EmitNode(), llvm::X86InstrInfo::getBaseOpcodeFor(), getImplicitDefs(), getImplicitUses(), getName(), getNumDelaySlots(), getNumOperands(), getSchedClass(), hasDelaySlot(), isBarrier(), isBranch(), isCall(), isCCInstr(), isLoad(), isNop(), isReturn(), isStore(), isTerminatorInstr(), isTwoAddrInstr(), maxImmedConstant(), maxLatency(), minLatency(), llvm::LiveVariables::runOnMachineFunction(), and usesCustomDAGSchedInsertionHook().

virtual int llvm::TargetInstrInfo::getImmedConstantPos ( MachineOpCode  Opcode  )  const [inline, virtual]

Reimplemented in llvm::SparcV9InstrInfo.

Definition at line 327 of file TargetInstrInfo.h.

const unsigned* llvm::TargetInstrInfo::getImplicitDefs ( MachineOpCode  Opcode  )  const [inline]

Definition at line 160 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::ImplicitDefs.

const unsigned* llvm::TargetInstrInfo::getImplicitUses ( MachineOpCode  Opcode  )  const [inline]

Definition at line 156 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::ImplicitUses.

const char* llvm::TargetInstrInfo::getName ( MachineOpCode  Opcode  )  const [inline]

Definition at line 144 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::Name.

Referenced by llvm::CloneBasicBlock(), llvm::SDNode::getOperationName(), llvm::MachineInstr::print(), and llvm::SimplifyCFG().

unsigned llvm::TargetInstrInfo::getNumDelaySlots ( MachineOpCode  Opcode  )  const [inline]

Definition at line 293 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::numDelaySlots.

Referenced by llvm::ChooseInstructionsForDelaySlots(), llvm::FindSlotChoices(), llvm::FindUsefulInstructionsForDelaySlots(), and llvm::ReplaceNopsWithUsefulInstr().

unsigned llvm::TargetInstrInfo::getNumOpcodes (  )  const [inline]

Definition at line 134 of file TargetInstrInfo.h.

int llvm::TargetInstrInfo::getNumOperands ( MachineOpCode  Opcode  )  const [inline]

Definition at line 148 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::numOperands.

InstrSchedClass llvm::TargetInstrInfo::getSchedClass ( MachineOpCode  Opcode  )  const [inline]

Definition at line 152 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::schedClass.

Referenced by llvm::TargetSchedInfo::getSchedClass().

bool llvm::TargetInstrInfo::hasDelaySlot ( unsigned  Opcode  )  const [inline]

hasDelaySlot - Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 305 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_DELAY_SLOT_FLAG.

virtual bool llvm::TargetInstrInfo::hasResultInterlock ( MachineOpCode  Opcode  )  const [inline, virtual]

Reimplemented in llvm::SparcV9InstrInfo.

Definition at line 309 of file TargetInstrInfo.h.

virtual void llvm::TargetInstrInfo::insertGoto ( MachineBasicBlock MBB,
MachineBasicBlock TMBB 
) const [inline, virtual]

Insert a goto (unconditional branch) sequence to TMBB, at the end of MBB

Reimplemented in llvm::X86InstrInfo.

Definition at line 262 of file TargetInstrInfo.h.

Referenced by ReplaceUsesOfBlockWith().

virtual void llvm::TargetInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const [inline, virtual]

insertNoop - Insert a noop into the instruction stream at the specified point.

Reimplemented in llvm::PPCInstrInfo.

Definition at line 278 of file TargetInstrInfo.h.

References abort().

Referenced by llvm::ScheduleDAG::EmitNoop().

bool llvm::TargetInstrInfo::isBarrier ( MachineOpCode  Opcode  )  const [inline]

isBarrier - Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.

Definition at line 187 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_BARRIER_FLAG.

bool llvm::TargetInstrInfo::isBranch ( MachineOpCode  Opcode  )  const [inline]

Definition at line 180 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_BRANCH_FLAG.

Referenced by llvm::ChooseInstructionsForDelaySlots(), llvm::MSchedGraphSB::MSchedGraphSB(), llvm::NodeCanFillDelaySlot(), and llvm::X86InstrInfo::reverseBranchCondition().

bool llvm::TargetInstrInfo::isCall ( MachineOpCode  Opcode  )  const [inline]

Definition at line 191 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_CALL_FLAG.

Referenced by llvm::LiveRangeInfo::constructLiveRanges().

bool llvm::TargetInstrInfo::isCCInstr ( MachineOpCode  Opcode  )  const [inline]

Definition at line 296 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_CC_FLAG.

bool llvm::TargetInstrInfo::isLoad ( MachineOpCode  Opcode  )  const [inline]

Definition at line 194 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_LOAD_FLAG.

Referenced by llvm::NodeCanFillDelaySlot().

virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlot ( MachineInstr MI,
int &  FrameIndex 
) const [inline, virtual]

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Reimplemented in llvm::AlphaInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.

Definition at line 221 of file TargetInstrInfo.h.

virtual bool llvm::TargetInstrInfo::isMoveInstr ( const MachineInstr MI,
unsigned &  sourceReg,
unsigned &  destReg 
) const [inline, virtual]

Return true if the instruction is a register to register move and leave the source and dest operands in the passed parameters.

Reimplemented in llvm::AlphaInstrInfo, llvm::IA64InstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.

Definition at line 210 of file TargetInstrInfo.h.

Referenced by llvm::LiveIntervals::runOnMachineFunction().

bool llvm::TargetInstrInfo::isNop ( MachineOpCode  Opcode  )  const [inline]

Definition at line 299 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_NOP_FLAG.

Referenced by llvm::FindUsefulInstructionsForDelaySlots(), llvm::MSchedGraphSB::MSchedGraphSB(), and llvm::ReplaceNopsWithUsefulInstr().

bool llvm::TargetInstrInfo::isReturn ( MachineOpCode  Opcode  )  const [inline]

Definition at line 169 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_RET_FLAG.

Referenced by llvm::LiveRangeInfo::constructLiveRanges(), llvm::LiveVariables::runOnMachineFunction(), and llvm::SparcV9RegInfo::suggestReg4RetValue().

bool llvm::TargetInstrInfo::isStore ( MachineOpCode  Opcode  )  const [inline]

Definition at line 197 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_STORE_FLAG.

virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlot ( MachineInstr MI,
int &  FrameIndex 
) const [inline, virtual]

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Reimplemented in llvm::AlphaInstrInfo, llvm::PPCInstrInfo, llvm::SparcInstrInfo, and llvm::X86InstrInfo.

Definition at line 230 of file TargetInstrInfo.h.

bool llvm::TargetInstrInfo::isTerminatorInstr ( unsigned  Opcode  )  const [inline]

Definition at line 176 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_TERMINATOR_FLAG.

Referenced by llvm::MachineBasicBlock::getFirstTerminator(), and ReplaceUsesOfBlockWith().

bool llvm::TargetInstrInfo::isTwoAddrInstr ( MachineOpCode  Opcode  )  const [inline]

Definition at line 173 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_2_ADDR_FLAG.

virtual uint64_t llvm::TargetInstrInfo::maxImmedConstant ( MachineOpCode  Opcode,
bool &  isSignExtended 
) const [inline, virtual]

Definition at line 343 of file TargetInstrInfo.h.

References get(), llvm::TargetInstrDescriptor::immedIsSignExtended, and llvm::TargetInstrDescriptor::maxImmedConst.

Referenced by constantFitsInImmedField().

virtual int llvm::TargetInstrInfo::maxLatency ( MachineOpCode  Opcode  )  const [inline, virtual]

Definition at line 320 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::latency.

Referenced by llvm::FindUsefulInstructionsForDelaySlots().

virtual int llvm::TargetInstrInfo::minLatency ( MachineOpCode  Opcode  )  const [inline, virtual]

Definition at line 316 of file TargetInstrInfo.h.

References get(), and llvm::TargetInstrDescriptor::latency.

virtual MachineBasicBlock::iterator llvm::TargetInstrInfo::reverseBranchCondition ( MachineBasicBlock::iterator  MI  )  const [inline, virtual]

Reverses the branch condition of the MachineInstr pointed by MI. The instruction is replaced and the new MI is returned.

Reimplemented in llvm::X86InstrInfo.

Definition at line 270 of file TargetInstrInfo.h.

References abort().

bool llvm::TargetInstrInfo::usesCustomDAGSchedInsertionHook ( unsigned  Opcode  )  const [inline]

usesCustomDAGSchedInsertionHook - Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.

Definition at line 204 of file TargetInstrInfo.h.

References llvm::TargetInstrDescriptor::Flags, get(), and llvm::M_USES_CUSTOM_DAG_SCHED_INSERTION.


The documentation for this class was generated from the following files: