LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Register Information Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 namespace { // Register classes... 00012 // F4RC Register Class... 00013 const unsigned F4RC[] = { 00014 Alpha::F0, Alpha::F1, Alpha::F10, Alpha::F11, Alpha::F12, Alpha::F13, Alpha::F14, Alpha::F15, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21, Alpha::F22, Alpha::F23, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, Alpha::F2, Alpha::F3, Alpha::F4, Alpha::F5, Alpha::F6, Alpha::F7, Alpha::F8, Alpha::F9, Alpha::F31, 00015 }; 00016 00017 // F8RC Register Class... 00018 const unsigned F8RC[] = { 00019 Alpha::F0, Alpha::F1, Alpha::F10, Alpha::F11, Alpha::F12, Alpha::F13, Alpha::F14, Alpha::F15, Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21, Alpha::F22, Alpha::F23, Alpha::F24, Alpha::F25, Alpha::F26, Alpha::F27, Alpha::F28, Alpha::F29, Alpha::F30, Alpha::F2, Alpha::F3, Alpha::F4, Alpha::F5, Alpha::F6, Alpha::F7, Alpha::F8, Alpha::F9, Alpha::F31, 00020 }; 00021 00022 // GPRC Register Class... 00023 const unsigned GPRC[] = { 00024 Alpha::R0, Alpha::R1, Alpha::R2, Alpha::R3, Alpha::R4, Alpha::R5, Alpha::R6, Alpha::R7, Alpha::R8, Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21, Alpha::R22, Alpha::R23, Alpha::R24, Alpha::R25, Alpha::R28, Alpha::R27, Alpha::R26, Alpha::R29, Alpha::R9, Alpha::R10, Alpha::R11, Alpha::R12, Alpha::R13, Alpha::R14, Alpha::R15, Alpha::R30, Alpha::R31, 00025 }; 00026 00027 // F4RCVTs Register Class Value Types... 00028 const MVT::ValueType F4RCVTs[] = { 00029 MVT::f32, MVT::Other 00030 }; 00031 00032 // F8RCVTs Register Class Value Types... 00033 const MVT::ValueType F8RCVTs[] = { 00034 MVT::f64, MVT::Other 00035 }; 00036 00037 // GPRCVTs Register Class Value Types... 00038 const MVT::ValueType GPRCVTs[] = { 00039 MVT::i64, MVT::Other 00040 }; 00041 00042 } // end anonymous namespace 00043 00044 namespace Alpha { // Register class instances 00045 F4RCClass F4RCRegClass; 00046 F8RCClass F8RCRegClass; 00047 GPRCClass GPRCRegClass; 00048 00049 F4RCClass::iterator 00050 F4RCClass::allocation_order_end(MachineFunction &MF) const { 00051 return end()-1; 00052 } 00053 00054 F4RCClass::F4RCClass() : TargetRegisterClass(F4RCVTs, 4, 8, F4RC, F4RC + 32) {} 00055 00056 F8RCClass::iterator 00057 F8RCClass::allocation_order_end(MachineFunction &MF) const { 00058 return end()-1; 00059 } 00060 00061 F8RCClass::F8RCClass() : TargetRegisterClass(F8RCVTs, 8, 8, F8RC, F8RC + 32) {} 00062 00063 GPRCClass::iterator 00064 GPRCClass::allocation_order_end(MachineFunction &MF) const { 00065 return end()-3; 00066 } 00067 00068 GPRCClass::GPRCClass() : TargetRegisterClass(GPRCVTs, 8, 8, GPRC, GPRC + 32) {} 00069 } 00070 00071 namespace { 00072 const TargetRegisterClass* const RegisterClasses[] = { 00073 &Alpha::F4RCRegClass, 00074 &Alpha::F8RCRegClass, 00075 &Alpha::GPRCRegClass, 00076 }; 00077 const unsigned Empty_AliasSet[] = { 0 }; 00078 00079 const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors 00080 { "NOREG", 0 }, 00081 { "$f0", Empty_AliasSet }, 00082 { "$f1", Empty_AliasSet }, 00083 { "$f10", Empty_AliasSet }, 00084 { "$f11", Empty_AliasSet }, 00085 { "$f12", Empty_AliasSet }, 00086 { "$f13", Empty_AliasSet }, 00087 { "$f14", Empty_AliasSet }, 00088 { "$f15", Empty_AliasSet }, 00089 { "$f16", Empty_AliasSet }, 00090 { "$f17", Empty_AliasSet }, 00091 { "$f18", Empty_AliasSet }, 00092 { "$f19", Empty_AliasSet }, 00093 { "$f2", Empty_AliasSet }, 00094 { "$f20", Empty_AliasSet }, 00095 { "$f21", Empty_AliasSet }, 00096 { "$f22", Empty_AliasSet }, 00097 { "$f23", Empty_AliasSet }, 00098 { "$f24", Empty_AliasSet }, 00099 { "$f25", Empty_AliasSet }, 00100 { "$f26", Empty_AliasSet }, 00101 { "$f27", Empty_AliasSet }, 00102 { "$f28", Empty_AliasSet }, 00103 { "$f29", Empty_AliasSet }, 00104 { "$f3", Empty_AliasSet }, 00105 { "$f30", Empty_AliasSet }, 00106 { "$f31", Empty_AliasSet }, 00107 { "$f4", Empty_AliasSet }, 00108 { "$f5", Empty_AliasSet }, 00109 { "$f6", Empty_AliasSet }, 00110 { "$f7", Empty_AliasSet }, 00111 { "$f8", Empty_AliasSet }, 00112 { "$f9", Empty_AliasSet }, 00113 { "$0", Empty_AliasSet }, 00114 { "$1", Empty_AliasSet }, 00115 { "$10", Empty_AliasSet }, 00116 { "$11", Empty_AliasSet }, 00117 { "$12", Empty_AliasSet }, 00118 { "$13", Empty_AliasSet }, 00119 { "$14", Empty_AliasSet }, 00120 { "$15", Empty_AliasSet }, 00121 { "$16", Empty_AliasSet }, 00122 { "$17", Empty_AliasSet }, 00123 { "$18", Empty_AliasSet }, 00124 { "$19", Empty_AliasSet }, 00125 { "$2", Empty_AliasSet }, 00126 { "$20", Empty_AliasSet }, 00127 { "$21", Empty_AliasSet }, 00128 { "$22", Empty_AliasSet }, 00129 { "$23", Empty_AliasSet }, 00130 { "$24", Empty_AliasSet }, 00131 { "$25", Empty_AliasSet }, 00132 { "$26", Empty_AliasSet }, 00133 { "$27", Empty_AliasSet }, 00134 { "$28", Empty_AliasSet }, 00135 { "$29", Empty_AliasSet }, 00136 { "$3", Empty_AliasSet }, 00137 { "$30", Empty_AliasSet }, 00138 { "$31", Empty_AliasSet }, 00139 { "$4", Empty_AliasSet }, 00140 { "$5", Empty_AliasSet }, 00141 { "$6", Empty_AliasSet }, 00142 { "$7", Empty_AliasSet }, 00143 { "$8", Empty_AliasSet }, 00144 { "$9", Empty_AliasSet }, 00145 }; 00146 } 00147 00148 AlphaGenRegisterInfo::AlphaGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode) 00149 : MRegisterInfo(RegisterDescriptors, 65, RegisterClasses, RegisterClasses+3, 00150 CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 00151 00152 const unsigned* AlphaGenRegisterInfo::getCalleeSaveRegs() const { 00153 static const unsigned CalleeSaveRegs[] = { 00154 Alpha::R9, Alpha::R10, Alpha::R11, Alpha::R12, Alpha::R13, Alpha::R14, Alpha::F2, Alpha::F3, Alpha::F4, Alpha::F5, Alpha::F6, Alpha::F7, Alpha::F8, Alpha::F9, 0 00155 }; 00156 return CalleeSaveRegs; 00157 } 00158 00159 const TargetRegisterClass* const* 00160 AlphaGenRegisterInfo::getCalleeSaveRegClasses() const { 00161 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 00162 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0 00163 }; 00164 return CalleeSaveRegClasses; 00165 } 00166 00167 int AlphaGenRegisterInfo::getDwarfRegNum(unsigned RegNum) const { 00168 static const int DwarfRegNums[] = { -1, // NoRegister 00169 33, 34, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 35, 53, 54, 55, 00170 56, 57, 58, 59, 60, 61, 62, 36, 63, 64, 37, 38, 39, 40, 41, 42, 00171 0, 1, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 2, 20, 21, 22, 00172 23, 24, 25, 26, 27, 28, 29, 3, 30, 31, 4, 5, 6, 7, 8, 9 00173 }; 00174 assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) && 00175 "RegNum exceeds number of registers"); 00176 return DwarfRegNums[RegNum]; 00177 } 00178 00179 } // End llvm namespace