LLVM API Documentation
00001 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file describes how to lower LLVM code to machine code. This has two 00011 // main components: 00012 // 00013 // 1. Which ValueTypes are natively supported by the target. 00014 // 2. Which operations are supported for supported ValueTypes. 00015 // 3. Cost thresholds for alternative implementations of certain operations. 00016 // 00017 // In addition it has a few other components, like information about FP 00018 // immediates. 00019 // 00020 //===----------------------------------------------------------------------===// 00021 00022 #ifndef LLVM_TARGET_TARGETLOWERING_H 00023 #define LLVM_TARGET_TARGETLOWERING_H 00024 00025 #include "llvm/Type.h" 00026 #include "llvm/CodeGen/SelectionDAGNodes.h" 00027 #include <map> 00028 00029 namespace llvm { 00030 class Value; 00031 class Function; 00032 class TargetMachine; 00033 class TargetData; 00034 class TargetRegisterClass; 00035 class SDNode; 00036 class SDOperand; 00037 class SelectionDAG; 00038 class MachineBasicBlock; 00039 class MachineInstr; 00040 00041 //===----------------------------------------------------------------------===// 00042 /// TargetLowering - This class defines information used to lower LLVM code to 00043 /// legal SelectionDAG operators that the target instruction selector can accept 00044 /// natively. 00045 /// 00046 /// This class also defines callbacks that targets must implement to lower 00047 /// target-specific constructs to SelectionDAG operators. 00048 /// 00049 class TargetLowering { 00050 public: 00051 /// LegalizeAction - This enum indicates whether operations are valid for a 00052 /// target, and if not, what action should be used to make them valid. 00053 enum LegalizeAction { 00054 Legal, // The target natively supports this operation. 00055 Promote, // This operation should be executed in a larger type. 00056 Expand, // Try to expand this to other ops, otherwise use a libcall. 00057 Custom // Use the LowerOperation hook to implement custom lowering. 00058 }; 00059 00060 enum OutOfRangeShiftAmount { 00061 Undefined, // Oversized shift amounts are undefined (default). 00062 Mask, // Shift amounts are auto masked (anded) to value size. 00063 Extend // Oversized shift pulls in zeros or sign bits. 00064 }; 00065 00066 enum SetCCResultValue { 00067 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 00068 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 00069 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 00070 }; 00071 00072 enum SchedPreference { 00073 SchedulingForLatency, // Scheduling for shortest total latency. 00074 SchedulingForRegPressure // Scheduling for lowest register pressure. 00075 }; 00076 00077 TargetLowering(TargetMachine &TM); 00078 virtual ~TargetLowering(); 00079 00080 TargetMachine &getTargetMachine() const { return TM; } 00081 const TargetData &getTargetData() const { return TD; } 00082 00083 bool isLittleEndian() const { return IsLittleEndian; } 00084 MVT::ValueType getPointerTy() const { return PointerTy; } 00085 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 00086 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 00087 00088 /// isSetCCExpensive - Return true if the setcc operation is expensive for 00089 /// this target. 00090 bool isSetCCExpensive() const { return SetCCIsExpensive; } 00091 00092 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 00093 /// a sequence of several shifts, adds, and multiplies for this target. 00094 bool isIntDivCheap() const { return IntDivIsCheap; } 00095 00096 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 00097 /// srl/add/sra. 00098 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 00099 00100 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 00101 /// 00102 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 00103 00104 /// getSetCCResultContents - For targets without boolean registers, this flag 00105 /// returns information about the contents of the high-bits in the setcc 00106 /// result register. 00107 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 00108 00109 /// getSchedulingPreference - Return target scheduling preference. 00110 SchedPreference getSchedulingPreference() const { 00111 return SchedPreferenceInfo; 00112 } 00113 00114 /// getRegClassFor - Return the register class that should be used for the 00115 /// specified value type. This may only be called on legal types. 00116 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 00117 TargetRegisterClass *RC = RegClassForVT[VT]; 00118 assert(RC && "This value type is not natively supported!"); 00119 return RC; 00120 } 00121 00122 /// isTypeLegal - Return true if the target has native support for the 00123 /// specified value type. This means that it has a register that directly 00124 /// holds it without promotions or expansions. 00125 bool isTypeLegal(MVT::ValueType VT) const { 00126 return RegClassForVT[VT] != 0; 00127 } 00128 00129 class ValueTypeActionImpl { 00130 /// ValueTypeActions - This is a bitvector that contains two bits for each 00131 /// value type, where the two bits correspond to the LegalizeAction enum. 00132 /// This can be queried with "getTypeAction(VT)". 00133 uint32_t ValueTypeActions[2]; 00134 public: 00135 ValueTypeActionImpl() { 00136 ValueTypeActions[0] = ValueTypeActions[1] = 0; 00137 } 00138 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 00139 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 00140 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 00141 } 00142 00143 LegalizeAction getTypeAction(MVT::ValueType VT) const { 00144 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 00145 } 00146 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 00147 assert(unsigned(VT >> 4) < 00148 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 00149 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 00150 } 00151 }; 00152 00153 const ValueTypeActionImpl &getValueTypeActions() const { 00154 return ValueTypeActions; 00155 } 00156 00157 /// getTypeAction - Return how we should legalize values of this type, either 00158 /// it is already legal (return 'Legal') or we need to promote it to a larger 00159 /// type (return 'Promote'), or we need to expand it into multiple registers 00160 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 00161 LegalizeAction getTypeAction(MVT::ValueType VT) const { 00162 return ValueTypeActions.getTypeAction(VT); 00163 } 00164 00165 /// getTypeToTransformTo - For types supported by the target, this is an 00166 /// identity function. For types that must be promoted to larger types, this 00167 /// returns the larger type to promote to. For types that are larger than the 00168 /// largest integer register, this contains one step in the expansion to get 00169 /// to the smaller register. 00170 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 00171 return TransformToType[VT]; 00172 } 00173 00174 /// getPackedTypeBreakdown - Packed types are broken down into some number of 00175 /// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values 00176 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 00177 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. 00178 /// 00179 /// This method returns the number of registers needed, and the VT for each 00180 /// register. It also returns the VT of the PackedType elements before they 00181 /// are promoted/expanded. 00182 /// 00183 unsigned getPackedTypeBreakdown(const PackedType *PTy, 00184 MVT::ValueType &PTyElementVT, 00185 MVT::ValueType &PTyLegalElementVT) const; 00186 00187 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 00188 legal_fpimm_iterator legal_fpimm_begin() const { 00189 return LegalFPImmediates.begin(); 00190 } 00191 legal_fpimm_iterator legal_fpimm_end() const { 00192 return LegalFPImmediates.end(); 00193 } 00194 00195 /// isShuffleMaskLegal - Targets can use this to indicate that they only 00196 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 00197 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 00198 /// are assumed to be legal. 00199 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 00200 return true; 00201 } 00202 00203 /// getOperationAction - Return how this operation should be treated: either 00204 /// it is legal, needs to be promoted to a larger size, needs to be 00205 /// expanded to some other code sequence, or the target has a custom expander 00206 /// for it. 00207 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 00208 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 00209 } 00210 00211 /// isOperationLegal - Return true if the specified operation is legal on this 00212 /// target. 00213 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 00214 return getOperationAction(Op, VT) == Legal || 00215 getOperationAction(Op, VT) == Custom; 00216 } 00217 00218 /// getTypeToPromoteTo - If the action for this operation is to promote, this 00219 /// method returns the ValueType to promote to. 00220 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 00221 assert(getOperationAction(Op, VT) == Promote && 00222 "This operation isn't promoted!"); 00223 00224 // See if this has an explicit type specified. 00225 std::map<std::pair<unsigned, MVT::ValueType>, 00226 MVT::ValueType>::const_iterator PTTI = 00227 PromoteToType.find(std::make_pair(Op, VT)); 00228 if (PTTI != PromoteToType.end()) return PTTI->second; 00229 00230 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 00231 "Cannot autopromote this type, add it with AddPromotedToType."); 00232 00233 MVT::ValueType NVT = VT; 00234 do { 00235 NVT = (MVT::ValueType)(NVT+1); 00236 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 00237 "Didn't find type to promote to!"); 00238 } while (!isTypeLegal(NVT) || 00239 getOperationAction(Op, NVT) == Promote); 00240 return NVT; 00241 } 00242 00243 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 00244 /// This is fixed by the LLVM operations except for the pointer size. 00245 MVT::ValueType getValueType(const Type *Ty) const { 00246 switch (Ty->getTypeID()) { 00247 default: assert(0 && "Unknown type!"); 00248 case Type::VoidTyID: return MVT::isVoid; 00249 case Type::BoolTyID: return MVT::i1; 00250 case Type::UByteTyID: 00251 case Type::SByteTyID: return MVT::i8; 00252 case Type::ShortTyID: 00253 case Type::UShortTyID: return MVT::i16; 00254 case Type::IntTyID: 00255 case Type::UIntTyID: return MVT::i32; 00256 case Type::LongTyID: 00257 case Type::ULongTyID: return MVT::i64; 00258 case Type::FloatTyID: return MVT::f32; 00259 case Type::DoubleTyID: return MVT::f64; 00260 case Type::PointerTyID: return PointerTy; 00261 case Type::PackedTyID: return MVT::Vector; 00262 } 00263 } 00264 00265 /// getNumElements - Return the number of registers that this ValueType will 00266 /// eventually require. This is always one for all non-integer types, is 00267 /// one for any types promoted to live in larger registers, but may be more 00268 /// than one for types (like i64) that are split into pieces. 00269 unsigned getNumElements(MVT::ValueType VT) const { 00270 return NumElementsForVT[VT]; 00271 } 00272 00273 /// hasTargetDAGCombine - If true, the target has custom DAG combine 00274 /// transformations that it can perform for the specified node. 00275 bool hasTargetDAGCombine(ISD::NodeType NT) const { 00276 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 00277 } 00278 00279 /// This function returns the maximum number of store operations permitted 00280 /// to replace a call to llvm.memset. The value is set by the target at the 00281 /// performance threshold for such a replacement. 00282 /// @brief Get maximum # of store operations permitted for llvm.memset 00283 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 00284 00285 /// This function returns the maximum number of store operations permitted 00286 /// to replace a call to llvm.memcpy. The value is set by the target at the 00287 /// performance threshold for such a replacement. 00288 /// @brief Get maximum # of store operations permitted for llvm.memcpy 00289 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 00290 00291 /// This function returns the maximum number of store operations permitted 00292 /// to replace a call to llvm.memmove. The value is set by the target at the 00293 /// performance threshold for such a replacement. 00294 /// @brief Get maximum # of store operations permitted for llvm.memmove 00295 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 00296 00297 /// This function returns true if the target allows unaligned memory accesses. 00298 /// This is used, for example, in situations where an array copy/move/set is 00299 /// converted to a sequence of store operations. It's use helps to ensure that 00300 /// such replacements don't generate code that causes an alignment error 00301 /// (trap) on the target machine. 00302 /// @brief Determine if the target supports unaligned memory accesses. 00303 bool allowsUnalignedMemoryAccesses() const { 00304 return allowUnalignedMemoryAccesses; 00305 } 00306 00307 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp 00308 /// to implement llvm.setjmp. 00309 bool usesUnderscoreSetJmpLongJmp() const { 00310 return UseUnderscoreSetJmpLongJmp; 00311 } 00312 00313 /// getStackPointerRegisterToSaveRestore - If a physical register, this 00314 /// specifies the register that llvm.savestack/llvm.restorestack should save 00315 /// and restore. 00316 unsigned getStackPointerRegisterToSaveRestore() const { 00317 return StackPointerRegisterToSaveRestore; 00318 } 00319 00320 //===--------------------------------------------------------------------===// 00321 // TargetLowering Optimization Methods 00322 // 00323 00324 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 00325 /// SDOperands for returning information from TargetLowering to its clients 00326 /// that want to combine 00327 struct TargetLoweringOpt { 00328 SelectionDAG &DAG; 00329 SDOperand Old; 00330 SDOperand New; 00331 00332 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 00333 00334 bool CombineTo(SDOperand O, SDOperand N) { 00335 Old = O; 00336 New = N; 00337 return true; 00338 } 00339 00340 /// ShrinkDemandedConstant - Check to see if the specified operand of the 00341 /// specified instruction is a constant integer. If so, check to see if there 00342 /// are any bits set in the constant that are not demanded. If so, shrink the 00343 /// constant and return true. 00344 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 00345 }; 00346 00347 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 00348 /// use this predicate to simplify operations downstream. Op and Mask are 00349 /// known to be the same type. 00350 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 00351 const; 00352 00353 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 00354 /// known to be either zero or one and return them in the KnownZero/KnownOne 00355 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 00356 /// processing. Targets can implement the computeMaskedBitsForTargetNode 00357 /// method, to allow target nodes to be understood. 00358 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 00359 uint64_t &KnownOne, unsigned Depth = 0) const; 00360 00361 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 00362 /// DemandedMask bits of the result of Op are ever used downstream. If we can 00363 /// use this information to simplify Op, create a new simplified DAG node and 00364 /// return true, returning the original and new nodes in Old and New. 00365 /// Otherwise, analyze the expression and return a mask of KnownOne and 00366 /// KnownZero bits for the expression (used to simplify the caller). 00367 /// The KnownZero/One bits may only be accurate for those bits in the 00368 /// DemandedMask. 00369 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 00370 uint64_t &KnownZero, uint64_t &KnownOne, 00371 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 00372 00373 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 00374 /// Mask are known to be either zero or one and return them in the 00375 /// KnownZero/KnownOne bitsets. 00376 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 00377 uint64_t Mask, 00378 uint64_t &KnownZero, 00379 uint64_t &KnownOne, 00380 unsigned Depth = 0) const; 00381 00382 struct DAGCombinerInfo { 00383 void *DC; // The DAG Combiner object. 00384 bool BeforeLegalize; 00385 public: 00386 SelectionDAG &DAG; 00387 00388 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc) 00389 : DC(dc), BeforeLegalize(bl), DAG(dag) {} 00390 00391 bool isBeforeLegalize() const { return BeforeLegalize; } 00392 00393 void AddToWorklist(SDNode *N); 00394 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 00395 SDOperand CombineTo(SDNode *N, SDOperand Res); 00396 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 00397 }; 00398 00399 /// PerformDAGCombine - This method will be invoked for all target nodes and 00400 /// for any target-independent nodes that the target has registered with 00401 /// invoke it for. 00402 /// 00403 /// The semantics are as follows: 00404 /// Return Value: 00405 /// SDOperand.Val == 0 - No change was made 00406 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 00407 /// otherwise - N should be replaced by the returned Operand. 00408 /// 00409 /// In addition, methods provided by DAGCombinerInfo may be used to perform 00410 /// more complex transformations. 00411 /// 00412 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 00413 00414 //===--------------------------------------------------------------------===// 00415 // TargetLowering Configuration Methods - These methods should be invoked by 00416 // the derived class constructor to configure this object for the target. 00417 // 00418 00419 protected: 00420 00421 /// setShiftAmountType - Describe the type that should be used for shift 00422 /// amounts. This type defaults to the pointer type. 00423 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 00424 00425 /// setSetCCResultType - Describe the type that shoudl be used as the result 00426 /// of a setcc operation. This defaults to the pointer type. 00427 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 00428 00429 /// setSetCCResultContents - Specify how the target extends the result of a 00430 /// setcc operation in a register. 00431 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 00432 00433 /// setSchedulingPreference - Specify the target scheduling preference. 00434 void setSchedulingPreference(SchedPreference Pref) { 00435 SchedPreferenceInfo = Pref; 00436 } 00437 00438 /// setShiftAmountFlavor - Describe how the target handles out of range shift 00439 /// amounts. 00440 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 00441 ShiftAmtHandling = OORSA; 00442 } 00443 00444 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to 00445 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or 00446 /// the non _ versions. Defaults to false. 00447 void setUseUnderscoreSetJmpLongJmp(bool Val) { 00448 UseUnderscoreSetJmpLongJmp = Val; 00449 } 00450 00451 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 00452 /// specifies the register that llvm.savestack/llvm.restorestack should save 00453 /// and restore. 00454 void setStackPointerRegisterToSaveRestore(unsigned R) { 00455 StackPointerRegisterToSaveRestore = R; 00456 } 00457 00458 /// setSetCCIxExpensive - This is a short term hack for targets that codegen 00459 /// setcc as a conditional branch. This encourages the code generator to fold 00460 /// setcc operations into other operations if possible. 00461 void setSetCCIsExpensive() { SetCCIsExpensive = true; } 00462 00463 /// setIntDivIsCheap - Tells the code generator that integer divide is 00464 /// expensive, and if possible, should be replaced by an alternate sequence 00465 /// of instructions not containing an integer divide. 00466 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 00467 00468 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 00469 /// srl/add/sra for a signed divide by power of two, and let the target handle 00470 /// it. 00471 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 00472 00473 /// addRegisterClass - Add the specified register class as an available 00474 /// regclass for the specified value type. This indicates the selector can 00475 /// handle values of that class natively. 00476 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 00477 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 00478 RegClassForVT[VT] = RC; 00479 } 00480 00481 /// computeRegisterProperties - Once all of the register classes are added, 00482 /// this allows us to compute derived properties we expose. 00483 void computeRegisterProperties(); 00484 00485 /// setOperationAction - Indicate that the specified operation does not work 00486 /// with the specified type and indicate what to do about it. 00487 void setOperationAction(unsigned Op, MVT::ValueType VT, 00488 LegalizeAction Action) { 00489 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 00490 "Table isn't big enough!"); 00491 OpActions[Op] &= ~(3ULL << VT*2); 00492 OpActions[Op] |= (uint64_t)Action << VT*2; 00493 } 00494 00495 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 00496 /// promotion code defaults to trying a larger integer/fp until it can find 00497 /// one that works. If that default is insufficient, this method can be used 00498 /// by the target to override the default. 00499 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 00500 MVT::ValueType DestVT) { 00501 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 00502 } 00503 00504 /// addLegalFPImmediate - Indicate that this target can instruction select 00505 /// the specified FP immediate natively. 00506 void addLegalFPImmediate(double Imm) { 00507 LegalFPImmediates.push_back(Imm); 00508 } 00509 00510 /// setTargetDAGCombine - Targets should invoke this method for each target 00511 /// independent node that they want to provide a custom DAG combiner for by 00512 /// implementing the PerformDAGCombine virtual method. 00513 void setTargetDAGCombine(ISD::NodeType NT) { 00514 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 00515 } 00516 00517 public: 00518 00519 //===--------------------------------------------------------------------===// 00520 // Lowering methods - These methods must be implemented by targets so that 00521 // the SelectionDAGLowering code knows how to lower these. 00522 // 00523 00524 /// LowerArguments - This hook must be implemented to indicate how we should 00525 /// lower the arguments for the specified function, into the specified DAG. 00526 virtual std::vector<SDOperand> 00527 LowerArguments(Function &F, SelectionDAG &DAG); 00528 00529 /// LowerCallTo - This hook lowers an abstract call to a function into an 00530 /// actual call. This returns a pair of operands. The first element is the 00531 /// return value for the function (if RetTy is not VoidTy). The second 00532 /// element is the outgoing token chain. 00533 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy; 00534 virtual std::pair<SDOperand, SDOperand> 00535 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 00536 unsigned CallingConv, bool isTailCall, SDOperand Callee, 00537 ArgListTy &Args, SelectionDAG &DAG) = 0; 00538 00539 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or 00540 /// llvm.frameaddress (depending on the value of the first argument). The 00541 /// return values are the result pointer and the resultant token chain. If 00542 /// not implemented, both of these intrinsics will return null. 00543 virtual std::pair<SDOperand, SDOperand> 00544 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 00545 SelectionDAG &DAG); 00546 00547 /// LowerOperation - This callback is invoked for operations that are 00548 /// unsupported by the target, which are registered to use 'custom' lowering, 00549 /// and whose defined values are all legal. 00550 /// If the target has no operations that require custom lowering, it need not 00551 /// implement this. The default implementation of this aborts. 00552 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 00553 00554 /// CustomPromoteOperation - This callback is invoked for operations that are 00555 /// unsupported by the target, are registered to use 'custom' lowering, and 00556 /// whose type needs to be promoted. 00557 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 00558 00559 /// getTargetNodeName() - This method returns the name of a target specific 00560 /// DAG node. 00561 virtual const char *getTargetNodeName(unsigned Opcode) const; 00562 00563 //===--------------------------------------------------------------------===// 00564 // Inline Asm Support hooks 00565 // 00566 00567 enum ConstraintType { 00568 C_Register, // Constraint represents a single register. 00569 C_RegisterClass, // Constraint represents one or more registers. 00570 C_Memory, // Memory constraint. 00571 C_Other, // Something else. 00572 C_Unknown // Unsupported constraint. 00573 }; 00574 00575 /// getConstraintType - Given a constraint letter, return the type of 00576 /// constraint it is for this target. 00577 virtual ConstraintType getConstraintType(char ConstraintLetter) const; 00578 00579 00580 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 00581 /// return a list of registers that can be used to satisfy the constraint. 00582 /// This should only be used for C_RegisterClass constraints. 00583 virtual std::vector<unsigned> 00584 getRegClassForInlineAsmConstraint(const std::string &Constraint, 00585 MVT::ValueType VT) const; 00586 00587 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 00588 /// {edx}), return the register number and the register class for the 00589 /// register. This should only be used for C_Register constraints. On error, 00590 /// this returns a register number of 0. 00591 virtual std::pair<unsigned, const TargetRegisterClass*> 00592 getRegForInlineAsmConstraint(const std::string &Constraint, 00593 MVT::ValueType VT) const; 00594 00595 00596 /// isOperandValidForConstraint - Return true if the specified SDOperand is 00597 /// valid for the specified target constraint letter. 00598 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 00599 00600 //===--------------------------------------------------------------------===// 00601 // Scheduler hooks 00602 // 00603 00604 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 00605 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 00606 // instructions are special in various ways, which require special support to 00607 // insert. The specified MachineInstr is created but not inserted into any 00608 // basic blocks, and the scheduler passes ownership of it to this method. 00609 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 00610 MachineBasicBlock *MBB); 00611 00612 //===--------------------------------------------------------------------===// 00613 // Loop Strength Reduction hooks 00614 // 00615 00616 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue 00617 /// can be used as the offset of the target addressing mode. 00618 virtual bool isLegalAddressImmediate(int64_t V) const; 00619 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 00620 00621 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator; 00622 legal_am_scale_iterator legal_am_scale_begin() const { 00623 return LegalAddressScales.begin(); 00624 } 00625 legal_am_scale_iterator legal_am_scale_end() const { 00626 return LegalAddressScales.end(); 00627 } 00628 00629 protected: 00630 /// addLegalAddressScale - Add a integer (> 1) value which can be used as 00631 /// scale in the target addressing mode. Note: the ordering matters so the 00632 /// least efficient ones should be entered first. 00633 void addLegalAddressScale(unsigned Scale) { 00634 LegalAddressScales.push_back(Scale); 00635 } 00636 00637 private: 00638 std::vector<unsigned> LegalAddressScales; 00639 00640 TargetMachine &TM; 00641 const TargetData &TD; 00642 00643 /// IsLittleEndian - True if this is a little endian target. 00644 /// 00645 bool IsLittleEndian; 00646 00647 /// PointerTy - The type to use for pointers, usually i32 or i64. 00648 /// 00649 MVT::ValueType PointerTy; 00650 00651 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 00652 /// PointerTy is. 00653 MVT::ValueType ShiftAmountTy; 00654 00655 OutOfRangeShiftAmount ShiftAmtHandling; 00656 00657 /// SetCCIsExpensive - This is a short term hack for targets that codegen 00658 /// setcc as a conditional branch. This encourages the code generator to fold 00659 /// setcc operations into other operations if possible. 00660 bool SetCCIsExpensive; 00661 00662 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 00663 /// constants into a sequence of muls, adds, and shifts. This is a hack until 00664 /// a real cost model is in place. If we ever optimize for size, this will be 00665 /// set to true unconditionally. 00666 bool IntDivIsCheap; 00667 00668 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 00669 /// srl/add/sra for a signed divide by power of two, and let the target handle 00670 /// it. 00671 bool Pow2DivIsCheap; 00672 00673 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 00674 /// PointerTy. 00675 MVT::ValueType SetCCResultTy; 00676 00677 /// SetCCResultContents - Information about the contents of the high-bits in 00678 /// the result of a setcc comparison operation. 00679 SetCCResultValue SetCCResultContents; 00680 00681 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 00682 /// total cycles or lowest register usage. 00683 SchedPreference SchedPreferenceInfo; 00684 00685 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and 00686 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false. 00687 bool UseUnderscoreSetJmpLongJmp; 00688 00689 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 00690 /// specifies the register that llvm.savestack/llvm.restorestack should save 00691 /// and restore. 00692 unsigned StackPointerRegisterToSaveRestore; 00693 00694 /// RegClassForVT - This indicates the default register class to use for 00695 /// each ValueType the target supports natively. 00696 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 00697 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 00698 00699 /// TransformToType - For any value types we are promoting or expanding, this 00700 /// contains the value type that we are changing to. For Expanded types, this 00701 /// contains one step of the expand (e.g. i64 -> i32), even if there are 00702 /// multiple steps required (e.g. i64 -> i16). For types natively supported 00703 /// by the system, this holds the same type (e.g. i32 -> i32). 00704 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 00705 00706 /// OpActions - For each operation and each value type, keep a LegalizeAction 00707 /// that indicates how instruction selection should deal with the operation. 00708 /// Most operations are Legal (aka, supported natively by the target), but 00709 /// operations that are not should be described. Note that operations on 00710 /// non-legal value types are not described here. 00711 uint64_t OpActions[156]; 00712 00713 ValueTypeActionImpl ValueTypeActions; 00714 00715 std::vector<double> LegalFPImmediates; 00716 00717 std::vector<std::pair<MVT::ValueType, 00718 TargetRegisterClass*> > AvailableRegClasses; 00719 00720 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 00721 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 00722 /// which sets a bit in this array. 00723 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 00724 00725 /// PromoteToType - For operations that must be promoted to a specific type, 00726 /// this holds the destination type. This map should be sparse, so don't hold 00727 /// it as an array. 00728 /// 00729 /// Targets add entries to this map with AddPromotedToType(..), clients access 00730 /// this with getTypeToPromoteTo(..). 00731 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 00732 00733 protected: 00734 /// When lowering %llvm.memset this field specifies the maximum number of 00735 /// store operations that may be substituted for the call to memset. Targets 00736 /// must set this value based on the cost threshold for that target. Targets 00737 /// should assume that the memset will be done using as many of the largest 00738 /// store operations first, followed by smaller ones, if necessary, per 00739 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 00740 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 00741 /// store. This only applies to setting a constant array of a constant size. 00742 /// @brief Specify maximum number of store instructions per memset call. 00743 unsigned maxStoresPerMemset; 00744 00745 /// When lowering %llvm.memcpy this field specifies the maximum number of 00746 /// store operations that may be substituted for a call to memcpy. Targets 00747 /// must set this value based on the cost threshold for that target. Targets 00748 /// should assume that the memcpy will be done using as many of the largest 00749 /// store operations first, followed by smaller ones, if necessary, per 00750 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 00751 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 00752 /// and one 1-byte store. This only applies to copying a constant array of 00753 /// constant size. 00754 /// @brief Specify maximum bytes of store instructions per memcpy call. 00755 unsigned maxStoresPerMemcpy; 00756 00757 /// When lowering %llvm.memmove this field specifies the maximum number of 00758 /// store instructions that may be substituted for a call to memmove. Targets 00759 /// must set this value based on the cost threshold for that target. Targets 00760 /// should assume that the memmove will be done using as many of the largest 00761 /// store operations first, followed by smaller ones, if necessary, per 00762 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 00763 /// with 8-bit alignment would result in nine 1-byte stores. This only 00764 /// applies to copying a constant array of constant size. 00765 /// @brief Specify maximum bytes of store instructions per memmove call. 00766 unsigned maxStoresPerMemmove; 00767 00768 /// This field specifies whether the target machine permits unaligned memory 00769 /// accesses. This is used, for example, to determine the size of store 00770 /// operations when copying small arrays and other similar tasks. 00771 /// @brief Indicate whether the target permits unaligned memory accesses. 00772 bool allowUnalignedMemoryAccesses; 00773 }; 00774 } // end llvm namespace 00775 00776 #endif