LLVM API Documentation
#include <ScheduleDAG.h>
Collaboration diagram for llvm::ScheduleDAG:
Public Member Functions | |
ScheduleDAG (SelectionDAG &dag, MachineBasicBlock *bb, const TargetMachine &tm) | |
virtual | ~ScheduleDAG () |
MachineBasicBlock * | Run () |
void | EmitNode (SDNode *Node, std::map< SDNode *, unsigned > &VRBaseMap) |
void | EmitNoop () |
virtual void | Schedule () |
Static Public Member Functions | |
static bool | isPassiveNode (SDNode *Node) |
Public Attributes | |
SelectionDAG & | DAG |
MachineBasicBlock * | BB |
const TargetMachine & | TM |
const TargetInstrInfo * | TII |
const MRegisterInfo * | MRI |
SSARegMap * | RegMap |
MachineConstantPool * | ConstPool |
Definition at line 74 of file ScheduleDAG.h.
llvm::ScheduleDAG::ScheduleDAG | ( | SelectionDAG & | dag, | |
MachineBasicBlock * | bb, | |||
const TargetMachine & | tm | |||
) | [inline] |
Definition at line 84 of file ScheduleDAG.h.
virtual llvm::ScheduleDAG::~ScheduleDAG | ( | ) | [inline, virtual] |
Definition at line 88 of file ScheduleDAG.h.
EmitNode - Generate machine code for an node and needed dependencies. VRBaseMap contains, for each already emitted node, the first virtual register number for the results of the node.
Definition at line 166 of file ScheduleDAG.cpp.
References llvm::MachineInstr::addExternalSymbolOperand(), llvm::MachineInstr::addMachineRegOperand(), llvm::MachineInstr::addRegOperand(), llvm::MachineInstr::addZeroExtImm64Operand(), BB, llvm::ISD::CopyFromReg, llvm::MRegisterInfo::copyRegToReg(), llvm::ISD::CopyToReg, CountOperands(), CountResults(), llvm::SSARegMap::createVirtualRegister(), CreateVirtualRegisters(), DAG, llvm::MachineOperand::Def, llvm::SDNode::dump(), E, llvm::MachineBasicBlock::end(), llvm::ISD::EntryToken, llvm::MVT::Flag, llvm::TargetInstrInfo::get(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SSARegMap::getRegClass(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getTargetOpcode(), llvm::SDOperand::getValueType(), llvm::SDNode::getValueType(), getVR(), I, II, llvm::TargetInstrInfo::INLINEASM, llvm::ISD::INLINEASM, llvm::MachineBasicBlock::insert(), llvm::TargetLowering::InsertAtEndOfBasicBlock(), llvm::SDNode::isTargetOpcode(), llvm::MRegisterInfo::isVirtualRegister(), llvm::M_USES_CUSTOM_DAG_SCHED_INSERTION, MI, MRI, Node, Reg, llvm::MRegisterInfo::regclass_begin(), llvm::MRegisterInfo::regclass_end(), RegMap, TII, llvm::ISD::TokenFactor, llvm::MachineOperand::Use, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and Val.
void ScheduleDAG::EmitNoop | ( | ) |
EmitNoop - Emit a noop instruction.
Definition at line 344 of file ScheduleDAG.cpp.
References BB, llvm::MachineBasicBlock::end(), llvm::TargetInstrInfo::insertNoop(), and TII.
static bool llvm::ScheduleDAG::isPassiveNode | ( | SDNode * | Node | ) | [inline, static] |
isPassiveNode - Return true if the node is a non-scheduled leaf.
Definition at line 96 of file ScheduleDAG.h.
References Node.
MachineBasicBlock * ScheduleDAG::Run | ( | ) |
Run - perform scheduling.
Definition at line 350 of file ScheduleDAG.cpp.
References BB, ConstPool, llvm::MachineFunction::getConstantPool(), llvm::TargetMachine::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::TargetMachine::getRegisterInfo(), llvm::MachineFunction::getSSARegMap(), MRI, RegMap, Schedule(), TII, and TM.
Referenced by llvm::SelectionDAGISel::ScheduleAndEmitDAG().
virtual void llvm::ScheduleDAG::Schedule | ( | ) | [inline, virtual] |
Schedule - Order nodes according to selected style.
Definition at line 120 of file ScheduleDAG.h.
Referenced by Run().