LLVM API Documentation

IA64ISelLowering.cpp

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00001 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by Duraid Madina and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the IA64ISelLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "IA64ISelLowering.h"
00015 #include "IA64MachineFunctionInfo.h"
00016 #include "IA64TargetMachine.h"
00017 #include "llvm/CodeGen/MachineFrameInfo.h"
00018 #include "llvm/CodeGen/MachineFunction.h"
00019 #include "llvm/CodeGen/MachineInstrBuilder.h"
00020 #include "llvm/CodeGen/SelectionDAG.h"
00021 #include "llvm/CodeGen/SSARegMap.h"
00022 #include "llvm/Constants.h"
00023 #include "llvm/Function.h"
00024 using namespace llvm;
00025 
00026 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
00027   : TargetLowering(TM) {
00028  
00029       // register class for general registers
00030       addRegisterClass(MVT::i64, IA64::GRRegisterClass);
00031 
00032       // register class for FP registers
00033       addRegisterClass(MVT::f64, IA64::FPRegisterClass);
00034 
00035       // register class for predicate registers
00036       addRegisterClass(MVT::i1, IA64::PRRegisterClass);
00037 
00038       setOperationAction(ISD::BR_CC            , MVT::Other, Expand);
00039       setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
00040 
00041       // ia64 uses SELECT not SELECT_CC
00042       setOperationAction(ISD::SELECT_CC        , MVT::Other,  Expand);
00043       
00044       // We need to handle ISD::RET for void functions ourselves,
00045       // so we get a chance to restore ar.pfs before adding a
00046       // br.ret insn
00047       setOperationAction(ISD::RET, MVT::Other, Custom);
00048 
00049       setSetCCResultType(MVT::i1);
00050       setShiftAmountType(MVT::i64);
00051 
00052       setOperationAction(ISD::EXTLOAD          , MVT::i1   , Promote);
00053 
00054       setOperationAction(ISD::ZEXTLOAD         , MVT::i1   , Expand);
00055 
00056       setOperationAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
00057       setOperationAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
00058       setOperationAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
00059       setOperationAction(ISD::SEXTLOAD         , MVT::i32  , Expand);
00060 
00061       setOperationAction(ISD::FREM             , MVT::f32  , Expand);
00062       setOperationAction(ISD::FREM             , MVT::f64  , Expand);
00063 
00064       setOperationAction(ISD::UREM             , MVT::f32  , Expand);
00065       setOperationAction(ISD::UREM             , MVT::f64  , Expand);
00066 
00067       setOperationAction(ISD::MEMMOVE          , MVT::Other, Expand);
00068       setOperationAction(ISD::MEMSET           , MVT::Other, Expand);
00069       setOperationAction(ISD::MEMCPY           , MVT::Other, Expand);
00070       
00071       setOperationAction(ISD::SINT_TO_FP       , MVT::i1   , Promote);
00072       setOperationAction(ISD::UINT_TO_FP       , MVT::i1   , Promote);
00073 
00074       // We don't support sin/cos/sqrt
00075       setOperationAction(ISD::FSIN , MVT::f64, Expand);
00076       setOperationAction(ISD::FCOS , MVT::f64, Expand);
00077       setOperationAction(ISD::FSQRT, MVT::f64, Expand);
00078       setOperationAction(ISD::FSIN , MVT::f32, Expand);
00079       setOperationAction(ISD::FCOS , MVT::f32, Expand);
00080       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
00081 
00082       // FIXME: IA64 supports fcopysign natively!
00083       setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
00084       setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
00085       
00086       // We don't have line number support yet.
00087       setOperationAction(ISD::LOCATION, MVT::Other, Expand);
00088       setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
00089       setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
00090 
00091       //IA64 has these, but they are not implemented
00092       setOperationAction(ISD::CTTZ , MVT::i64  , Expand);
00093       setOperationAction(ISD::CTLZ , MVT::i64  , Expand);
00094       setOperationAction(ISD::ROTL , MVT::i64  , Expand);
00095       setOperationAction(ISD::ROTR , MVT::i64  , Expand);
00096       setOperationAction(ISD::BSWAP, MVT::i64  , Expand);  // mux @rev
00097 
00098       // VASTART needs to be custom lowered to use the VarArgsFrameIndex
00099       setOperationAction(ISD::VAARG             , MVT::Other, Custom);
00100       setOperationAction(ISD::VASTART           , MVT::Other, Custom);
00101       
00102       // Use the default implementation.
00103       setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
00104       setOperationAction(ISD::VAEND             , MVT::Other, Expand);
00105       setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
00106       setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
00107       setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
00108 
00109       setStackPointerRegisterToSaveRestore(IA64::r12);
00110 
00111       computeRegisterProperties();
00112 
00113       setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
00114       addLegalFPImmediate(+0.0);
00115       addLegalFPImmediate(+1.0);
00116 }
00117 
00118 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
00119   switch (Opcode) {
00120   default: return 0;
00121   case IA64ISD::GETFD:  return "IA64ISD::GETFD";
00122   case IA64ISD::BRCALL: return "IA64ISD::BRCALL";  
00123   case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
00124   }
00125 }
00126   
00127 
00128 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
00129 static bool isFloatingPointZero(SDOperand Op) {
00130   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
00131     return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
00132   else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
00133     // Maybe this has already been legalized into the constant pool?
00134     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
00135       if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
00136         return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
00137   }
00138   return false;
00139 }
00140 
00141 std::vector<SDOperand>
00142 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
00143   std::vector<SDOperand> ArgValues;
00144   //
00145   // add beautiful description of IA64 stack frame format
00146   // here (from intel 24535803.pdf most likely)
00147   //
00148   MachineFunction &MF = DAG.getMachineFunction();
00149   MachineFrameInfo *MFI = MF.getFrameInfo();
00150   
00151   GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
00152   SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
00153   RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
00154   
00155   MachineBasicBlock& BB = MF.front();
00156 
00157   unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
00158                          IA64::r36, IA64::r37, IA64::r38, IA64::r39};
00159 
00160   unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
00161                         IA64::F12,IA64::F13,IA64::F14, IA64::F15};
00162 
00163   unsigned argVreg[8];
00164   unsigned argPreg[8];
00165   unsigned argOpc[8];
00166 
00167   unsigned used_FPArgs = 0; // how many FP args have been used so far?
00168 
00169   unsigned ArgOffset = 0;
00170   int count = 0;
00171 
00172   for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
00173     {
00174       SDOperand newroot, argt;
00175       if(count < 8) { // need to fix this logic? maybe.
00176 
00177         switch (getValueType(I->getType())) {
00178           default:
00179             assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n"); 
00180           case MVT::f32:
00181             // fixme? (well, will need to for weird FP structy stuff,
00182             // see intel ABI docs)
00183           case MVT::f64:
00184 //XXX            BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
00185             MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
00186             // floating point args go into f8..f15 as-needed, the increment
00187             argVreg[count] =                              // is below..:
00188             MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
00189             // FP args go into f8..f15 as needed: (hence the ++)
00190             argPreg[count] = args_FP[used_FPArgs++];
00191             argOpc[count] = IA64::FMOV;
00192             argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
00193                                                 MVT::f64);
00194             if (I->getType() == Type::FloatTy)
00195               argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
00196             break;
00197           case MVT::i1: // NOTE: as far as C abi stuff goes,
00198                         // bools are just boring old ints
00199           case MVT::i8:
00200           case MVT::i16:
00201           case MVT::i32:
00202           case MVT::i64:
00203 //XXX            BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
00204             MF.addLiveIn(args_int[count]); // mark this register as liveIn
00205             argVreg[count] =
00206             MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
00207             argPreg[count] = args_int[count];
00208             argOpc[count] = IA64::MOV;
00209             argt = newroot =
00210               DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
00211             if ( getValueType(I->getType()) != MVT::i64)
00212               argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
00213                   newroot);
00214             break;
00215         }
00216       } else { // more than 8 args go into the frame
00217         // Create the frame index object for this incoming parameter...
00218         ArgOffset = 16 + 8 * (count - 8);
00219         int FI = MFI->CreateFixedObject(8, ArgOffset);
00220 
00221         // Create the SelectionDAG nodes corresponding to a load
00222         //from this parameter
00223         SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
00224         argt = newroot = DAG.getLoad(getValueType(I->getType()),
00225                                      DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
00226       }
00227       ++count;
00228       DAG.setRoot(newroot.getValue(1));
00229       ArgValues.push_back(argt);
00230     }
00231 
00232 
00233   // Create a vreg to hold the output of (what will become)
00234   // the "alloc" instruction
00235   VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
00236   BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
00237   // we create a PSEUDO_ALLOC (pseudo)instruction for now
00238 /*
00239   BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
00240 
00241   // hmm:
00242   BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
00243   BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
00244   // ..hmm.
00245   
00246   BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
00247 
00248   // hmm:
00249   BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
00250   BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
00251   // ..hmm.
00252 */
00253 
00254   unsigned tempOffset=0;
00255 
00256   // if this is a varargs function, we simply lower llvm.va_start by
00257   // pointing to the first entry
00258   if(F.isVarArg()) {
00259     tempOffset=0;
00260     VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
00261   }
00262 
00263   // here we actually do the moving of args, and store them to the stack
00264   // too if this is a varargs function:
00265   for (int i = 0; i < count && i < 8; ++i) {
00266     BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
00267     if(F.isVarArg()) {
00268       // if this is a varargs function, we copy the input registers to the stack
00269       int FI = MFI->CreateFixedObject(8, tempOffset);
00270       tempOffset+=8;   //XXX: is it safe to use r22 like this?
00271       BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
00272       // FIXME: we should use st8.spill here, one day
00273       BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
00274     }
00275   }
00276 
00277   // Finally, inform the code generator which regs we return values in.
00278   // (see the ISD::RET: case in the instruction selector)
00279   switch (getValueType(F.getReturnType())) {
00280   default: assert(0 && "i have no idea where to return this type!");
00281   case MVT::isVoid: break;
00282   case MVT::i1:
00283   case MVT::i8:
00284   case MVT::i16:
00285   case MVT::i32:
00286   case MVT::i64:
00287     MF.addLiveOut(IA64::r8);
00288     break;
00289   case MVT::f32:
00290   case MVT::f64:
00291     MF.addLiveOut(IA64::F8);
00292     break;
00293   }
00294 
00295   return ArgValues;
00296 }
00297 
00298 std::pair<SDOperand, SDOperand>
00299 IA64TargetLowering::LowerCallTo(SDOperand Chain,
00300                                 const Type *RetTy, bool isVarArg,
00301                                 unsigned CallingConv, bool isTailCall,
00302                                 SDOperand Callee, ArgListTy &Args,
00303                                 SelectionDAG &DAG) {
00304 
00305   MachineFunction &MF = DAG.getMachineFunction();
00306 
00307   unsigned NumBytes = 16;
00308   unsigned outRegsUsed = 0;
00309 
00310   if (Args.size() > 8) {
00311     NumBytes += (Args.size() - 8) * 8;
00312     outRegsUsed = 8;
00313   } else {
00314     outRegsUsed = Args.size();
00315   }
00316 
00317   // FIXME? this WILL fail if we ever try to pass around an arg that
00318   // consumes more than a single output slot (a 'real' double, int128
00319   // some sort of aggregate etc.), as we'll underestimate how many 'outX'
00320   // registers we use. Hopefully, the assembler will notice.
00321   MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
00322     std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
00323 
00324   // keep stack frame 16-byte aligned
00325   //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!");
00326   NumBytes = (NumBytes+15) & ~15;
00327   
00328   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
00329 
00330   SDOperand StackPtr, NullSV;
00331   std::vector<SDOperand> Stores;
00332   std::vector<SDOperand> Converts;
00333   std::vector<SDOperand> RegValuesToPass;
00334   unsigned ArgOffset = 16;
00335   
00336   for (unsigned i = 0, e = Args.size(); i != e; ++i)
00337     {
00338       SDOperand Val = Args[i].first;
00339       MVT::ValueType ObjectVT = Val.getValueType();
00340       SDOperand ValToStore(0, 0), ValToConvert(0, 0);
00341       unsigned ObjSize=8;
00342       switch (ObjectVT) {
00343       default: assert(0 && "unexpected argument type!");
00344       case MVT::i1:
00345       case MVT::i8:
00346       case MVT::i16:
00347       case MVT::i32:
00348         //promote to 64-bits, sign/zero extending based on type
00349         //of the argument
00350         if(Args[i].second->isSigned())
00351           Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
00352         else
00353           Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
00354         // XXX: fall through
00355       case MVT::i64:
00356         //ObjSize = 8;
00357         if(RegValuesToPass.size() >= 8) {
00358           ValToStore = Val;
00359         } else {
00360           RegValuesToPass.push_back(Val);
00361         }
00362         break;
00363       case MVT::f32:
00364         //promote to 64-bits
00365         Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
00366         // XXX: fall through
00367       case MVT::f64:
00368         if(RegValuesToPass.size() >= 8) {
00369           ValToStore = Val;
00370         } else {
00371           RegValuesToPass.push_back(Val);
00372     if(1 /* TODO: if(calling external or varadic function)*/ ) {
00373       ValToConvert = Val; // additionally pass this FP value as an int
00374     }
00375         }
00376         break;
00377       }
00378       
00379       if(ValToStore.Val) {
00380         if(!StackPtr.Val) {
00381           StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
00382           NullSV = DAG.getSrcValue(NULL);
00383         }
00384         SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
00385         PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
00386         Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
00387                                      ValToStore, PtrOff, NullSV));
00388         ArgOffset += ObjSize;
00389       }
00390 
00391       if(ValToConvert.Val) {
00392   Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert)); 
00393       }
00394     }
00395 
00396   // Emit all stores, make sure they occur before any copies into physregs.
00397   if (!Stores.empty())
00398     Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
00399 
00400   static const unsigned IntArgRegs[] = {
00401     IA64::out0, IA64::out1, IA64::out2, IA64::out3, 
00402     IA64::out4, IA64::out5, IA64::out6, IA64::out7
00403   };
00404 
00405   static const unsigned FPArgRegs[] = {
00406     IA64::F8,  IA64::F9,  IA64::F10, IA64::F11, 
00407     IA64::F12, IA64::F13, IA64::F14, IA64::F15
00408   };
00409 
00410   SDOperand InFlag;
00411   
00412   // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
00413   SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
00414   Chain = GPBeforeCall.getValue(1);
00415   InFlag = Chain.getValue(2);
00416   SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
00417   Chain = SPBeforeCall.getValue(1);
00418   InFlag = Chain.getValue(2);
00419   SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
00420   Chain = RPBeforeCall.getValue(1);
00421   InFlag = Chain.getValue(2);
00422 
00423   // Build a sequence of copy-to-reg nodes chained together with token chain
00424   // and flag operands which copy the outgoing integer args into regs out[0-7]
00425   // mapped 1:1 and the FP args into regs F8-F15 "lazily"
00426   // TODO: for performance, we should only copy FP args into int regs when we
00427   // know this is required (i.e. for varardic or external (unknown) functions)
00428 
00429   // first to the FP->(integer representation) conversions, these are
00430   // flagged for now, but shouldn't have to be (TODO)
00431   unsigned seenConverts = 0;
00432   for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
00433     if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
00434       Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag);
00435       InFlag = Chain.getValue(1);
00436     }
00437   }
00438 
00439   // next copy args into the usual places, these are flagged
00440   unsigned usedFPArgs = 0;
00441   for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
00442     Chain = DAG.getCopyToReg(Chain,
00443       MVT::isInteger(RegValuesToPass[i].getValueType()) ?
00444                                           IntArgRegs[i] : FPArgRegs[usedFPArgs++],
00445       RegValuesToPass[i], InFlag);
00446     InFlag = Chain.getValue(1);
00447   }
00448 
00449   // If the callee is a GlobalAddress node (quite common, every direct call is)
00450   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
00451 /*
00452   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
00453     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
00454   }
00455 */
00456 
00457   std::vector<MVT::ValueType> NodeTys;
00458   std::vector<SDOperand> CallOperands;
00459   NodeTys.push_back(MVT::Other);   // Returns a chain
00460   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
00461   CallOperands.push_back(Chain);
00462   CallOperands.push_back(Callee);
00463 
00464   // emit the call itself
00465   if (InFlag.Val)
00466     CallOperands.push_back(InFlag);
00467   else
00468     assert(0 && "this should never happen!\n");
00469 
00470   // to make way for a hack:
00471   Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys, CallOperands);
00472   InFlag = Chain.getValue(1);
00473 
00474   // restore the GP, SP and RP after the call  
00475   Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
00476   InFlag = Chain.getValue(1);
00477   Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
00478   InFlag = Chain.getValue(1);
00479   Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
00480   InFlag = Chain.getValue(1);
00481  
00482   std::vector<MVT::ValueType> RetVals;
00483   RetVals.push_back(MVT::Other);
00484   RetVals.push_back(MVT::Flag);
00485  
00486   MVT::ValueType RetTyVT = getValueType(RetTy);
00487   SDOperand RetVal;
00488   if (RetTyVT != MVT::isVoid) {
00489     switch (RetTyVT) {
00490     default: assert(0 && "Unknown value type to return!");
00491     case MVT::i1: { // bools are just like other integers (returned in r8)
00492       // we *could* fall through to the truncate below, but this saves a
00493       // few redundant predicate ops
00494       SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
00495       InFlag = boolInR8.getValue(2);
00496       Chain = boolInR8.getValue(1);
00497       SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
00498       InFlag = zeroReg.getValue(2);
00499       Chain = zeroReg.getValue(1);  
00500       
00501       RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
00502       break;
00503     }
00504     case MVT::i8:
00505     case MVT::i16:
00506     case MVT::i32:
00507       RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
00508       Chain = RetVal.getValue(1);
00509       
00510       // keep track of whether it is sign or zero extended (todo: bools?)
00511 /* XXX
00512       RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
00513                            MVT::i64, RetVal, DAG.getValueType(RetTyVT));
00514 */
00515       RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
00516       break;
00517     case MVT::i64:
00518       RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
00519       Chain = RetVal.getValue(1);
00520       InFlag = RetVal.getValue(2); // XXX dead
00521       break;
00522     case MVT::f32:
00523       RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
00524       Chain = RetVal.getValue(1);
00525       RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
00526       break;
00527     case MVT::f64:
00528       RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
00529       Chain = RetVal.getValue(1);
00530       InFlag = RetVal.getValue(2); // XXX dead
00531       break;
00532     }
00533   }
00534   
00535   Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
00536                       DAG.getConstant(NumBytes, getPointerTy()));
00537   
00538   return std::make_pair(RetVal, Chain);
00539 }
00540 
00541 std::pair<SDOperand, SDOperand> IA64TargetLowering::
00542 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
00543                         SelectionDAG &DAG) {
00544   assert(0 && "LowerFrameReturnAddress unimplemented");
00545   abort();
00546 }
00547 
00548 SDOperand IA64TargetLowering::
00549 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
00550   switch (Op.getOpcode()) {
00551   default: assert(0 && "Should not custom lower this!");
00552   case ISD::RET: {
00553     SDOperand AR_PFSVal, Copy;
00554     
00555     switch(Op.getNumOperands()) {
00556      default:
00557       assert(0 && "Do not know how to return this many arguments!");
00558       abort();
00559     case 1: 
00560       AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
00561       AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS, 
00562                                    AR_PFSVal);
00563       return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
00564     case 2: {
00565       // Copy the result into the output register & restore ar.pfs
00566       MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
00567       unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
00568 
00569       AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
00570       Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
00571                               SDOperand());
00572       AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
00573                                    Copy.getValue(1));
00574       std::vector<MVT::ValueType> NodeTys;
00575       std::vector<SDOperand> RetOperands;
00576       NodeTys.push_back(MVT::Other);
00577       NodeTys.push_back(MVT::Flag);
00578       RetOperands.push_back(AR_PFSVal);
00579       RetOperands.push_back(AR_PFSVal.getValue(1));
00580       return DAG.getNode(IA64ISD::RET_FLAG, NodeTys, RetOperands);
00581     }
00582     }
00583     return SDOperand();
00584   }
00585   case ISD::VAARG: {
00586     MVT::ValueType VT = getPointerTy();
00587     SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), 
00588                                    Op.getOperand(2));
00589     // Increment the pointer, VAList, to the next vaarg
00590     SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, 
00591                                    DAG.getConstant(MVT::getSizeInBits(VT)/8, 
00592                                                    VT));
00593     // Store the incremented VAList to the legalized pointer
00594     VAIncr = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), VAIncr,
00595                          Op.getOperand(1), Op.getOperand(2));
00596     // Load the actual argument out of the pointer VAList
00597     return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0));
00598   }
00599   case ISD::VASTART: {
00600     // vastart just stores the address of the VarArgsFrameIndex slot into the
00601     // memory location argument.
00602     SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
00603     return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 
00604                        Op.getOperand(1), Op.getOperand(2));
00605   }
00606   }
00607 }