LLVM API Documentation
00001 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the X86 implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef X86INSTRUCTIONINFO_H 00015 #define X86INSTRUCTIONINFO_H 00016 00017 #include "llvm/Target/TargetInstrInfo.h" 00018 #include "X86RegisterInfo.h" 00019 00020 namespace llvm { 00021 00022 /// X86II - This namespace holds all of the target specific flags that 00023 /// instruction info tracks. 00024 /// 00025 namespace X86II { 00026 enum { 00027 //===------------------------------------------------------------------===// 00028 // Instruction types. These are the standard/most common forms for X86 00029 // instructions. 00030 // 00031 00032 // PseudoFrm - This represents an instruction that is a pseudo instruction 00033 // or one that has not been implemented yet. It is illegal to code generate 00034 // it, but tolerated for intermediate implementation stages. 00035 Pseudo = 0, 00036 00037 /// Raw - This form is for instructions that don't have any operands, so 00038 /// they are just a fixed opcode value, like 'leave'. 00039 RawFrm = 1, 00040 00041 /// AddRegFrm - This form is used for instructions like 'push r32' that have 00042 /// their one register operand added to their opcode. 00043 AddRegFrm = 2, 00044 00045 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 00046 /// to specify a destination, which in this case is a register. 00047 /// 00048 MRMDestReg = 3, 00049 00050 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 00051 /// to specify a destination, which in this case is memory. 00052 /// 00053 MRMDestMem = 4, 00054 00055 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 00056 /// to specify a source, which in this case is a register. 00057 /// 00058 MRMSrcReg = 5, 00059 00060 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 00061 /// to specify a source, which in this case is memory. 00062 /// 00063 MRMSrcMem = 6, 00064 00065 /// MRM[0-7][rm] - These forms are used to represent instructions that use 00066 /// a Mod/RM byte, and use the middle field to hold extended opcode 00067 /// information. In the intel manual these are represented as /0, /1, ... 00068 /// 00069 00070 // First, instructions that operate on a register r/m operand... 00071 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 00072 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 00073 00074 // Next, instructions that operate on a memory r/m operand... 00075 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 00076 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 00077 00078 // MRMInitReg - This form is used for instructions whose source and 00079 // destinations are the same register. 00080 MRMInitReg = 32, 00081 00082 FormMask = 63, 00083 00084 //===------------------------------------------------------------------===// 00085 // Actual flags... 00086 00087 // OpSize - Set if this instruction requires an operand size prefix (0x66), 00088 // which most often indicates that the instruction operates on 16 bit data 00089 // instead of 32 bit data. 00090 OpSize = 1 << 6, 00091 00092 // Op0Mask - There are several prefix bytes that are used to form two byte 00093 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 00094 // used to obtain the setting of this field. If no bits in this field is 00095 // set, there is no prefix byte for obtaining a multibyte opcode. 00096 // 00097 Op0Shift = 7, 00098 Op0Mask = 0xF << Op0Shift, 00099 00100 // TB - TwoByte - Set if this instruction has a two byte opcode, which 00101 // starts with a 0x0F byte before the real opcode. 00102 TB = 1 << Op0Shift, 00103 00104 // REP - The 0xF3 prefix byte indicating repetition of the following 00105 // instruction. 00106 REP = 2 << Op0Shift, 00107 00108 // D8-DF - These escape opcodes are used by the floating point unit. These 00109 // values must remain sequential. 00110 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 00111 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 00112 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 00113 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 00114 00115 // XS, XD - These prefix codes are for single and double precision scalar 00116 // floating point operations performed in the SSE registers. 00117 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 00118 00119 //===------------------------------------------------------------------===// 00120 // This two-bit field describes the size of an immediate operand. Zero is 00121 // unused so that we can tell if we forgot to set a value. 00122 ImmShift = 11, 00123 ImmMask = 7 << ImmShift, 00124 Imm8 = 1 << ImmShift, 00125 Imm16 = 2 << ImmShift, 00126 Imm32 = 3 << ImmShift, 00127 00128 //===------------------------------------------------------------------===// 00129 // FP Instruction Classification... Zero is non-fp instruction. 00130 00131 // FPTypeMask - Mask for all of the FP types... 00132 FPTypeShift = 13, 00133 FPTypeMask = 7 << FPTypeShift, 00134 00135 // NotFP - The default, set for instructions that do not use FP registers. 00136 NotFP = 0 << FPTypeShift, 00137 00138 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 00139 ZeroArgFP = 1 << FPTypeShift, 00140 00141 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 00142 OneArgFP = 2 << FPTypeShift, 00143 00144 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 00145 // result back to ST(0). For example, fcos, fsqrt, etc. 00146 // 00147 OneArgFPRW = 3 << FPTypeShift, 00148 00149 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 00150 // explicit argument, storing the result to either ST(0) or the implicit 00151 // argument. For example: fadd, fsub, fmul, etc... 00152 TwoArgFP = 4 << FPTypeShift, 00153 00154 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 00155 // explicit argument, but have no destination. Example: fucom, fucomi, ... 00156 CompareFP = 5 << FPTypeShift, 00157 00158 // CondMovFP - "2 operand" floating point conditional move instructions. 00159 CondMovFP = 6 << FPTypeShift, 00160 00161 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 00162 SpecialFP = 7 << FPTypeShift, 00163 00164 // Bit 15 is unused. 00165 OpcodeShift = 17, 00166 OpcodeMask = 0xFF << OpcodeShift, 00167 // Bits 25 -> 31 are unused 00168 }; 00169 } 00170 00171 class X86InstrInfo : public TargetInstrInfo { 00172 const X86RegisterInfo RI; 00173 public: 00174 X86InstrInfo(); 00175 00176 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 00177 /// such, whenever a client has an instance of instruction info, it should 00178 /// always be able to get register info as well (through this method). 00179 /// 00180 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 00181 00182 // Return true if the instruction is a register to register move and 00183 // leave the source and dest operands in the passed parameters. 00184 // 00185 bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, 00186 unsigned& destReg) const; 00187 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 00188 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 00189 00190 /// convertToThreeAddress - This method must be implemented by targets that 00191 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 00192 /// may be able to convert a two-address instruction into a true 00193 /// three-address instruction on demand. This allows the X86 target (for 00194 /// example) to convert ADD and SHL instructions into LEA instructions if they 00195 /// would require register copies due to two-addressness. 00196 /// 00197 /// This method returns a null pointer if the transformation cannot be 00198 /// performed, otherwise it returns the new instruction. 00199 /// 00200 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; 00201 00202 /// commuteInstruction - We have a few instructions that must be hacked on to 00203 /// commute them. 00204 /// 00205 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 00206 00207 00208 /// Insert a goto (unconditional branch) sequence to TMBB, at the 00209 /// end of MBB 00210 virtual void insertGoto(MachineBasicBlock& MBB, 00211 MachineBasicBlock& TMBB) const; 00212 00213 /// Reverses the branch condition of the MachineInstr pointed by 00214 /// MI. The instruction is replaced and the new MI is returned. 00215 virtual MachineBasicBlock::iterator 00216 reverseBranchCondition(MachineBasicBlock::iterator MI) const; 00217 00218 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 00219 // specified opcode number. 00220 // 00221 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 00222 return get(Opcode).TSFlags >> X86II::OpcodeShift; 00223 } 00224 }; 00225 00226 } // End llvm namespace 00227 00228 #endif