LLVM API Documentation

llvm::TargetLowering Class Reference

#include <TargetLowering.h>

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List of all members.

Public Types

typedef std::vector< double
>::const_iterator 
legal_fpimm_iterator
typedef std::vector< std::pair<
SDOperand, const Type * > > 
ArgListTy
typedef std::vector< unsigned
>::const_iterator 
legal_am_scale_iterator
 Legal
 Promote
 Expand
 Custom
 Undefined
 Mask
 Extend
 UndefinedSetCCResult
 ZeroOrOneSetCCResult
 ZeroOrNegativeOneSetCCResult
 SchedulingForLatency
 SchedulingForRegPressure
 C_Register
 C_RegisterClass
 C_Memory
 C_Other
 C_Unknown
enum  LegalizeAction { Legal, Promote, Expand, Custom }
enum  OutOfRangeShiftAmount { Undefined, Mask, Extend }
enum  SetCCResultValue { UndefinedSetCCResult, ZeroOrOneSetCCResult, ZeroOrNegativeOneSetCCResult }
enum  SchedPreference { SchedulingForLatency, SchedulingForRegPressure }
enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}

Public Member Functions

 TargetLowering (TargetMachine &TM)
virtual ~TargetLowering ()
TargetMachinegetTargetMachine () const
const TargetDatagetTargetData () const
bool isLittleEndian () const
MVT::ValueType getPointerTy () const
MVT::ValueType getShiftAmountTy () const
OutOfRangeShiftAmount getShiftAmountFlavor () const
bool isSetCCExpensive () const
bool isIntDivCheap () const
bool isPow2DivCheap () const
MVT::ValueType getSetCCResultTy () const
SetCCResultValue getSetCCResultContents () const
SchedPreference getSchedulingPreference () const
 getSchedulingPreference - Return target scheduling preference.
TargetRegisterClassgetRegClassFor (MVT::ValueType VT) const
bool isTypeLegal (MVT::ValueType VT) const
const ValueTypeActionImplgetValueTypeActions () const
LegalizeAction getTypeAction (MVT::ValueType VT) const
MVT::ValueType getTypeToTransformTo (MVT::ValueType VT) const
unsigned getPackedTypeBreakdown (const PackedType *PTy, MVT::ValueType &PTyElementVT, MVT::ValueType &PTyLegalElementVT) const
legal_fpimm_iterator legal_fpimm_begin () const
legal_fpimm_iterator legal_fpimm_end () const
virtual bool isShuffleMaskLegal (SDOperand Mask, MVT::ValueType VT) const
LegalizeAction getOperationAction (unsigned Op, MVT::ValueType VT) const
bool isOperationLegal (unsigned Op, MVT::ValueType VT) const
MVT::ValueType getTypeToPromoteTo (unsigned Op, MVT::ValueType VT) const
MVT::ValueType getValueType (const Type *Ty) const
unsigned getNumElements (MVT::ValueType VT) const
bool hasTargetDAGCombine (ISD::NodeType NT) const
unsigned getMaxStoresPerMemset () const
 Get maximum # of store operations permitted for llvm.memset.
unsigned getMaxStoresPerMemcpy () const
 Get maximum # of store operations permitted for llvm.memcpy.
unsigned getMaxStoresPerMemmove () const
 Get maximum # of store operations permitted for llvm.memmove.
bool allowsUnalignedMemoryAccesses () const
 Determine if the target supports unaligned memory accesses.
bool usesUnderscoreSetJmpLongJmp () const
unsigned getStackPointerRegisterToSaveRestore () const
bool MaskedValueIsZero (SDOperand Op, uint64_t Mask, unsigned Depth=0) const
void ComputeMaskedBits (SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const
bool SimplifyDemandedBits (SDOperand Op, uint64_t DemandedMask, uint64_t &KnownZero, uint64_t &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
virtual void computeMaskedBitsForTargetNode (const SDOperand Op, uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth=0) const
virtual SDOperand PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
virtual std::vector< SDOperandLowerArguments (Function &F, SelectionDAG &DAG)
virtual std::pair< SDOperand,
SDOperand
LowerCallTo (SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG)=0
virtual std::pair< SDOperand,
SDOperand
LowerFrameReturnAddress (bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG)
virtual SDOperand LowerOperation (SDOperand Op, SelectionDAG &DAG)
virtual SDOperand CustomPromoteOperation (SDOperand Op, SelectionDAG &DAG)
virtual const char * getTargetNodeName (unsigned Opcode) const
virtual ConstraintType getConstraintType (char ConstraintLetter) const
virtual std::vector< unsigned > getRegClassForInlineAsmConstraint (const std::string &Constraint, MVT::ValueType VT) const
virtual std::pair< unsigned,
const TargetRegisterClass * > 
getRegForInlineAsmConstraint (const std::string &Constraint, MVT::ValueType VT) const
virtual bool isOperandValidForConstraint (SDOperand Op, char ConstraintLetter)
virtual MachineBasicBlockInsertAtEndOfBasicBlock (MachineInstr *MI, MachineBasicBlock *MBB)
virtual bool isLegalAddressImmediate (int64_t V) const
virtual bool isLegalAddressImmediate (GlobalValue *GV) const
legal_am_scale_iterator legal_am_scale_begin () const
legal_am_scale_iterator legal_am_scale_end () const

Protected Member Functions

void setShiftAmountType (MVT::ValueType VT)
void setSetCCResultType (MVT::ValueType VT)
void setSetCCResultContents (SetCCResultValue Ty)
void setSchedulingPreference (SchedPreference Pref)
 setSchedulingPreference - Specify the target scheduling preference.
void setShiftAmountFlavor (OutOfRangeShiftAmount OORSA)
void setUseUnderscoreSetJmpLongJmp (bool Val)
void setStackPointerRegisterToSaveRestore (unsigned R)
void setSetCCIsExpensive ()
void setIntDivIsCheap (bool isCheap=true)
void setPow2DivIsCheap (bool isCheap=true)
void addRegisterClass (MVT::ValueType VT, TargetRegisterClass *RC)
void computeRegisterProperties ()
void setOperationAction (unsigned Op, MVT::ValueType VT, LegalizeAction Action)
void AddPromotedToType (unsigned Opc, MVT::ValueType OrigVT, MVT::ValueType DestVT)
void addLegalFPImmediate (double Imm)
void setTargetDAGCombine (ISD::NodeType NT)
void addLegalAddressScale (unsigned Scale)

Protected Attributes

unsigned maxStoresPerMemset
 Specify maximum number of store instructions per memset call.
unsigned maxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call.
unsigned maxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call.
bool allowUnalignedMemoryAccesses
 Indicate whether the target permits unaligned memory accesses.

Classes

struct  DAGCombinerInfo
struct  TargetLoweringOpt
class  ValueTypeActionImpl

Detailed Description

TargetLowering - This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively.

This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.

Definition at line 49 of file TargetLowering.h.


Member Typedef Documentation

typedef std::vector<std::pair<SDOperand, const Type*> > llvm::TargetLowering::ArgListTy

LowerCallTo - This hook lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain.

Definition at line 533 of file TargetLowering.h.

typedef std::vector<unsigned>::const_iterator llvm::TargetLowering::legal_am_scale_iterator

Definition at line 621 of file TargetLowering.h.

typedef std::vector<double>::const_iterator llvm::TargetLowering::legal_fpimm_iterator

Definition at line 187 of file TargetLowering.h.


Member Enumeration Documentation

enum llvm::TargetLowering::ConstraintType

Enumerator:
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 567 of file TargetLowering.h.

enum llvm::TargetLowering::LegalizeAction

LegalizeAction - This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator:
Legal 
Promote 
Expand 
Custom 

Definition at line 53 of file TargetLowering.h.

enum llvm::TargetLowering::OutOfRangeShiftAmount

Enumerator:
Undefined 
Mask 
Extend 

Definition at line 60 of file TargetLowering.h.

enum llvm::TargetLowering::SchedPreference

Enumerator:
SchedulingForLatency 
SchedulingForRegPressure 

Definition at line 72 of file TargetLowering.h.

enum llvm::TargetLowering::SetCCResultValue

Enumerator:
UndefinedSetCCResult 
ZeroOrOneSetCCResult 
ZeroOrNegativeOneSetCCResult 

Definition at line 66 of file TargetLowering.h.


Constructor & Destructor Documentation

TargetLowering::TargetLowering ( TargetMachine TM  ) 

Definition at line 23 of file TargetLowering.cpp.

References allowUnalignedMemoryAccesses, llvm::ISD::BUILTIN_OP_END, llvm::TargetData::getIntPtrType(), getValueType(), llvm::TargetData::isLittleEndian(), llvm::MVT::LAST_VALUETYPE, maxStoresPerMemcpy, maxStoresPerMemmove, maxStoresPerMemset, SchedulingForLatency, and Undefined.

TargetLowering::~TargetLowering (  )  [virtual]

Definition at line 45 of file TargetLowering.cpp.


Member Function Documentation

void llvm::TargetLowering::addLegalAddressScale ( unsigned  Scale  )  [inline, protected]

addLegalAddressScale - Add a integer (> 1) value which can be used as scale in the target addressing mode. Note: the ordering matters so the least efficient ones should be entered first.

Definition at line 633 of file TargetLowering.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::addLegalFPImmediate ( double  Imm  )  [inline, protected]

addLegalFPImmediate - Indicate that this target can instruction select the specified FP immediate natively.

Definition at line 506 of file TargetLowering.h.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::AddPromotedToType ( unsigned  Opc,
MVT::ValueType  OrigVT,
MVT::ValueType  DestVT 
) [inline, protected]

AddPromotedToType - If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.

Definition at line 499 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::addRegisterClass ( MVT::ValueType  VT,
TargetRegisterClass RC 
) [inline, protected]

addRegisterClass - Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.

Definition at line 476 of file TargetLowering.h.

References RC.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

bool llvm::TargetLowering::allowsUnalignedMemoryAccesses (  )  const [inline]

Determine if the target supports unaligned memory accesses.

This function returns true if the target allows unaligned memory accesses. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. It's use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Definition at line 303 of file TargetLowering.h.

References allowUnalignedMemoryAccesses.

Referenced by MeetsMaxMemopRequirement().

void TargetLowering::ComputeMaskedBits ( SDOperand  Op,
uint64_t  Mask,
uint64_t &  KnownZero,
uint64_t &  KnownOne,
unsigned  Depth = 0 
) const

ComputeMaskedBits - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. This code only analyzes bits in Mask, in order to short-circuit processing. Targets can implement the computeMaskedBitsForTargetNode method, to allow target nodes to be understood.

Definition at line 653 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::AssertZext, llvm::ISD::BUILTIN_OP_END, computeMaskedBitsForTargetNode(), llvm::ISD::Constant, llvm::CountLeadingZeros_64(), llvm::CountTrailingZeros_64(), llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::MVT::getIntVTBitMask(), llvm::MVT::getIntVTSignBit(), getSetCCResultContents(), llvm::MVT::getSizeInBits(), llvm::ConstantSDNode::getValue(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Log2_32(), Op, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, ZeroOrOneSetCCResult, and llvm::ISD::ZEXTLOAD.

Referenced by MaskedValueIsZero(), and SimplifyDemandedBits().

void TargetLowering::computeMaskedBitsForTargetNode ( const SDOperand  Op,
uint64_t  Mask,
uint64_t &  KnownZero,
uint64_t &  KnownOne,
unsigned  Depth = 0 
) const [virtual]

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 933 of file TargetLowering.cpp.

References llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and Op.

Referenced by ComputeMaskedBits().

void TargetLowering::computeRegisterProperties (  )  [protected]

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 85 of file TargetLowering.cpp.

References Expand, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::FIRST_VECTOR_VALUETYPE, getNumElements(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::LAST_VALUETYPE, llvm::MVT::LAST_VECTOR_VALUETYPE, Promote, SetValueTypeAction(), and llvm::MVT::Vector.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

SDOperand TargetLowering::CustomPromoteOperation ( SDOperand  Op,
SelectionDAG DAG 
) [virtual]

CustomPromoteOperation - This callback is invoked for operations that are unsupported by the target, are registered to use 'custom' lowering, and whose type needs to be promoted.

Reimplemented in llvm::AlphaTargetLowering.

Definition at line 2366 of file SelectionDAGISel.cpp.

References abort().

TargetLowering::ConstraintType TargetLowering::getConstraintType ( char  ConstraintLetter  )  const [virtual]

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 959 of file TargetLowering.cpp.

References C_Memory, C_Other, C_RegisterClass, and C_Unknown.

Referenced by llvm::PPCTargetLowering::getConstraintType(), and llvm::SelectionDAGLowering::visitInlineAsm().

unsigned llvm::TargetLowering::getMaxStoresPerMemcpy (  )  const [inline]

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement.

Definition at line 289 of file TargetLowering.h.

References maxStoresPerMemcpy.

Referenced by llvm::SelectionDAGLowering::visitMemIntrinsic().

unsigned llvm::TargetLowering::getMaxStoresPerMemmove (  )  const [inline]

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement.

Definition at line 295 of file TargetLowering.h.

References maxStoresPerMemmove.

unsigned llvm::TargetLowering::getMaxStoresPerMemset (  )  const [inline]

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement.

Definition at line 283 of file TargetLowering.h.

References maxStoresPerMemset.

Referenced by llvm::SelectionDAGLowering::visitMemIntrinsic().

unsigned llvm::TargetLowering::getNumElements ( MVT::ValueType  VT  )  const [inline]

getNumElements - Return the number of registers that this ValueType will eventually require. This is always one for all non-integer types, is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces.

Definition at line 269 of file TargetLowering.h.

Referenced by computeRegisterProperties(), llvm::FunctionLoweringInfo::CreateRegForValue(), llvm::FunctionLoweringInfo::FunctionLoweringInfo(), llvm::SelectionDAGLowering::GetRegistersForValue(), and LowerArguments().

LegalizeAction llvm::TargetLowering::getOperationAction ( unsigned  Op,
MVT::ValueType  VT 
) const [inline]

getOperationAction - Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 207 of file TargetLowering.h.

Referenced by getTypeToPromoteTo(), and isOperationLegal().

unsigned llvm::TargetLowering::getPackedTypeBreakdown ( const PackedType PTy,
MVT::ValueType PTyElementVT,
MVT::ValueType PTyLegalElementVT 
) const

getPackedTypeBreakdown - Packed types are broken down into some number of legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT of the PackedType elements before they are promoted/expanded.

Referenced by llvm::FunctionLoweringInfo::FunctionLoweringInfo().

MVT::ValueType llvm::TargetLowering::getPointerTy (  )  const [inline]

Definition at line 84 of file TargetLowering.h.

Referenced by llvm::SelectionDAGLowering::getValue(), LowerArguments(), llvm::PPCTargetLowering::LowerArguments(), llvm::X86TargetLowering::LowerCallTo(), llvm::PPCTargetLowering::LowerCallTo(), llvm::IA64TargetLowering::LowerCallTo(), llvm::AlphaTargetLowering::LowerCallTo(), llvm::X86TargetLowering::LowerFrameReturnAddress(), LowerFrameReturnAddress(), llvm::X86TargetLowering::LowerOperation(), llvm::IA64TargetLowering::LowerOperation(), llvm::AlphaTargetLowering::LowerOperation(), llvm::SelectionDAGLowering::visitAlloca(), llvm::SelectionDAGLowering::visitCall(), llvm::SelectionDAGLowering::visitExtractElement(), llvm::SelectionDAGLowering::visitFree(), llvm::SelectionDAGLowering::visitInlineAsm(), llvm::SelectionDAGLowering::visitInsertElement(), llvm::SelectionDAGLowering::visitIntrinsicCall(), llvm::SelectionDAGLowering::visitMalloc(), and llvm::SelectionDAGLowering::visitTargetIntrinsic().

TargetRegisterClass* llvm::TargetLowering::getRegClassFor ( MVT::ValueType  VT  )  const [inline]

getRegClassFor - Return the register class that should be used for the specified value type. This may only be called on legal types.

Definition at line 116 of file TargetLowering.h.

References RC.

Referenced by llvm::IA64TargetLowering::LowerArguments(), llvm::AlphaTargetLowering::LowerArguments(), llvm::SelectionDAGISel::MakeReg(), and llvm::FunctionLoweringInfo::MakeReg().

virtual std::vector<unsigned> llvm::TargetLowering::getRegClassForInlineAsmConstraint ( const std::string &  Constraint,
MVT::ValueType  VT 
) const [virtual]

getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), return a list of registers that can be used to satisfy the constraint. This should only be used for C_RegisterClass constraints.

Referenced by llvm::SelectionDAGLowering::GetRegistersForValue().

virtual std::pair<unsigned, const TargetRegisterClass*> llvm::TargetLowering::getRegForInlineAsmConstraint ( const std::string &  Constraint,
MVT::ValueType  VT 
) const [virtual]

getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.

Referenced by llvm::SelectionDAGLowering::GetRegistersForValue(), and llvm::SelectionDAGLowering::visitInlineAsm().

SchedPreference llvm::TargetLowering::getSchedulingPreference (  )  const [inline]

getSchedulingPreference - Return target scheduling preference.

Definition at line 110 of file TargetLowering.h.

Referenced by llvm::SelectionDAGISel::ScheduleAndEmitDAG().

SetCCResultValue llvm::TargetLowering::getSetCCResultContents (  )  const [inline]

getSetCCResultContents - For targets without boolean registers, this flag returns information about the contents of the high-bits in the setcc result register.

Definition at line 107 of file TargetLowering.h.

Referenced by ComputeMaskedBits(), and SimplifyDemandedBits().

MVT::ValueType llvm::TargetLowering::getSetCCResultTy (  )  const [inline]

getSetCCResultTy - Return the ValueType of the result of setcc operations.

Definition at line 102 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::LowerOperation().

OutOfRangeShiftAmount llvm::TargetLowering::getShiftAmountFlavor (  )  const [inline]

Definition at line 86 of file TargetLowering.h.

MVT::ValueType llvm::TargetLowering::getShiftAmountTy (  )  const [inline]

Definition at line 85 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::LowerOperation(), llvm::SelectionDAGLowering::visitGetElementPtr(), and llvm::SelectionDAGLowering::visitShift().

unsigned llvm::TargetLowering::getStackPointerRegisterToSaveRestore (  )  const [inline]

getStackPointerRegisterToSaveRestore - If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 316 of file TargetLowering.h.

const TargetData& llvm::TargetLowering::getTargetData (  )  const [inline]

Definition at line 81 of file TargetLowering.h.

Referenced by llvm::FunctionLoweringInfo::FunctionLoweringInfo(), llvm::X86TargetLowering::LowerOperation(), llvm::SelectionDAGISel::runOnFunction(), llvm::SelectionDAGLowering::visitAlloca(), llvm::SelectionDAGLowering::visitFree(), and llvm::SelectionDAGLowering::visitMalloc().

TargetMachine& llvm::TargetLowering::getTargetMachine (  )  const [inline]

Definition at line 80 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::getTarget(), llvm::X86TargetLowering::isLegalAddressImmediate(), llvm::X86TargetLowering::LowerOperation(), llvm::PPCTargetLowering::LowerOperation(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::SelectionDAGISel::runOnFunction(), and llvm::SelectionDAGLowering::visitAlloca().

const char * TargetLowering::getTargetNodeName ( unsigned  Opcode  )  const [virtual]

getTargetNodeName() - This method returns the name of a target specific DAG node.

Reimplemented in llvm::AlphaTargetLowering, llvm::IA64TargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 141 of file TargetLowering.cpp.

Referenced by llvm::SDNode::getOperationName().

LegalizeAction llvm::TargetLowering::getTypeAction ( MVT::ValueType  VT  )  const [inline]

getTypeAction - Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Definition at line 161 of file TargetLowering.h.

References llvm::TargetLowering::ValueTypeActionImpl::getTypeAction().

Referenced by LowerArguments(), and llvm::SelectionDAGLowering::visitUserOp2().

MVT::ValueType llvm::TargetLowering::getTypeToPromoteTo ( unsigned  Op,
MVT::ValueType  VT 
) const [inline]

getTypeToPromoteTo - If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 220 of file TargetLowering.h.

References getOperationAction(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isTypeLegal(), llvm::MVT::isVoid, and Promote.

MVT::ValueType llvm::TargetLowering::getTypeToTransformTo ( MVT::ValueType  VT  )  const [inline]

getTypeToTransformTo - For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register.

Definition at line 170 of file TargetLowering.h.

Referenced by llvm::FunctionLoweringInfo::CreateRegForValue(), LowerArguments(), llvm::SelectionDAGLowering::visitUnreachable(), and llvm::SelectionDAGLowering::visitUserOp2().

MVT::ValueType llvm::TargetLowering::getValueType ( const Type Ty  )  const [inline]

getValueType - Return the MVT::ValueType corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size.

Definition at line 245 of file TargetLowering.h.

References llvm::Type::BoolTyID, llvm::Type::DoubleTyID, llvm::MVT::f32, llvm::MVT::f64, llvm::Type::FloatTyID, llvm::Type::getTypeID(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Type::IntTyID, llvm::MVT::isVoid, llvm::Type::LongTyID, llvm::Type::PackedTyID, llvm::Type::PointerTyID, llvm::Type::SByteTyID, llvm::Type::ShortTyID, Ty, llvm::Type::UByteTyID, llvm::Type::UIntTyID, llvm::Type::ULongTyID, llvm::Type::UShortTyID, llvm::MVT::Vector, and llvm::Type::VoidTyID.

Referenced by llvm::FunctionLoweringInfo::CreateRegForValue(), llvm::FunctionLoweringInfo::FunctionLoweringInfo(), llvm::SelectionDAGLowering::getLoadFrom(), llvm::SelectionDAGLowering::getValue(), LowerArguments(), llvm::PPCTargetLowering::LowerArguments(), llvm::IA64TargetLowering::LowerArguments(), llvm::AlphaTargetLowering::LowerArguments(), llvm::PPCTargetLowering::LowerCallTo(), llvm::IA64TargetLowering::LowerCallTo(), llvm::AlphaTargetLowering::LowerCallTo(), TargetLowering(), llvm::SelectionDAGLowering::visitBinary(), llvm::SelectionDAGLowering::visitCast(), llvm::SelectionDAGLowering::visitExtractElement(), llvm::SelectionDAGLowering::visitInlineAsm(), llvm::SelectionDAGLowering::visitTargetIntrinsic(), and llvm::SelectionDAGLowering::visitVAArg().

const ValueTypeActionImpl& llvm::TargetLowering::getValueTypeActions (  )  const [inline]

Definition at line 153 of file TargetLowering.h.

bool llvm::TargetLowering::hasTargetDAGCombine ( ISD::NodeType  NT  )  const [inline]

hasTargetDAGCombine - If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 275 of file TargetLowering.h.

MachineBasicBlock * TargetLowering::InsertAtEndOfBasicBlock ( MachineInstr MI,
MachineBasicBlock MBB 
) [virtual]

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 2196 of file SelectionDAGISel.cpp.

References abort().

Referenced by llvm::ScheduleDAG::EmitNode().

bool llvm::TargetLowering::isIntDivCheap (  )  const [inline]

isIntDivCheap() - Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 94 of file TargetLowering.h.

bool TargetLowering::isLegalAddressImmediate ( GlobalValue GV  )  const [virtual]

Reimplemented in llvm::X86TargetLowering.

Definition at line 1050 of file TargetLowering.cpp.

bool TargetLowering::isLegalAddressImmediate ( int64_t  V  )  const [virtual]

isLegalAddressImmediate - Return true if the integer value or GlobalValue can be used as the offset of the target addressing mode.

Reimplemented in llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 1047 of file TargetLowering.cpp.

Referenced by isTargetConstant().

bool llvm::TargetLowering::isLittleEndian (  )  const [inline]

Definition at line 83 of file TargetLowering.h.

Referenced by getMemsetStringVal(), and LowerArguments().

bool TargetLowering::isOperandValidForConstraint ( SDOperand  Op,
char  ConstraintLetter 
) [virtual]

isOperandValidForConstraint - Return true if the specified SDOperand is valid for the specified target constraint letter.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 983 of file TargetLowering.cpp.

Referenced by llvm::PPCTargetLowering::isOperandValidForConstraint(), and llvm::SelectionDAGLowering::visitInlineAsm().

bool llvm::TargetLowering::isOperationLegal ( unsigned  Op,
MVT::ValueType  VT 
) const [inline]

isOperationLegal - Return true if the specified operation is legal on this target.

Definition at line 213 of file TargetLowering.h.

References Custom, getOperationAction(), and Legal.

bool llvm::TargetLowering::isPow2DivCheap (  )  const [inline]

isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of srl/add/sra.

Definition at line 98 of file TargetLowering.h.

bool llvm::TargetLowering::isSetCCExpensive (  )  const [inline]

isSetCCExpensive - Return true if the setcc operation is expensive for this target.

Definition at line 90 of file TargetLowering.h.

virtual bool llvm::TargetLowering::isShuffleMaskLegal ( SDOperand  Mask,
MVT::ValueType  VT 
) const [inline, virtual]

isShuffleMaskLegal - Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Definition at line 199 of file TargetLowering.h.

bool llvm::TargetLowering::isTypeLegal ( MVT::ValueType  VT  )  const [inline]

isTypeLegal - Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.

Definition at line 125 of file TargetLowering.h.

Referenced by computeRegisterProperties(), llvm::FunctionLoweringInfo::CreateRegForValue(), getTypeToPromoteTo(), isAllocatableRegister(), LowerArguments(), MeetsMaxMemopRequirement(), SetValueTypeAction(), and llvm::SelectionDAGLowering::visitTargetIntrinsic().

legal_am_scale_iterator llvm::TargetLowering::legal_am_scale_begin (  )  const [inline]

Definition at line 622 of file TargetLowering.h.

legal_am_scale_iterator llvm::TargetLowering::legal_am_scale_end (  )  const [inline]

Definition at line 625 of file TargetLowering.h.

legal_fpimm_iterator llvm::TargetLowering::legal_fpimm_begin (  )  const [inline]

Definition at line 188 of file TargetLowering.h.

legal_fpimm_iterator llvm::TargetLowering::legal_fpimm_end (  )  const [inline]

Definition at line 191 of file TargetLowering.h.

std::vector< SDOperand > TargetLowering::LowerArguments ( Function F,
SelectionDAG DAG 
) [virtual]

LowerArguments - This hook must be implemented to indicate how we should lower the arguments for the specified function, into the specified DAG.

Reimplemented in llvm::AlphaTargetLowering, llvm::IA64TargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 2237 of file SelectionDAGISel.cpp.

References llvm::ISD::AssertSext, llvm::ISD::AssertZext, DAG, E, Expand, F, llvm::ISD::FORMAL_ARGUMENTS, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getNumElements(), getPointerTy(), llvm::MVT::getSizeInBits(), llvm::Value::getType(), getTypeAction(), getTypeToTransformTo(), llvm::SelectionDAG::getValueType(), getValueType(), llvm::MVT::getVectorType(), llvm::PPCISD::Hi, llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), isLittleEndian(), llvm::Type::isSigned(), isTypeLegal(), Legal, llvm::PPCISD::Lo, Op, llvm::MVT::Other, Promote, RetVals, llvm::SDOperand::Val, and llvm::MVT::Vector.

virtual std::pair<SDOperand, SDOperand> llvm::TargetLowering::LowerCallTo ( SDOperand  Chain,
const Type RetTy,
bool  isVarArg,
unsigned  CallingConv,
bool  isTailCall,
SDOperand  Callee,
ArgListTy Args,
SelectionDAG DAG 
) [pure virtual]

Referenced by llvm::SelectionDAGLowering::visitCall(), llvm::SelectionDAGLowering::visitFree(), and llvm::SelectionDAGLowering::visitMalloc().

std::pair< SDOperand, SDOperand > TargetLowering::LowerFrameReturnAddress ( bool  isFrameAddr,
SDOperand  Chain,
unsigned  Depth,
SelectionDAG DAG 
) [virtual]

LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or llvm.frameaddress (depending on the value of the first argument). The return values are the result pointer and the resultant token chain. If not implemented, both of these intrinsics will return null.

Reimplemented in llvm::IA64TargetLowering, and llvm::X86TargetLowering.

Definition at line 2355 of file SelectionDAGISel.cpp.

References DAG, llvm::SelectionDAG::getConstant(), and getPointerTy().

Referenced by llvm::SelectionDAGLowering::visitFrameReturnAddress().

SDOperand TargetLowering::LowerOperation ( SDOperand  Op,
SelectionDAG DAG 
) [virtual]

LowerOperation - This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented in llvm::AlphaTargetLowering, llvm::IA64TargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 2360 of file SelectionDAGISel.cpp.

References abort().

bool TargetLowering::MaskedValueIsZero ( SDOperand  Op,
uint64_t  Mask,
unsigned  Depth = 0 
) const

MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.

Definition at line 641 of file TargetLowering.cpp.

References ComputeMaskedBits(), and Op.

SDOperand TargetLowering::PerformDAGCombine ( SDNode N,
DAGCombinerInfo DCI 
) const [virtual]

PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDOperand.Val == 0 - No change was made SDOperand.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Definition at line 949 of file TargetLowering.cpp.

void llvm::TargetLowering::setIntDivIsCheap ( bool  isCheap = true  )  [inline, protected]

setIntDivIsCheap - Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.

Definition at line 466 of file TargetLowering.h.

void llvm::TargetLowering::setOperationAction ( unsigned  Op,
MVT::ValueType  VT,
LegalizeAction  Action 
) [inline, protected]

setOperationAction - Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Definition at line 487 of file TargetLowering.h.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setPow2DivIsCheap ( bool  isCheap = true  )  [inline, protected]

setPow2DivIsCheap - Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.

Definition at line 471 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLowering::setSchedulingPreference ( SchedPreference  Pref  )  [inline, protected]

setSchedulingPreference - Specify the target scheduling preference.

Definition at line 434 of file TargetLowering.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setSetCCIsExpensive (  )  [inline, protected]

setSetCCIxExpensive - This is a short term hack for targets that codegen setcc as a conditional branch. This encourages the code generator to fold setcc operations into other operations if possible.

Definition at line 461 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLowering::setSetCCResultContents ( SetCCResultValue  Ty  )  [inline, protected]

setSetCCResultContents - Specify how the target extends the result of a setcc operation in a register.

Definition at line 431 of file TargetLowering.h.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setSetCCResultType ( MVT::ValueType  VT  )  [inline, protected]

setSetCCResultType - Describe the type that shoudl be used as the result of a setcc operation. This defaults to the pointer type.

Definition at line 427 of file TargetLowering.h.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setShiftAmountFlavor ( OutOfRangeShiftAmount  OORSA  )  [inline, protected]

setShiftAmountFlavor - Describe how the target handles out of range shift amounts.

Definition at line 440 of file TargetLowering.h.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setShiftAmountType ( MVT::ValueType  VT  )  [inline, protected]

setShiftAmountType - Describe the type that should be used for shift amounts. This type defaults to the pointer type.

Definition at line 423 of file TargetLowering.h.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setStackPointerRegisterToSaveRestore ( unsigned  R  )  [inline, protected]

setStackPointerRegisterToSaveRestore - If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 454 of file TargetLowering.h.

Referenced by llvm::AlphaTargetLowering::AlphaTargetLowering(), llvm::IA64TargetLowering::IA64TargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

void llvm::TargetLowering::setTargetDAGCombine ( ISD::NodeType  NT  )  [inline, protected]

setTargetDAGCombine - Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

Definition at line 513 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

void llvm::TargetLowering::setUseUnderscoreSetJmpLongJmp ( bool  Val  )  [inline, protected]

setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or the non _ versions. Defaults to false.

Definition at line 447 of file TargetLowering.h.

Referenced by llvm::PPCTargetLowering::PPCTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

bool TargetLowering::SimplifyDemandedBits ( SDOperand  Op,
uint64_t  DemandedMask,
uint64_t &  KnownZero,
uint64_t &  KnownOne,
TargetLoweringOpt TLO,
unsigned  Depth = 0 
) const

SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

Definition at line 225 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::AssertZext, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), ComputeMaskedBits(), llvm::ISD::Constant, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntVTBitMask(), llvm::MVT::getIntVTSignBit(), llvm::SelectionDAG::getNode(), getSetCCResultContents(), llvm::MVT::getSizeInBits(), llvm::Value::hasOneUse(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Log2_32(), Op, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::UNDEF, llvm::Use::Val, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, ZeroOrOneSetCCResult, and llvm::ISD::ZEXTLOAD.

bool llvm::TargetLowering::usesUnderscoreSetJmpLongJmp (  )  const [inline]

usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 309 of file TargetLowering.h.

Referenced by llvm::SelectionDAGLowering::visitIntrinsicCall().


Member Data Documentation

bool llvm::TargetLowering::allowUnalignedMemoryAccesses [protected]

Indicate whether the target permits unaligned memory accesses.

This field specifies whether the target machine permits unaligned memory accesses. This is used, for example, to determine the size of store operations when copying small arrays and other similar tasks.

Definition at line 772 of file TargetLowering.h.

Referenced by allowsUnalignedMemoryAccesses(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

unsigned llvm::TargetLowering::maxStoresPerMemcpy [protected]

Specify maximum bytes of store instructions per memcpy call.

When lowering llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 755 of file TargetLowering.h.

Referenced by getMaxStoresPerMemcpy(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

unsigned llvm::TargetLowering::maxStoresPerMemmove [protected]

Specify maximum bytes of store instructions per memmove call.

When lowering llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 766 of file TargetLowering.h.

Referenced by getMaxStoresPerMemmove(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

unsigned llvm::TargetLowering::maxStoresPerMemset [protected]

Specify maximum number of store instructions per memset call.

When lowering llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 743 of file TargetLowering.h.

Referenced by getMaxStoresPerMemset(), TargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().


The documentation for this class was generated from the following files: