LLVM API Documentation
00001 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file describes an abstract interface used to get information about a 00011 // target machines register file. This information is used for a variety of 00012 // purposed, especially register allocation. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #ifndef LLVM_TARGET_MREGISTERINFO_H 00017 #define LLVM_TARGET_MREGISTERINFO_H 00018 00019 #include "llvm/CodeGen/MachineBasicBlock.h" 00020 #include "llvm/CodeGen/ValueTypes.h" 00021 #include <cassert> 00022 #include <functional> 00023 00024 namespace llvm { 00025 00026 class Type; 00027 class MachineFunction; 00028 class MachineInstr; 00029 class MachineLocation; 00030 class MachineMove; 00031 class TargetRegisterClass; 00032 00033 /// TargetRegisterDesc - This record contains all of the information known about 00034 /// a particular register. The AliasSet field (if not null) contains a pointer 00035 /// to a Zero terminated array of registers that this register aliases. This is 00036 /// needed for architectures like X86 which have AL alias AX alias EAX. 00037 /// Registers that this does not apply to simply should set this to null. 00038 /// 00039 struct TargetRegisterDesc { 00040 const char *Name; // Assembly language name for the register 00041 const unsigned *AliasSet; // Register Alias Set, described above 00042 }; 00043 00044 class TargetRegisterClass { 00045 public: 00046 typedef const unsigned* iterator; 00047 typedef const unsigned* const_iterator; 00048 00049 typedef const MVT::ValueType* vt_iterator; 00050 private: 00051 const vt_iterator VTs; 00052 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 00053 const iterator RegsBegin, RegsEnd; 00054 public: 00055 TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al, 00056 iterator RB, iterator RE) 00057 : VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {} 00058 virtual ~TargetRegisterClass() {} // Allow subclasses 00059 00060 // begin/end - Return all of the registers in this class. 00061 iterator begin() const { return RegsBegin; } 00062 iterator end() const { return RegsEnd; } 00063 00064 // getNumRegs - Return the number of registers in this class 00065 unsigned getNumRegs() const { return RegsEnd-RegsBegin; } 00066 00067 // getRegister - Return the specified register in the class 00068 unsigned getRegister(unsigned i) const { 00069 assert(i < getNumRegs() && "Register number out of range!"); 00070 return RegsBegin[i]; 00071 } 00072 00073 /// contains - Return true if the specified register is included in this 00074 /// register class. 00075 bool contains(unsigned Reg) const { 00076 for (iterator I = begin(), E = end(); I != E; ++I) 00077 if (*I == Reg) return true; 00078 return false; 00079 } 00080 00081 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 00082 /// 00083 bool hasType(MVT::ValueType vt) const { 00084 for(int i = 0; VTs[i] != MVT::Other; ++i) 00085 if (VTs[i] == vt) 00086 return true; 00087 return false; 00088 } 00089 00090 /// vt_begin - Loop over all of the value types that can be represented by 00091 /// values in this register class. 00092 vt_iterator vt_begin() const { 00093 return VTs; 00094 } 00095 00096 /// vt_begin - Loop over all of the value types that can be represented by 00097 /// values in this register class. 00098 vt_iterator vt_end() const { 00099 vt_iterator I = VTs; 00100 while (*I != MVT::Other) ++I; 00101 return I; 00102 } 00103 00104 00105 /// allocation_order_begin/end - These methods define a range of registers 00106 /// which specify the registers in this class that are valid to register 00107 /// allocate, and the preferred order to allocate them in. For example, 00108 /// callee saved registers should be at the end of the list, because it is 00109 /// cheaper to allocate caller saved registers. 00110 /// 00111 /// These methods take a MachineFunction argument, which can be used to tune 00112 /// the allocatable registers based on the characteristics of the function. 00113 /// One simple example is that the frame pointer register can be used if 00114 /// frame-pointer-elimination is performed. 00115 /// 00116 /// By default, these methods return all registers in the class. 00117 /// 00118 virtual iterator allocation_order_begin(MachineFunction &MF) const { 00119 return begin(); 00120 } 00121 virtual iterator allocation_order_end(MachineFunction &MF) const { 00122 return end(); 00123 } 00124 00125 00126 00127 /// getSize - Return the size of the register in bytes, which is also the size 00128 /// of a stack slot allocated to hold a spilled copy of this register. 00129 unsigned getSize() const { return RegSize; } 00130 00131 /// getAlignment - Return the minimum required alignment for a register of 00132 /// this class. 00133 unsigned getAlignment() const { return Alignment; } 00134 }; 00135 00136 00137 /// MRegisterInfo base class - We assume that the target defines a static array 00138 /// of TargetRegisterDesc objects that represent all of the machine registers 00139 /// that the target has. As such, we simply have to track a pointer to this 00140 /// array so that we can turn register number into a register descriptor. 00141 /// 00142 class MRegisterInfo { 00143 public: 00144 typedef const TargetRegisterClass * const * regclass_iterator; 00145 private: 00146 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 00147 unsigned NumRegs; // Number of entries in the array 00148 00149 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 00150 00151 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 00152 protected: 00153 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 00154 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, 00155 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1); 00156 virtual ~MRegisterInfo(); 00157 public: 00158 00159 enum { // Define some target independent constants 00160 /// NoRegister - This 'hard' register is a 'noop' register for all backends. 00161 /// This is used as the destination register for instructions that do not 00162 /// produce a value. Some frontends may use this as an operand register to 00163 /// mean special things, for example, the Sparc backend uses R0 to mean %g0 00164 /// which always PRODUCES the value 0. The X86 backend does not use this 00165 /// value as an operand register, except for memory references. 00166 /// 00167 NoRegister = 0, 00168 00169 /// FirstVirtualRegister - This is the first register number that is 00170 /// considered to be a 'virtual' register, which is part of the SSA 00171 /// namespace. This must be the same for all targets, which means that each 00172 /// target is limited to 1024 registers. 00173 /// 00174 FirstVirtualRegister = 1024 00175 }; 00176 00177 /// isPhysicalRegister - Return true if the specified register number is in 00178 /// the physical register namespace. 00179 static bool isPhysicalRegister(unsigned Reg) { 00180 assert(Reg && "this is not a register!"); 00181 return Reg < FirstVirtualRegister; 00182 } 00183 00184 /// isVirtualRegister - Return true if the specified register number is in 00185 /// the virtual register namespace. 00186 static bool isVirtualRegister(unsigned Reg) { 00187 assert(Reg && "this is not a register!"); 00188 return Reg >= FirstVirtualRegister; 00189 } 00190 00191 /// getAllocatableSet - Returns a bitset indexed by register number 00192 /// indicating if a register is allocatable or not. 00193 std::vector<bool> getAllocatableSet(MachineFunction &MF) const; 00194 00195 const TargetRegisterDesc &operator[](unsigned RegNo) const { 00196 assert(RegNo < NumRegs && 00197 "Attempting to access record for invalid register number!"); 00198 return Desc[RegNo]; 00199 } 00200 00201 /// Provide a get method, equivalent to [], but more useful if we have a 00202 /// pointer to this object. 00203 /// 00204 const TargetRegisterDesc &get(unsigned RegNo) const { 00205 return operator[](RegNo); 00206 } 00207 00208 /// getAliasSet - Return the set of registers aliased by the specified 00209 /// register, or a null list of there are none. The list returned is zero 00210 /// terminated. 00211 /// 00212 const unsigned *getAliasSet(unsigned RegNo) const { 00213 return get(RegNo).AliasSet; 00214 } 00215 00216 /// getName - Return the symbolic target specific name for the specified 00217 /// physical register. 00218 const char *getName(unsigned RegNo) const { 00219 return get(RegNo).Name; 00220 } 00221 00222 /// getNumRegs - Return the number of registers this target has 00223 /// (useful for sizing arrays holding per register information) 00224 unsigned getNumRegs() const { 00225 return NumRegs; 00226 } 00227 00228 /// areAliases - Returns true if the two registers alias each other, 00229 /// false otherwise 00230 bool areAliases(unsigned regA, unsigned regB) const { 00231 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) 00232 if (*Alias == regB) return true; 00233 return false; 00234 } 00235 00236 /// getCalleeSaveRegs - Return a null-terminated list of all of the 00237 /// callee-save registers on this target. 00238 virtual const unsigned* getCalleeSaveRegs() const = 0; 00239 00240 /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred 00241 /// register classes to spill each callee-saved register with. The order and 00242 /// length of this list match the getCalleeSaveRegs() list. 00243 virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0; 00244 00245 //===--------------------------------------------------------------------===// 00246 // Register Class Information 00247 // 00248 00249 /// Register class iterators 00250 /// 00251 regclass_iterator regclass_begin() const { return RegClassBegin; } 00252 regclass_iterator regclass_end() const { return RegClassEnd; } 00253 00254 unsigned getNumRegClasses() const { 00255 return regclass_end()-regclass_begin(); 00256 } 00257 00258 //===--------------------------------------------------------------------===// 00259 // Interfaces used by the register allocator and stack frame 00260 // manipulation passes to move data around between registers, 00261 // immediates and memory. The return value is the number of 00262 // instructions added to (negative if removed from) the basic block. 00263 // 00264 00265 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 00266 MachineBasicBlock::iterator MI, 00267 unsigned SrcReg, int FrameIndex, 00268 const TargetRegisterClass *RC) const = 0; 00269 00270 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 00271 MachineBasicBlock::iterator MI, 00272 unsigned DestReg, int FrameIndex, 00273 const TargetRegisterClass *RC) const = 0; 00274 00275 virtual void copyRegToReg(MachineBasicBlock &MBB, 00276 MachineBasicBlock::iterator MI, 00277 unsigned DestReg, unsigned SrcReg, 00278 const TargetRegisterClass *RC) const = 0; 00279 00280 /// foldMemoryOperand - Attempt to fold a load or store of the 00281 /// specified stack slot into the specified machine instruction for 00282 /// the specified operand. If this is possible, a new instruction 00283 /// is returned with the specified operand folded, otherwise NULL is 00284 /// returned. The client is responsible for removing the old 00285 /// instruction and adding the new one in the instruction stream 00286 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 00287 unsigned OpNum, 00288 int FrameIndex) const { 00289 return 0; 00290 } 00291 00292 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 00293 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 00294 /// targets use pseudo instructions in order to abstract away the difference 00295 /// between operating with a frame pointer and operating without, through the 00296 /// use of these two instructions. 00297 /// 00298 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 00299 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 00300 00301 00302 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 00303 /// code insertion to eliminate call frame setup and destroy pseudo 00304 /// instructions (but only if the Target is using them). It is responsible 00305 /// for eliminating these instructions, replacing them with concrete 00306 /// instructions. This method need only be implemented if using call frame 00307 /// setup/destroy pseudo instructions. 00308 /// 00309 virtual void 00310 eliminateCallFramePseudoInstr(MachineFunction &MF, 00311 MachineBasicBlock &MBB, 00312 MachineBasicBlock::iterator MI) const { 00313 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 00314 "eliminateCallFramePseudoInstr must be implemented if using" 00315 " call frame setup/destroy pseudo instructions!"); 00316 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 00317 } 00318 00319 /// processFunctionBeforeFrameFinalized - This method is called immediately 00320 /// before the specified functions frame layout (MF.getFrameInfo()) is 00321 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 00322 /// replaced with direct constants. This method is optional. The return value 00323 /// is the number of instructions added to (negative if removed from) the 00324 /// basic block 00325 /// 00326 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 00327 } 00328 00329 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 00330 /// frame indices from instructions which may use them. The instruction 00331 /// referenced by the iterator contains an MO_FrameIndex operand which must be 00332 /// eliminated by this method. This method may modify or replace the 00333 /// specified instruction, as long as it keeps the iterator pointing the the 00334 /// finished product. The return value is the number of instructions 00335 /// added to (negative if removed from) the basic block. 00336 /// 00337 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0; 00338 00339 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 00340 /// the function. The return value is the number of instructions 00341 /// added to (negative if removed from) the basic block (entry for prologue). 00342 /// 00343 virtual void emitPrologue(MachineFunction &MF) const = 0; 00344 virtual void emitEpilogue(MachineFunction &MF, 00345 MachineBasicBlock &MBB) const = 0; 00346 00347 //===--------------------------------------------------------------------===// 00348 /// Debug information queries. 00349 00350 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 00351 /// number. Returns -1 if there is no equivalent value. 00352 virtual int getDwarfRegNum(unsigned RegNum) const = 0; 00353 00354 /// getFrameRegister - This method should return the register used as a base 00355 /// for values allocated in the current stack frame. 00356 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 00357 00358 /// getRARegister - This method should return the register where the return 00359 /// address can be found. 00360 virtual unsigned getRARegister() const = 0; 00361 00362 /// getLocation - This method should return the actual location of a frame 00363 /// variable given the frame index. The location is returned in ML. 00364 /// Subclasses should override this method for special handling of frame 00365 /// variables and call MRegisterInfo::getLocation for the default action. 00366 virtual void getLocation(MachineFunction &MF, unsigned Index, 00367 MachineLocation &ML) const; 00368 00369 /// getInitialFrameState - Returns a list of machine moves that are assumed 00370 /// on entry to all functions. Note that LabelID is ignored (assumed to be 00371 /// the beginning of the function.) 00372 virtual void getInitialFrameState(std::vector<MachineMove *> &Moves) const; 00373 }; 00374 00375 // This is useful when building DenseMaps keyed on virtual registers 00376 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 00377 unsigned operator()(unsigned Reg) const { 00378 return Reg - MRegisterInfo::FirstVirtualRegister; 00379 } 00380 }; 00381 00382 } // End llvm namespace 00383 00384 #endif