LLVM API Documentation
00001 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file describes the target machine instructions to the code generator. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef LLVM_TARGET_TARGETINSTRINFO_H 00015 #define LLVM_TARGET_TARGETINSTRINFO_H 00016 00017 #include "llvm/CodeGen/MachineBasicBlock.h" 00018 #include "llvm/Support/DataTypes.h" 00019 #include <vector> 00020 #include <cassert> 00021 00022 namespace llvm { 00023 00024 class MachineInstr; 00025 class TargetMachine; 00026 class Value; 00027 class Type; 00028 class Instruction; 00029 class Constant; 00030 class Function; 00031 class MachineCodeForInstruction; 00032 class TargetRegisterClass; 00033 00034 //--------------------------------------------------------------------------- 00035 // Data types used to define information about a single machine instruction 00036 //--------------------------------------------------------------------------- 00037 00038 typedef short MachineOpCode; 00039 typedef unsigned InstrSchedClass; 00040 00041 //--------------------------------------------------------------------------- 00042 // struct TargetInstrDescriptor: 00043 // Predefined information about each machine instruction. 00044 // Designed to initialized statically. 00045 // 00046 00047 const unsigned M_NOP_FLAG = 1 << 0; 00048 const unsigned M_BRANCH_FLAG = 1 << 1; 00049 const unsigned M_CALL_FLAG = 1 << 2; 00050 const unsigned M_RET_FLAG = 1 << 3; 00051 const unsigned M_BARRIER_FLAG = 1 << 4; 00052 const unsigned M_DELAY_SLOT_FLAG = 1 << 5; 00053 const unsigned M_CC_FLAG = 1 << 6; 00054 const unsigned M_LOAD_FLAG = 1 << 7; 00055 const unsigned M_STORE_FLAG = 1 << 8; 00056 00057 // M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 00058 const unsigned M_2_ADDR_FLAG = 1 << 9; 00059 00060 // M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 00061 // changed into a 3-address instruction if the first two operands cannot be 00062 // assigned to the same register. The target must implement the 00063 // TargetInstrInfo::convertToThreeAddress method for this instruction. 00064 const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10; 00065 00066 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 00067 // Z), which produces the same result if Y and Z are exchanged. 00068 const unsigned M_COMMUTABLE = 1 << 11; 00069 00070 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 00071 // block? Typically this is things like return and branch instructions. 00072 // Various passes use this to insert code into the bottom of a basic block, but 00073 // before control flow occurs. 00074 const unsigned M_TERMINATOR_FLAG = 1 << 12; 00075 00076 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 00077 // insertion support when the DAG scheduler is inserting it into a machine basic 00078 // block. 00079 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 13; 00080 00081 /// TargetOperandInfo - This holds information about one operand of a machine 00082 /// instruction, indicating the register class for register operands, etc. 00083 /// 00084 class TargetOperandInfo { 00085 public: 00086 /// RegClass - This specifies the register class of the operand if the 00087 /// operand is a register. If not, this contains null. 00088 const TargetRegisterClass *RegClass; 00089 00090 /// Currently no other information. 00091 }; 00092 00093 00094 class TargetInstrDescriptor { 00095 public: 00096 const char * Name; // Assembly language mnemonic for the opcode. 00097 int numOperands; // Number of args; -1 if variable #args 00098 int resultPos; // Position of the result; -1 if no result 00099 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 00100 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 00101 // smallest -ve value is -(maxImmedConst+1). 00102 unsigned numDelaySlots; // Number of delay slots after instruction 00103 unsigned latency; // Latency in machine cycles 00104 InstrSchedClass schedClass; // enum identifying instr sched class 00105 unsigned Flags; // flags identifying machine instr class 00106 unsigned TSFlags; // Target Specific Flag values 00107 const unsigned *ImplicitUses; // Registers implicitly read by this instr 00108 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 00109 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 00110 }; 00111 00112 00113 //--------------------------------------------------------------------------- 00114 /// 00115 /// TargetInstrInfo - Interface to description of machine instructions 00116 /// 00117 class TargetInstrInfo { 00118 const TargetInstrDescriptor* desc; // raw array to allow static init'n 00119 unsigned NumOpcodes; // number of entries in the desc array 00120 unsigned numRealOpCodes; // number of non-dummy op codes 00121 00122 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 00123 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 00124 public: 00125 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 00126 virtual ~TargetInstrInfo(); 00127 00128 // Invariant opcodes: All instruction sets have these as their low opcodes. 00129 enum { 00130 PHI = 0, 00131 INLINEASM = 1 00132 }; 00133 00134 unsigned getNumOpcodes() const { return NumOpcodes; } 00135 00136 /// get - Return the machine instruction descriptor that corresponds to the 00137 /// specified instruction opcode. 00138 /// 00139 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 00140 assert((unsigned)Opcode < NumOpcodes); 00141 return desc[Opcode]; 00142 } 00143 00144 const char *getName(MachineOpCode Opcode) const { 00145 return get(Opcode).Name; 00146 } 00147 00148 int getNumOperands(MachineOpCode Opcode) const { 00149 return get(Opcode).numOperands; 00150 } 00151 00152 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 00153 return get(Opcode).schedClass; 00154 } 00155 00156 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 00157 return get(Opcode).ImplicitUses; 00158 } 00159 00160 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 00161 return get(Opcode).ImplicitDefs; 00162 } 00163 00164 00165 // 00166 // Query instruction class flags according to the machine-independent 00167 // flags listed above. 00168 // 00169 bool isReturn(MachineOpCode Opcode) const { 00170 return get(Opcode).Flags & M_RET_FLAG; 00171 } 00172 00173 bool isTwoAddrInstr(MachineOpCode Opcode) const { 00174 return get(Opcode).Flags & M_2_ADDR_FLAG; 00175 } 00176 bool isTerminatorInstr(unsigned Opcode) const { 00177 return get(Opcode).Flags & M_TERMINATOR_FLAG; 00178 } 00179 00180 bool isBranch(MachineOpCode Opcode) const { 00181 return get(Opcode).Flags & M_BRANCH_FLAG; 00182 } 00183 00184 /// isBarrier - Returns true if the specified instruction stops control flow 00185 /// from executing the instruction immediately following it. Examples include 00186 /// unconditional branches and return instructions. 00187 bool isBarrier(MachineOpCode Opcode) const { 00188 return get(Opcode).Flags & M_BARRIER_FLAG; 00189 } 00190 00191 bool isCall(MachineOpCode Opcode) const { 00192 return get(Opcode).Flags & M_CALL_FLAG; 00193 } 00194 bool isLoad(MachineOpCode Opcode) const { 00195 return get(Opcode).Flags & M_LOAD_FLAG; 00196 } 00197 bool isStore(MachineOpCode Opcode) const { 00198 return get(Opcode).Flags & M_STORE_FLAG; 00199 } 00200 00201 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 00202 /// custom insertion support when the DAG scheduler is inserting it into a 00203 /// machine basic block. 00204 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 00205 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 00206 } 00207 00208 /// Return true if the instruction is a register to register move 00209 /// and leave the source and dest operands in the passed parameters. 00210 virtual bool isMoveInstr(const MachineInstr& MI, 00211 unsigned& sourceReg, 00212 unsigned& destReg) const { 00213 return false; 00214 } 00215 00216 /// isLoadFromStackSlot - If the specified machine instruction is a direct 00217 /// load from a stack slot, return the virtual or physical register number of 00218 /// the destination along with the FrameIndex of the loaded stack slot. If 00219 /// not, return 0. This predicate must return 0 if the instruction has 00220 /// any side effects other than loading from the stack slot. 00221 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 00222 return 0; 00223 } 00224 00225 /// isStoreToStackSlot - If the specified machine instruction is a direct 00226 /// store to a stack slot, return the virtual or physical register number of 00227 /// the source reg along with the FrameIndex of the loaded stack slot. If 00228 /// not, return 0. This predicate must return 0 if the instruction has 00229 /// any side effects other than storing to the stack slot. 00230 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 00231 return 0; 00232 } 00233 00234 /// convertToThreeAddress - This method must be implemented by targets that 00235 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 00236 /// may be able to convert a two-address instruction into a true 00237 /// three-address instruction on demand. This allows the X86 target (for 00238 /// example) to convert ADD and SHL instructions into LEA instructions if they 00239 /// would require register copies due to two-addressness. 00240 /// 00241 /// This method returns a null pointer if the transformation cannot be 00242 /// performed, otherwise it returns the new instruction. 00243 /// 00244 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 00245 return 0; 00246 } 00247 00248 /// commuteInstruction - If a target has any instructions that are commutable, 00249 /// but require converting to a different instruction or making non-trivial 00250 /// changes to commute them, this method can overloaded to do this. The 00251 /// default implementation of this method simply swaps the first two operands 00252 /// of MI and returns it. 00253 /// 00254 /// If a target wants to make more aggressive changes, they can construct and 00255 /// return a new machine instruction. If an instruction cannot commute, it 00256 /// can also return null. 00257 /// 00258 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 00259 00260 /// Insert a goto (unconditional branch) sequence to TMBB, at the 00261 /// end of MBB 00262 virtual void insertGoto(MachineBasicBlock& MBB, 00263 MachineBasicBlock& TMBB) const { 00264 assert(0 && "Target didn't implement insertGoto!"); 00265 } 00266 00267 /// Reverses the branch condition of the MachineInstr pointed by 00268 /// MI. The instruction is replaced and the new MI is returned. 00269 virtual MachineBasicBlock::iterator 00270 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 00271 assert(0 && "Target didn't implement reverseBranchCondition!"); 00272 abort(); 00273 return MI; 00274 } 00275 00276 /// insertNoop - Insert a noop into the instruction stream at the specified 00277 /// point. 00278 virtual void insertNoop(MachineBasicBlock &MBB, 00279 MachineBasicBlock::iterator MI) const { 00280 assert(0 && "Target didn't implement insertNoop!"); 00281 abort(); 00282 } 00283 00284 //------------------------------------------------------------------------- 00285 // Code generation support for creating individual machine instructions 00286 // 00287 // WARNING: These methods are Sparc specific 00288 // 00289 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 00290 // 00291 //------------------------------------------------------------------------- 00292 00293 unsigned getNumDelaySlots(MachineOpCode Opcode) const { 00294 return get(Opcode).numDelaySlots; 00295 } 00296 bool isCCInstr(MachineOpCode Opcode) const { 00297 return get(Opcode).Flags & M_CC_FLAG; 00298 } 00299 bool isNop(MachineOpCode Opcode) const { 00300 return get(Opcode).Flags & M_NOP_FLAG; 00301 } 00302 00303 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 00304 /// which must be filled by the code generator. 00305 bool hasDelaySlot(unsigned Opcode) const { 00306 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 00307 } 00308 00309 virtual bool hasResultInterlock(MachineOpCode Opcode) const { 00310 return true; 00311 } 00312 00313 // 00314 // Latencies for individual instructions and instruction pairs 00315 // 00316 virtual int minLatency(MachineOpCode Opcode) const { 00317 return get(Opcode).latency; 00318 } 00319 00320 virtual int maxLatency(MachineOpCode Opcode) const { 00321 return get(Opcode).latency; 00322 } 00323 00324 // 00325 // Which operand holds an immediate constant? Returns -1 if none 00326 // 00327 virtual int getImmedConstantPos(MachineOpCode Opcode) const { 00328 return -1; // immediate position is machine specific, so say -1 == "none" 00329 } 00330 00331 // Check if the specified constant fits in the immediate field 00332 // of this machine instruction 00333 // 00334 virtual bool constantFitsInImmedField(MachineOpCode Opcode, 00335 int64_t intValue) const; 00336 00337 // Return the largest positive constant that can be held in the IMMED field 00338 // of this machine instruction. 00339 // isSignExtended is set to true if the value is sign-extended before use 00340 // (this is true for all immediate fields in SPARC instructions). 00341 // Return 0 if the instruction has no IMMED field. 00342 // 00343 virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 00344 bool &isSignExtended) const { 00345 isSignExtended = get(Opcode).immedIsSignExtended; 00346 return get(Opcode).maxImmedConst; 00347 } 00348 }; 00349 00350 } // End llvm namespace 00351 00352 #endif