LLVM API Documentation
00001 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the declaration of the MachineInstr class, which is the 00011 // basic representation for all target dependent machine instructions used by 00012 // the back end. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #ifndef LLVM_CODEGEN_MACHINEINSTR_H 00017 #define LLVM_CODEGEN_MACHINEINSTR_H 00018 00019 #include "llvm/ADT/iterator" 00020 #include "llvm/Support/DataTypes.h" 00021 #include <vector> 00022 #include <cassert> 00023 00024 namespace llvm { 00025 00026 class Value; 00027 class Function; 00028 class MachineBasicBlock; 00029 class TargetMachine; 00030 class GlobalValue; 00031 00032 template <typename T> struct ilist_traits; 00033 template <typename T> struct ilist; 00034 00035 typedef short MachineOpCode; 00036 00037 //===----------------------------------------------------------------------===// 00038 // class MachineOperand 00039 // 00040 // Purpose: 00041 // Representation of each machine instruction operand. 00042 // This class is designed so that you can allocate a vector of operands 00043 // first and initialize each one later. 00044 // 00045 // E.g, for this VM instruction: 00046 // ptr = alloca type, numElements 00047 // we generate 2 machine instructions on the SPARC: 00048 // 00049 // mul Constant, Numelements -> Reg 00050 // add %sp, Reg -> Ptr 00051 // 00052 // Each instruction has 3 operands, listed above. Of those: 00053 // - Reg, NumElements, and Ptr are of operand type MO_Register. 00054 // - Constant is of operand type MO_SignExtendedImmed on the SPARC. 00055 // 00056 // For the register operands, the virtual register type is as follows: 00057 // 00058 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field 00059 // MachineInstr* minstr will point to the instruction that computes reg. 00060 // 00061 // - %sp will be of virtual register type MO_MachineReg. 00062 // The field regNum identifies the machine register. 00063 // 00064 // - NumElements will be of virtual register type MO_VirtualReg. 00065 // The field Value* value identifies the value. 00066 // 00067 // - Ptr will also be of virtual register type MO_VirtualReg. 00068 // Again, the field Value* value identifies the value. 00069 // 00070 //===----------------------------------------------------------------------===// 00071 00072 struct MachineOperand { 00073 private: 00074 // Bit fields of the flags variable used for different operand properties 00075 enum { 00076 DEFFLAG = 0x01, // this is a def of the operand 00077 USEFLAG = 0x02, // this is a use of the operand 00078 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 00079 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 00080 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 00081 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 00082 PCRELATIVE = 0x40 // Operand is relative to PC, not a global address 00083 }; 00084 00085 public: 00086 // UseType - This enum describes how the machine operand is used by 00087 // the instruction. Note that the MachineInstr/Operator class 00088 // currently uses bool arguments to represent this information 00089 // instead of an enum. Eventually this should change over to use 00090 // this _easier to read_ representation instead. 00091 // 00092 enum UseType { 00093 Use = USEFLAG, /// only read 00094 Def = DEFFLAG, /// only written 00095 UseAndDef = Use | Def /// read AND written 00096 }; 00097 00098 enum MachineOperandType { 00099 MO_VirtualRegister, // virtual register for *value 00100 MO_MachineRegister, // pre-assigned machine register `regNum' 00101 MO_CCRegister, 00102 MO_SignExtendedImmed, 00103 MO_UnextendedImmed, 00104 MO_PCRelativeDisp, 00105 MO_MachineBasicBlock, // MachineBasicBlock reference 00106 MO_FrameIndex, // Abstract Stack Frame Index 00107 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 00108 MO_ExternalSymbol, // Name of external global symbol 00109 MO_GlobalAddress // Address of a global value 00110 }; 00111 00112 private: 00113 union { 00114 Value* value; // BasicBlockVal for a label operand. 00115 // ConstantVal for a non-address immediate. 00116 // Virtual register for an SSA operand, 00117 // including hidden operands required for 00118 // the generated machine code. 00119 // LLVM global for MO_GlobalAddress. 00120 00121 int64_t immedVal; // Constant value for an explicit constant 00122 00123 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 00124 const char *SymbolName; // For MO_ExternalSymbol type 00125 } contents; 00126 00127 char flags; // see bit field definitions above 00128 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 00129 union { 00130 int regNum; // register number for an explicit register 00131 // will be set for a value after reg allocation 00132 00133 int offset; // Offset to address of global or external, only 00134 // valid for MO_GlobalAddress, MO_ExternalSym 00135 // and MO_ConstantPoolIndex 00136 } extra; 00137 00138 void zeroContents () { 00139 memset (&contents, 0, sizeof (contents)); 00140 memset (&extra, 0, sizeof (extra)); 00141 } 00142 00143 MachineOperand(int64_t ImmVal = 0, 00144 MachineOperandType OpTy = MO_VirtualRegister, int Offset = 0) 00145 : flags(0), opType(OpTy) { 00146 zeroContents (); 00147 contents.immedVal = ImmVal; 00148 if (OpTy == MachineOperand::MO_ConstantPoolIndex) 00149 extra.offset = Offset; 00150 else 00151 extra.regNum = -1; 00152 } 00153 00154 MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) 00155 : flags(UseTy), opType(OpTy) { 00156 zeroContents (); 00157 extra.regNum = Reg; 00158 } 00159 00160 MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy, 00161 bool isPCRelative = false) 00162 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { 00163 assert(OpTy != MachineOperand::MO_GlobalAddress); 00164 zeroContents(); 00165 contents.value = V; 00166 extra.regNum = -1; 00167 } 00168 00169 MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy, 00170 bool isPCRelative = false, int Offset = 0) 00171 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { 00172 assert(OpTy == MachineOperand::MO_GlobalAddress); 00173 zeroContents (); 00174 contents.value = (Value*)V; 00175 extra.offset = Offset; 00176 } 00177 00178 MachineOperand(MachineBasicBlock *mbb) 00179 : flags(0), opType(MO_MachineBasicBlock) { 00180 zeroContents (); 00181 contents.MBB = mbb; 00182 extra.regNum = -1; 00183 } 00184 00185 MachineOperand(const char *SymName, bool isPCRelative, int Offset) 00186 : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) { 00187 zeroContents (); 00188 contents.SymbolName = SymName; 00189 extra.offset = Offset; 00190 } 00191 00192 public: 00193 MachineOperand(const MachineOperand &M) 00194 : flags(M.flags), opType(M.opType) { 00195 zeroContents (); 00196 contents = M.contents; 00197 extra = M.extra; 00198 } 00199 00200 00201 ~MachineOperand() {} 00202 00203 const MachineOperand &operator=(const MachineOperand &MO) { 00204 contents = MO.contents; 00205 flags = MO.flags; 00206 opType = MO.opType; 00207 extra = MO.extra; 00208 return *this; 00209 } 00210 00211 /// getType - Returns the MachineOperandType for this operand. 00212 /// 00213 MachineOperandType getType() const { return opType; } 00214 00215 /// getUseType - Returns the MachineOperandUseType of this operand. 00216 /// 00217 UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } 00218 00219 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 00220 /// indicates whether this operand should be emitted as a PC relative value 00221 /// instead of a global address. This is used for operands of the forms: 00222 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 00223 /// 00224 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 00225 00226 /// isRegister - Return true if this operand is a register operand. The X86 00227 /// backend currently can't decide whether to use MO_MR or MO_VR to represent 00228 /// them, so we accept both. 00229 /// 00230 /// Note: The sparc backend should not use this method. 00231 /// 00232 bool isRegister() const { 00233 return opType == MO_MachineRegister || opType == MO_VirtualRegister; 00234 } 00235 00236 /// Accessors that tell you what kind of MachineOperand you're looking at. 00237 /// 00238 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 00239 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 00240 bool isImmediate() const { 00241 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 00242 } 00243 bool isFrameIndex() const { return opType == MO_FrameIndex; } 00244 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 00245 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 00246 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 00247 00248 /// getVRegValueOrNull - Get the Value* out of a MachineOperand if it 00249 /// has one. This is deprecated and only used by the SPARC v9 backend. 00250 /// 00251 Value* getVRegValueOrNull() const { 00252 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 00253 isPCRelativeDisp()) ? contents.value : NULL; 00254 } 00255 00256 /// MachineOperand accessors that only work on certain types of 00257 /// MachineOperand... 00258 /// 00259 Value* getVRegValue() const { 00260 assert ((opType == MO_VirtualRegister || opType == MO_CCRegister 00261 || isPCRelativeDisp()) && "Wrong MachineOperand accessor"); 00262 return contents.value; 00263 } 00264 int getMachineRegNum() const { 00265 assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor"); 00266 return extra.regNum; 00267 } 00268 int64_t getImmedValue() const { 00269 assert(isImmediate() && "Wrong MachineOperand accessor"); 00270 return contents.immedVal; 00271 } 00272 MachineBasicBlock *getMachineBasicBlock() const { 00273 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 00274 return contents.MBB; 00275 } 00276 void setMachineBasicBlock(MachineBasicBlock *MBB) { 00277 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 00278 contents.MBB = MBB; 00279 } 00280 int getFrameIndex() const { 00281 assert(isFrameIndex() && "Wrong MachineOperand accessor"); 00282 return (int)contents.immedVal; 00283 } 00284 unsigned getConstantPoolIndex() const { 00285 assert(isConstantPoolIndex() && "Wrong MachineOperand accessor"); 00286 return (unsigned)contents.immedVal; 00287 } 00288 GlobalValue *getGlobal() const { 00289 assert(isGlobalAddress() && "Wrong MachineOperand accessor"); 00290 return (GlobalValue*)contents.value; 00291 } 00292 int getOffset() const { 00293 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) && 00294 "Wrong MachineOperand accessor"); 00295 return extra.offset; 00296 } 00297 const char *getSymbolName() const { 00298 assert(isExternalSymbol() && "Wrong MachineOperand accessor"); 00299 return contents.SymbolName; 00300 } 00301 00302 /// MachineOperand methods for testing that work on any kind of 00303 /// MachineOperand... 00304 /// 00305 bool isUse () const { return flags & USEFLAG; } 00306 MachineOperand& setUse () { flags |= USEFLAG; return *this; } 00307 bool isDef () const { return flags & DEFFLAG; } 00308 MachineOperand& setDef () { flags |= DEFFLAG; return *this; } 00309 bool isHiBits32 () const { return flags & HIFLAG32; } 00310 bool isLoBits32 () const { return flags & LOFLAG32; } 00311 bool isHiBits64 () const { return flags & HIFLAG64; } 00312 bool isLoBits64 () const { return flags & LOFLAG64; } 00313 00314 /// hasAllocatedReg - Returns true iff a machine register has been 00315 /// allocated to this operand. 00316 /// 00317 bool hasAllocatedReg() const { 00318 return (extra.regNum >= 0 && 00319 (opType == MO_VirtualRegister || opType == MO_CCRegister || 00320 opType == MO_MachineRegister)); 00321 } 00322 00323 /// getReg - Returns the register number. It is a runtime error to call this 00324 /// if a register is not allocated. 00325 /// 00326 unsigned getReg() const { 00327 assert(hasAllocatedReg()); 00328 return extra.regNum; 00329 } 00330 00331 /// MachineOperand mutators... 00332 /// 00333 void setReg(unsigned Reg) { 00334 // This method's comment used to say: 'TODO: get rid of this duplicate 00335 // code.' It's not clear where the duplication is. 00336 assert(hasAllocatedReg() && "This operand cannot have a register number!"); 00337 extra.regNum = Reg; 00338 } 00339 00340 void setValueReg(Value *val) { 00341 assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*"); 00342 contents.value = val; 00343 } 00344 00345 void setImmedValue(int immVal) { 00346 assert(isImmediate() && "Wrong MachineOperand mutator"); 00347 contents.immedVal = immVal; 00348 } 00349 00350 void setOffset(int Offset) { 00351 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) && 00352 "Wrong MachineOperand accessor"); 00353 extra.offset = Offset; 00354 } 00355 00356 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 00357 00358 /// markHi32, markLo32, etc. - These methods are deprecated and only used by 00359 /// the SPARC v9 back-end. 00360 /// 00361 void markHi32() { flags |= HIFLAG32; } 00362 void markLo32() { flags |= LOFLAG32; } 00363 void markHi64() { flags |= HIFLAG64; } 00364 void markLo64() { flags |= LOFLAG64; } 00365 00366 private: 00367 /// setRegForValue - Replaces the Value with its corresponding physical 00368 /// register after register allocation is complete. This is deprecated 00369 /// and only used by the SPARC v9 back-end. 00370 /// 00371 void setRegForValue(int reg) { 00372 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 00373 opType == MO_MachineRegister); 00374 extra.regNum = reg; 00375 } 00376 00377 friend class MachineInstr; 00378 }; 00379 00380 00381 //===----------------------------------------------------------------------===// 00382 // class MachineInstr 00383 // 00384 // Purpose: 00385 // Representation of each machine instruction. 00386 // 00387 // MachineOpCode must be an enum, defined separately for each target. 00388 // E.g., It is defined in SparcInstructionSelection.h for the SPARC. 00389 // 00390 // There are 2 kinds of operands: 00391 // 00392 // (1) Explicit operands of the machine instruction in vector operands[] 00393 // 00394 // (2) "Implicit operands" are values implicitly used or defined by the 00395 // machine instruction, such as arguments to a CALL, return value of 00396 // a CALL (if any), and return value of a RETURN. 00397 //===----------------------------------------------------------------------===// 00398 00399 class MachineInstr { 00400 short Opcode; // the opcode 00401 unsigned char numImplicitRefs; // number of implicit operands 00402 std::vector<MachineOperand> operands; // the operands 00403 MachineInstr* prev, *next; // links for our intrusive list 00404 MachineBasicBlock* parent; // pointer to the owning basic block 00405 00406 // OperandComplete - Return true if it's illegal to add a new operand 00407 bool OperandsComplete() const; 00408 00409 //Constructor used by clone() method 00410 MachineInstr(const MachineInstr&); 00411 00412 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 00413 00414 // Intrusive list support 00415 // 00416 friend struct ilist_traits<MachineInstr>; 00417 00418 public: 00419 MachineInstr(short Opcode, unsigned numOperands); 00420 00421 /// MachineInstr ctor - This constructor only does a _reserve_ of the 00422 /// operands, not a resize for them. It is expected that if you use this that 00423 /// you call add* methods below to fill up the operands, instead of the Set 00424 /// methods. Eventually, the "resizing" ctors will be phased out. 00425 /// 00426 MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY); 00427 00428 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 00429 /// the MachineInstr is created and added to the end of the specified basic 00430 /// block. 00431 /// 00432 MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps); 00433 00434 ~MachineInstr(); 00435 00436 const MachineBasicBlock* getParent() const { return parent; } 00437 MachineBasicBlock* getParent() { return parent; } 00438 00439 /// getOpcode - Returns the opcode of this MachineInstr. 00440 /// 00441 const int getOpcode() const { return Opcode; } 00442 00443 /// Access to explicit operands of the instruction. 00444 /// 00445 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 00446 00447 const MachineOperand& getOperand(unsigned i) const { 00448 assert(i < getNumOperands() && "getOperand() out of range!"); 00449 return operands[i]; 00450 } 00451 MachineOperand& getOperand(unsigned i) { 00452 assert(i < getNumOperands() && "getOperand() out of range!"); 00453 return operands[i]; 00454 } 00455 00456 // 00457 // Access to explicit or implicit operands of the instruction 00458 // This returns the i'th entry in the operand vector. 00459 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 00460 // depending on whether i < N or i >= N. 00461 // 00462 const MachineOperand& getExplOrImplOperand(unsigned i) const { 00463 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 00464 return (i < getNumOperands()? getOperand(i) 00465 : getImplicitOp(i - getNumOperands())); 00466 } 00467 00468 // 00469 // Access to implicit operands of the instruction 00470 // 00471 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 00472 00473 MachineOperand& getImplicitOp(unsigned i) { 00474 assert(i < numImplicitRefs && "implicit ref# out of range!"); 00475 return operands[i + operands.size() - numImplicitRefs]; 00476 } 00477 const MachineOperand& getImplicitOp(unsigned i) const { 00478 assert(i < numImplicitRefs && "implicit ref# out of range!"); 00479 return operands[i + operands.size() - numImplicitRefs]; 00480 } 00481 00482 Value* getImplicitRef(unsigned i) { 00483 return getImplicitOp(i).getVRegValue(); 00484 } 00485 const Value* getImplicitRef(unsigned i) const { 00486 return getImplicitOp(i).getVRegValue(); 00487 } 00488 00489 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 00490 ++numImplicitRefs; 00491 addRegOperand(V, isDef, isDefAndUse); 00492 } 00493 void setImplicitRef(unsigned i, Value* V) { 00494 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 00495 SetMachineOperandVal(i + getNumOperands(), 00496 MachineOperand::MO_VirtualRegister, V); 00497 } 00498 00499 /// clone - Create a copy of 'this' instruction that is identical in 00500 /// all ways except the the instruction has no parent, prev, or next. 00501 MachineInstr* clone() const; 00502 00503 // 00504 // Debugging support 00505 // 00506 void print(std::ostream &OS, const TargetMachine *TM) const; 00507 void dump() const; 00508 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 00509 00510 // Define iterators to access the Value operands of the Machine Instruction. 00511 // Note that these iterators only enumerate the explicit operands. 00512 // begin() and end() are defined to produce these iterators. NOTE, these are 00513 // SparcV9 specific! 00514 // 00515 template<class _MI, class _V> class ValOpIterator; 00516 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 00517 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 00518 00519 00520 //===--------------------------------------------------------------------===// 00521 // Accessors to add operands when building up machine instructions 00522 // 00523 00524 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 00525 /// operands list... 00526 /// 00527 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 00528 assert(!OperandsComplete() && 00529 "Trying to add an operand to a machine instr that is already done!"); 00530 operands.push_back( 00531 MachineOperand(V, MachineOperand::MO_VirtualRegister, 00532 !isDef ? MachineOperand::Use : 00533 (isDefAndUse ? MachineOperand::UseAndDef : 00534 MachineOperand::Def))); 00535 } 00536 00537 void addRegOperand(Value *V, 00538 MachineOperand::UseType UTy = MachineOperand::Use, 00539 bool isPCRelative = false) { 00540 assert(!OperandsComplete() && 00541 "Trying to add an operand to a machine instr that is already done!"); 00542 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 00543 UTy, isPCRelative)); 00544 } 00545 00546 void addCCRegOperand(Value *V, 00547 MachineOperand::UseType UTy = MachineOperand::Use) { 00548 assert(!OperandsComplete() && 00549 "Trying to add an operand to a machine instr that is already done!"); 00550 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 00551 false)); 00552 } 00553 00554 00555 /// addRegOperand - Add a symbolic virtual register reference... 00556 /// 00557 void addRegOperand(int reg, bool isDef) { 00558 assert(!OperandsComplete() && 00559 "Trying to add an operand to a machine instr that is already done!"); 00560 operands.push_back( 00561 MachineOperand(reg, MachineOperand::MO_VirtualRegister, 00562 isDef ? MachineOperand::Def : MachineOperand::Use)); 00563 } 00564 00565 /// addRegOperand - Add a symbolic virtual register reference... 00566 /// 00567 void addRegOperand(int reg, 00568 MachineOperand::UseType UTy = MachineOperand::Use) { 00569 assert(!OperandsComplete() && 00570 "Trying to add an operand to a machine instr that is already done!"); 00571 operands.push_back( 00572 MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); 00573 } 00574 00575 /// addPCDispOperand - Add a PC relative displacement operand to the MI 00576 /// 00577 void addPCDispOperand(Value *V) { 00578 assert(!OperandsComplete() && 00579 "Trying to add an operand to a machine instr that is already done!"); 00580 operands.push_back( 00581 MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use)); 00582 } 00583 00584 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 00585 /// 00586 void addMachineRegOperand(int reg, bool isDef) { 00587 assert(!OperandsComplete() && 00588 "Trying to add an operand to a machine instr that is already done!"); 00589 operands.push_back( 00590 MachineOperand(reg, MachineOperand::MO_MachineRegister, 00591 isDef ? MachineOperand::Def : MachineOperand::Use)); 00592 } 00593 00594 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 00595 /// 00596 void addMachineRegOperand(int reg, 00597 MachineOperand::UseType UTy = MachineOperand::Use) { 00598 assert(!OperandsComplete() && 00599 "Trying to add an operand to a machine instr that is already done!"); 00600 operands.push_back( 00601 MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy)); 00602 } 00603 00604 /// addZeroExtImmOperand - Add a zero extended constant argument to the 00605 /// machine instruction. 00606 /// 00607 void addZeroExtImmOperand(int intValue) { 00608 assert(!OperandsComplete() && 00609 "Trying to add an operand to a machine instr that is already done!"); 00610 operands.push_back( 00611 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); 00612 } 00613 00614 /// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument 00615 /// to the machine instruction. 00616 /// 00617 void addZeroExtImm64Operand(uint64_t intValue) { 00618 assert(!OperandsComplete() && 00619 "Trying to add an operand to a machine instr that is already done!"); 00620 operands.push_back( 00621 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); 00622 } 00623 00624 /// addSignExtImmOperand - Add a zero extended constant argument to the 00625 /// machine instruction. 00626 /// 00627 void addSignExtImmOperand(int intValue) { 00628 assert(!OperandsComplete() && 00629 "Trying to add an operand to a machine instr that is already done!"); 00630 operands.push_back( 00631 MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed)); 00632 } 00633 00634 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 00635 assert(!OperandsComplete() && 00636 "Trying to add an operand to a machine instr that is already done!"); 00637 operands.push_back(MachineOperand(MBB)); 00638 } 00639 00640 /// addFrameIndexOperand - Add an abstract frame index to the instruction 00641 /// 00642 void addFrameIndexOperand(unsigned Idx) { 00643 assert(!OperandsComplete() && 00644 "Trying to add an operand to a machine instr that is already done!"); 00645 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 00646 } 00647 00648 /// addConstantPoolndexOperand - Add a constant pool object index to the 00649 /// instruction. 00650 /// 00651 void addConstantPoolIndexOperand(unsigned I, int Offset=0) { 00652 assert(!OperandsComplete() && 00653 "Trying to add an operand to a machine instr that is already done!"); 00654 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 00655 } 00656 00657 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) { 00658 assert(!OperandsComplete() && 00659 "Trying to add an operand to a machine instr that is already done!"); 00660 operands.push_back( 00661 MachineOperand(GV, MachineOperand::MO_GlobalAddress, 00662 MachineOperand::Use, isPCRelative, Offset)); 00663 } 00664 00665 /// addExternalSymbolOperand - Add an external symbol operand to this instr 00666 /// 00667 void addExternalSymbolOperand(const char *SymName, bool isPCRelative) { 00668 operands.push_back(MachineOperand(SymName, isPCRelative, 0)); 00669 } 00670 00671 //===--------------------------------------------------------------------===// 00672 // Accessors used to modify instructions in place. 00673 // 00674 // FIXME: Move this stuff to MachineOperand itself! 00675 00676 /// replace - Support to rewrite a machine instruction in place: for now, 00677 /// simply replace() and then set new operands with Set.*Operand methods 00678 /// below. 00679 /// 00680 void replace(short Opcode, unsigned numOperands); 00681 00682 /// setOpcode - Replace the opcode of the current instruction with a new one. 00683 /// 00684 void setOpcode(unsigned Op) { Opcode = Op; } 00685 00686 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 00687 /// fewer operand than it started with. 00688 /// 00689 void RemoveOperand(unsigned i) { 00690 operands.erase(operands.begin()+i); 00691 } 00692 00693 // Access to set the operands when building the machine instruction 00694 // 00695 void SetMachineOperandVal(unsigned i, 00696 MachineOperand::MachineOperandType operandType, 00697 Value* V); 00698 00699 void SetMachineOperandConst(unsigned i, 00700 MachineOperand::MachineOperandType operandType, 00701 int intValue); 00702 00703 void SetMachineOperandReg(unsigned i, int regNum); 00704 00705 00706 unsigned substituteValue(const Value* oldVal, Value* newVal, 00707 bool defsOnly, bool notDefsAndUses, 00708 bool& someArgsWereIgnored); 00709 00710 // SetRegForOperand - 00711 // SetRegForImplicitRef - 00712 // Mark an explicit or implicit operand with its allocated physical register. 00713 // 00714 void SetRegForOperand(unsigned i, int regNum); 00715 void SetRegForImplicitRef(unsigned i, int regNum); 00716 00717 // 00718 // Iterator to enumerate machine operands. NOTE, this is SPARCV9 specific! 00719 // 00720 template<class MITy, class VTy> 00721 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 00722 unsigned i; 00723 MITy MI; 00724 00725 void skipToNextVal() { 00726 while (i < MI->getNumOperands() && 00727 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 00728 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 00729 && MI->getOperand(i).getVRegValue() != 0)) 00730 ++i; 00731 } 00732 00733 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 00734 skipToNextVal(); 00735 } 00736 00737 public: 00738 typedef ValOpIterator<MITy, VTy> _Self; 00739 00740 inline VTy operator*() const { 00741 return MI->getOperand(i).getVRegValue(); 00742 } 00743 00744 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 00745 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 00746 00747 inline VTy operator->() const { return operator*(); } 00748 00749 inline bool isUse() const { return MI->getOperand(i).isUse(); } 00750 inline bool isDef() const { return MI->getOperand(i).isDef(); } 00751 00752 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 00753 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 00754 00755 inline bool operator==(const _Self &y) const { 00756 return i == y.i; 00757 } 00758 inline bool operator!=(const _Self &y) const { 00759 return !operator==(y); 00760 } 00761 00762 static _Self begin(MITy MI) { 00763 return _Self(MI, 0); 00764 } 00765 static _Self end(MITy MI) { 00766 return _Self(MI, MI->getNumOperands()); 00767 } 00768 }; 00769 00770 // Note: These are Sparc-V9 specific! 00771 val_op_iterator begin() { return val_op_iterator::begin(this); } 00772 val_op_iterator end() { return val_op_iterator::end(this); } 00773 const_val_op_iterator begin() const { 00774 return const_val_op_iterator::begin(this); 00775 } 00776 const_val_op_iterator end() const { 00777 return const_val_op_iterator::end(this); 00778 } 00779 }; 00780 00781 //===----------------------------------------------------------------------===// 00782 // Debugging Support 00783 00784 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 00785 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 00786 void PrintMachineInstructions(const Function *F); 00787 00788 } // End llvm namespace 00789 00790 #endif