LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned EmptyImpList[] = { 0 }; 00012 static const unsigned ImplicitList1[] = { PPC::CR0, 0 }; 00013 static const unsigned ImplicitList2[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; 00014 static const unsigned ImplicitList3[] = { PPC::LR, 0 }; 00015 static const unsigned ImplicitList4[] = { PPC::CR6, 0 }; 00016 00017 static const TargetOperandInfo OperandInfo2[] = { { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00018 static const TargetOperandInfo OperandInfo3[] = { { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, }; 00019 static const TargetOperandInfo OperandInfo4[] = { { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { 0 }, }; 00020 static const TargetOperandInfo OperandInfo5[] = { { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00021 static const TargetOperandInfo OperandInfo6[] = { { 0 }, }; 00022 static const TargetOperandInfo OperandInfo7[] = { { &PPC::CRRCRegClass }, { 0 }, }; 00023 static const TargetOperandInfo OperandInfo8[] = { { &PPC::CRRCRegClass }, { 0 }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00024 static const TargetOperandInfo OperandInfo9[] = { { &PPC::CRRCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00025 static const TargetOperandInfo OperandInfo10[] = { { &PPC::CRRCRegClass }, { &PPC::GPRCRegClass }, { 0 }, }; 00026 static const TargetOperandInfo OperandInfo11[] = { { &PPC::CRRCRegClass }, { 0 }, { &PPC::GPRCRegClass }, { 0 }, }; 00027 static const TargetOperandInfo OperandInfo12[] = { { &PPC::CRRCRegClass }, { 0 }, { 0 }, }; 00028 static const TargetOperandInfo OperandInfo13[] = { { 0 }, { 0 }, { 0 }, { 0 }, }; 00029 static const TargetOperandInfo OperandInfo14[] = { { 0 }, { 0 }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00030 static const TargetOperandInfo OperandInfo15[] = { { 0 }, { 0 }, { 0 }, }; 00031 static const TargetOperandInfo OperandInfo16[] = { { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, }; 00032 static const TargetOperandInfo OperandInfo17[] = { { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, }; 00033 static const TargetOperandInfo OperandInfo18[] = { { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, }; 00034 static const TargetOperandInfo OperandInfo19[] = { { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, }; 00035 static const TargetOperandInfo OperandInfo20[] = { { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, }; 00036 static const TargetOperandInfo OperandInfo21[] = { { &PPC::CRRCRegClass }, { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, }; 00037 static const TargetOperandInfo OperandInfo22[] = { { &PPC::CRRCRegClass }, { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, }; 00038 static const TargetOperandInfo OperandInfo23[] = { { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, }; 00039 static const TargetOperandInfo OperandInfo24[] = { { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, }; 00040 static const TargetOperandInfo OperandInfo25[] = { { &PPC::F8RCRegClass }, { &PPC::F4RCRegClass }, }; 00041 static const TargetOperandInfo OperandInfo26[] = { { &PPC::F4RCRegClass }, { &PPC::F8RCRegClass }, }; 00042 static const TargetOperandInfo OperandInfo27[] = { { &PPC::F4RCRegClass }, { &PPC::F8RCRegClass }, { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, }; 00043 static const TargetOperandInfo OperandInfo28[] = { { &PPC::F4RCRegClass }, }; 00044 static const TargetOperandInfo OperandInfo29[] = { { &PPC::F8RCRegClass }, }; 00045 static const TargetOperandInfo OperandInfo30[] = { { &PPC::GPRCRegClass }, }; 00046 static const TargetOperandInfo OperandInfo31[] = { { &PPC::VRRCRegClass }, }; 00047 static const TargetOperandInfo OperandInfo32[] = { { &PPC::GPRCRegClass }, { 0 }, { &PPC::GPRCRegClass }, }; 00048 static const TargetOperandInfo OperandInfo33[] = { { &PPC::GPRCRegClass }, { 0 }, { &PPC::GPRCRegClass }, }; 00049 static const TargetOperandInfo OperandInfo34[] = { { &PPC::G8RCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00050 static const TargetOperandInfo OperandInfo35[] = { { &PPC::F8RCRegClass }, { 0 }, { &PPC::GPRCRegClass }, }; 00051 static const TargetOperandInfo OperandInfo36[] = { { &PPC::F8RCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00052 static const TargetOperandInfo OperandInfo37[] = { { &PPC::F4RCRegClass }, { 0 }, { &PPC::GPRCRegClass }, }; 00053 static const TargetOperandInfo OperandInfo38[] = { { &PPC::F4RCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00054 static const TargetOperandInfo OperandInfo39[] = { { &PPC::GPRCRegClass }, { 0 }, }; 00055 static const TargetOperandInfo OperandInfo40[] = { { &PPC::VRRCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, }; 00056 static const TargetOperandInfo OperandInfo41[] = { { &PPC::CRRCRegClass }, { &PPC::CRRCRegClass }, }; 00057 static const TargetOperandInfo OperandInfo42[] = { { 0 }, { &PPC::GPRCRegClass }, }; 00058 static const TargetOperandInfo OperandInfo43[] = { { &PPC::GPRCRegClass }, { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, }; 00059 static const TargetOperandInfo OperandInfo44[] = { { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, { 0 }, { 0 }, }; 00060 static const TargetOperandInfo OperandInfo45[] = { { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, { &PPC::G8RCRegClass }, { 0 }, { 0 }, }; 00061 static const TargetOperandInfo OperandInfo46[] = { { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { 0 }, { 0 }, { 0 }, }; 00062 static const TargetOperandInfo OperandInfo47[] = { { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { 0 }, { 0 }, { 0 }, }; 00063 static const TargetOperandInfo OperandInfo48[] = { { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { 0 }, { 0 }, }; 00064 static const TargetOperandInfo OperandInfo49[] = { { &PPC::F4RCRegClass }, { &PPC::CRRCRegClass }, { &PPC::F4RCRegClass }, { &PPC::F4RCRegClass }, { 0 }, }; 00065 static const TargetOperandInfo OperandInfo50[] = { { &PPC::F8RCRegClass }, { &PPC::CRRCRegClass }, { &PPC::F8RCRegClass }, { &PPC::F8RCRegClass }, { 0 }, }; 00066 static const TargetOperandInfo OperandInfo51[] = { { &PPC::GPRCRegClass }, { &PPC::CRRCRegClass }, { &PPC::GPRCRegClass }, { &PPC::GPRCRegClass }, { 0 }, }; 00067 static const TargetOperandInfo OperandInfo52[] = { { &PPC::VRRCRegClass }, { &PPC::CRRCRegClass }, { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, { 0 }, }; 00068 static const TargetOperandInfo OperandInfo53[] = { { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, }; 00069 static const TargetOperandInfo OperandInfo54[] = { { &PPC::VRRCRegClass }, { 0 }, { &PPC::VRRCRegClass }, }; 00070 static const TargetOperandInfo OperandInfo55[] = { { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, }; 00071 static const TargetOperandInfo OperandInfo56[] = { { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, }; 00072 static const TargetOperandInfo OperandInfo57[] = { { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, { &PPC::VRRCRegClass }, { 0 }, }; 00073 static const TargetOperandInfo OperandInfo58[] = { { &PPC::VRRCRegClass }, { 0 }, }; 00074 00075 static const TargetInstrDescriptor PPCInsts[] = { 00076 { "PHI", -1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, 0 }, // Inst #0 = PHI 00077 { "INLINEASM", -1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, 0 }, // Inst #1 = INLINEASM 00078 { "ADD4", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #2 = ADD4 00079 { "ADD8", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #3 = ADD8 00080 { "ADDC", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #4 = ADDC 00081 { "ADDE", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #5 = ADDE 00082 { "ADDI", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #6 = ADDI 00083 { "ADDIC", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #7 = ADDIC 00084 { "ADDICo", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #8 = ADDICo 00085 { "ADDIS", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #9 = ADDIS 00086 { "ADDME", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #10 = ADDME 00087 { "ADDZE", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #11 = ADDZE 00088 { "ADJCALLSTACKDOWN", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #12 = ADJCALLSTACKDOWN 00089 { "ADJCALLSTACKUP", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #13 = ADJCALLSTACKUP 00090 { "AND", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #14 = AND 00091 { "ANDC", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #15 = ANDC 00092 { "ANDISo", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, ImplicitList1, OperandInfo4 }, // Inst #16 = ANDISo 00093 { "ANDIo", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, ImplicitList1, OperandInfo4 }, // Inst #17 = ANDIo 00094 { "ANDo", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, ImplicitList1, OperandInfo2 }, // Inst #18 = ANDo 00095 { "B", 1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #19 = B 00096 { "BCTR", 0, -1, 0, false, 0, 0, 0, 0|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, 0 }, // Inst #20 = BCTR 00097 { "BCTRL", -1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|(7<<3), EmptyImpList, ImplicitList2, 0 }, // Inst #21 = BCTRL 00098 { "BEQ", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #22 = BEQ 00099 { "BGE", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #23 = BGE 00100 { "BGT", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #24 = BGT 00101 { "BL", -1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|(7<<3), EmptyImpList, ImplicitList2, 0 }, // Inst #25 = BL 00102 { "BLA", -1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|(7<<3), EmptyImpList, ImplicitList2, 0 }, // Inst #26 = BLA 00103 { "BLE", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #27 = BLE 00104 { "BLR", 0, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, 0 }, // Inst #28 = BLR 00105 { "BLT", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #29 = BLT 00106 { "BNE", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #30 = BNE 00107 { "BNU", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #31 = BNU 00108 { "BUN", 2, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo7 }, // Inst #32 = BUN 00109 { "CMP", 4, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #33 = CMP 00110 { "CMPD", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #34 = CMPD 00111 { "CMPDI", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #35 = CMPDI 00112 { "CMPI", 4, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo11 }, // Inst #36 = CMPI 00113 { "CMPL", 4, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo8 }, // Inst #37 = CMPL 00114 { "CMPLD", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #38 = CMPLD 00115 { "CMPLDI", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #39 = CMPLDI 00116 { "CMPLI", 4, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo11 }, // Inst #40 = CMPLI 00117 { "CMPLW", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #41 = CMPLW 00118 { "CMPLWI", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #42 = CMPLWI 00119 { "CMPW", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo9 }, // Inst #43 = CMPW 00120 { "CMPWI", 3, -1, 0, false, 0, 0, 11, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo10 }, // Inst #44 = CMPWI 00121 { "CNTLZW", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #45 = CNTLZW 00122 { "COND_BRANCH", 3, -1, 0, false, 0, 0, 52, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(7<<3), EmptyImpList, EmptyImpList, OperandInfo12 }, // Inst #46 = COND_BRANCH 00123 { "DIVD", 3, -1, 0, false, 0, 0, 12, 0, 0|1|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #47 = DIVD 00124 { "DIVDU", 3, -1, 0, false, 0, 0, 12, 0, 0|1|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #48 = DIVDU 00125 { "DIVW", 3, -1, 0, false, 0, 0, 13, 0, 0|1|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #49 = DIVW 00126 { "DIVWU", 3, -1, 0, false, 0, 0, 13, 0, 0|1|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #50 = DIVWU 00127 { "DSS", 4, -1, 0, false, 0, 0, 33, 0, 0, EmptyImpList, EmptyImpList, OperandInfo13 }, // Inst #51 = DSS 00128 { "DST", 4, -1, 0, false, 0, 0, 33, 0, 0, EmptyImpList, EmptyImpList, OperandInfo14 }, // Inst #52 = DST 00129 { "DSTST", 4, -1, 0, false, 0, 0, 33, 0, 0, EmptyImpList, EmptyImpList, OperandInfo14 }, // Inst #53 = DSTST 00130 { "DWARF_LABEL", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo6 }, // Inst #54 = DWARF_LABEL 00131 { "DWARF_LOC", 3, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo15 }, // Inst #55 = DWARF_LOC 00132 { "EQV", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #56 = EQV 00133 { "EXTSB", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #57 = EXTSB 00134 { "EXTSH", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #58 = EXTSH 00135 { "EXTSW", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo16 }, // Inst #59 = EXTSW 00136 { "EXTSW_32", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #60 = EXTSW_32 00137 { "FABSD", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #61 = FABSD 00138 { "FABSS", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #62 = FABSS 00139 { "FADD", 3, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo19 }, // Inst #63 = FADD 00140 { "FADDS", 3, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo20 }, // Inst #64 = FADDS 00141 { "FCFID", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #65 = FCFID 00142 { "FCMPUD", 3, -1, 0, false, 0, 0, 4, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo21 }, // Inst #66 = FCMPUD 00143 { "FCMPUS", 3, -1, 0, false, 0, 0, 4, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo22 }, // Inst #67 = FCMPUS 00144 { "FCTIDZ", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #68 = FCTIDZ 00145 { "FCTIWZ", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #69 = FCTIWZ 00146 { "FDIV", 3, -1, 0, false, 0, 0, 5, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo19 }, // Inst #70 = FDIV 00147 { "FDIVS", 3, -1, 0, false, 0, 0, 6, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo20 }, // Inst #71 = FDIVS 00148 { "FMADD", 4, -1, 0, false, 0, 0, 7, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #72 = FMADD 00149 { "FMADDS", 4, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo24 }, // Inst #73 = FMADDS 00150 { "FMRD", 2, -1, 0, false, 0, 0, 8, 0, 0, EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #74 = FMRD 00151 { "FMRS", 2, -1, 0, false, 0, 0, 8, 0, 0, EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #75 = FMRS 00152 { "FMRSD", 2, -1, 0, false, 0, 0, 8, 0, 0, EmptyImpList, EmptyImpList, OperandInfo25 }, // Inst #76 = FMRSD 00153 { "FMSUB", 4, -1, 0, false, 0, 0, 7, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #77 = FMSUB 00154 { "FMSUBS", 4, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo24 }, // Inst #78 = FMSUBS 00155 { "FMUL", 3, -1, 0, false, 0, 0, 7, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo19 }, // Inst #79 = FMUL 00156 { "FMULS", 3, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo20 }, // Inst #80 = FMULS 00157 { "FNABSD", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #81 = FNABSD 00158 { "FNABSS", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #82 = FNABSS 00159 { "FNEGD", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #83 = FNEGD 00160 { "FNEGS", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #84 = FNEGS 00161 { "FNMADD", 4, -1, 0, false, 0, 0, 7, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #85 = FNMADD 00162 { "FNMADDS", 4, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo24 }, // Inst #86 = FNMADDS 00163 { "FNMSUB", 4, -1, 0, false, 0, 0, 7, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #87 = FNMSUB 00164 { "FNMSUBS", 4, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo24 }, // Inst #88 = FNMSUBS 00165 { "FRSP", 2, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo26 }, // Inst #89 = FRSP 00166 { "FSELD", 4, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo23 }, // Inst #90 = FSELD 00167 { "FSELS", 4, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo27 }, // Inst #91 = FSELS 00168 { "FSQRT", 2, -1, 0, false, 0, 0, 10, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo17 }, // Inst #92 = FSQRT 00169 { "FSQRTS", 2, -1, 0, false, 0, 0, 10, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo18 }, // Inst #93 = FSQRTS 00170 { "FSUB", 3, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo19 }, // Inst #94 = FSUB 00171 { "FSUBS", 3, -1, 0, false, 0, 0, 8, 0, 0|(3<<3), EmptyImpList, EmptyImpList, OperandInfo20 }, // Inst #95 = FSUBS 00172 { "IMPLICIT_DEF_F4", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo28 }, // Inst #96 = IMPLICIT_DEF_F4 00173 { "IMPLICIT_DEF_F8", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo29 }, // Inst #97 = IMPLICIT_DEF_F8 00174 { "IMPLICIT_DEF_GPR", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #98 = IMPLICIT_DEF_GPR 00175 { "IMPLICIT_DEF_VRRC", 1, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo31 }, // Inst #99 = IMPLICIT_DEF_VRRC 00176 { "LA", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #100 = LA 00177 { "LBZ", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #101 = LBZ 00178 { "LBZX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #102 = LBZX 00179 { "LD", 3, -1, 0, false, 0, 0, 35, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo33 }, // Inst #103 = LD 00180 { "LDX", 3, -1, 0, false, 0, 0, 35, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo34 }, // Inst #104 = LDX 00181 { "LFD", 3, -1, 0, false, 0, 0, 37, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo35 }, // Inst #105 = LFD 00182 { "LFDX", 3, -1, 0, false, 0, 0, 38, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo36 }, // Inst #106 = LFDX 00183 { "LFS", 3, -1, 0, false, 0, 0, 38, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo37 }, // Inst #107 = LFS 00184 { "LFSX", 3, -1, 0, false, 0, 0, 38, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo38 }, // Inst #108 = LFSX 00185 { "LHA", 3, -1, 0, false, 0, 0, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #109 = LHA 00186 { "LHAX", 3, -1, 0, false, 0, 0, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #110 = LHAX 00187 { "LHZ", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #111 = LHZ 00188 { "LHZX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #112 = LHZX 00189 { "LI", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo39 }, // Inst #113 = LI 00190 { "LIS", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo39 }, // Inst #114 = LIS 00191 { "LVEBX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #115 = LVEBX 00192 { "LVEHX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #116 = LVEHX 00193 { "LVEWX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #117 = LVEWX 00194 { "LVSL", 3, -1, 0, false, 0, 0, 33, 0, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #118 = LVSL 00195 { "LVSR", 3, -1, 0, false, 0, 0, 33, 0, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #119 = LVSR 00196 { "LVX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #120 = LVX 00197 { "LVXL", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #121 = LVXL 00198 { "LWA", 3, -1, 0, false, 0, 0, 42, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo33 }, // Inst #122 = LWA 00199 { "LWAX", 3, -1, 0, false, 0, 0, 39, 0|M_LOAD_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo34 }, // Inst #123 = LWAX 00200 { "LWZ", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #124 = LWZ 00201 { "LWZU", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo33 }, // Inst #125 = LWZU 00202 { "LWZX", 3, -1, 0, false, 0, 0, 33, 0|M_LOAD_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #126 = LWZX 00203 { "MCRF", 2, -1, 0, false, 0, 0, 2, 0, 0|1|(4<<3), EmptyImpList, EmptyImpList, OperandInfo41 }, // Inst #127 = MCRF 00204 { "MFCR", 1, -1, 0, false, 0, 0, 54, 0, 0|(4<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #128 = MFCR 00205 { "MFCTR", 1, -1, 0, false, 0, 0, 56, 0, 0|1|(1<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #129 = MFCTR 00206 { "MFLR", 1, -1, 0, false, 0, 0, 56, 0, 0|1|(1<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #130 = MFLR 00207 { "MFOCRF", 2, -1, 0, false, 0, 0, 54, 0, 0|1|(4<<3), EmptyImpList, EmptyImpList, OperandInfo39 }, // Inst #131 = MFOCRF 00208 { "MFVRSAVE", 1, -1, 0, false, 0, 0, 14, 0, 0|1|(1<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #132 = MFVRSAVE 00209 { "MFVSCR", 1, -1, 0, false, 0, 0, 33, 0, 0, EmptyImpList, EmptyImpList, OperandInfo31 }, // Inst #133 = MFVSCR 00210 { "MTCRF", 2, -1, 0, false, 0, 0, 3, 0, 0|(4<<3), EmptyImpList, EmptyImpList, OperandInfo42 }, // Inst #134 = MTCRF 00211 { "MTCTR", 1, -1, 0, false, 0, 0, 60, 0, 0|1|(1<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #135 = MTCTR 00212 { "MTLR", 1, -1, 0, false, 0, 0, 60, 0, 0|1|(1<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #136 = MTLR 00213 { "MTVRSAVE", 1, -1, 0, false, 0, 0, 14, 0, 0|(1<<1)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo30 }, // Inst #137 = MTVRSAVE 00214 { "MTVSCR", 1, -1, 0, false, 0, 0, 33, 0, 0, EmptyImpList, EmptyImpList, OperandInfo31 }, // Inst #138 = MTVSCR 00215 { "MULHD", 3, -1, 0, false, 0, 0, 20, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #139 = MULHD 00216 { "MULHDU", 3, -1, 0, false, 0, 0, 21, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #140 = MULHDU 00217 { "MULHW", 3, -1, 0, false, 0, 0, 20, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #141 = MULHW 00218 { "MULHWU", 3, -1, 0, false, 0, 0, 21, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #142 = MULHWU 00219 { "MULLD", 3, -1, 0, false, 0, 0, 19, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #143 = MULLD 00220 { "MULLI", 3, -1, 0, false, 0, 0, 22, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #144 = MULLI 00221 { "MULLW", 3, -1, 0, false, 0, 0, 20, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #145 = MULLW 00222 { "MovePCtoLR", 1, -1, 0, false, 0, 0, 52, 0, 0|(7<<3), EmptyImpList, ImplicitList3, OperandInfo6 }, // Inst #146 = MovePCtoLR 00223 { "NAND", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #147 = NAND 00224 { "NEG", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #148 = NEG 00225 { "NOP", 0, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, 0 }, // Inst #149 = NOP 00226 { "NOR", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #150 = NOR 00227 { "OR4", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #151 = OR4 00228 { "OR4To8", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo34 }, // Inst #152 = OR4To8 00229 { "OR8", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #153 = OR8 00230 { "OR8To4", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo43 }, // Inst #154 = OR8To4 00231 { "ORC", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #155 = ORC 00232 { "ORI", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #156 = ORI 00233 { "ORIS", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #157 = ORIS 00234 { "ORo", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, ImplicitList1, OperandInfo2 }, // Inst #158 = ORo 00235 { "RLDICL", 4, -1, 0, false, 0, 0, 25, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo44 }, // Inst #159 = RLDICL 00236 { "RLDICR", 4, -1, 0, false, 0, 0, 25, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo44 }, // Inst #160 = RLDICR 00237 { "RLDIMI", 5, -1, 0, false, 0, 0, 25, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo45 }, // Inst #161 = RLDIMI 00238 { "RLWIMI", 6, -1, 0, false, 0, 0, 24, 0|M_2_ADDR_FLAG|M_COMMUTABLE, 0|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo46 }, // Inst #162 = RLWIMI 00239 { "RLWINM", 5, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo47 }, // Inst #163 = RLWINM 00240 { "RLWINMo", 5, -1, 0, false, 0, 0, 14, 0, 0|(1<<2)|(1<<3), EmptyImpList, ImplicitList1, OperandInfo47 }, // Inst #164 = RLWINMo 00241 { "RLWNM", 5, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo48 }, // Inst #165 = RLWNM 00242 { "SELECT_CC_F4", 5, -1, 0, false, 0, 0, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), EmptyImpList, EmptyImpList, OperandInfo49 }, // Inst #166 = SELECT_CC_F4 00243 { "SELECT_CC_F8", 5, -1, 0, false, 0, 0, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), EmptyImpList, EmptyImpList, OperandInfo50 }, // Inst #167 = SELECT_CC_F8 00244 { "SELECT_CC_Int", 5, -1, 0, false, 0, 0, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), EmptyImpList, EmptyImpList, OperandInfo51 }, // Inst #168 = SELECT_CC_Int 00245 { "SELECT_CC_VRRC", 5, -1, 0, false, 0, 0, 52, 0|M_USES_CUSTOM_DAG_SCHED_INSERTION, 0|(1<<1), EmptyImpList, EmptyImpList, OperandInfo52 }, // Inst #169 = SELECT_CC_VRRC 00246 { "SLD", 3, -1, 0, false, 0, 0, 25, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #170 = SLD 00247 { "SLW", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #171 = SLW 00248 { "SRAD", 3, -1, 0, false, 0, 0, 25, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #172 = SRAD 00249 { "SRADI", 3, -1, 0, false, 0, 0, 25, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #173 = SRADI 00250 { "SRAW", 3, -1, 0, false, 0, 0, 26, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #174 = SRAW 00251 { "SRAWI", 3, -1, 0, false, 0, 0, 26, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #175 = SRAWI 00252 { "SRD", 3, -1, 0, false, 0, 0, 25, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo3 }, // Inst #176 = SRD 00253 { "SRW", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #177 = SRW 00254 { "STB", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #178 = STB 00255 { "STBX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #179 = STBX 00256 { "STD", 3, -1, 0, false, 0, 0, 46, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo33 }, // Inst #180 = STD 00257 { "STDUX", 3, -1, 0, false, 0, 0, 46, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #181 = STDUX 00258 { "STDX", 3, -1, 0, false, 0, 0, 46, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #182 = STDX 00259 { "STDX_32", 3, -1, 0, false, 0, 0, 46, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #183 = STDX_32 00260 { "STD_32", 3, -1, 0, false, 0, 0, 46, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #184 = STD_32 00261 { "STFD", 3, -1, 0, false, 0, 0, 51, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo35 }, // Inst #185 = STFD 00262 { "STFDX", 3, -1, 0, false, 0, 0, 51, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo36 }, // Inst #186 = STFDX 00263 { "STFIWX", 3, -1, 0, false, 0, 0, 51, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo36 }, // Inst #187 = STFIWX 00264 { "STFS", 3, -1, 0, false, 0, 0, 51, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo37 }, // Inst #188 = STFS 00265 { "STFSX", 3, -1, 0, false, 0, 0, 51, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo38 }, // Inst #189 = STFSX 00266 { "STH", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #190 = STH 00267 { "STHX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #191 = STHX 00268 { "STVEBX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #192 = STVEBX 00269 { "STVEHX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #193 = STVEHX 00270 { "STVEWX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #194 = STVEWX 00271 { "STVX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #195 = STVX 00272 { "STVXL", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo40 }, // Inst #196 = STVXL 00273 { "STW", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo32 }, // Inst #197 = STW 00274 { "STWU", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo33 }, // Inst #198 = STWU 00275 { "STWUX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #199 = STWUX 00276 { "STWX", 3, -1, 0, false, 0, 0, 33, 0|M_STORE_FLAG, 0|(1<<2)|(2<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #200 = STWX 00277 { "SUBF", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #201 = SUBF 00278 { "SUBFC", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<2)|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #202 = SUBFC 00279 { "SUBFE", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #203 = SUBFE 00280 { "SUBFIC", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #204 = SUBFIC 00281 { "SUBFME", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #205 = SUBFME 00282 { "SUBFZE", 2, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #206 = SUBFZE 00283 { "UPDATE_VRSAVE", 2, -1, 0, false, 0, 0, 52, 0, 0, EmptyImpList, EmptyImpList, OperandInfo5 }, // Inst #207 = UPDATE_VRSAVE 00284 { "VADDCUW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #208 = VADDCUW 00285 { "VADDFP", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #209 = VADDFP 00286 { "VADDSBS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #210 = VADDSBS 00287 { "VADDSHS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #211 = VADDSHS 00288 { "VADDSWS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #212 = VADDSWS 00289 { "VADDUBM", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #213 = VADDUBM 00290 { "VADDUBS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #214 = VADDUBS 00291 { "VADDUHM", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #215 = VADDUHM 00292 { "VADDUHS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #216 = VADDUHS 00293 { "VADDUWM", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #217 = VADDUWM 00294 { "VADDUWS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #218 = VADDUWS 00295 { "VAND", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #219 = VAND 00296 { "VANDC", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #220 = VANDC 00297 { "VAVGSB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #221 = VAVGSB 00298 { "VAVGSH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #222 = VAVGSH 00299 { "VAVGSW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #223 = VAVGSW 00300 { "VAVGUB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #224 = VAVGUB 00301 { "VAVGUH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #225 = VAVGUH 00302 { "VAVGUW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #226 = VAVGUW 00303 { "VCFSX", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #227 = VCFSX 00304 { "VCFUX", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #228 = VCFUX 00305 { "VCMPBFP", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #229 = VCMPBFP 00306 { "VCMPBFPo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #230 = VCMPBFPo 00307 { "VCMPEQFP", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #231 = VCMPEQFP 00308 { "VCMPEQFPo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #232 = VCMPEQFPo 00309 { "VCMPEQUB", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #233 = VCMPEQUB 00310 { "VCMPEQUBo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #234 = VCMPEQUBo 00311 { "VCMPEQUH", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #235 = VCMPEQUH 00312 { "VCMPEQUHo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #236 = VCMPEQUHo 00313 { "VCMPEQUW", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #237 = VCMPEQUW 00314 { "VCMPEQUWo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #238 = VCMPEQUWo 00315 { "VCMPGEFP", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #239 = VCMPGEFP 00316 { "VCMPGEFPo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #240 = VCMPGEFPo 00317 { "VCMPGTFP", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #241 = VCMPGTFP 00318 { "VCMPGTFPo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #242 = VCMPGTFPo 00319 { "VCMPGTSB", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #243 = VCMPGTSB 00320 { "VCMPGTSBo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #244 = VCMPGTSBo 00321 { "VCMPGTSH", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #245 = VCMPGTSH 00322 { "VCMPGTSHo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #246 = VCMPGTSHo 00323 { "VCMPGTSW", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #247 = VCMPGTSW 00324 { "VCMPGTSWo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #248 = VCMPGTSWo 00325 { "VCMPGTUB", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #249 = VCMPGTUB 00326 { "VCMPGTUBo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #250 = VCMPGTUBo 00327 { "VCMPGTUH", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #251 = VCMPGTUH 00328 { "VCMPGTUHo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #252 = VCMPGTUHo 00329 { "VCMPGTUW", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #253 = VCMPGTUW 00330 { "VCMPGTUWo", 3, -1, 0, false, 0, 0, 68, 0, 0|(5<<3), EmptyImpList, ImplicitList4, OperandInfo53 }, // Inst #254 = VCMPGTUWo 00331 { "VCTSXS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #255 = VCTSXS 00332 { "VCTUXS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #256 = VCTUXS 00333 { "VEXPTEFP", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #257 = VEXPTEFP 00334 { "VLOGEFP", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #258 = VLOGEFP 00335 { "VMADDFP", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #259 = VMADDFP 00336 { "VMAXFP", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #260 = VMAXFP 00337 { "VMAXSB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #261 = VMAXSB 00338 { "VMAXSH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #262 = VMAXSH 00339 { "VMAXSW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #263 = VMAXSW 00340 { "VMAXUB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #264 = VMAXUB 00341 { "VMAXUH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #265 = VMAXUH 00342 { "VMAXUW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #266 = VMAXUW 00343 { "VMHADDSHS", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #267 = VMHADDSHS 00344 { "VMHRADDSHS", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #268 = VMHRADDSHS 00345 { "VMINFP", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #269 = VMINFP 00346 { "VMINSB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #270 = VMINSB 00347 { "VMINSH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #271 = VMINSH 00348 { "VMINSW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #272 = VMINSW 00349 { "VMINUB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #273 = VMINUB 00350 { "VMINUH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #274 = VMINUH 00351 { "VMINUW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #275 = VMINUW 00352 { "VMLADDUHM", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #276 = VMLADDUHM 00353 { "VMRGHB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #277 = VMRGHB 00354 { "VMRGHH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #278 = VMRGHH 00355 { "VMRGHW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #279 = VMRGHW 00356 { "VMRGLB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #280 = VMRGLB 00357 { "VMRGLH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #281 = VMRGLH 00358 { "VMRGLW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #282 = VMRGLW 00359 { "VMSUMMBM", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #283 = VMSUMMBM 00360 { "VMSUMSHM", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #284 = VMSUMSHM 00361 { "VMSUMSHS", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #285 = VMSUMSHS 00362 { "VMSUMUBM", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #286 = VMSUMUBM 00363 { "VMSUMUHM", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #287 = VMSUMUHM 00364 { "VMSUMUHS", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #288 = VMSUMUHS 00365 { "VMULESB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #289 = VMULESB 00366 { "VMULESH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #290 = VMULESH 00367 { "VMULEUB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #291 = VMULEUB 00368 { "VMULEUH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #292 = VMULEUH 00369 { "VMULOSB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #293 = VMULOSB 00370 { "VMULOSH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #294 = VMULOSH 00371 { "VMULOUB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #295 = VMULOUB 00372 { "VMULOUH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #296 = VMULOUH 00373 { "VNMSUBFP", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #297 = VNMSUBFP 00374 { "VNOR", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #298 = VNOR 00375 { "VOR", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #299 = VOR 00376 { "VPERM", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #300 = VPERM 00377 { "VPKPX", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #301 = VPKPX 00378 { "VPKSHSS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #302 = VPKSHSS 00379 { "VPKSHUS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #303 = VPKSHUS 00380 { "VPKSWSS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #304 = VPKSWSS 00381 { "VPKSWUS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #305 = VPKSWUS 00382 { "VPKUHUM", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #306 = VPKUHUM 00383 { "VPKUHUS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #307 = VPKUHUS 00384 { "VPKUWUM", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #308 = VPKUWUM 00385 { "VPKUWUS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #309 = VPKUWUS 00386 { "VREFP", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #310 = VREFP 00387 { "VRFIM", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #311 = VRFIM 00388 { "VRFIN", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #312 = VRFIN 00389 { "VRFIP", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #313 = VRFIP 00390 { "VRFIZ", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #314 = VRFIZ 00391 { "VRLB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #315 = VRLB 00392 { "VRLH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #316 = VRLH 00393 { "VRLW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #317 = VRLW 00394 { "VRSQRTEFP", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #318 = VRSQRTEFP 00395 { "VSEL", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo56 }, // Inst #319 = VSEL 00396 { "VSL", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #320 = VSL 00397 { "VSLB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #321 = VSLB 00398 { "VSLDOI", 4, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo57 }, // Inst #322 = VSLDOI 00399 { "VSLH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #323 = VSLH 00400 { "VSLO", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #324 = VSLO 00401 { "VSLW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #325 = VSLW 00402 { "VSPLTB", 3, -1, 0, false, 0, 0, 71, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #326 = VSPLTB 00403 { "VSPLTH", 3, -1, 0, false, 0, 0, 71, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #327 = VSPLTH 00404 { "VSPLTISB", 2, -1, 0, false, 0, 0, 71, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo58 }, // Inst #328 = VSPLTISB 00405 { "VSPLTISH", 2, -1, 0, false, 0, 0, 71, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo58 }, // Inst #329 = VSPLTISH 00406 { "VSPLTISW", 2, -1, 0, false, 0, 0, 71, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo58 }, // Inst #330 = VSPLTISW 00407 { "VSPLTW", 3, -1, 0, false, 0, 0, 71, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo54 }, // Inst #331 = VSPLTW 00408 { "VSR", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #332 = VSR 00409 { "VSRAB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #333 = VSRAB 00410 { "VSRAH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #334 = VSRAH 00411 { "VSRAW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #335 = VSRAW 00412 { "VSRB", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #336 = VSRB 00413 { "VSRH", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #337 = VSRH 00414 { "VSRO", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #338 = VSRO 00415 { "VSRW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #339 = VSRW 00416 { "VSUBCUW", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #340 = VSUBCUW 00417 { "VSUBFP", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #341 = VSUBFP 00418 { "VSUBSBS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #342 = VSUBSBS 00419 { "VSUBSHS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #343 = VSUBSHS 00420 { "VSUBSWS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #344 = VSUBSWS 00421 { "VSUBUBM", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #345 = VSUBUBM 00422 { "VSUBUBS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #346 = VSUBUBS 00423 { "VSUBUHM", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #347 = VSUBUHM 00424 { "VSUBUHS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #348 = VSUBUHS 00425 { "VSUBUWM", 3, -1, 0, false, 0, 0, 70, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #349 = VSUBUWM 00426 { "VSUBUWS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #350 = VSUBUWS 00427 { "VSUM2SWS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #351 = VSUM2SWS 00428 { "VSUM4SBS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #352 = VSUM4SBS 00429 { "VSUM4SHS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #353 = VSUM4SHS 00430 { "VSUM4UBS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #354 = VSUM4UBS 00431 { "VSUMSWS", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #355 = VSUMSWS 00432 { "VUPKHPX", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #356 = VUPKHPX 00433 { "VUPKHSB", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #357 = VUPKHSB 00434 { "VUPKHSH", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #358 = VUPKHSH 00435 { "VUPKLPX", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #359 = VUPKLPX 00436 { "VUPKLSB", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #360 = VUPKLSB 00437 { "VUPKLSH", 2, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo55 }, // Inst #361 = VUPKLSH 00438 { "VXOR", 3, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo53 }, // Inst #362 = VXOR 00439 { "V_SET0", 1, -1, 0, false, 0, 0, 67, 0, 0|(5<<3), EmptyImpList, EmptyImpList, OperandInfo31 }, // Inst #363 = V_SET0 00440 { "XOR", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo2 }, // Inst #364 = XOR 00441 { "XORI", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #365 = XORI 00442 { "XORIS", 3, -1, 0, false, 0, 0, 14, 0, 0|(1<<3), EmptyImpList, EmptyImpList, OperandInfo4 }, // Inst #366 = XORIS 00443 }; 00444 } // End llvm namespace