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PPC32ISelSimple.cpp

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00001 //===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 
00010 #define DEBUG_TYPE "isel"
00011 #include "PowerPC.h"
00012 #include "PowerPCInstrBuilder.h"
00013 #include "PowerPCInstrInfo.h"
00014 #include "PPC32TargetMachine.h"
00015 #include "llvm/Constants.h"
00016 #include "llvm/DerivedTypes.h"
00017 #include "llvm/Function.h"
00018 #include "llvm/Instructions.h"
00019 #include "llvm/Pass.h"
00020 #include "llvm/CodeGen/IntrinsicLowering.h"
00021 #include "llvm/CodeGen/MachineConstantPool.h"
00022 #include "llvm/CodeGen/MachineFrameInfo.h"
00023 #include "llvm/CodeGen/MachineFunction.h"
00024 #include "llvm/CodeGen/SSARegMap.h"
00025 #include "llvm/Target/MRegisterInfo.h"
00026 #include "llvm/Target/TargetMachine.h"
00027 #include "llvm/Support/GetElementPtrTypeIterator.h"
00028 #include "llvm/Support/InstVisitor.h"
00029 #include "llvm/Support/Debug.h"
00030 #include "llvm/ADT/Statistic.h"
00031 #include <vector>
00032 using namespace llvm;
00033 
00034 namespace {
00035   /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
00036   /// PPC Representation.
00037   ///
00038   enum TypeClass {
00039     cByte, cShort, cInt, cFP32, cFP64, cLong
00040   };
00041 }
00042 
00043 /// getClass - Turn a primitive type into a "class" number which is based on the
00044 /// size of the type, and whether or not it is floating point.
00045 ///
00046 static inline TypeClass getClass(const Type *Ty) {
00047   switch (Ty->getTypeID()) {
00048   case Type::SByteTyID:
00049   case Type::UByteTyID:   return cByte;      // Byte operands are class #0
00050   case Type::ShortTyID:
00051   case Type::UShortTyID:  return cShort;     // Short operands are class #1
00052   case Type::IntTyID:
00053   case Type::UIntTyID:
00054   case Type::PointerTyID: return cInt;       // Ints and pointers are class #2
00055 
00056   case Type::FloatTyID:   return cFP32;      // Single float is #3
00057   case Type::DoubleTyID:  return cFP64;      // Double Point is #4
00058 
00059   case Type::LongTyID:
00060   case Type::ULongTyID:   return cLong;      // Longs are class #5
00061   default:
00062     assert(0 && "Invalid type to getClass!");
00063     return cByte;  // not reached
00064   }
00065 }
00066 
00067 // getClassB - Just like getClass, but treat boolean values as ints.
00068 static inline TypeClass getClassB(const Type *Ty) {
00069   if (Ty == Type::BoolTy) return cByte;
00070   return getClass(Ty);
00071 }
00072 
00073 namespace {
00074   struct PPC32ISel : public FunctionPass, InstVisitor<PPC32ISel> {
00075     PPC32TargetMachine &TM;
00076     MachineFunction *F;                 // The function we are compiling into
00077     MachineBasicBlock *BB;              // The current MBB we are compiling
00078     int VarArgsFrameIndex;              // FrameIndex for start of varargs area
00079     
00080     /// CollapsedGepOp - This struct is for recording the intermediate results 
00081     /// used to calculate the base, index, and offset of a GEP instruction.
00082     struct CollapsedGepOp {
00083       ConstantSInt *offset; // the current offset into the struct/array
00084       Value *index;         // the index of the array element
00085       ConstantUInt *size;   // the size of each array element
00086       CollapsedGepOp(ConstantSInt *o, Value *i, ConstantUInt *s) :
00087         offset(o), index(i), size(s) {}
00088     };
00089 
00090     /// FoldedGEP - This struct is for recording the necessary information to 
00091     /// emit the GEP in a load or store instruction, used by emitGEPOperation.
00092     struct FoldedGEP {
00093       unsigned base;
00094       unsigned index;
00095       ConstantSInt *offset;
00096       FoldedGEP() : base(0), index(0), offset(0) {}
00097       FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) : 
00098         base(b), index(i), offset(o) {}
00099     };
00100     
00101     /// RlwimiRec - This struct is for recording the arguments to a PowerPC 
00102     /// rlwimi instruction to be output for a particular Instruction::Or when
00103     /// we recognize the pattern for rlwimi, starting with a shift or and.
00104     struct RlwimiRec { 
00105       Value *Target, *Insert;
00106       unsigned Shift, MB, ME;
00107       RlwimiRec() : Target(0), Insert(0), Shift(0), MB(0), ME(0) {}
00108       RlwimiRec(Value *tgt, Value *ins, unsigned s, unsigned b, unsigned e) :
00109         Target(tgt), Insert(ins), Shift(s), MB(b), ME(e) {}
00110     };
00111     
00112     // External functions used in the Module
00113     Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn, 
00114       *__umoddi3Fn,  *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
00115       *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
00116 
00117     // Mapping between Values and SSA Regs
00118     std::map<Value*, unsigned> RegMap;
00119 
00120     // MBBMap - Mapping between LLVM BB -> Machine BB
00121     std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
00122 
00123     // AllocaMap - Mapping from fixed sized alloca instructions to the
00124     // FrameIndex for the alloca.
00125     std::map<AllocaInst*, unsigned> AllocaMap;
00126 
00127     // GEPMap - Mapping between basic blocks and GEP definitions
00128     std::map<GetElementPtrInst*, FoldedGEP> GEPMap;
00129     
00130     // RlwimiMap  - Mapping between BinaryOperand (Or) instructions and info
00131     // needed to properly emit a rlwimi instruction in its place.
00132     std::map<Instruction *, RlwimiRec> InsertMap;
00133 
00134     // A rlwimi instruction is the combination of at least three instructions.
00135     // Keep a vector of instructions to skip around so that we do not try to
00136     // emit instructions that were folded into a rlwimi.
00137     std::vector<Instruction *> SkipList;
00138 
00139     // A Reg to hold the base address used for global loads and stores, and a
00140     // flag to set whether or not we need to emit it for this function.
00141     unsigned GlobalBaseReg;
00142     bool GlobalBaseInitialized;
00143     
00144     PPC32ISel(TargetMachine &tm):TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
00145       F(0), BB(0) {}
00146 
00147     bool doInitialization(Module &M) {
00148       // Add external functions that we may call
00149       Type *i = Type::IntTy;
00150       Type *d = Type::DoubleTy;
00151       Type *f = Type::FloatTy;
00152       Type *l = Type::LongTy;
00153       Type *ul = Type::ULongTy;
00154       Type *voidPtr = PointerType::get(Type::SByteTy);
00155       // float fmodf(float, float);
00156       fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
00157       // double fmod(double, double);
00158       fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
00159       // int __cmpdi2(long, long);
00160       __cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
00161       // long __moddi3(long, long);
00162       __moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
00163       // long __divdi3(long, long);
00164       __divdi3Fn = M.getOrInsertFunction("__divdi3", l, l, l, 0);
00165       // unsigned long __umoddi3(unsigned long, unsigned long);
00166       __umoddi3Fn = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
00167       // unsigned long __udivdi3(unsigned long, unsigned long);
00168       __udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
00169       // long __fixsfdi(float)
00170       __fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
00171       // long __fixdfdi(double)
00172       __fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
00173       // unsigned long __fixunssfdi(float)
00174       __fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
00175       // unsigned long __fixunsdfdi(double)
00176       __fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
00177       // float __floatdisf(long)
00178       __floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
00179       // double __floatdidf(long)
00180       __floatdidfFn = M.getOrInsertFunction("__floatdidf", d, l, 0);
00181       // void* malloc(size_t)
00182       mallocFn = M.getOrInsertFunction("malloc", voidPtr, Type::UIntTy, 0);
00183       // void free(void*)
00184       freeFn = M.getOrInsertFunction("free", Type::VoidTy, voidPtr, 0);
00185       return false;
00186     }
00187 
00188     /// runOnFunction - Top level implementation of instruction selection for
00189     /// the entire function.
00190     ///
00191     bool runOnFunction(Function &Fn) {
00192       // First pass over the function, lower any unknown intrinsic functions
00193       // with the IntrinsicLowering class.
00194       LowerUnknownIntrinsicFunctionCalls(Fn);
00195 
00196       F = &MachineFunction::construct(&Fn, TM);
00197 
00198       // Create all of the machine basic blocks for the function...
00199       for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
00200         F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
00201 
00202       BB = &F->front();
00203 
00204       // Make sure we re-emit a set of the global base reg if necessary
00205       GlobalBaseInitialized = false;
00206 
00207       // Copy incoming arguments off of the stack...
00208       LoadArgumentsToVirtualRegs(Fn);
00209 
00210       // Instruction select everything except PHI nodes
00211       visit(Fn);
00212 
00213       // Select the PHI nodes
00214       SelectPHINodes();
00215 
00216       GEPMap.clear();
00217       RegMap.clear();
00218       MBBMap.clear();
00219       InsertMap.clear();
00220       AllocaMap.clear();
00221       SkipList.clear();
00222       F = 0;
00223       // We always build a machine code representation for the function
00224       return true;
00225     }
00226 
00227     virtual const char *getPassName() const {
00228       return "PowerPC Simple Instruction Selection";
00229     }
00230 
00231     /// visitBasicBlock - This method is called when we are visiting a new basic
00232     /// block.  This simply creates a new MachineBasicBlock to emit code into
00233     /// and adds it to the current MachineFunction.  Subsequent visit* for
00234     /// instructions will be invoked for all instructions in the basic block.
00235     ///
00236     void visitBasicBlock(BasicBlock &LLVM_BB) {
00237       BB = MBBMap[&LLVM_BB];
00238     }
00239 
00240     /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
00241     /// function, lowering any calls to unknown intrinsic functions into the
00242     /// equivalent LLVM code.
00243     ///
00244     void LowerUnknownIntrinsicFunctionCalls(Function &F);
00245 
00246     /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
00247     /// from the stack into virtual registers.
00248     ///
00249     void LoadArgumentsToVirtualRegs(Function &F);
00250 
00251     /// SelectPHINodes - Insert machine code to generate phis.  This is tricky
00252     /// because we have to generate our sources into the source basic blocks,
00253     /// not the current one.
00254     ///
00255     void SelectPHINodes();
00256 
00257     // Visitation methods for various instructions.  These methods simply emit
00258     // fixed PowerPC code for each instruction.
00259 
00260     // Control flow operators.
00261     void visitReturnInst(ReturnInst &RI);
00262     void visitBranchInst(BranchInst &BI);
00263     void visitUnreachableInst(UnreachableInst &UI) {}
00264 
00265     struct ValueRecord {
00266       Value *Val;
00267       unsigned Reg;
00268       const Type *Ty;
00269       ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
00270       ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
00271     };
00272 
00273     void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
00274                 const std::vector<ValueRecord> &Args, bool isVarArg);
00275     void visitCallInst(CallInst &I);
00276     void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
00277 
00278     // Arithmetic operators
00279     void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
00280     void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
00281     void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
00282     void visitMul(BinaryOperator &B);
00283 
00284     void visitDiv(BinaryOperator &B) { visitDivRem(B); }
00285     void visitRem(BinaryOperator &B) { visitDivRem(B); }
00286     void visitDivRem(BinaryOperator &B);
00287 
00288     // Bitwise operators
00289     void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
00290     void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
00291     void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
00292 
00293     // Comparison operators...
00294     void visitSetCondInst(SetCondInst &I);
00295     unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
00296                             MachineBasicBlock *MBB,
00297                             MachineBasicBlock::iterator MBBI);
00298     void visitSelectInst(SelectInst &SI);
00299     
00300     
00301     // Memory Instructions
00302     void visitLoadInst(LoadInst &I);
00303     void visitStoreInst(StoreInst &I);
00304     void visitGetElementPtrInst(GetElementPtrInst &I);
00305     void visitAllocaInst(AllocaInst &I);
00306     void visitMallocInst(MallocInst &I);
00307     void visitFreeInst(FreeInst &I);
00308     
00309     // Other operators
00310     void visitShiftInst(ShiftInst &I);
00311     void visitPHINode(PHINode &I) {}      // PHI nodes handled by second pass
00312     void visitCastInst(CastInst &I);
00313     void visitVANextInst(VANextInst &I);
00314     void visitVAArgInst(VAArgInst &I);
00315 
00316     void visitInstruction(Instruction &I) {
00317       std::cerr << "Cannot instruction select: " << I;
00318       abort();
00319     }
00320 
00321     unsigned ExtendOrClear(MachineBasicBlock *MBB,
00322                            MachineBasicBlock::iterator IP,
00323                            Value *Op0);
00324 
00325     /// promote32 - Make a value 32-bits wide, and put it somewhere.
00326     ///
00327     void promote32(unsigned targetReg, const ValueRecord &VR);
00328 
00329     /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
00330     /// constant expression GEP support.
00331     ///
00332     void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
00333                           GetElementPtrInst *GEPI, bool foldGEP);
00334 
00335     /// emitCastOperation - Common code shared between visitCastInst and
00336     /// constant expression cast support.
00337     ///
00338     void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
00339                            Value *Src, const Type *DestTy, unsigned TargetReg);
00340 
00341 
00342     /// emitBitfieldInsert - return true if we were able to fold the sequence of
00343     /// instructions into a bitfield insert (rlwimi).
00344     bool emitBitfieldInsert(User *OpUser, unsigned DestReg);
00345                                   
00346     /// emitBitfieldExtract - return true if we were able to fold the sequence
00347     /// of instructions into a bitfield extract (rlwinm).
00348     bool emitBitfieldExtract(MachineBasicBlock *MBB, 
00349                              MachineBasicBlock::iterator IP,
00350                              User *OpUser, unsigned DestReg);
00351 
00352     /// emitBinaryConstOperation - Used by several functions to emit simple
00353     /// arithmetic and logical operations with constants on a register rather
00354     /// than a Value.
00355     ///
00356     void emitBinaryConstOperation(MachineBasicBlock *MBB, 
00357                                   MachineBasicBlock::iterator IP,
00358                                   unsigned Op0Reg, ConstantInt *Op1, 
00359                                   unsigned Opcode, unsigned DestReg);
00360 
00361     /// emitSimpleBinaryOperation - Implement simple binary operators for 
00362     /// integral types.  OperatorClass is one of: 0 for Add, 1 for Sub, 
00363     /// 2 for And, 3 for Or, 4 for Xor.
00364     ///
00365     void emitSimpleBinaryOperation(MachineBasicBlock *BB,
00366                                    MachineBasicBlock::iterator IP,
00367                                    BinaryOperator *BO, Value *Op0, Value *Op1,
00368                                    unsigned OperatorClass, unsigned TargetReg);
00369 
00370     /// emitBinaryFPOperation - This method handles emission of floating point
00371     /// Add (0), Sub (1), Mul (2), and Div (3) operations.
00372     void emitBinaryFPOperation(MachineBasicBlock *BB,
00373                                MachineBasicBlock::iterator IP,
00374                                Value *Op0, Value *Op1,
00375                                unsigned OperatorClass, unsigned TargetReg);
00376 
00377     void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
00378                       Value *Op0, Value *Op1, unsigned TargetReg);
00379 
00380     void doMultiply(MachineBasicBlock *MBB,
00381                     MachineBasicBlock::iterator IP,
00382                     unsigned DestReg, Value *Op0, Value *Op1);
00383   
00384     /// doMultiplyConst - This method will multiply the value in Op0Reg by the
00385     /// value of the ContantInt *CI
00386     void doMultiplyConst(MachineBasicBlock *MBB, 
00387                          MachineBasicBlock::iterator IP,
00388                          unsigned DestReg, Value *Op0, ConstantInt *CI);
00389 
00390     void emitDivRemOperation(MachineBasicBlock *BB,
00391                              MachineBasicBlock::iterator IP,
00392                              Value *Op0, Value *Op1, bool isDiv,
00393                              unsigned TargetReg);
00394 
00395     /// emitSetCCOperation - Common code shared between visitSetCondInst and
00396     /// constant expression support.
00397     ///
00398     void emitSetCCOperation(MachineBasicBlock *BB,
00399                             MachineBasicBlock::iterator IP,
00400                             Value *Op0, Value *Op1, unsigned Opcode,
00401                             unsigned TargetReg);
00402 
00403     /// emitShiftOperation - Common code shared between visitShiftInst and
00404     /// constant expression support.
00405     ///
00406     void emitShiftOperation(MachineBasicBlock *MBB,
00407                             MachineBasicBlock::iterator IP,
00408                             Value *Op, Value *ShiftAmount, bool isLeftShift,
00409                             const Type *ResultTy, ShiftInst *SI, 
00410                             unsigned DestReg);
00411       
00412     /// emitSelectOperation - Common code shared between visitSelectInst and the
00413     /// constant expression support.
00414     ///
00415     void emitSelectOperation(MachineBasicBlock *MBB,
00416                              MachineBasicBlock::iterator IP,
00417                              Value *Cond, Value *TrueVal, Value *FalseVal,
00418                              unsigned DestReg);
00419 
00420     /// getGlobalBaseReg - Output the instructions required to put the
00421     /// base address to use for accessing globals into a register.  Returns the
00422     /// register containing the base address.
00423     ///
00424     unsigned getGlobalBaseReg(MachineBasicBlock *MBB,
00425                                   MachineBasicBlock::iterator IP);
00426 
00427     /// copyConstantToRegister - Output the instructions required to put the
00428     /// specified constant into the specified register.
00429     ///
00430     void copyConstantToRegister(MachineBasicBlock *MBB,
00431                                 MachineBasicBlock::iterator MBBI,
00432                                 Constant *C, unsigned Reg);
00433 
00434     void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
00435                    unsigned LHS, unsigned RHS);
00436 
00437     /// makeAnotherReg - This method returns the next register number we haven't
00438     /// yet used.
00439     ///
00440     /// Long values are handled somewhat specially.  They are always allocated
00441     /// as pairs of 32 bit integer values.  The register number returned is the
00442     /// high 32 bits of the long value, and the regNum+1 is the low 32 bits.
00443     ///
00444     unsigned makeAnotherReg(const Type *Ty) {
00445       assert(dynamic_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo()) &&
00446              "Current target doesn't have PPC reg info??");
00447       const PPC32RegisterInfo *PPCRI =
00448         static_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo());
00449       if (Ty == Type::LongTy || Ty == Type::ULongTy) {
00450         const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy);
00451         // Create the upper part
00452         F->getSSARegMap()->createVirtualRegister(RC);
00453         // Create the lower part.
00454         return F->getSSARegMap()->createVirtualRegister(RC)-1;
00455       }
00456 
00457       // Add the mapping of regnumber => reg class to MachineFunction
00458       const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
00459       return F->getSSARegMap()->createVirtualRegister(RC);
00460     }
00461 
00462     /// getReg - This method turns an LLVM value into a register number.
00463     ///
00464     unsigned getReg(Value &V) { return getReg(&V); }  // Allow references
00465     unsigned getReg(Value *V) {
00466       // Just append to the end of the current bb.
00467       MachineBasicBlock::iterator It = BB->end();
00468       return getReg(V, BB, It);
00469     }
00470     unsigned getReg(Value *V, MachineBasicBlock *MBB,
00471                     MachineBasicBlock::iterator IPt);
00472     
00473     /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
00474     /// is okay to use as an immediate argument to a certain binary operation
00475     bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
00476                                     bool Shifted);
00477 
00478     /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
00479     /// that is to be statically allocated with the initial stack frame
00480     /// adjustment.
00481     unsigned getFixedSizedAllocaFI(AllocaInst *AI);
00482   };
00483 }
00484 
00485 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
00486 /// instruction in the entry block, return it.  Otherwise, return a null
00487 /// pointer.
00488 static AllocaInst *dyn_castFixedAlloca(Value *V) {
00489   if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
00490     BasicBlock *BB = AI->getParent();
00491     if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
00492       return AI;
00493   }
00494   return 0;
00495 }
00496 
00497 /// getReg - This method turns an LLVM value into a register number.
00498 ///
00499 unsigned PPC32ISel::getReg(Value *V, MachineBasicBlock *MBB,
00500                            MachineBasicBlock::iterator IPt) {
00501   if (Constant *C = dyn_cast<Constant>(V)) {
00502     unsigned Reg = makeAnotherReg(V->getType());
00503     copyConstantToRegister(MBB, IPt, C, Reg);
00504     return Reg;
00505   } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
00506     // Do not emit noop casts at all, unless it's a double -> float cast.
00507     if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
00508       return getReg(CI->getOperand(0), MBB, IPt);
00509   } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
00510     unsigned Reg = makeAnotherReg(V->getType());
00511     unsigned FI = getFixedSizedAllocaFI(AI);
00512     addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
00513     return Reg;
00514   }
00515 
00516   unsigned &Reg = RegMap[V];
00517   if (Reg == 0) {
00518     Reg = makeAnotherReg(V->getType());
00519     RegMap[V] = Reg;
00520   }
00521 
00522   return Reg;
00523 }
00524 
00525 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
00526 /// is okay to use as an immediate argument to a certain binary operator.
00527 /// The shifted argument determines if the immediate is suitable to be used with
00528 /// the PowerPC instructions such as addis which concatenate 16 bits of the
00529 /// immediate with 16 bits of zeroes.
00530 ///
00531 bool PPC32ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
00532                                            bool Shifted) {
00533   ConstantSInt *Op1Cs;
00534   ConstantUInt *Op1Cu;
00535 
00536   // For shifted immediates, any value with the low halfword cleared may be used
00537   if (Shifted) {
00538     if (((int32_t)CI->getRawValue() & 0x0000FFFF) == 0)
00539       return true;
00540     else
00541       return false;
00542   }
00543 
00544   // Treat subfic like addi for the purposes of constant validation
00545   if (Opcode == 5) Opcode = 0;
00546       
00547   // addi, subfic, compare, and non-indexed load take SIMM
00548   bool cond1 = (Opcode < 2)
00549     && ((int32_t)CI->getRawValue() <= 32767)
00550     && ((int32_t)CI->getRawValue() >= -32768);
00551 
00552   // ANDIo, ORI, and XORI take unsigned values
00553   bool cond2 = (Opcode >= 2)
00554     && (Op1Cs = dyn_cast<ConstantSInt>(CI))
00555     && (Op1Cs->getValue() >= 0)
00556     && (Op1Cs->getValue() <= 65535);
00557 
00558   // ANDIo, ORI, and XORI take UIMMs, so they can be larger
00559   bool cond3 = (Opcode >= 2)
00560     && (Op1Cu = dyn_cast<ConstantUInt>(CI))
00561     && (Op1Cu->getValue() <= 65535);
00562 
00563   if (cond1 || cond2 || cond3)
00564     return true;
00565 
00566   return false;
00567 }
00568 
00569 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
00570 /// that is to be statically allocated with the initial stack frame
00571 /// adjustment.
00572 unsigned PPC32ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
00573   // Already computed this?
00574   std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
00575   if (I != AllocaMap.end() && I->first == AI) return I->second;
00576 
00577   const Type *Ty = AI->getAllocatedType();
00578   ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
00579   unsigned TySize = TM.getTargetData().getTypeSize(Ty);
00580   TySize *= CUI->getValue();   // Get total allocated size...
00581   unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
00582       
00583   // Create a new stack object using the frame manager...
00584   int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
00585   AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
00586   return FrameIdx;
00587 }
00588 
00589 
00590 /// getGlobalBaseReg - Output the instructions required to put the
00591 /// base address to use for accessing globals into a register.
00592 ///
00593 unsigned PPC32ISel::getGlobalBaseReg(MachineBasicBlock *MBB,
00594                                      MachineBasicBlock::iterator IP) {
00595   if (!GlobalBaseInitialized) {
00596     // Insert the set of GlobalBaseReg into the first MBB of the function
00597     MachineBasicBlock &FirstMBB = F->front();
00598     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
00599     GlobalBaseReg = makeAnotherReg(Type::IntTy);
00600     BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
00601     BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
00602     GlobalBaseInitialized = true;
00603   }
00604   return GlobalBaseReg;
00605 }
00606 
00607 /// copyConstantToRegister - Output the instructions required to put the
00608 /// specified constant into the specified register.
00609 ///
00610 void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
00611                                        MachineBasicBlock::iterator IP,
00612                                        Constant *C, unsigned R) {
00613   if (isa<UndefValue>(C)) {
00614     BuildMI(*MBB, IP, PPC::IMPLICIT_DEF, 0, R);
00615     return;
00616   }
00617   if (C->getType()->isIntegral()) {
00618     unsigned Class = getClassB(C->getType());
00619 
00620     if (Class == cLong) {
00621       if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
00622         uint64_t uval = CUI->getValue();
00623         unsigned hiUVal = uval >> 32;
00624         unsigned loUVal = uval;
00625         ConstantUInt *CUHi = ConstantUInt::get(Type::UIntTy, hiUVal);
00626         ConstantUInt *CULo = ConstantUInt::get(Type::UIntTy, loUVal);
00627         copyConstantToRegister(MBB, IP, CUHi, R);
00628         copyConstantToRegister(MBB, IP, CULo, R+1);
00629         return;
00630       } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
00631         int64_t sval = CSI->getValue();
00632         int hiSVal = sval >> 32;
00633         int loSVal = sval;
00634         ConstantSInt *CSHi = ConstantSInt::get(Type::IntTy, hiSVal);
00635         ConstantSInt *CSLo = ConstantSInt::get(Type::IntTy, loSVal);
00636         copyConstantToRegister(MBB, IP, CSHi, R);
00637         copyConstantToRegister(MBB, IP, CSLo, R+1);
00638         return;
00639       } else {
00640         std::cerr << "Unhandled long constant type!\n";
00641         abort();
00642       }
00643     }
00644     
00645     assert(Class <= cInt && "Type not handled yet!");
00646 
00647     // Handle bool
00648     if (C->getType() == Type::BoolTy) {
00649       BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
00650       return;
00651     }
00652     
00653     // Handle int
00654     if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
00655       unsigned uval = CUI->getValue();
00656       if (uval < 32768) {
00657         BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
00658       } else {
00659         unsigned Temp = makeAnotherReg(Type::IntTy);
00660         BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
00661         BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval & 0xFFFF);
00662       }
00663       return;
00664     } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
00665       int sval = CSI->getValue();
00666       if (sval < 32768 && sval >= -32768) {
00667         BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
00668       } else {
00669         unsigned Temp = makeAnotherReg(Type::IntTy);
00670         BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
00671         BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval & 0xFFFF);
00672       }
00673       return;
00674     }
00675     std::cerr << "Unhandled integer constant!\n";
00676     abort();
00677   } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
00678     // We need to spill the constant to memory...
00679     MachineConstantPool *CP = F->getConstantPool();
00680     unsigned CPI = CP->getConstantPoolIndex(CFP);
00681     const Type *Ty = CFP->getType();
00682 
00683     assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
00684 
00685     // Load addr of constant to reg; constant is located at base + distance
00686     unsigned GlobalBase = makeAnotherReg(Type::IntTy);
00687     unsigned Reg1 = makeAnotherReg(Type::IntTy);
00688     unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
00689     // Move value at base + distance into return reg
00690     BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1)
00691       .addReg(getGlobalBaseReg(MBB, IP)).addConstantPoolIndex(CPI);
00692     BuildMI(*MBB, IP, Opcode, 2, R).addConstantPoolIndex(CPI).addReg(Reg1);
00693   } else if (isa<ConstantPointerNull>(C)) {
00694     // Copy zero (null pointer) to the register.
00695     BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
00696   } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
00697     // GV is located at base + distance
00698     
00699     unsigned GlobalBase = makeAnotherReg(Type::IntTy);
00700     unsigned TmpReg = makeAnotherReg(GV->getType());
00701     
00702     // Move value at base + distance into return reg
00703     BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
00704       .addReg(getGlobalBaseReg(MBB, IP)).addGlobalAddress(GV);
00705 
00706     if (GV->hasWeakLinkage() || GV->isExternal()) {
00707       BuildMI(*MBB, IP, PPC::LWZ, 2, R).addGlobalAddress(GV).addReg(TmpReg);
00708     } else {
00709       BuildMI(*MBB, IP, PPC::LA, 2, R).addReg(TmpReg).addGlobalAddress(GV);
00710     }
00711   } else {
00712     std::cerr << "Offending constant: " << *C << "\n";
00713     assert(0 && "Type not handled yet!");
00714   }
00715 }
00716 
00717 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
00718 /// the stack into virtual registers.
00719 void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
00720   unsigned ArgOffset = 24;
00721   unsigned GPR_remaining = 8;
00722   unsigned FPR_remaining = 13;
00723   unsigned GPR_idx = 0, FPR_idx = 0;
00724   static const unsigned GPR[] = { 
00725     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
00726     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
00727   };
00728   static const unsigned FPR[] = {
00729     PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
00730     PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
00731   };
00732     
00733   MachineFrameInfo *MFI = F->getFrameInfo();
00734  
00735   for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
00736     bool ArgLive = !I->use_empty();
00737     unsigned Reg = ArgLive ? getReg(*I) : 0;
00738     int FI;          // Frame object index
00739 
00740     switch (getClassB(I->getType())) {
00741     case cByte:
00742       if (ArgLive) {
00743         FI = MFI->CreateFixedObject(4, ArgOffset);
00744         if (GPR_remaining > 0) {
00745           BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
00746           BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
00747             .addReg(GPR[GPR_idx]);
00748         } else {
00749           addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
00750         }
00751       }
00752       break;
00753     case cShort:
00754       if (ArgLive) {
00755         FI = MFI->CreateFixedObject(4, ArgOffset);
00756         if (GPR_remaining > 0) {
00757           BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
00758           BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
00759             .addReg(GPR[GPR_idx]);
00760         } else {
00761           addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
00762         }
00763       }
00764       break;
00765     case cInt:
00766       if (ArgLive) {
00767         FI = MFI->CreateFixedObject(4, ArgOffset);
00768         if (GPR_remaining > 0) {
00769           BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
00770           BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
00771             .addReg(GPR[GPR_idx]);
00772         } else {
00773           addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
00774         }
00775       }
00776       break;
00777     case cLong:
00778       if (ArgLive) {
00779         FI = MFI->CreateFixedObject(8, ArgOffset);
00780         if (GPR_remaining > 1) {
00781           BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
00782           BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
00783           BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
00784             .addReg(GPR[GPR_idx]);
00785           BuildMI(BB, PPC::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
00786             .addReg(GPR[GPR_idx+1]);
00787         } else {
00788           addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
00789           addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg+1), FI, 4);
00790         }
00791       }
00792       // longs require 4 additional bytes and use 2 GPRs
00793       ArgOffset += 4;
00794       if (GPR_remaining > 1) {
00795         GPR_remaining--;
00796         GPR_idx++;
00797       }
00798       break;
00799     case cFP32:
00800      if (ArgLive) {
00801         FI = MFI->CreateFixedObject(4, ArgOffset);
00802 
00803         if (FPR_remaining > 0) {
00804           BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
00805           BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
00806           FPR_remaining--;
00807           FPR_idx++;
00808         } else {
00809           addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
00810         }
00811       }
00812       break;
00813     case cFP64:
00814       if (ArgLive) {
00815         FI = MFI->CreateFixedObject(8, ArgOffset);
00816 
00817         if (FPR_remaining > 0) {
00818           BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
00819           BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
00820           FPR_remaining--;
00821           FPR_idx++;
00822         } else {
00823           addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
00824         }
00825       }
00826 
00827       // doubles require 4 additional bytes and use 2 GPRs of param space
00828       ArgOffset += 4;   
00829       if (GPR_remaining > 0) {
00830         GPR_remaining--;
00831         GPR_idx++;
00832       }
00833       break;
00834     default:
00835       assert(0 && "Unhandled argument type!");
00836     }
00837     ArgOffset += 4;  // Each argument takes at least 4 bytes on the stack...
00838     if (GPR_remaining > 0) {
00839       GPR_remaining--;    // uses up 2 GPRs
00840       GPR_idx++;
00841     }
00842   }
00843 
00844   // If the function takes variable number of arguments, add a frame offset for
00845   // the start of the first vararg value... this is used to expand
00846   // llvm.va_start.
00847   if (Fn.getFunctionType()->isVarArg())
00848     VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
00849 }
00850 
00851 
00852 /// SelectPHINodes - Insert machine code to generate phis.  This is tricky
00853 /// because we have to generate our sources into the source basic blocks, not
00854 /// the current one.
00855 ///
00856 void PPC32ISel::SelectPHINodes() {
00857   const TargetInstrInfo &TII = *TM.getInstrInfo();
00858   const Function &LF = *F->getFunction();  // The LLVM function...
00859   for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
00860     const BasicBlock *BB = I;
00861     MachineBasicBlock &MBB = *MBBMap[I];
00862 
00863     // Loop over all of the PHI nodes in the LLVM basic block...
00864     MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
00865     for (BasicBlock::const_iterator I = BB->begin();
00866          PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
00867 
00868       // Create a new machine instr PHI node, and insert it.
00869       unsigned PHIReg = getReg(*PN);
00870       MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
00871                                     PPC::PHI, PN->getNumOperands(), PHIReg);
00872 
00873       MachineInstr *LongPhiMI = 0;
00874       if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
00875         LongPhiMI = BuildMI(MBB, PHIInsertPoint,
00876                             PPC::PHI, PN->getNumOperands(), PHIReg+1);
00877 
00878       // PHIValues - Map of blocks to incoming virtual registers.  We use this
00879       // so that we only initialize one incoming value for a particular block,
00880       // even if the block has multiple entries in the PHI node.
00881       //
00882       std::map<MachineBasicBlock*, unsigned> PHIValues;
00883 
00884       for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
00885         MachineBasicBlock *PredMBB = 0;
00886         for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
00887              PE = MBB.pred_end (); PI != PE; ++PI)
00888           if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
00889             PredMBB = *PI;
00890             break;
00891           }
00892         assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
00893 
00894         unsigned ValReg;
00895         std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
00896           PHIValues.lower_bound(PredMBB);
00897 
00898         if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
00899           // We already inserted an initialization of the register for this
00900           // predecessor.  Recycle it.
00901           ValReg = EntryIt->second;
00902         } else {
00903           // Get the incoming value into a virtual register.
00904           //
00905           Value *Val = PN->getIncomingValue(i);
00906 
00907           // If this is a constant or GlobalValue, we may have to insert code
00908           // into the basic block to compute it into a virtual register.
00909           if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
00910               isa<GlobalValue>(Val)) {
00911             // Simple constants get emitted at the end of the basic block,
00912             // before any terminator instructions.  We "know" that the code to
00913             // move a constant into a register will never clobber any flags.
00914             ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
00915           } else {
00916             // Because we don't want to clobber any values which might be in
00917             // physical registers with the computation of this constant (which
00918             // might be arbitrarily complex if it is a constant expression),
00919             // just insert the computation at the top of the basic block.
00920             MachineBasicBlock::iterator PI = PredMBB->begin();
00921 
00922             // Skip over any PHI nodes though!
00923             while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
00924               ++PI;
00925 
00926             ValReg = getReg(Val, PredMBB, PI);
00927           }
00928 
00929           // Remember that we inserted a value for this PHI for this predecessor
00930           PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
00931         }
00932 
00933         PhiMI->addRegOperand(ValReg);
00934         PhiMI->addMachineBasicBlockOperand(PredMBB);
00935         if (LongPhiMI) {
00936           LongPhiMI->addRegOperand(ValReg+1);
00937           LongPhiMI->addMachineBasicBlockOperand(PredMBB);
00938         }
00939       }
00940 
00941       // Now that we emitted all of the incoming values for the PHI node, make
00942       // sure to reposition the InsertPoint after the PHI that we just added.
00943       // This is needed because we might have inserted a constant into this
00944       // block, right after the PHI's which is before the old insert point!
00945       PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
00946       ++PHIInsertPoint;
00947     }
00948   }
00949 }
00950 
00951 
00952 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
00953 // it into the conditional branch or select instruction which is the only user
00954 // of the cc instruction.  This is the case if the conditional branch is the
00955 // only user of the setcc, and if the setcc is in the same basic block as the
00956 // conditional branch.
00957 //
00958 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
00959   if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
00960     if (SCI->hasOneUse()) {
00961       Instruction *User = cast<Instruction>(SCI->use_back());
00962       if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
00963           SCI->getParent() == User->getParent())
00964         return SCI;
00965     }
00966   return 0;
00967 }
00968 
00969 // canFoldGEPIntoLoadOrStore - Return the GEP instruction if we can fold it into
00970 // the load or store instruction that is the only user of the GEP.
00971 //
00972 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
00973   if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V)) {
00974     bool AllUsesAreMem = true;
00975     for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end(); 
00976          I != E; ++I) {
00977       Instruction *User = cast<Instruction>(*I);
00978 
00979       // If the GEP is the target of a store, but not the source, then we are ok
00980       // to fold it.
00981       if (isa<StoreInst>(User) &&
00982           GEPI->getParent() == User->getParent() &&
00983           User->getOperand(0) != GEPI &&
00984           User->getOperand(1) == GEPI)
00985         continue;
00986 
00987       // If the GEP is the source of a load, then we're always ok to fold it
00988       if (isa<LoadInst>(User) &&
00989           GEPI->getParent() == User->getParent() &&
00990           User->getOperand(0) == GEPI)
00991         continue;
00992 
00993       // if we got to this point, than the instruction was not a load or store
00994       // that we are capable of folding the GEP into.
00995       AllUsesAreMem = false;
00996       break;
00997     }
00998     if (AllUsesAreMem)
00999       return GEPI;
01000   }
01001   return 0;
01002 }
01003 
01004 
01005 // Return a fixed numbering for setcc instructions which does not depend on the
01006 // order of the opcodes.
01007 //
01008 static unsigned getSetCCNumber(unsigned Opcode) {
01009   switch (Opcode) {
01010   default: assert(0 && "Unknown setcc instruction!");
01011   case Instruction::SetEQ: return 0;
01012   case Instruction::SetNE: return 1;
01013   case Instruction::SetLT: return 2;
01014   case Instruction::SetGE: return 3;
01015   case Instruction::SetGT: return 4;
01016   case Instruction::SetLE: return 5;
01017   }
01018 }
01019 
01020 static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
01021   switch (Opcode) {
01022   default: assert(0 && "Unknown setcc instruction!");
01023   case Instruction::SetEQ: return PPC::BEQ;
01024   case Instruction::SetNE: return PPC::BNE;
01025   case Instruction::SetLT: return PPC::BLT;
01026   case Instruction::SetGE: return PPC::BGE;
01027   case Instruction::SetGT: return PPC::BGT;
01028   case Instruction::SetLE: return PPC::BLE;
01029   }
01030 }
01031 
01032 /// emitUCOM - emits an unordered FP compare.
01033 void PPC32ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
01034                          unsigned LHS, unsigned RHS) {
01035     BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
01036 }
01037 
01038 unsigned PPC32ISel::ExtendOrClear(MachineBasicBlock *MBB,
01039                                   MachineBasicBlock::iterator IP,
01040                                   Value *Op0) {
01041   const Type *CompTy = Op0->getType();
01042   unsigned Reg = getReg(Op0, MBB, IP);
01043   unsigned Class = getClassB(CompTy);
01044 
01045   // Since we know that boolean values will be either zero or one, we don't
01046   // have to extend or clear them.
01047   if (CompTy == Type::BoolTy)
01048     return Reg;
01049 
01050   // Before we do a comparison or SetCC, we have to make sure that we truncate
01051   // the source registers appropriately.
01052   if (Class == cByte) {
01053     unsigned TmpReg = makeAnotherReg(CompTy);
01054     if (CompTy->isSigned())
01055       BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Reg);
01056     else
01057       BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Reg).addImm(0)
01058         .addImm(24).addImm(31);
01059     Reg = TmpReg;
01060   } else if (Class == cShort) {
01061     unsigned TmpReg = makeAnotherReg(CompTy);
01062     if (CompTy->isSigned())
01063       BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Reg);
01064     else
01065       BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Reg).addImm(0)
01066         .addImm(16).addImm(31);
01067     Reg = TmpReg;
01068   }
01069   return Reg;
01070 }
01071 
01072 /// EmitComparison - emits a comparison of the two operands, returning the
01073 /// extended setcc code to use.  The result is in CR0.
01074 ///
01075 unsigned PPC32ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
01076                                    MachineBasicBlock *MBB,
01077                                    MachineBasicBlock::iterator IP) {
01078   // The arguments are already supposed to be of the same type.
01079   const Type *CompTy = Op0->getType();
01080   unsigned Class = getClassB(CompTy);
01081   unsigned Op0r = ExtendOrClear(MBB, IP, Op0);
01082   
01083   // Use crand for lt, gt and crandc for le, ge
01084   unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
01085   // ? cr1[lt] : cr1[gt]
01086   unsigned CR1field = (OpNum == 2 || OpNum == 3) ? 4 : 5;
01087   // ? cr0[lt] : cr0[gt]
01088   unsigned CR0field = (OpNum == 2 || OpNum == 5) ? 0 : 1;
01089   unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
01090   unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
01091 
01092   // Special case handling of: cmp R, i
01093   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
01094     if (Class == cByte || Class == cShort || Class == cInt) {
01095       unsigned Op1v = CI->getRawValue() & 0xFFFF;
01096       unsigned OpClass = (CompTy->isSigned()) ? 0 : 2;
01097       
01098       // Treat compare like ADDI for the purposes of immediate suitability
01099       if (canUseAsImmediateForOpcode(CI, OpClass, false)) {
01100         BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
01101       } else {
01102         unsigned Op1r = getReg(Op1, MBB, IP);
01103         BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
01104       }
01105       return OpNum;
01106     } else {
01107       assert(Class == cLong && "Unknown integer class!");
01108       unsigned LowCst = CI->getRawValue();
01109       unsigned HiCst = CI->getRawValue() >> 32;
01110       if (OpNum < 2) {    // seteq, setne
01111         unsigned LoLow = makeAnotherReg(Type::IntTy);
01112         unsigned LoTmp = makeAnotherReg(Type::IntTy);
01113         unsigned HiLow = makeAnotherReg(Type::IntTy);
01114         unsigned HiTmp = makeAnotherReg(Type::IntTy);
01115         unsigned FinalTmp = makeAnotherReg(Type::IntTy);
01116 
01117         BuildMI(*MBB, IP, PPC::XORI, 2, LoLow).addReg(Op0r+1)
01118           .addImm(LowCst & 0xFFFF);
01119         BuildMI(*MBB, IP, PPC::XORIS, 2, LoTmp).addReg(LoLow)
01120           .addImm(LowCst >> 16);
01121         BuildMI(*MBB, IP, PPC::XORI, 2, HiLow).addReg(Op0r)
01122           .addImm(HiCst & 0xFFFF);
01123         BuildMI(*MBB, IP, PPC::XORIS, 2, HiTmp).addReg(HiLow)
01124           .addImm(HiCst >> 16);
01125         BuildMI(*MBB, IP, PPC::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
01126         return OpNum;
01127       } else {
01128         unsigned ConstReg = makeAnotherReg(CompTy);
01129         copyConstantToRegister(MBB, IP, CI, ConstReg);
01130 
01131         // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
01132         BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r)
01133           .addReg(ConstReg);
01134         BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1)
01135           .addReg(ConstReg+1);
01136         BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
01137         BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
01138           .addImm(2);
01139         return OpNum;
01140       }
01141     }
01142   }
01143 
01144   unsigned Op1r = getReg(Op1, MBB, IP);
01145 
01146   switch (Class) {
01147   default: assert(0 && "Unknown type class!");
01148   case cByte:
01149   case cShort:
01150   case cInt:
01151     BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
01152     break;
01153 
01154   case cFP32:
01155   case cFP64:
01156     emitUCOM(MBB, IP, Op0r, Op1r);
01157     break;
01158 
01159   case cLong:
01160     if (OpNum < 2) {    // seteq, setne
01161       unsigned LoTmp = makeAnotherReg(Type::IntTy);
01162       unsigned HiTmp = makeAnotherReg(Type::IntTy);
01163       unsigned FinalTmp = makeAnotherReg(Type::IntTy);
01164       BuildMI(*MBB, IP, PPC::XOR, 2, HiTmp).addReg(Op0r).addReg(Op1r);
01165       BuildMI(*MBB, IP, PPC::XOR, 2, LoTmp).addReg(Op0r+1).addReg(Op1r+1);
01166       BuildMI(*MBB, IP, PPC::ORo,  2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
01167       break;  // Allow the sete or setne to be generated from flags set by OR
01168     } else {
01169       unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
01170       unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
01171 
01172       // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
01173       BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
01174       BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1).addReg(Op1r+1);
01175       BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
01176       BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
01177         .addImm(2);
01178       return OpNum;
01179     }
01180   }
01181   return OpNum;
01182 }
01183 
01184 /// visitSetCondInst - emit code to calculate the condition via
01185 /// EmitComparison(), and possibly store a 0 or 1 to a register as a result
01186 ///
01187 void PPC32ISel::visitSetCondInst(SetCondInst &I) {
01188   if (canFoldSetCCIntoBranchOrSelect(&I))
01189     return;
01190 
01191   MachineBasicBlock::iterator MI = BB->end();
01192   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
01193   const Type *Ty = Op0->getType();
01194   unsigned Class = getClassB(Ty);
01195   unsigned Opcode = I.getOpcode();
01196   unsigned OpNum = getSetCCNumber(Opcode);      
01197   unsigned DestReg = getReg(I);
01198 
01199   // If the comparison type is byte, short, or int, then we can emit a
01200   // branchless version of the SetCC that puts 0 (false) or 1 (true) in the
01201   // destination register.
01202   if (Class <= cInt) {
01203     ConstantInt *CI = dyn_cast<ConstantInt>(Op1);
01204 
01205     if (CI && CI->getRawValue() == 0) {
01206       unsigned Op0Reg = ExtendOrClear(BB, MI, Op0);
01207     
01208       // comparisons against constant zero and negative one often have shorter
01209       // and/or faster sequences than the set-and-branch general case, handled
01210       // below.
01211       switch(OpNum) {
01212       case 0: { // eq0
01213         unsigned TempReg = makeAnotherReg(Type::IntTy);
01214         BuildMI(*BB, MI, PPC::CNTLZW, 1, TempReg).addReg(Op0Reg);
01215         BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(TempReg).addImm(27)
01216           .addImm(5).addImm(31);
01217         break;
01218         } 
01219       case 1: { // ne0
01220         unsigned TempReg = makeAnotherReg(Type::IntTy);
01221         BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
01222         BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
01223         break;
01224         } 
01225       case 2: { // lt0, always false if unsigned
01226         if (Ty->isSigned())
01227           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(1)
01228             .addImm(31).addImm(31);
01229         else
01230           BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(0);
01231         break;
01232         }
01233       case 3: { // ge0, always true if unsigned
01234         if (Ty->isSigned()) { 
01235           unsigned TempReg = makeAnotherReg(Type::IntTy);
01236           BuildMI(*BB, MI, PPC::RLWINM, 4, TempReg).addReg(Op0Reg).addImm(1)
01237             .addImm(31).addImm(31);
01238           BuildMI(*BB, MI, PPC::XORI, 2, DestReg).addReg(TempReg).addImm(1);
01239         } else {
01240           BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(1);
01241         }
01242         break;
01243         }
01244       case 4: { // gt0, equivalent to ne0 if unsigned
01245         unsigned Temp1 = makeAnotherReg(Type::IntTy);
01246         unsigned Temp2 = makeAnotherReg(Type::IntTy);
01247         if (Ty->isSigned()) { 
01248           BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
01249           BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
01250           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
01251             .addImm(31).addImm(31);
01252         } else {
01253           BuildMI(*BB, MI, PPC::ADDIC, 2, Temp1).addReg(Op0Reg).addSImm(-1);
01254           BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(Temp1).addReg(Op0Reg);
01255         }
01256         break;
01257         }
01258       case 5: { // le0, equivalent to eq0 if unsigned
01259         unsigned Temp1 = makeAnotherReg(Type::IntTy);
01260         unsigned Temp2 = makeAnotherReg(Type::IntTy);
01261         if (Ty->isSigned()) { 
01262           BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
01263           BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
01264           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
01265             .addImm(31).addImm(31);
01266         } else {
01267           BuildMI(*BB, MI, PPC::CNTLZW, 1, Temp1).addReg(Op0Reg);
01268           BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp1).addImm(27)
01269             .addImm(5).addImm(31);
01270         }
01271         break;
01272         }
01273       } // switch
01274       return;
01275     }
01276   }
01277   unsigned PPCOpcode = getPPCOpcodeForSetCCNumber(Opcode);
01278 
01279   // Create an iterator with which to insert the MBB for copying the false value
01280   // and the MBB to hold the PHI instruction for this SetCC.
01281   MachineBasicBlock *thisMBB = BB;
01282   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01283   ilist<MachineBasicBlock>::iterator It = BB;
01284   ++It;
01285   
01286   //  thisMBB:
01287   //  ...
01288   //   cmpTY cr0, r1, r2
01289   //   %TrueValue = li 1
01290   //   bCC sinkMBB
01291   EmitComparison(Opcode, Op0, Op1, BB, BB->end());
01292   unsigned TrueValue = makeAnotherReg(I.getType());
01293   BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
01294   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
01295   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
01296   BuildMI(BB, PPCOpcode, 2).addReg(PPC::CR0).addMBB(sinkMBB);
01297   F->getBasicBlockList().insert(It, copy0MBB);
01298   F->getBasicBlockList().insert(It, sinkMBB);
01299   // Update machine-CFG edges
01300   BB->addSuccessor(copy0MBB);
01301   BB->addSuccessor(sinkMBB);
01302 
01303   //  copy0MBB:
01304   //   %FalseValue = li 0
01305   //   fallthrough
01306   BB = copy0MBB;
01307   unsigned FalseValue = makeAnotherReg(I.getType());
01308   BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
01309   // Update machine-CFG edges
01310   BB->addSuccessor(sinkMBB);
01311 
01312   //  sinkMBB:
01313   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
01314   //  ...
01315   BB = sinkMBB;
01316   BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
01317     .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
01318 }
01319 
01320 void PPC32ISel::visitSelectInst(SelectInst &SI) {
01321   unsigned DestReg = getReg(SI);
01322   MachineBasicBlock::iterator MII = BB->end();
01323   emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
01324                       SI.getFalseValue(), DestReg);
01325 }
01326  
01327 /// emitSelect - Common code shared between visitSelectInst and the constant
01328 /// expression support.
01329 void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
01330                                     MachineBasicBlock::iterator IP,
01331                                     Value *Cond, Value *TrueVal, 
01332                                     Value *FalseVal, unsigned DestReg) {
01333   unsigned SelectClass = getClassB(TrueVal->getType());
01334   unsigned Opcode;
01335 
01336   // See if we can fold the setcc into the select instruction, or if we have
01337   // to get the register of the Cond value
01338   if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
01339     // We successfully folded the setcc into the select instruction.
01340     unsigned OpNum = getSetCCNumber(SCI->getOpcode());
01341     if (OpNum >= 2 && OpNum <= 5) {
01342       unsigned SetCondClass = getClassB(SCI->getOperand(0)->getType());
01343       if ((SetCondClass == cFP32 || SetCondClass == cFP64) &&
01344           (SelectClass == cFP32 || SelectClass == cFP64)) {
01345         unsigned CondReg = getReg(SCI->getOperand(0), MBB, IP);
01346         unsigned TrueReg = getReg(TrueVal, MBB, IP);
01347         unsigned FalseReg = getReg(FalseVal, MBB, IP);
01348         // if the comparison of the floating point value used to for the select
01349         // is against 0, then we can emit an fsel without subtraction.
01350         ConstantFP *Op1C = dyn_cast<ConstantFP>(SCI->getOperand(1));
01351         if (Op1C && (Op1C->isExactlyValue(-0.0) || Op1C->isExactlyValue(0.0))) {
01352           switch(OpNum) {
01353           case 2:   // LT
01354             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(CondReg)
01355               .addReg(FalseReg).addReg(TrueReg);
01356             break;
01357           case 3:   // GE == !LT
01358             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(CondReg)
01359               .addReg(TrueReg).addReg(FalseReg);
01360             break;
01361           case 4: {  // GT
01362             unsigned NegatedReg = makeAnotherReg(SCI->getOperand(0)->getType());
01363             BuildMI(*MBB, IP, PPC::FNEG, 1, NegatedReg).addReg(CondReg);
01364             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(NegatedReg)
01365               .addReg(FalseReg).addReg(TrueReg);
01366             }
01367             break;
01368           case 5: {  // LE == !GT
01369             unsigned NegatedReg = makeAnotherReg(SCI->getOperand(0)->getType());
01370             BuildMI(*MBB, IP, PPC::FNEG, 1, NegatedReg).addReg(CondReg);
01371             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(NegatedReg)
01372               .addReg(TrueReg).addReg(FalseReg);
01373             }
01374             break;
01375           default:
01376             assert(0 && "Invalid SetCC opcode to fsel");
01377             abort();
01378             break;
01379           }
01380         } else {
01381           unsigned OtherCondReg = getReg(SCI->getOperand(1), MBB, IP);
01382           unsigned SelectReg = makeAnotherReg(SCI->getOperand(0)->getType());
01383           switch(OpNum) {
01384           case 2:   // LT
01385             BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(CondReg)
01386               .addReg(OtherCondReg);
01387             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
01388               .addReg(FalseReg).addReg(TrueReg);
01389             break;
01390           case 3:   // GE == !LT
01391             BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(CondReg)
01392               .addReg(OtherCondReg);
01393             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
01394               .addReg(TrueReg).addReg(FalseReg);
01395             break;
01396           case 4:   // GT
01397             BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(OtherCondReg)
01398               .addReg(CondReg);
01399             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
01400               .addReg(FalseReg).addReg(TrueReg);
01401             break;
01402           case 5:   // LE == !GT
01403             BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(OtherCondReg)
01404               .addReg(CondReg);
01405             BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
01406               .addReg(TrueReg).addReg(FalseReg);
01407             break;
01408           default:
01409             assert(0 && "Invalid SetCC opcode to fsel");
01410             abort();
01411             break;
01412           }
01413         }
01414         return;
01415       }
01416     }
01417     OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
01418     Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
01419   } else {
01420     unsigned CondReg = getReg(Cond, MBB, IP);
01421     BuildMI(*MBB, IP, PPC::CMPWI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
01422     Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
01423   }
01424 
01425   MachineBasicBlock *thisMBB = BB;
01426   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01427   ilist<MachineBasicBlock>::iterator It = BB;
01428   ++It;
01429 
01430   //  thisMBB:
01431   //  ...
01432   //   cmpTY cr0, r1, r2
01433   //   bCC copy1MBB
01434   //   fallthrough --> copy0MBB
01435   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
01436   MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
01437   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
01438   BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
01439   F->getBasicBlockList().insert(It, copy0MBB);
01440   F->getBasicBlockList().insert(It, copy1MBB);
01441   F->getBasicBlockList().insert(It, sinkMBB);
01442   // Update machine-CFG edges
01443   BB->addSuccessor(copy0MBB);
01444   BB->addSuccessor(copy1MBB);
01445 
01446   //  copy0MBB:
01447   //   %FalseValue = ...
01448   //   b sinkMBB
01449   BB = copy0MBB;
01450   unsigned FalseValue = getReg(FalseVal, BB, BB->begin());
01451   BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
01452   // Update machine-CFG edges
01453   BB->addSuccessor(sinkMBB);
01454 
01455   //  copy1MBB:
01456   //   %TrueValue = ...
01457   //   fallthrough
01458   BB = copy1MBB;
01459   unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
01460   // Update machine-CFG edges
01461   BB->addSuccessor(sinkMBB);
01462 
01463   //  sinkMBB:
01464   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
01465   //  ...
01466   BB = sinkMBB;
01467   BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
01468     .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
01469     
01470   // For a register pair representing a long value, define the second reg
01471   // FIXME: Can this really be correct for selecting longs?
01472   if (getClassB(TrueVal->getType()) == cLong)
01473     BuildMI(BB, PPC::LI, 1, DestReg+1).addImm(0);
01474   return;
01475 }
01476 
01477 
01478 
01479 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
01480 /// operand, in the specified target register.
01481 ///
01482 void PPC32ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
01483   bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
01484 
01485   Value *Val = VR.Val;
01486   const Type *Ty = VR.Ty;
01487   if (Val) {
01488     if (Constant *C = dyn_cast<Constant>(Val)) {
01489       Val = ConstantExpr::getCast(C, Type::IntTy);
01490       if (isa<ConstantExpr>(Val))   // Could not fold
01491         Val = C;
01492       else
01493         Ty = Type::IntTy;           // Folded!
01494     }
01495 
01496     // If this is a simple constant, just emit a load directly to avoid the copy
01497     if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
01498       copyConstantToRegister(BB, BB->end(), CI, targetReg);
01499       return;
01500     }
01501   }
01502 
01503   // Make sure we have the register number for this value...
01504   unsigned Reg = Val ? getReg(Val) : VR.Reg;
01505   switch (getClassB(Ty)) {
01506   case cByte:
01507     // Extend value into target register (8->32)
01508     if (Ty == Type::BoolTy)
01509       BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
01510     else if (isUnsigned)
01511       BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
01512         .addZImm(24).addZImm(31);
01513     else
01514       BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
01515     break;
01516   case cShort:
01517     // Extend value into target register (16->32)
01518     if (isUnsigned)
01519       BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
01520         .addZImm(16).addZImm(31);
01521     else
01522       BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
01523     break;
01524   case cInt:
01525     // Move value into target register (32->32)
01526     BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
01527     break;
01528   default:
01529     assert(0 && "Unpromotable operand class in promote32");
01530   }
01531 }
01532 
01533 /// visitReturnInst - implemented with BLR
01534 ///
01535 void PPC32ISel::visitReturnInst(ReturnInst &I) {
01536   // Only do the processing if this is a non-void return
01537   if (I.getNumOperands() > 0) {
01538     Value *RetVal = I.getOperand(0);
01539     switch (getClassB(RetVal->getType())) {
01540     case cByte:   // integral return values: extend or move into r3 and return
01541     case cShort:
01542     case cInt:
01543       promote32(PPC::R3, ValueRecord(RetVal));
01544       break;
01545     case cFP32:
01546     case cFP64: {   // Floats & Doubles: Return in f1
01547       unsigned RetReg = getReg(RetVal);
01548       BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
01549       break;
01550     }
01551     case cLong: {
01552       unsigned RetReg = getReg(RetVal);
01553       BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(RetReg).addReg(RetReg);
01554       BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(RetReg+1).addReg(RetReg+1);
01555       break;
01556     }
01557     default:
01558       visitInstruction(I);
01559     }
01560   }
01561   BuildMI(BB, PPC::BLR, 1).addImm(0);
01562 }
01563 
01564 // getBlockAfter - Return the basic block which occurs lexically after the
01565 // specified one.
01566 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
01567   Function::iterator I = BB; ++I;  // Get iterator to next block
01568   return I != BB->getParent()->end() ? &*I : 0;
01569 }
01570 
01571 /// visitBranchInst - Handle conditional and unconditional branches here.  Note
01572 /// that since code layout is frozen at this point, that if we are trying to
01573 /// jump to a block that is the immediate successor of the current block, we can
01574 /// just make a fall-through (but we don't currently).
01575 ///
01576 void PPC32ISel::visitBranchInst(BranchInst &BI) {
01577   // Update machine-CFG edges
01578   BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
01579   if (BI.isConditional())
01580     BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
01581   
01582   BasicBlock *NextBB = getBlockAfter(BI.getParent());  // BB after current one
01583 
01584   if (!BI.isConditional()) {  // Unconditional branch?
01585     if (BI.getSuccessor(0) != NextBB) 
01586       BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
01587     return;
01588   }
01589   
01590   // See if we can fold the setcc into the branch itself...
01591   SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
01592   if (SCI == 0) {
01593     // Nope, cannot fold setcc into this branch.  Emit a branch on a condition
01594     // computed some other way...
01595     unsigned condReg = getReg(BI.getCondition());
01596     BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
01597       .addImm(0);
01598     if (BI.getSuccessor(1) == NextBB) {
01599       if (BI.getSuccessor(0) != NextBB)
01600         BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
01601           .addMBB(MBBMap[BI.getSuccessor(0)])
01602           .addMBB(MBBMap[BI.getSuccessor(1)]);
01603     } else {
01604       BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
01605         .addMBB(MBBMap[BI.getSuccessor(1)])
01606         .addMBB(MBBMap[BI.getSuccessor(0)]);
01607       if (BI.getSuccessor(0) != NextBB)
01608         BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
01609     }
01610     return;
01611   }
01612 
01613   unsigned OpNum = getSetCCNumber(SCI->getOpcode());
01614   unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
01615   MachineBasicBlock::iterator MII = BB->end();
01616   OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
01617   
01618   if (BI.getSuccessor(0) != NextBB) {
01619     BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
01620       .addMBB(MBBMap[BI.getSuccessor(0)])
01621       .addMBB(MBBMap[BI.getSuccessor(1)]);
01622     if (BI.getSuccessor(1) != NextBB)
01623       BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
01624   } else {
01625     // Change to the inverse condition...
01626     if (BI.getSuccessor(1) != NextBB) {
01627       Opcode = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
01628       BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
01629         .addMBB(MBBMap[BI.getSuccessor(1)])
01630         .addMBB(MBBMap[BI.getSuccessor(0)]);
01631     }
01632   }
01633 }
01634 
01635 /// doCall - This emits an abstract call instruction, setting up the arguments
01636 /// and the return value as appropriate.  For the actual function call itself,
01637 /// it inserts the specified CallMI instruction into the stream.
01638 ///
01639 /// FIXME: See Documentation at the following URL for "correct" behavior
01640 /// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
01641 void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
01642                        const std::vector<ValueRecord> &Args, bool isVarArg) {
01643   // Count how many bytes are to be pushed on the stack, including the linkage
01644   // area, and parameter passing area.
01645   unsigned NumBytes = 24;
01646   unsigned ArgOffset = 24;
01647 
01648   if (!Args.empty()) {
01649     for (unsigned i = 0, e = Args.size(); i != e; ++i)
01650       switch (getClassB(Args[i].Ty)) {
01651       case cByte: case cShort: case cInt:
01652         NumBytes += 4; break;
01653       case cLong:
01654         NumBytes += 8; break;
01655       case cFP32:
01656         NumBytes += 4; break;
01657       case cFP64:
01658         NumBytes += 8; break;
01659         break;
01660       default: assert(0 && "Unknown class!");
01661       }
01662 
01663     // Just to be safe, we'll always reserve the full 24 bytes of linkage area 
01664     // plus 32 bytes of argument space in case any called code gets funky on us.
01665     if (NumBytes < 56) NumBytes = 56;
01666 
01667     // Adjust the stack pointer for the new arguments...
01668     // These functions are automatically eliminated by the prolog/epilog pass
01669     BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
01670 
01671     // Arguments go on the stack in reverse order, as specified by the ABI.
01672     // Offset to the paramater area on the stack is 24.
01673     int GPR_remaining = 8, FPR_remaining = 13;
01674     unsigned GPR_idx = 0, FPR_idx = 0;
01675     static const unsigned GPR[] = { 
01676       PPC::R3, PPC::R4, PPC::R5, PPC::R6,
01677       PPC::R7, PPC::R8, PPC::R9, PPC::R10,
01678     };
01679     static const unsigned FPR[] = {
01680       PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, 
01681       PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, 
01682       PPC::F13
01683     };
01684     
01685     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
01686       unsigned ArgReg;
01687       switch (getClassB(Args[i].Ty)) {
01688       case cByte:
01689       case cShort:
01690         // Promote arg to 32 bits wide into a temporary register...
01691         ArgReg = makeAnotherReg(Type::UIntTy);
01692         promote32(ArgReg, Args[i]);
01693           
01694         // Reg or stack?
01695         if (GPR_remaining > 0) {
01696           BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
01697             .addReg(ArgReg);
01698           CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
01699         }
01700         if (GPR_remaining <= 0 || isVarArg) {
01701           BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
01702             .addReg(PPC::R1);
01703         }
01704         break;
01705       case cInt:
01706         ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
01707 
01708         // Reg or stack?
01709         if (GPR_remaining > 0) {
01710           BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
01711             .addReg(ArgReg);
01712           CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
01713         }
01714         if (GPR_remaining <= 0 || isVarArg) {
01715           BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
01716             .addReg(PPC::R1);
01717         }
01718         break;
01719       case cLong:
01720         ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
01721 
01722         // Reg or stack?  Note that PPC calling conventions state that long args
01723         // are passed rN = hi, rN+1 = lo, opposite of LLVM.
01724         if (GPR_remaining > 1) {
01725           BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
01726             .addReg(ArgReg);
01727           BuildMI(BB, PPC::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg+1)
01728             .addReg(ArgReg+1);
01729           CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
01730           CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
01731         }
01732         if (GPR_remaining <= 1 || isVarArg) {
01733           BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
01734             .addReg(PPC::R1);
01735           BuildMI(BB, PPC::STW, 3).addReg(ArgReg+1).addSImm(ArgOffset+4)
01736             .addReg(PPC::R1);
01737         }
01738 
01739         ArgOffset += 4;        // 8 byte entry, not 4.
01740         GPR_remaining -= 1;    // uses up 2 GPRs
01741         GPR_idx += 1;
01742         break;
01743       case cFP32:
01744         ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
01745         // Reg or stack?
01746         if (FPR_remaining > 0) {
01747           BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
01748           CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
01749           FPR_remaining--;
01750           FPR_idx++;
01751           
01752           // If this is a vararg function, and there are GPRs left, also
01753           // pass the float in an int.  Otherwise, put it on the stack.
01754           if (isVarArg) {
01755             BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
01756             .addReg(PPC::R1);
01757             if (GPR_remaining > 0) {
01758               BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
01759               .addSImm(ArgOffset).addReg(PPC::R1);
01760               CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
01761             }
01762           }
01763         } else {
01764           BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
01765           .addReg(PPC::R1);
01766         }
01767         break;
01768       case cFP64:
01769         ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
01770         // Reg or stack?
01771         if (FPR_remaining > 0) {
01772           BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
01773           CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
01774           FPR_remaining--;
01775           FPR_idx++;
01776           // For vararg functions, must pass doubles via int regs as well
01777           if (isVarArg) {
01778             BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
01779             .addReg(PPC::R1);
01780             
01781             // Doubles can be split across reg + stack for varargs
01782             if (GPR_remaining > 0) {
01783               BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx]).addSImm(ArgOffset)
01784               .addReg(PPC::R1);
01785               CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
01786             }
01787             if (GPR_remaining > 1) {
01788               BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx+1])
01789                 .addSImm(ArgOffset+4).addReg(PPC::R1);
01790               CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
01791             }
01792           }
01793         } else {
01794           BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
01795           .addReg(PPC::R1);
01796         }
01797         // Doubles use 8 bytes, and 2 GPRs worth of param space
01798         ArgOffset += 4;
01799         GPR_remaining--;
01800         GPR_idx++;
01801         break;
01802         
01803       default: assert(0 && "Unknown class!");
01804       }
01805       ArgOffset += 4;
01806       GPR_remaining--;
01807       GPR_idx++;
01808     }
01809   } else {
01810     BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
01811   }
01812   
01813   BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
01814   BB->push_back(CallMI);
01815   
01816   // These functions are automatically eliminated by the prolog/epilog pass
01817   BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
01818 
01819   // If there is a return value, scavenge the result from the location the call
01820   // leaves it in...
01821   //
01822   if (Ret.Ty != Type::VoidTy) {
01823     unsigned DestClass = getClassB(Ret.Ty);
01824     switch (DestClass) {
01825     case cByte:
01826     case cShort:
01827     case cInt:
01828       // Integral results are in r3
01829       BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
01830       break;
01831     case cFP32:   // Floating-point return values live in f1
01832     case cFP64:
01833       BuildMI(BB, PPC::FMR, 1, Ret.Reg).addReg(PPC::F1);
01834       break;
01835     case cLong:   // Long values are in r3:r4
01836       BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
01837       BuildMI(BB, PPC::OR, 2, Ret.Reg+1).addReg(PPC::R4).addReg(PPC::R4);
01838       break;
01839     default: assert(0 && "Unknown class!");
01840     }
01841   }
01842 }
01843 
01844 
01845 /// visitCallInst - Push args on stack and do a procedure call instruction.
01846 void PPC32ISel::visitCallInst(CallInst &CI) {
01847   MachineInstr *TheCall;
01848   Function *F = CI.getCalledFunction();
01849   if (F) {
01850     // Is it an intrinsic function call?
01851     if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
01852       visitIntrinsicCall(ID, CI);   // Special intrinsics are not handled here
01853       return;
01854     }
01855     // Emit a CALL instruction with PC-relative displacement.
01856     TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
01857   } else {  // Emit an indirect call through the CTR
01858     unsigned Reg = getReg(CI.getCalledValue());
01859     BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Reg).addReg(Reg);
01860     BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
01861     TheCall = BuildMI(PPC::CALLindirect, 2).addZImm(20).addZImm(0)
01862       .addReg(PPC::R12);
01863   }
01864 
01865   std::vector<ValueRecord> Args;
01866   for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
01867     Args.push_back(ValueRecord(CI.getOperand(i)));
01868 
01869   unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
01870   bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
01871   doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
01872 }         
01873 
01874 
01875 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
01876 ///
01877 static Value *dyncastIsNan(Value *V) {
01878   if (CallInst *CI = dyn_cast<CallInst>(V))
01879     if (Function *F = CI->getCalledFunction())
01880       if (F->getIntrinsicID() == Intrinsic::isunordered)
01881         return CI->getOperand(1);
01882   return 0;
01883 }
01884 
01885 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
01886 /// or's whos operands are all calls to the isnan predicate.
01887 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
01888   assert(dyncastIsNan(V) && "The value isn't an isnan call!");
01889 
01890   // Check all uses, which will be or's of isnans if this predicate is true.
01891   for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
01892     Instruction *I = cast<Instruction>(*UI);
01893     if (I->getOpcode() != Instruction::Or) return false;
01894     if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
01895     if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
01896   }
01897 
01898   return true;
01899 }
01900 
01901 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
01902 /// function, lowering any calls to unknown intrinsic functions into the
01903 /// equivalent LLVM code.
01904 ///
01905 void PPC32ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
01906   for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
01907     for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
01908       if (CallInst *CI = dyn_cast<CallInst>(I++))
01909         if (Function *F = CI->getCalledFunction())
01910           switch (F->getIntrinsicID()) {
01911           case Intrinsic::not_intrinsic:
01912           case Intrinsic::vastart:
01913           case Intrinsic::vacopy:
01914           case Intrinsic::vaend:
01915           case Intrinsic::returnaddress:
01916           case Intrinsic::frameaddress:
01917             // FIXME: should lower these ourselves
01918             // case Intrinsic::isunordered:
01919             // case Intrinsic::memcpy: -> doCall().  system memcpy almost
01920             // guaranteed to be faster than anything we generate ourselves
01921             // We directly implement these intrinsics
01922             break;
01923           case Intrinsic::readio: {
01924             // On PPC, memory operations are in-order.  Lower this intrinsic
01925             // into a volatile load.
01926             Instruction *Before = CI->getPrev();
01927             LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
01928             CI->replaceAllUsesWith(LI);
01929             BB->getInstList().erase(CI);
01930             break;
01931           }
01932           case Intrinsic::writeio: {
01933             // On PPC, memory operations are in-order.  Lower this intrinsic
01934             // into a volatile store.
01935             Instruction *Before = CI->getPrev();
01936             StoreInst *SI = new StoreInst(CI->getOperand(1),
01937                                           CI->getOperand(2), true, CI);
01938             CI->replaceAllUsesWith(SI);
01939             BB->getInstList().erase(CI);
01940             break;
01941           }
01942           default:
01943             // All other intrinsic calls we must lower.
01944             Instruction *Before = CI->getPrev();
01945             TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
01946             if (Before) {        // Move iterator to instruction after call
01947               I = Before; ++I;
01948             } else {
01949               I = BB->begin();
01950             }
01951           }
01952 }
01953 
01954 void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
01955   unsigned TmpReg1, TmpReg2, TmpReg3;
01956   switch (ID) {
01957   case Intrinsic::vastart:
01958     // Get the address of the first vararg value...
01959     TmpReg1 = getReg(CI);
01960     addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex, 
01961                       0, false);
01962     return;
01963 
01964   case Intrinsic::vacopy:
01965     TmpReg1 = getReg(CI);
01966     TmpReg2 = getReg(CI.getOperand(1));
01967     BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
01968     return;
01969   case Intrinsic::vaend: return;
01970 
01971   case Intrinsic::returnaddress:
01972     TmpReg1 = getReg(CI);
01973     if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
01974       MachineFrameInfo *MFI = F->getFrameInfo();
01975       unsigned NumBytes = MFI->getStackSize();
01976       
01977       BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
01978         .addReg(PPC::R1);
01979     } else {
01980       // Values other than zero are not implemented yet.
01981       BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
01982     }
01983     return;
01984 
01985   case Intrinsic::frameaddress:
01986     TmpReg1 = getReg(CI);
01987     if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
01988       BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(PPC::R1).addReg(PPC::R1);
01989     } else {
01990       // Values other than zero are not implemented yet.
01991       BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
01992     }
01993     return;
01994     
01995 #if 0
01996     // This may be useful for supporting isunordered
01997   case Intrinsic::isnan:
01998     // If this is only used by 'isunordered' style comparisons, don't emit it.
01999     if (isOnlyUsedByUnorderedComparisons(&CI)) return;
02000     TmpReg1 = getReg(CI.getOperand(1));
02001     emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
02002     TmpReg2 = makeAnotherReg(Type::IntTy);
02003     BuildMI(BB, PPC::MFCR, TmpReg2);
02004     TmpReg3 = getReg(CI);
02005     BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
02006     return;
02007 #endif
02008     
02009   default: assert(0 && "Error: unknown intrinsics should have been lowered!");
02010   }
02011 }
02012 
02013 /// visitSimpleBinary - Implement simple binary operators for integral types...
02014 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
02015 /// Xor.
02016 ///
02017 void PPC32ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
02018   if (std::find(SkipList.begin(), SkipList.end(), &B) != SkipList.end())
02019     return;
02020 
02021   unsigned DestReg = getReg(B);
02022   MachineBasicBlock::iterator MI = BB->end();
02023   RlwimiRec RR = InsertMap[&B];
02024   if (RR.Target != 0) {
02025     unsigned TargetReg = getReg(RR.Target, BB, MI);
02026     unsigned InsertReg = getReg(RR.Insert, BB, MI);
02027     BuildMI(*BB, MI, PPC::RLWIMI, 5, DestReg).addReg(TargetReg)
02028       .addReg(InsertReg).addImm(RR.Shift).addImm(RR.MB).addImm(RR.ME);
02029     return;
02030   }
02031     
02032   unsigned Class = getClassB(B.getType());
02033   Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
02034   emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
02035 }
02036 
02037 /// emitBinaryFPOperation - This method handles emission of floating point
02038 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
02039 void PPC32ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
02040                                       MachineBasicBlock::iterator IP,
02041                                       Value *Op0, Value *Op1,
02042                                       unsigned OperatorClass, unsigned DestReg){
02043 
02044   static const unsigned OpcodeTab[][4] = {
02045     { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS },  // Float
02046     { PPC::FADD,  PPC::FSUB,  PPC::FMUL,  PPC::FDIV },   // Double
02047   };
02048 
02049   // Special case: R1 = op <const fp>, R2
02050   if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
02051     if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
02052       // -0.0 - X === -X
02053       unsigned op1Reg = getReg(Op1, BB, IP);
02054       BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
02055       return;
02056     }
02057 
02058   unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass];
02059   unsigned Op0r = getReg(Op0, BB, IP);
02060   unsigned Op1r = getReg(Op1, BB, IP);
02061   BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
02062 }
02063 
02064 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N.  It
02065 // returns zero when the input is not exactly a power of two.
02066 static unsigned ExactLog2(unsigned Val) {
02067   if (Val == 0 || (Val & (Val-1))) return 0;
02068   unsigned Count = 0;
02069   while (Val != 1) {
02070     Val >>= 1;
02071     ++Count;
02072   }
02073   return Count;
02074 }
02075 
02076 // isRunOfOnes - returns true if Val consists of one contiguous run of 1's with
02077 // any number of 0's on either side.  the 1's are allowed to wrap from LSB to
02078 // MSB.  so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.  0x0F0F0000 is
02079 // not, since all 1's are not contiguous.
02080 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
02081   bool isRun = true;
02082   MB = 0; 
02083   ME = 0;
02084 
02085   // look for first set bit
02086   int i = 0;
02087   for (; i < 32; i++) {
02088     if ((Val & (1 << (31 - i))) != 0) {
02089       MB = i;
02090       ME = i;
02091       break;
02092     }
02093   }
02094   
02095   // look for last set bit
02096   for (; i < 32; i++) {
02097     if ((Val & (1 << (31 - i))) == 0)
02098       break;
02099     ME = i;
02100   }
02101 
02102   // look for next set bit
02103   for (; i < 32; i++) {
02104     if ((Val & (1 << (31 - i))) != 0)
02105       break;
02106   }
02107   
02108   // if we exhausted all the bits, we found a match at this point for 0*1*0*
02109   if (i == 32)
02110     return true;
02111 
02112   // since we just encountered more 1's, if it doesn't wrap around to the
02113   // most significant bit of the word, then we did not find a match to 1*0*1* so
02114   // exit.
02115   if (MB != 0)
02116     return false;
02117 
02118   // look for last set bit
02119   for (MB = i; i < 32; i++) {
02120     if ((Val & (1 << (31 - i))) == 0)
02121       break;
02122   }
02123   
02124   // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
02125   // the value is not a run of ones.
02126   if (i == 32)
02127     return true;
02128   return false;
02129 }
02130 
02131 /// isInsertAndHalf - Helper function for emitBitfieldInsert.  Returns true if
02132 /// OpUser has one use, is used by an or instruction, and is itself an and whose
02133 /// second operand is a constant int.  Optionally, set OrI to the Or instruction
02134 /// that is the sole user of OpUser, and Op1User to the other operand of the Or
02135 /// instruction.
02136 static bool isInsertAndHalf(User *OpUser, Instruction **Op1User, 
02137                             Instruction **OrI, unsigned &Mask) {
02138   // If this instruction doesn't have one use, then return false.
02139   if (!OpUser->hasOneUse())
02140     return false;
02141   
02142   Mask = 0xFFFFFFFF;
02143   if (BinaryOperator *BO = dyn_cast<BinaryOperator>(OpUser))
02144     if (BO->getOpcode() == Instruction::And) {
02145       Value *AndUse = *(OpUser->use_begin());
02146       if (BinaryOperator *Or = dyn_cast<BinaryOperator>(AndUse)) {
02147         if (Or->getOpcode() == Instruction::Or) {
02148           if (ConstantInt *CI = dyn_cast<ConstantInt>(OpUser->getOperand(1))) {
02149             if (OrI) *OrI = Or;
02150             if (Op1User) {
02151               if (Or->getOperand(0) == OpUser)
02152                 *Op1User = dyn_cast<Instruction>(Or->getOperand(1));
02153               else
02154                 *Op1User = dyn_cast<Instruction>(Or->getOperand(0));
02155             }
02156             Mask &= CI->getRawValue();
02157             return true;
02158           }
02159         }
02160       }
02161     }
02162   return false;
02163 }
02164 
02165 /// isInsertShiftHalf - Helper function for emitBitfieldInsert.  Returns true if
02166 /// OpUser has one use, is used by an or instruction, and is itself a shift
02167 /// instruction that is either used directly by the or instruction, or is used
02168 /// by an and instruction whose second operand is a constant int, and which is
02169 /// used by the or instruction.
02170 static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User, 
02171                               Instruction **OrI, Instruction **OptAndI, 
02172                               unsigned &Shift, unsigned &Mask) {
02173   // If this instruction doesn't have one use, then return false.
02174   if (!OpUser->hasOneUse())
02175     return false;
02176   
02177   Mask = 0xFFFFFFFF;
02178   if (ShiftInst *SI = dyn_cast<ShiftInst>(OpUser)) {
02179     if (ConstantInt *CI = dyn_cast<ConstantInt>(SI->getOperand(1))) {
02180       Shift = CI->getRawValue();
02181       if (SI->getOpcode() == Instruction::Shl)
02182         Mask <<= Shift;
02183       else if (!SI->getOperand(0)->getType()->isSigned()) {
02184         Mask >>= Shift;
02185         Shift = 32 - Shift;
02186       }
02187 
02188       // Now check to see if the shift instruction is used by an or.
02189       Value *ShiftUse = *(OpUser->use_begin());
02190       Value *OptAndICopy = 0;
02191       if (BinaryOperator *BO = dyn_cast<BinaryOperator>(ShiftUse)) {
02192         if (BO->getOpcode() == Instruction::And && BO->hasOneUse()) {
02193           if (ConstantInt *ACI = dyn_cast<ConstantInt>(BO->getOperand(1))) {
02194             if (OptAndI) *OptAndI = BO;
02195             OptAndICopy = BO;
02196             Mask &= ACI->getRawValue();
02197             BO = dyn_cast<BinaryOperator>(*(BO->use_begin()));
02198           }
02199         }
02200         if (BO && BO->getOpcode() == Instruction::Or) {
02201           if (OrI) *OrI = BO;
02202           if (Op1User) {
02203             if (BO->getOperand(0) == OpUser || BO->getOperand(0) == OptAndICopy)
02204               *Op1User = dyn_cast<Instruction>(BO->getOperand(1));
02205             else
02206               *Op1User = dyn_cast<Instruction>(BO->getOperand(0));
02207           }
02208           return true;
02209         }
02210       }
02211     }
02212   }
02213   return false;
02214 }
02215 
02216 /// emitBitfieldInsert - turn a shift used only by an and with immediate into 
02217 /// the rotate left word immediate then mask insert (rlwimi) instruction.
02218 /// Patterns matched:
02219 /// 1. or shl, and   5. or (shl-and), and   9. or and, and
02220 /// 2. or and, shl   6. or and, (shl-and)
02221 /// 3. or shr, and   7. or (shr-and), and
02222 /// 4. or and, shr   8. or and, (shr-and)
02223 bool PPC32ISel::emitBitfieldInsert(User *OpUser, unsigned DestReg) {
02224   // Instructions to skip if we match any of the patterns
02225   Instruction *Op0User, *Op1User = 0, *OptAndI = 0, *OrI = 0;
02226   unsigned TgtMask, InsMask, Amount = 0;
02227   bool matched = false;
02228 
02229   // We require OpUser to be an instruction to continue
02230   Op0User = dyn_cast<Instruction>(OpUser);
02231   if (0 == Op0User)
02232     return false;
02233 
02234   // Look for cases 2, 4, 6, 8, and 9
02235   if (isInsertAndHalf(Op0User, &Op1User, &OrI, TgtMask))
02236     if (Op1User)
02237       if (isInsertAndHalf(Op1User, 0, 0, InsMask))
02238         matched = true;
02239       else if (isInsertShiftHalf(Op1User, 0, 0, &OptAndI, Amount, InsMask))
02240         matched = true;
02241   
02242   // Look for cases 1, 3, 5, and 7.  Force the shift argument to be the one
02243   // inserted into the target, since rlwimi can only rotate the value inserted,
02244   // not the value being inserted into.
02245   if (matched == false)
02246     if (isInsertShiftHalf(Op0User, &Op1User, &OrI, &OptAndI, Amount, InsMask))
02247       if (Op1User && isInsertAndHalf(Op1User, 0, 0, TgtMask)) {
02248         std::swap(Op0User, Op1User);
02249         matched = true;
02250       }
02251   
02252   // We didn't succeed in matching one of the patterns, so return false
02253   if (matched == false)
02254     return false;
02255   
02256   // If the masks xor to -1, and the insert mask is a run of ones, then we have
02257   // succeeded in matching one of the cases for generating rlwimi.  Update the
02258   // skip lists and users of the Instruction::Or.
02259   unsigned MB, ME;
02260   if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && isRunOfOnes(InsMask, MB, ME)) {
02261     SkipList.push_back(Op0User);
02262     SkipList.push_back(Op1User);
02263     SkipList.push_back(OptAndI);
02264     InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0), 
02265                                Amount, MB, ME);
02266     return true;
02267   }
02268   return false;
02269 }
02270 
02271 /// emitBitfieldExtract - turn a shift used only by an and with immediate into the
02272 /// rotate left word immediate then and with mask (rlwinm) instruction.
02273 bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB, 
02274                                     MachineBasicBlock::iterator IP,
02275                                     User *OpUser, unsigned DestReg) {
02276   return false;
02277   /*
02278   // Instructions to skip if we match any of the patterns
02279   Instruction *Op0User, *Op1User = 0;
02280   unsigned ShiftMask, AndMask, Amount = 0;
02281   bool matched = false;
02282 
02283   // We require OpUser to be an instruction to continue
02284   Op0User = dyn_cast<Instruction>(OpUser);
02285   if (0 == Op0User)
02286     return false;
02287 
02288   if (isExtractShiftHalf)
02289     if (isExtractAndHalf)
02290       matched = true;
02291   
02292   if (matched == false && isExtractAndHalf)
02293     if (isExtractShiftHalf)
02294     matched = true;
02295   
02296   if (matched == false)
02297     return false;
02298 
02299   if (isRunOfOnes(Imm, MB, ME)) {
02300     unsigned SrcReg = getReg(Op, MBB, IP);
02301     BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(Rotate)
02302       .addImm(MB).addImm(ME);
02303     Op1User->replaceAllUsesWith(Op0User);
02304     SkipList.push_back(BO);
02305     return true;
02306   }
02307   */
02308 }
02309 
02310 /// emitBinaryConstOperation - Implement simple binary operators for integral
02311 /// types with a constant operand.  Opcode is one of: 0 for Add, 1 for Sub, 
02312 /// 2 for And, 3 for Or, 4 for Xor, and 5 for Subtract-From.
02313 ///
02314 void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB, 
02315                                          MachineBasicBlock::iterator IP,
02316                                          unsigned Op0Reg, ConstantInt *Op1, 
02317                                          unsigned Opcode, unsigned DestReg) {
02318   static const unsigned OpTab[] = {
02319     PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR, PPC::SUBF
02320   };
02321   static const unsigned ImmOpTab[2][6] = {
02322     {  PPC::ADDI,  PPC::ADDI,  PPC::ANDIo,  PPC::ORI,  PPC::XORI, PPC::SUBFIC },
02323     { PPC::ADDIS, PPC::ADDIS, PPC::ANDISo, PPC::ORIS, PPC::XORIS, PPC::SUBFIC }
02324   };
02325 
02326   // Handle subtract now by inverting the constant value: X-4 == X+(-4)
02327   if (Opcode == 1) {
02328     Op1 = cast<ConstantInt>(ConstantExpr::getNeg(Op1));
02329     Opcode = 0;
02330   }
02331   
02332   // xor X, -1 -> not X
02333   if (Opcode == 4 && Op1->isAllOnesValue()) {
02334     BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
02335     return;
02336   }
02337   
02338   if (Opcode == 2 && !Op1->isNullValue()) {
02339     unsigned MB, ME, mask = Op1->getRawValue();
02340     if (isRunOfOnes(mask, MB, ME)) {
02341       BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(0)
02342         .addImm(MB).addImm(ME);
02343       return;
02344     }
02345   }
02346 
02347   // PowerPC 16 bit signed immediates are sign extended before use by the
02348   // instruction.  Therefore, we can only split up an add of a reg with a 32 bit
02349   // immediate into addis and addi if the sign bit of the low 16 bits is cleared
02350   // so that for register A, const imm X, we don't end up with
02351   // A + XXXX0000 + FFFFXXXX.
02352   bool WontSignExtend = (0 == (Op1->getRawValue() & 0x8000));
02353 
02354   // For Add, Sub, and SubF the instruction takes a signed immediate.  For And,
02355   // Or, and Xor, the instruction takes an unsigned immediate.  There is no 
02356   // shifted immediate form of SubF so disallow its opcode for those constants.
02357   if (canUseAsImmediateForOpcode(Op1, Opcode, false)) {
02358     if (Opcode < 2 || Opcode == 5)
02359       BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(Op0Reg)
02360         .addSImm(Op1->getRawValue());
02361     else
02362       BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(Op0Reg)
02363         .addZImm(Op1->getRawValue());
02364   } else if (canUseAsImmediateForOpcode(Op1, Opcode, true) && (Opcode < 5)) {
02365     if (Opcode < 2)
02366       BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, DestReg).addReg(Op0Reg)
02367         .addSImm(Op1->getRawValue() >> 16);
02368     else
02369       BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, DestReg).addReg(Op0Reg)
02370         .addZImm(Op1->getRawValue() >> 16);
02371   } else if ((Opcode < 2 && WontSignExtend) || Opcode == 3 || Opcode == 4) {
02372     unsigned TmpReg = makeAnotherReg(Op1->getType());
02373     if (Opcode < 2) {
02374       BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, TmpReg).addReg(Op0Reg)
02375         .addSImm(Op1->getRawValue() >> 16);
02376       BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(TmpReg)
02377         .addSImm(Op1->getRawValue());
02378     } else {
02379       BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, TmpReg).addReg(Op0Reg)
02380         .addZImm(Op1->getRawValue() >> 16);
02381       BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(TmpReg)
02382         .addZImm(Op1->getRawValue());
02383     }
02384   } else {
02385     unsigned Op1Reg = getReg(Op1, MBB, IP);
02386     BuildMI(*MBB, IP, OpTab[Opcode], 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
02387   }
02388 }
02389 
02390 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
02391 /// types...  OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
02392 /// Or, 4 for Xor.
02393 ///
02394 void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
02395                                           MachineBasicBlock::iterator IP,
02396                                           BinaryOperator *BO, 
02397                                           Value *Op0, Value *Op1,
02398                                           unsigned OperatorClass, 
02399                                           unsigned DestReg) {
02400   // Arithmetic and Bitwise operators
02401   static const unsigned OpcodeTab[] = {
02402     PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
02403   };
02404   static const unsigned LongOpTab[2][5] = {
02405     { PPC::ADDC,  PPC::SUBC, PPC::AND, PPC::OR, PPC::XOR },
02406     { PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
02407   };
02408   
02409   unsigned Class = getClassB(Op0->getType());
02410 
02411   if (Class == cFP32 || Class == cFP64) {
02412     assert(OperatorClass < 2 && "No logical ops for FP!");
02413     emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
02414     return;
02415   }
02416 
02417   if (Op0->getType() == Type::BoolTy) {
02418     if (OperatorClass == 3)
02419       // If this is an or of two isnan's, emit an FP comparison directly instead
02420       // of or'ing two isnan's together.
02421       if (Value *LHS = dyncastIsNan(Op0))
02422         if (Value *RHS = dyncastIsNan(Op1)) {
02423           unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
02424           unsigned TmpReg = makeAnotherReg(Type::IntTy);
02425           emitUCOM(MBB, IP, Op0Reg, Op1Reg);
02426           BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
02427           BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
02428             .addImm(31).addImm(31);
02429           return;
02430         }
02431   }
02432 
02433   // Special case: op <const int>, Reg
02434   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
02435     if (Class != cLong) {
02436       unsigned Opcode = (OperatorClass == 1) ? 5 : OperatorClass;
02437       unsigned Op1r = getReg(Op1, MBB, IP);
02438       emitBinaryConstOperation(MBB, IP, Op1r, CI, Opcode, DestReg);
02439       return;
02440     }
02441   // Special case: op Reg, <const int>
02442   if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1))
02443     if (Class != cLong) {
02444       if (emitBitfieldInsert(BO, DestReg))
02445         return;
02446       
02447       unsigned Op0r = getReg(Op0, MBB, IP);
02448       emitBinaryConstOperation(MBB, IP, Op0r, CI, OperatorClass, DestReg);
02449       return;
02450     }
02451 
02452   // We couldn't generate an immediate variant of the op, load both halves into
02453   // registers and emit the appropriate opcode.
02454   unsigned Op0r = getReg(Op0, MBB, IP);
02455   unsigned Op1r = getReg(Op1, MBB, IP);
02456 
02457   if (Class != cLong) {
02458     unsigned Opcode = OpcodeTab[OperatorClass];
02459     BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
02460   } else {
02461     BuildMI(*MBB, IP, LongOpTab[0][OperatorClass], 2, DestReg+1).addReg(Op0r+1)
02462       .addReg(Op1r+1);
02463     BuildMI(*MBB, IP, LongOpTab[1][OperatorClass], 2, DestReg).addReg(Op0r)
02464       .addReg(Op1r);
02465   }
02466   return;
02467 }
02468 
02469 /// doMultiply - Emit appropriate instructions to multiply together the
02470 /// Values Op0 and Op1, and put the result in DestReg.
02471 ///
02472 void PPC32ISel::doMultiply(MachineBasicBlock *MBB,
02473                            MachineBasicBlock::iterator IP,
02474                            unsigned DestReg, Value *Op0, Value *Op1) {
02475   unsigned Class0 = getClass(Op0->getType());
02476   unsigned Class1 = getClass(Op1->getType());
02477   
02478   unsigned Op0r = getReg(Op0, MBB, IP);
02479   unsigned Op1r = getReg(Op1, MBB, IP);
02480   
02481   // 64 x 64 -> 64
02482   if (Class0 == cLong && Class1 == cLong) {
02483     unsigned Tmp1 = makeAnotherReg(Type::IntTy);
02484     unsigned Tmp2 = makeAnotherReg(Type::IntTy);
02485     unsigned Tmp3 = makeAnotherReg(Type::IntTy);
02486     unsigned Tmp4 = makeAnotherReg(Type::IntTy);
02487     BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r+1);
02488     BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
02489     BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Op1r);
02490     BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
02491     BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r+1);
02492     BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
02493     return;
02494   }
02495   
02496   // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
02497   if (Class0 == cLong && Class1 <= cInt) {
02498     unsigned Tmp0 = makeAnotherReg(Type::IntTy);
02499     unsigned Tmp1 = makeAnotherReg(Type::IntTy);
02500     unsigned Tmp2 = makeAnotherReg(Type::IntTy);
02501     unsigned Tmp3 = makeAnotherReg(Type::IntTy);
02502     unsigned Tmp4 = makeAnotherReg(Type::IntTy);
02503     if (Op1->getType()->isSigned())
02504       BuildMI(*MBB, IP, PPC::SRAWI, 2, Tmp0).addReg(Op1r).addImm(31);
02505     else
02506       BuildMI(*MBB, IP, PPC::LI, 2, Tmp0).addSImm(0);
02507     BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r);
02508     BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r);
02509     BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Tmp0);
02510     BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
02511     BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r);
02512     BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
02513     return;
02514   }
02515   
02516   // 32 x 32 -> 32
02517   if (Class0 <= cInt && Class1 <= cInt) {
02518     BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
02519     return;
02520   }
02521   
02522   assert(0 && "doMultiply cannot operate on unknown type!");
02523 }
02524 
02525 /// doMultiplyConst - This method will multiply the value in Op0 by the
02526 /// value of the ContantInt *CI
02527 void PPC32ISel::doMultiplyConst(MachineBasicBlock *MBB,
02528                                 MachineBasicBlock::iterator IP,
02529                                 unsigned DestReg, Value *Op0, ConstantInt *CI) {
02530   unsigned Class = getClass(Op0->getType());
02531 
02532   // Mul op0, 0 ==> 0
02533   if (CI->isNullValue()) {
02534     BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
02535     if (Class == cLong)
02536       BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
02537     return;
02538   }
02539   
02540   // Mul op0, 1 ==> op0
02541   if (CI->equalsInt(1)) {
02542     unsigned Op0r = getReg(Op0, MBB, IP);
02543     BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
02544     if (Class == cLong)
02545       BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
02546     return;
02547   }
02548 
02549   // If the element size is exactly a power of 2, use a shift to get it.
02550   if (unsigned Shift = ExactLog2(CI->getRawValue())) {
02551     ConstantUInt *ShiftCI = ConstantUInt::get(Type::UByteTy, Shift);
02552     emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), 0, DestReg);
02553     return;
02554   }
02555   
02556   // If 32 bits or less and immediate is in right range, emit mul by immediate
02557   if (Class == cByte || Class == cShort || Class == cInt) {
02558     if (canUseAsImmediateForOpcode(CI, 0, false)) {
02559       unsigned Op0r = getReg(Op0, MBB, IP);
02560       unsigned imm = CI->getRawValue() & 0xFFFF;
02561       BuildMI(*MBB, IP, PPC::MULLI, 2, DestReg).addReg(Op0r).addSImm(imm);
02562       return;
02563     }
02564   }
02565   
02566   doMultiply(MBB, IP, DestReg, Op0, CI);
02567 }
02568 
02569 void PPC32ISel::visitMul(BinaryOperator &I) {
02570   unsigned ResultReg = getReg(I);
02571 
02572   Value *Op0 = I.getOperand(0);
02573   Value *Op1 = I.getOperand(1);
02574 
02575   MachineBasicBlock::iterator IP = BB->end();
02576   emitMultiply(BB, IP, Op0, Op1, ResultReg);
02577 }
02578 
02579 void PPC32ISel::emitMultiply(MachineBasicBlock *MBB,
02580                              MachineBasicBlock::iterator IP,
02581                              Value *Op0, Value *Op1, unsigned DestReg) {
02582   TypeClass Class = getClass(Op0->getType());
02583 
02584   switch (Class) {
02585   case cByte:
02586   case cShort:
02587   case cInt:
02588   case cLong:
02589     if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
02590       doMultiplyConst(MBB, IP, DestReg, Op0, CI);
02591     } else {
02592       doMultiply(MBB, IP, DestReg, Op0, Op1);
02593     }
02594     return;
02595   case cFP32:
02596   case cFP64:
02597     emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
02598     return;
02599     break;
02600   }
02601 }
02602 
02603 
02604 /// visitDivRem - Handle division and remainder instructions... these
02605 /// instruction both require the same instructions to be generated, they just
02606 /// select the result from a different register.  Note that both of these
02607 /// instructions work differently for signed and unsigned operands.
02608 ///
02609 void PPC32ISel::visitDivRem(BinaryOperator &I) {
02610   unsigned ResultReg = getReg(I);
02611   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
02612 
02613   MachineBasicBlock::iterator IP = BB->end();
02614   emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
02615                       ResultReg);
02616 }
02617 
02618 void PPC32ISel::emitDivRemOperation(MachineBasicBlock *MBB,
02619                                     MachineBasicBlock::iterator IP,
02620                                     Value *Op0, Value *Op1, bool isDiv,
02621                                     unsigned ResultReg) {
02622   const Type *Ty = Op0->getType();
02623   unsigned Class = getClass(Ty);
02624   switch (Class) {
02625   case cFP32:
02626     if (isDiv) {
02627       // Floating point divide...
02628       emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
02629       return;
02630     } else {
02631       // Floating point remainder via fmodf(float x, float y);
02632       unsigned Op0Reg = getReg(Op0, MBB, IP);
02633       unsigned Op1Reg = getReg(Op1, MBB, IP);
02634       MachineInstr *TheCall =
02635         BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
02636       std::vector<ValueRecord> Args;
02637       Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
02638       Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
02639       doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
02640     }
02641     return;
02642   case cFP64:
02643     if (isDiv) {
02644       // Floating point divide...
02645       emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
02646       return;
02647     } else {               
02648       // Floating point remainder via fmod(double x, double y);
02649       unsigned Op0Reg = getReg(Op0, MBB, IP);
02650       unsigned Op1Reg = getReg(Op1, MBB, IP);
02651       MachineInstr *TheCall =
02652         BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
02653       std::vector<ValueRecord> Args;
02654       Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
02655       Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
02656       doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
02657     }
02658     return;
02659   case cLong: {
02660     static Function* const Funcs[] =
02661       { __moddi3Fn, __divdi3Fn, __umoddi3Fn, __udivdi3Fn };
02662     unsigned Op0Reg = getReg(Op0, MBB, IP);
02663     unsigned Op1Reg = getReg(Op1, MBB, IP);
02664     unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
02665     MachineInstr *TheCall =
02666       BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
02667 
02668     std::vector<ValueRecord> Args;
02669     Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
02670     Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
02671     doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
02672     return;
02673   }
02674   case cByte: case cShort: case cInt:
02675     break;          // Small integrals, handled below...
02676   default: assert(0 && "Unknown class!");
02677   }
02678 
02679   // Special case signed division by power of 2.
02680   if (isDiv)
02681     if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
02682       assert(Class != cLong && "This doesn't handle 64-bit divides!");
02683       int V = CI->getValue();
02684 
02685       if (V == 1) {       // X /s 1 => X
02686         unsigned Op0Reg = getReg(Op0, MBB, IP);
02687         BuildMI(*MBB, IP, PPC::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
02688         return;
02689       }
02690 
02691       if (V == -1) {      // X /s -1 => -X
02692         unsigned Op0Reg = getReg(Op0, MBB, IP);
02693         BuildMI(*MBB, IP, PPC::NEG, 1, ResultReg).addReg(Op0Reg);
02694         return;
02695       }
02696 
02697       unsigned log2V = ExactLog2(V);
02698       if (log2V != 0 && Ty->isSigned()) {
02699         unsigned Op0Reg = getReg(Op0, MBB, IP);
02700         unsigned TmpReg = makeAnotherReg(Op0->getType());
02701         
02702         BuildMI(*MBB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
02703         BuildMI(*MBB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
02704         return;
02705       }
02706     }
02707 
02708   unsigned Op0Reg = getReg(Op0, MBB, IP);
02709 
02710   if (isDiv) {
02711     unsigned Op1Reg = getReg(Op1, MBB, IP);
02712     unsigned Opcode = Ty->isSigned() ? PPC::DIVW : PPC::DIVWU;
02713     BuildMI(*MBB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
02714   } else { // Remainder
02715     // FIXME: don't load the CI part of a CI divide twice
02716     ConstantInt *CI = dyn_cast<ConstantInt>(Op1);
02717     unsigned TmpReg1 = makeAnotherReg(Op0->getType());
02718     unsigned TmpReg2 = makeAnotherReg(Op0->getType());
02719     emitDivRemOperation(MBB, IP, Op0, Op1, true, TmpReg1);
02720     if (CI && canUseAsImmediateForOpcode(CI, 0, false)) {
02721       BuildMI(*MBB, IP, PPC::MULLI, 2, TmpReg2).addReg(TmpReg1)
02722         .addSImm(CI->getRawValue());
02723     } else {
02724       unsigned Op1Reg = getReg(Op1, MBB, IP);
02725       BuildMI(*MBB, IP, PPC::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
02726     }
02727     BuildMI(*MBB, IP, PPC::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
02728   }
02729 }
02730 
02731 
02732 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
02733 /// for constant immediate shift values, and for constant immediate
02734 /// shift values equal to 1. Even the general case is sort of special,
02735 /// because the shift amount has to be in CL, not just any old register.
02736 ///
02737 void PPC32ISel::visitShiftInst(ShiftInst &I) {
02738   if (std::find(SkipList.begin(), SkipList.end(), &I) != SkipList.end())
02739     return;
02740 
02741   MachineBasicBlock::iterator IP = BB->end();
02742   emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
02743                      I.getOpcode() == Instruction::Shl, I.getType(),
02744                      &I, getReg(I));
02745 }
02746 
02747 /// emitShiftOperation - Common code shared between visitShiftInst and
02748 /// constant expression support.
02749 ///
02750 void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
02751                                    MachineBasicBlock::iterator IP,
02752                                    Value *Op, Value *ShiftAmount, 
02753                                    bool isLeftShift, const Type *ResultTy,
02754                                    ShiftInst *SI, unsigned DestReg) {
02755   bool isSigned = ResultTy->isSigned ();
02756   unsigned Class = getClass (ResultTy);
02757   
02758   // Longs, as usual, are handled specially...
02759   if (Class == cLong) {
02760     unsigned SrcReg = getReg (Op, MBB, IP);
02761     // If we have a constant shift, we can generate much more efficient code
02762     // than for a variable shift by using the rlwimi instruction.
02763     if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
02764       unsigned Amount = CUI->getValue();
02765       if (Amount == 0) {
02766         BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
02767         BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1)
02768           .addReg(SrcReg+1).addReg(SrcReg+1);
02769 
02770       } else if (Amount < 32) {
02771         unsigned TempReg = makeAnotherReg(ResultTy);
02772         if (isLeftShift) {
02773           BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg)
02774             .addImm(Amount).addImm(0).addImm(31-Amount);
02775           BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg).addReg(TempReg)
02776             .addReg(SrcReg+1).addImm(Amount).addImm(32-Amount).addImm(31);
02777           BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
02778             .addImm(Amount).addImm(0).addImm(31-Amount);
02779         } else {
02780           BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg+1)
02781             .addImm(32-Amount).addImm(Amount).addImm(31);
02782           BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
02783             .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
02784           BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
02785             .addImm(32-Amount).addImm(Amount).addImm(31);
02786         }
02787       } else {                 // Shifting more than 32 bits
02788         Amount -= 32;
02789         if (isLeftShift) {
02790           if (Amount != 0) {
02791             BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg+1)
02792               .addImm(Amount).addImm(0).addImm(31-Amount);
02793           } else {
02794             BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg+1)
02795               .addReg(SrcReg+1);
02796           }
02797           BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
02798         } else {
02799           if (Amount != 0) {
02800             if (isSigned)
02801               BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg+1).addReg(SrcReg)
02802                 .addImm(Amount);
02803             else
02804               BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg)
02805                 .addImm(32-Amount).addImm(Amount).addImm(31);
02806           } else {
02807             BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
02808               .addReg(SrcReg);
02809           }
02810           BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
02811         }
02812       }
02813     } else {
02814       unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
02815       unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
02816       unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
02817       unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
02818       unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
02819       unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
02820       unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
02821       
02822       if (isLeftShift) {
02823         BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
02824           .addSImm(32);
02825         BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg2).addReg(SrcReg)
02826           .addReg(ShiftAmountReg);
02827         BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg3).addReg(SrcReg+1)
02828           .addReg(TmpReg1);
02829         BuildMI(*MBB, IP, PPC::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
02830         BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
02831           .addSImm(-32);
02832         BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg6).addReg(SrcReg+1)
02833           .addReg(TmpReg5);
02834         BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(TmpReg4)
02835           .addReg(TmpReg6);
02836         BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
02837           .addReg(ShiftAmountReg);
02838       } else {
02839         if (isSigned) { // shift right algebraic 
02840           MachineBasicBlock *TmpMBB =new MachineBasicBlock(BB->getBasicBlock());
02841           MachineBasicBlock *PhiMBB =new MachineBasicBlock(BB->getBasicBlock());
02842           MachineBasicBlock *OldMBB = BB;
02843           ilist<MachineBasicBlock>::iterator It = BB; ++It;
02844           F->getBasicBlockList().insert(It, TmpMBB);
02845           F->getBasicBlockList().insert(It, PhiMBB);
02846           BB->addSuccessor(TmpMBB);
02847           BB->addSuccessor(PhiMBB);
02848 
02849           BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
02850             .addSImm(32);
02851           BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
02852             .addReg(ShiftAmountReg);
02853           BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
02854             .addReg(TmpReg1);
02855           BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
02856             .addReg(TmpReg3);
02857           BuildMI(*MBB, IP, PPC::ADDICo, 2, TmpReg5).addReg(ShiftAmountReg)
02858             .addSImm(-32);
02859           BuildMI(*MBB, IP, PPC::SRAW, 2, TmpReg6).addReg(SrcReg)
02860             .addReg(TmpReg5);
02861           BuildMI(*MBB, IP, PPC::SRAW, 2, DestReg).addReg(SrcReg)
02862             .addReg(ShiftAmountReg);
02863           BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
02864  
02865           // OrMBB:
02866           //   Select correct least significant half if the shift amount > 32
02867           BB = TmpMBB;
02868           unsigned OrReg = makeAnotherReg(Type::IntTy);
02869           BuildMI(BB, PPC::OR, 2, OrReg).addReg(TmpReg6).addReg(TmpReg6);
02870           TmpMBB->addSuccessor(PhiMBB);
02871           
02872           BB = PhiMBB;
02873           BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(TmpReg4).addMBB(OldMBB)
02874             .addReg(OrReg).addMBB(TmpMBB);
02875         } else { // shift right logical
02876           BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
02877             .addSImm(32);
02878           BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
02879             .addReg(ShiftAmountReg);
02880           BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
02881             .addReg(TmpReg1);
02882           BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
02883             .addReg(TmpReg3);
02884           BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
02885             .addSImm(-32);
02886           BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg6).addReg(SrcReg)
02887             .addReg(TmpReg5);
02888           BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(TmpReg4)
02889             .addReg(TmpReg6);
02890           BuildMI(*MBB, IP, PPC::SRW, 2, DestReg).addReg(SrcReg)
02891             .addReg(ShiftAmountReg);
02892         }
02893       }
02894     }
02895     return;
02896   }
02897 
02898   if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
02899     // The shift amount is constant, guaranteed to be a ubyte. Get its value.
02900     assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
02901     unsigned Amount = CUI->getValue();
02902     
02903     // If this is a shift with one use, and that use is an And instruction,
02904     // then attempt to emit a bitfield operation.
02905     if (SI && emitBitfieldInsert(SI, DestReg))
02906       return;
02907     
02908     unsigned SrcReg = getReg (Op, MBB, IP);
02909     if (Amount == 0) {
02910       BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
02911     } else if (isLeftShift) {
02912       BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
02913         .addImm(Amount).addImm(0).addImm(31-Amount);
02914     } else {
02915       if (isSigned) {
02916         BuildMI(*MBB, IP, PPC::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
02917       } else {
02918         BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
02919           .addImm(32-Amount).addImm(Amount).addImm(31);
02920       }
02921     }
02922   } else {                  // The shift amount is non-constant.
02923     unsigned SrcReg = getReg (Op, MBB, IP);
02924     unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
02925 
02926     if (isLeftShift) {
02927       BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
02928         .addReg(ShiftAmountReg);
02929     } else {
02930       BuildMI(*MBB, IP, isSigned ? PPC::SRAW : PPC::SRW, 2, DestReg)
02931         .addReg(SrcReg).addReg(ShiftAmountReg);
02932     }
02933   }
02934 }
02935 
02936 /// LoadNeedsSignExtend - On PowerPC, there is no load byte with sign extend.
02937 /// Therefore, if this is a byte load and the destination type is signed, we
02938 /// would normally need to also emit a sign extend instruction after the load.
02939 /// However, store instructions don't care whether a signed type was sign
02940 /// extended across a whole register.  Also, a SetCC instruction will emit its
02941 /// own sign extension to force the value into the appropriate range, so we
02942 /// need not emit it here.  Ideally, this kind of thing wouldn't be necessary
02943 /// once LLVM's type system is improved.
02944 static bool LoadNeedsSignExtend(LoadInst &LI) {
02945   if (cByte == getClassB(LI.getType()) && LI.getType()->isSigned()) {
02946     bool AllUsesAreStoresOrSetCC = true;
02947     for (Value::use_iterator I = LI.use_begin(), E = LI.use_end(); I != E; ++I){
02948       if (isa<SetCondInst>(*I))
02949         continue;
02950       if (StoreInst *SI = dyn_cast<StoreInst>(*I))
02951         if (cByte == getClassB(SI->getOperand(0)->getType()))
02952         continue;
02953       AllUsesAreStoresOrSetCC = false;
02954       break;
02955     }
02956     if (!AllUsesAreStoresOrSetCC)
02957       return true;
02958   }
02959   return false;
02960 }
02961 
02962 /// visitLoadInst - Implement LLVM load instructions.  Pretty straightforward
02963 /// mapping of LLVM classes to PPC load instructions, with the exception of
02964 /// signed byte loads, which need a sign extension following them.
02965 ///
02966 void PPC32ISel::visitLoadInst(LoadInst &I) {
02967   // Immediate opcodes, for reg+imm addressing
02968   static const unsigned ImmOpcodes[] = { 
02969     PPC::LBZ, PPC::LHZ, PPC::LWZ, 
02970     PPC::LFS, PPC::LFD, PPC::LWZ
02971   };
02972   // Indexed opcodes, for reg+reg addressing
02973   static const unsigned IdxOpcodes[] = {
02974     PPC::LBZX, PPC::LHZX, PPC::LWZX,
02975     PPC::LFSX, PPC::LFDX, PPC::LWZX
02976   };
02977 
02978   unsigned Class     = getClassB(I.getType());
02979   unsigned ImmOpcode = ImmOpcodes[Class];
02980   unsigned IdxOpcode = IdxOpcodes[Class];
02981   unsigned DestReg   = getReg(I);
02982   Value *SourceAddr  = I.getOperand(0);
02983   
02984   if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
02985   if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
02986 
02987   // If this is a fixed size alloca, emit a load directly from the stack slot
02988   // corresponding to it.
02989   if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
02990     unsigned FI = getFixedSizedAllocaFI(AI);
02991     if (Class == cLong) {
02992       addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
02993       addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg+1), FI, 4);
02994     } else if (LoadNeedsSignExtend(I)) {
02995       unsigned TmpReg = makeAnotherReg(I.getType());
02996       addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
02997       BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
02998     } else {
02999       addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
03000     }
03001     return;
03002   }
03003   
03004   // If the offset fits in 16 bits, we can emit a reg+imm load, otherwise, we
03005   // use the index from the FoldedGEP struct and use reg+reg addressing.
03006   if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
03007 
03008     // Generate the code for the GEP and get the components of the folded GEP
03009     emitGEPOperation(BB, BB->end(), GEPI, true);
03010     unsigned baseReg = GEPMap[GEPI].base;
03011     unsigned indexReg = GEPMap[GEPI].index;
03012     ConstantSInt *offset = GEPMap[GEPI].offset;
03013 
03014     if (Class != cLong) {
03015       unsigned TmpReg = LoadNeedsSignExtend(I) ? makeAnotherReg(I.getType())
03016                                                : DestReg;
03017       if (indexReg == 0)
03018         BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
03019           .addReg(baseReg);
03020       else
03021         BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
03022       if (LoadNeedsSignExtend(I))
03023         BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
03024     } else {
03025       indexReg = (indexReg != 0) ? indexReg : getReg(offset);
03026       unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
03027       BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
03028       BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
03029       BuildMI(BB, IdxOpcode, 2, DestReg+1).addReg(indexPlus4).addReg(baseReg);
03030     }
03031     return;
03032   }
03033   
03034   // The fallback case, where the load was from a source that could not be
03035   // folded into the load instruction. 
03036   unsigned SrcAddrReg = getReg(SourceAddr);
03037     
03038   if (Class == cLong) {
03039     BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
03040     BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
03041   } else if (LoadNeedsSignExtend(I)) {
03042     unsigned TmpReg = makeAnotherReg(I.getType());
03043     BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
03044     BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
03045   } else {
03046     BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
03047   }
03048 }
03049 
03050 /// visitStoreInst - Implement LLVM store instructions
03051 ///
03052 void PPC32ISel::visitStoreInst(StoreInst &I) {
03053   // Immediate opcodes, for reg+imm addressing
03054   static const unsigned ImmOpcodes[] = {
03055     PPC::STB, PPC::STH, PPC::STW, 
03056     PPC::STFS, PPC::STFD, PPC::STW
03057   };
03058   // Indexed opcodes, for reg+reg addressing
03059   static const unsigned IdxOpcodes[] = {
03060     PPC::STBX, PPC::STHX, PPC::STWX, 
03061     PPC::STFSX, PPC::STFDX, PPC::STWX
03062   };
03063   
03064   Value *SourceAddr  = I.getOperand(1);
03065   const Type *ValTy  = I.getOperand(0)->getType();
03066   unsigned Class     = getClassB(ValTy);
03067   unsigned ImmOpcode = ImmOpcodes[Class];
03068   unsigned IdxOpcode = IdxOpcodes[Class];
03069   unsigned ValReg    = getReg(I.getOperand(0));
03070 
03071   // If this is a fixed size alloca, emit a store directly to the stack slot
03072   // corresponding to it.
03073   if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
03074     unsigned FI = getFixedSizedAllocaFI(AI);
03075     addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg), FI);
03076     if (Class == cLong)
03077       addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1), FI, 4);
03078     return;
03079   }
03080   
03081   // If the offset fits in 16 bits, we can emit a reg+imm store, otherwise, we
03082   // use the index from the FoldedGEP struct and use reg+reg addressing.
03083   if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
03084     // Generate the code for the GEP and get the components of the folded GEP
03085     emitGEPOperation(BB, BB->end(), GEPI, true);
03086     unsigned baseReg = GEPMap[GEPI].base;
03087     unsigned indexReg = GEPMap[GEPI].index;
03088     ConstantSInt *offset = GEPMap[GEPI].offset;
03089     
03090     if (Class != cLong) {
03091       if (indexReg == 0)
03092         BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
03093           .addReg(baseReg);
03094       else
03095         BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg)
03096           .addReg(baseReg);
03097     } else {
03098       indexReg = (indexReg != 0) ? indexReg : getReg(offset);
03099       unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
03100       BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
03101       BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
03102       BuildMI(BB, IdxOpcode, 3).addReg(ValReg+1).addReg(indexPlus4)
03103         .addReg(baseReg);
03104     }
03105     return;
03106   }
03107   
03108   // If the store address wasn't the only use of a GEP, we fall back to the
03109   // standard path: store the ValReg at the value in AddressReg.
03110   unsigned AddressReg  = getReg(I.getOperand(1));
03111   if (Class == cLong) {
03112     BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
03113     BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1).addSImm(4).addReg(AddressReg);
03114     return;
03115   }
03116   BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
03117 }
03118 
03119 
03120 /// visitCastInst - Here we have various kinds of copying with or without sign
03121 /// extension going on.
03122 ///
03123 void PPC32ISel::visitCastInst(CastInst &CI) {
03124   Value *Op = CI.getOperand(0);
03125 
03126   unsigned SrcClass = getClassB(Op->getType());
03127   unsigned DestClass = getClassB(CI.getType());
03128 
03129   // Noop casts are not emitted: getReg will return the source operand as the
03130   // register to use for any uses of the noop cast.
03131   if (DestClass == SrcClass) return;
03132 
03133   // If this is a cast from a 32-bit integer to a Long type, and the only uses
03134   // of the cast are GEP instructions, then the cast does not need to be
03135   // generated explicitly, it will be folded into the GEP.
03136   if (DestClass == cLong && SrcClass == cInt) {
03137     bool AllUsesAreGEPs = true;
03138     for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
03139       if (!isa<GetElementPtrInst>(*I)) {
03140         AllUsesAreGEPs = false;
03141         break;
03142       }        
03143     if (AllUsesAreGEPs) return;
03144   }
03145   
03146   unsigned DestReg = getReg(CI);
03147   MachineBasicBlock::iterator MI = BB->end();
03148 
03149   // If this is a cast from an integer type to a ubyte, with one use where the
03150   // use is the shift amount argument of a shift instruction, just emit a move
03151   // instead (since the shift instruction will only look at the low 5 bits
03152   // regardless of how it is sign extended)
03153   if (CI.getType() == Type::UByteTy && SrcClass <= cInt && CI.hasOneUse()) {
03154     ShiftInst *SI = dyn_cast<ShiftInst>(*(CI.use_begin()));
03155     if (SI && (SI->getOperand(1) == &CI)) {
03156       unsigned SrcReg = getReg(Op, BB, MI);
03157       BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
03158       return; 
03159     }
03160   }
03161 
03162   // If this is a cast from an byte, short, or int to an integer type of equal
03163   // or lesser width, and all uses of the cast are store instructions then dont
03164   // emit them, as the store instruction will implicitly not store the zero or
03165   // sign extended bytes.
03166   if (SrcClass <= cInt && SrcClass >= DestClass) {
03167     bool AllUsesAreStores = true;
03168     for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
03169       if (!isa<StoreInst>(*I)) {
03170         AllUsesAreStores = false;
03171         break;
03172       }        
03173     // Turn this cast directly into a move instruction, which the register
03174     // allocator will deal with.
03175     if (AllUsesAreStores) { 
03176       unsigned SrcReg = getReg(Op, BB, MI);
03177       BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
03178       return; 
03179     }
03180   }
03181   emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
03182 }
03183 
03184 /// emitCastOperation - Common code shared between visitCastInst and constant
03185 /// expression cast support.
03186 ///
03187 void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
03188                                   MachineBasicBlock::iterator IP,
03189                                   Value *Src, const Type *DestTy,
03190                                   unsigned DestReg) {
03191   const Type *SrcTy = Src->getType();
03192   unsigned SrcClass = getClassB(SrcTy);
03193   unsigned DestClass = getClassB(DestTy);
03194   unsigned SrcReg = getReg(Src, MBB, IP);
03195 
03196   // Implement casts from bool to integer types as a move operation
03197   if (SrcTy == Type::BoolTy) {
03198     switch (DestClass) {
03199     case cByte:
03200     case cShort:
03201     case cInt:
03202       BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
03203       return;
03204     case cLong:
03205       BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addImm(0);
03206       BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg).addReg(SrcReg);
03207       return;
03208     default:
03209       break;
03210     }
03211   }
03212 
03213   // Implement casts to bool by using compare on the operand followed by set if
03214   // not zero on the result.
03215   if (DestTy == Type::BoolTy) {
03216     switch (SrcClass) {
03217     case cByte:
03218     case cShort:
03219     case cInt: {
03220       unsigned TmpReg = makeAnotherReg(Type::IntTy);
03221       BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg).addSImm(-1);
03222       BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
03223       break;
03224     }
03225     case cLong: {
03226       unsigned TmpReg = makeAnotherReg(Type::IntTy);
03227       unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
03228       BuildMI(*MBB, IP, PPC::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
03229       BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg2).addSImm(-1);
03230       BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg)
03231         .addReg(SrcReg2);
03232       break;
03233     }
03234     case cFP32:
03235     case cFP64:
03236       unsigned TmpReg = makeAnotherReg(Type::IntTy);
03237       unsigned ConstZero = getReg(ConstantFP::get(Type::DoubleTy, 0.0), BB, IP);
03238       BuildMI(*MBB, IP, PPC::FCMPU, PPC::CR7).addReg(SrcReg).addReg(ConstZero);
03239       BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
03240       BuildMI(*MBB, IP, PPC::RLWINM, DestReg).addReg(TmpReg).addImm(31)
03241         .addImm(31).addImm(31);
03242     }
03243     return;
03244   }
03245 
03246   // Handle cast of Float -> Double
03247   if (SrcClass == cFP32 && DestClass == cFP64) {
03248     BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
03249     return;
03250   }
03251   
03252   // Handle cast of Double -> Float
03253   if (SrcClass == cFP64 && DestClass == cFP32) {
03254     BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
03255     return;
03256   }
03257   
03258   // Handle casts from integer to floating point now...
03259   if (DestClass == cFP32 || DestClass == cFP64) {
03260 
03261     // Emit a library call for long to float conversion
03262     if (SrcClass == cLong) {
03263       Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
03264       if (SrcTy->isSigned()) {
03265         std::vector<ValueRecord> Args;
03266         Args.push_back(ValueRecord(SrcReg, SrcTy));
03267         MachineInstr *TheCall =
03268           BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
03269         doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
03270       } else {
03271         std::vector<ValueRecord> CmpArgs, ClrArgs, SetArgs;
03272         unsigned ZeroLong = getReg(ConstantUInt::get(SrcTy, 0));
03273         unsigned CondReg = makeAnotherReg(Type::IntTy);
03274 
03275         // Update machine-CFG edges
03276         MachineBasicBlock *ClrMBB = new MachineBasicBlock(BB->getBasicBlock());
03277         MachineBasicBlock *SetMBB = new MachineBasicBlock(BB->getBasicBlock());
03278         MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
03279         MachineBasicBlock *OldMBB = BB;
03280         ilist<MachineBasicBlock>::iterator It = BB; ++It;
03281         F->getBasicBlockList().insert(It, ClrMBB);
03282         F->getBasicBlockList().insert(It, SetMBB);
03283         F->getBasicBlockList().insert(It, PhiMBB);
03284         BB->addSuccessor(ClrMBB);
03285         BB->addSuccessor(SetMBB);
03286 
03287         CmpArgs.push_back(ValueRecord(SrcReg, SrcTy));
03288         CmpArgs.push_back(ValueRecord(ZeroLong, SrcTy));
03289         MachineInstr *TheCall =
03290           BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(__cmpdi2Fn, true);
03291         doCall(ValueRecord(CondReg, Type::IntTy), TheCall, CmpArgs, false);
03292         BuildMI(*MBB, IP, PPC::CMPWI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
03293         BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(SetMBB);
03294 
03295         // ClrMBB
03296         BB = ClrMBB;
03297         unsigned ClrReg = makeAnotherReg(DestTy);
03298         ClrArgs.push_back(ValueRecord(SrcReg, SrcTy));
03299         TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
03300         doCall(ValueRecord(ClrReg, DestTy), TheCall, ClrArgs, false);
03301         BuildMI(BB, PPC::B, 1).addMBB(PhiMBB);
03302         BB->addSuccessor(PhiMBB);
03303         
03304         // SetMBB
03305         BB = SetMBB;
03306         unsigned SetReg = makeAnotherReg(DestTy);
03307         unsigned CallReg = makeAnotherReg(DestTy);
03308         unsigned ShiftedReg = makeAnotherReg(SrcTy);
03309         ConstantSInt *Const1 = ConstantSInt::get(Type::IntTy, 1);
03310         emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0, 
03311                            ShiftedReg);
03312         SetArgs.push_back(ValueRecord(ShiftedReg, SrcTy));
03313         TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
03314         doCall(ValueRecord(CallReg, DestTy), TheCall, SetArgs, false);
03315         unsigned SetOpcode = (DestClass == cFP32) ? PPC::FADDS : PPC::FADD;
03316         BuildMI(BB, SetOpcode, 2, SetReg).addReg(CallReg).addReg(CallReg);
03317         BB->addSuccessor(PhiMBB);
03318         
03319         // PhiMBB
03320         BB = PhiMBB;
03321         BuildMI(BB, PPC::PHI, 4, DestReg).addReg(ClrReg).addMBB(ClrMBB)
03322           .addReg(SetReg).addMBB(SetMBB);
03323       }
03324       return;
03325     }
03326     
03327     // Make sure we're dealing with a full 32 bits
03328     if (SrcClass < cInt) {
03329       unsigned TmpReg = makeAnotherReg(Type::IntTy);
03330       promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
03331       SrcReg = TmpReg;
03332     }
03333     
03334     // Spill the integer to memory and reload it from there.
03335     // Also spill room for a special conversion constant
03336     int ValueFrameIdx =
03337       F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
03338 
03339     MachineConstantPool *CP = F->getConstantPool();
03340     unsigned constantHi = makeAnotherReg(Type::IntTy);
03341     unsigned TempF = makeAnotherReg(Type::DoubleTy);
03342     
03343     if (!SrcTy->isSigned()) {
03344       ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
03345       unsigned ConstF = getReg(CFP, BB, IP);
03346       BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
03347       addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi), 
03348                         ValueFrameIdx);
03349       addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg), 
03350                         ValueFrameIdx, 4);
03351       addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
03352       BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
03353     } else {
03354       ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000008p52);
03355       unsigned ConstF = getReg(CFP, BB, IP);
03356       unsigned TempLo = makeAnotherReg(Type::IntTy);
03357       BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
03358       addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi), 
03359                         ValueFrameIdx);
03360       BuildMI(*MBB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
03361       addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo), 
03362                         ValueFrameIdx, 4);
03363       addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
03364       BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
03365     }
03366     return;
03367   }
03368 
03369   // Handle casts from floating point to integer now...
03370   if (SrcClass == cFP32 || SrcClass == cFP64) {
03371     static Function* const Funcs[] =
03372       { __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
03373     // emit library call
03374     if (DestClass == cLong) {
03375       bool isDouble = SrcClass == cFP64;
03376       unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
03377       std::vector<ValueRecord> Args;
03378       Args.push_back(ValueRecord(SrcReg, SrcTy));
03379       Function *floatFn = Funcs[nameIndex];
03380       MachineInstr *TheCall =
03381         BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
03382       doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
03383       return;
03384     }
03385 
03386     int ValueFrameIdx =
03387       F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
03388 
03389     if (DestTy->isSigned()) {
03390       unsigned TempReg = makeAnotherReg(Type::DoubleTy);
03391       
03392       // Convert to integer in the FP reg and store it to a stack slot
03393       BuildMI(*MBB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
03394       addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3)
03395                           .addReg(TempReg), ValueFrameIdx);
03396 
03397       // There is no load signed byte opcode, so we must emit a sign extend for
03398       // that particular size.  Make sure to source the new integer from the 
03399       // correct offset.
03400       if (DestClass == cByte) {
03401         unsigned TempReg2 = makeAnotherReg(DestTy);
03402         addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2), 
03403                           ValueFrameIdx, 7);
03404         BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
03405       } else {
03406         int offset = (DestClass == cShort) ? 6 : 4;
03407         unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
03408         addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg), 
03409                           ValueFrameIdx, offset);
03410       }
03411     } else {
03412       unsigned Zero = getReg(ConstantFP::get(Type::DoubleTy, 0.0f));
03413       double maxInt = (1LL << 32) - 1;
03414       unsigned MaxInt = getReg(ConstantFP::get(Type::DoubleTy, maxInt));
03415       double border = 1LL << 31;
03416       unsigned Border = getReg(ConstantFP::get(Type::DoubleTy, border));
03417       unsigned UseZero = makeAnotherReg(Type::DoubleTy);
03418       unsigned UseMaxInt = makeAnotherReg(Type::DoubleTy);
03419       unsigned UseChoice = makeAnotherReg(Type::DoubleTy);
03420       unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
03421       unsigned TmpReg2 = makeAnotherReg(Type::DoubleTy);
03422       unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
03423       unsigned IntTmp = makeAnotherReg(Type::IntTy);
03424       unsigned XorReg = makeAnotherReg(Type::IntTy);
03425       int FrameIdx = 
03426         F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
03427       // Update machine-CFG edges
03428       MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
03429       MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
03430       MachineBasicBlock *OldMBB = BB;
03431       ilist<MachineBasicBlock>::iterator It = BB; ++It;
03432       F->getBasicBlockList().insert(It, XorMBB);
03433       F->getBasicBlockList().insert(It, PhiMBB);
03434       BB->addSuccessor(XorMBB);
03435       BB->addSuccessor(PhiMBB);
03436 
03437       // Convert from floating point to unsigned 32-bit value
03438       // Use 0 if incoming value is < 0.0
03439       BuildMI(*MBB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
03440         .addReg(Zero);
03441       // Use 2**32 - 1 if incoming value is >= 2**32
03442       BuildMI(*MBB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
03443       BuildMI(*MBB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
03444         .addReg(UseZero).addReg(MaxInt);
03445       // Subtract 2**31
03446       BuildMI(*MBB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
03447       // Use difference if >= 2**31
03448       BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
03449         .addReg(Border);
03450       BuildMI(*MBB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
03451         .addReg(UseChoice);
03452       // Convert to integer
03453       BuildMI(*MBB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
03454       addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3).addReg(ConvReg),
03455                         FrameIdx);
03456       if (DestClass == cByte) {
03457         addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, DestReg),
03458                           FrameIdx, 7);
03459       } else if (DestClass == cShort) {
03460         addFrameReference(BuildMI(*MBB, IP, PPC::LHZ, 2, DestReg),
03461                           FrameIdx, 6);
03462       } if (DestClass == cInt) {
03463         addFrameReference(BuildMI(*MBB, IP, PPC::LWZ, 2, IntTmp),
03464                           FrameIdx, 4);
03465         BuildMI(*MBB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
03466         BuildMI(*MBB, IP, PPC::B, 1).addMBB(XorMBB);
03467 
03468         // XorMBB:
03469         //   add 2**31 if input was >= 2**31
03470         BB = XorMBB;
03471         BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
03472         XorMBB->addSuccessor(PhiMBB);
03473 
03474         // PhiMBB:
03475         //   DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
03476         BB = PhiMBB;
03477         BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
03478           .addReg(XorReg).addMBB(XorMBB);
03479       }
03480     }
03481     return;
03482   }
03483 
03484   // Check our invariants
03485   assert((SrcClass <= cInt || SrcClass == cLong) && 
03486          "Unhandled source class for cast operation!");
03487   assert((DestClass <= cInt || DestClass == cLong) && 
03488          "Unhandled destination class for cast operation!");
03489 
03490   bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
03491   bool destUnsigned = DestTy->isUnsigned();
03492 
03493   // Unsigned -> Unsigned, clear if larger, 
03494   if (sourceUnsigned && destUnsigned) {
03495     // handle long dest class now to keep switch clean
03496     if (DestClass == cLong) {
03497       BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
03498       BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
03499         .addReg(SrcReg);
03500       return;
03501     }
03502 
03503     // handle u{ byte, short, int } x u{ byte, short, int }
03504     unsigned clearBits = (SrcClass == cByte || DestClass == cByte) ? 24 : 16;
03505     switch (SrcClass) {
03506     case cByte:
03507     case cShort:
03508       BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
03509         .addImm(0).addImm(clearBits).addImm(31);
03510       break;
03511     case cLong:
03512       ++SrcReg;
03513       // Fall through
03514     case cInt:
03515       BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
03516         .addImm(0).addImm(clearBits).addImm(31);
03517       break;
03518     }
03519     return;
03520   }
03521 
03522   // Signed -> Signed
03523   if (!sourceUnsigned && !destUnsigned) {
03524     // handle long dest class now to keep switch clean
03525     if (DestClass == cLong) {
03526       BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
03527       BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
03528         .addReg(SrcReg);
03529       return;
03530     }
03531 
03532     // handle { byte, short, int } x { byte, short, int }
03533     switch (SrcClass) {
03534     case cByte:
03535       BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
03536       break;
03537     case cShort:
03538       if (DestClass == cByte)
03539         BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
03540       else
03541         BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
03542       break;
03543     case cLong:
03544       ++SrcReg;
03545       // Fall through
03546     case cInt:
03547       if (DestClass == cByte)
03548         BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
03549       else if (DestClass == cShort)
03550         BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
03551       else
03552         BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
03553       break;
03554     }
03555     return;
03556   }
03557 
03558   // Unsigned -> Signed
03559   if (sourceUnsigned && !destUnsigned) {
03560     // handle long dest class now to keep switch clean
03561     if (DestClass == cLong) {
03562       BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
03563       BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
03564         .addReg(SrcReg);
03565       return;
03566     }
03567 
03568     // handle u{ byte, short, int } -> { byte, short, int }
03569     switch (SrcClass) {
03570     case cByte:
03571       // uByte 255 -> signed short/int == 255
03572       BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
03573         .addImm(24).addImm(31);
03574       break;
03575     case cShort:
03576       if (DestClass == cByte)
03577         BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
03578       else
03579         BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
03580           .addImm(16).addImm(31);
03581       break;
03582     case cLong:
03583       ++SrcReg;
03584       // Fall through
03585     case cInt:
03586       if (DestClass == cByte)
03587         BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
03588       else if (DestClass == cShort)
03589         BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
03590       else
03591         BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
03592       break;
03593     }
03594     return;
03595   }
03596 
03597   // Signed -> Unsigned
03598   if (!sourceUnsigned && destUnsigned) {
03599     // handle long dest class now to keep switch clean
03600     if (DestClass == cLong) {
03601       BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
03602       BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
03603         .addReg(SrcReg);
03604       return;
03605     }
03606 
03607     // handle { byte, short, int } -> u{ byte, short, int }
03608     unsigned clearBits = (DestClass == cByte) ? 24 : 16;
03609     switch (SrcClass) {
03610     case cByte:
03611        BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
03612        break;
03613     case cShort:
03614       if (DestClass == cByte)
03615         BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
03616           .addImm(0).addImm(clearBits).addImm(31);
03617       else
03618         BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
03619       break;
03620     case cLong:
03621       ++SrcReg;
03622       // Fall through
03623     case cInt:
03624       if (DestClass == cInt)
03625         BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
03626       else
03627         BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
03628           .addImm(0).addImm(clearBits).addImm(31);
03629       break;
03630     }
03631     return;
03632   }
03633 
03634   // Anything we haven't handled already, we can't (yet) handle at all.
03635   std::cerr << "Unhandled cast from " << SrcTy->getDescription()
03636             << "to " << DestTy->getDescription() << '\n';
03637   abort();
03638 }
03639 
03640 /// visitVANextInst - Implement the va_next instruction...
03641 ///
03642 void PPC32ISel::visitVANextInst(VANextInst &I) {
03643   unsigned VAList = getReg(I.getOperand(0));
03644   unsigned DestReg = getReg(I);
03645 
03646   unsigned Size;
03647   switch (I.getArgType()->getTypeID()) {
03648   default:
03649     std::cerr << I;
03650     assert(0 && "Error: bad type for va_next instruction!");
03651     return;
03652   case Type::PointerTyID:
03653   case Type::UIntTyID:
03654   case Type::IntTyID:
03655     Size = 4;
03656     break;
03657   case Type::ULongTyID:
03658   case Type::LongTyID:
03659   case Type::DoubleTyID:
03660     Size = 8;
03661     break;
03662   }
03663 
03664   // Increment the VAList pointer...
03665   BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
03666 }
03667 
03668 void PPC32ISel::visitVAArgInst(VAArgInst &I) {
03669   unsigned VAList = getReg(I.getOperand(0));
03670   unsigned DestReg = getReg(I);
03671 
03672   switch (I.getType()->getTypeID()) {
03673   default:
03674     std::cerr << I;
03675     assert(0 && "Error: bad type for va_next instruction!");
03676     return;
03677   case Type::PointerTyID:
03678   case Type::UIntTyID:
03679   case Type::IntTyID:
03680     BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
03681     break;
03682   case Type::ULongTyID:
03683   case Type::LongTyID:
03684     BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
03685     BuildMI(BB, PPC::LWZ, 2, DestReg+1).addSImm(4).addReg(VAList);
03686     break;
03687   case Type::FloatTyID:
03688     BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
03689     break;
03690   case Type::DoubleTyID:
03691     BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
03692     break;
03693   }
03694 }
03695 
03696 /// visitGetElementPtrInst - instruction-select GEP instructions
03697 ///
03698 void PPC32ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
03699   if (canFoldGEPIntoLoadOrStore(&I))
03700     return;
03701 
03702   emitGEPOperation(BB, BB->end(), &I, false);
03703 }
03704 
03705 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
03706 /// constant expression GEP support.
03707 ///
03708 void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
03709                                  MachineBasicBlock::iterator IP,
03710                                  GetElementPtrInst *GEPI, bool GEPIsFolded) {
03711   // If we've already emitted this particular GEP, just return to avoid
03712   // multiple definitions of the base register.
03713   if (GEPIsFolded && (GEPMap[GEPI].base != 0))
03714     return;
03715   
03716   Value *Src = GEPI->getOperand(0);
03717   User::op_iterator IdxBegin = GEPI->op_begin()+1;
03718   User::op_iterator IdxEnd = GEPI->op_end();
03719   const TargetData &TD = TM.getTargetData();
03720   const Type *Ty = Src->getType();
03721   int64_t constValue = 0;
03722   
03723   // Record the operations to emit the GEP in a vector so that we can emit them
03724   // after having analyzed the entire instruction.
03725   std::vector<CollapsedGepOp> ops;
03726   
03727   // GEPs have zero or more indices; we must perform a struct access
03728   // or array access for each one.
03729   for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
03730        ++oi) {
03731     Value *idx = *oi;
03732     if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
03733       // It's a struct access.  idx is the index into the structure,
03734       // which names the field. Use the TargetData structure to
03735       // pick out what the layout of the structure is in memory.
03736       // Use the (constant) structure index's value to find the
03737       // right byte offset from the StructLayout class's list of
03738       // structure member offsets.
03739       unsigned fieldIndex = cast<ConstantUInt>(idx)->getValue();
03740 
03741       // StructType member offsets are always constant values.  Add it to the
03742       // running total.
03743       constValue += TD.getStructLayout(StTy)->MemberOffsets[fieldIndex];
03744 
03745       // The next type is the member of the structure selected by the index.
03746       Ty = StTy->getElementType (fieldIndex);
03747     } else if (const SequentialType *SqTy = dyn_cast<SequentialType>(Ty)) {
03748       // Many GEP instructions use a [cast (int/uint) to LongTy] as their
03749       // operand.  Handle this case directly now...
03750       if (CastInst *CI = dyn_cast<CastInst>(idx))
03751         if (CI->getOperand(0)->getType() == Type::IntTy ||
03752             CI->getOperand(0)->getType() == Type::UIntTy)
03753           idx = CI->getOperand(0);
03754 
03755       // It's an array or pointer access: [ArraySize x ElementType].
03756       // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
03757       // must find the size of the pointed-to type (Not coincidentally, the next
03758       // type is the type of the elements in the array).
03759       Ty = SqTy->getElementType();
03760       unsigned elementSize = TD.getTypeSize(Ty);
03761       
03762       if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
03763         if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
03764           constValue += CS->getValue() * elementSize;
03765         else if (ConstantUInt *CU = dyn_cast<ConstantUInt>(C))
03766           constValue += CU->getValue() * elementSize;
03767         else
03768           assert(0 && "Invalid ConstantInt GEP index type!");
03769       } else {
03770         // Push current gep state to this point as an add and multiply
03771         ops.push_back(CollapsedGepOp(
03772           ConstantSInt::get(Type::IntTy, constValue),
03773           idx, ConstantUInt::get(Type::UIntTy, elementSize)));
03774 
03775         constValue = 0;
03776       }
03777     }
03778   }
03779   // Emit instructions for all the collapsed ops
03780   unsigned indexReg = 0;
03781   for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
03782       cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
03783     CollapsedGepOp& cgo = *cgo_i;
03784 
03785     // Avoid emitting known move instructions here for the register allocator
03786     // to deal with later.  val * 1 == val.  val + 0 == val.
03787     unsigned TmpReg1;
03788     if (cgo.size->getValue() == 1) {
03789       TmpReg1 = getReg(cgo.index, MBB, IP);
03790     } else {
03791       TmpReg1 = makeAnotherReg(Type::IntTy);
03792       doMultiplyConst(MBB, IP, TmpReg1, cgo.index, cgo.size);
03793     }
03794     
03795     unsigned TmpReg2;
03796     if (cgo.offset->isNullValue()) { 
03797       TmpReg2 = TmpReg1;
03798     } else {
03799       TmpReg2 = makeAnotherReg(Type::IntTy);
03800       emitBinaryConstOperation(MBB, IP, TmpReg1, cgo.offset, 0, TmpReg2);
03801     }
03802     
03803     if (indexReg == 0)
03804       indexReg = TmpReg2;
03805     else {
03806       unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
03807       BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg3).addReg(indexReg).addReg(TmpReg2);
03808       indexReg = TmpReg3;
03809     }
03810   }
03811   
03812   // We now have a base register, an index register, and possibly a constant
03813   // remainder.  If the GEP is going to be folded, we try to generate the
03814   // optimal addressing mode.
03815   ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
03816   
03817   // If we are emitting this during a fold, copy the current base register to
03818   // the target, and save the current constant offset so the folding load or
03819   // store can try and use it as an immediate.
03820   if (GEPIsFolded) {
03821     if (indexReg == 0) {
03822       if (!canUseAsImmediateForOpcode(remainder, 0, false)) {
03823         indexReg = getReg(remainder, MBB, IP);
03824         remainder = 0;
03825       }
03826     } else if (!remainder->isNullValue()) {
03827       unsigned TmpReg = makeAnotherReg(Type::IntTy);
03828       emitBinaryConstOperation(MBB, IP, indexReg, remainder, 0, TmpReg);
03829       indexReg = TmpReg;
03830       remainder = 0;
03831     }
03832     unsigned basePtrReg = getReg(Src, MBB, IP);
03833     GEPMap[GEPI] = FoldedGEP(basePtrReg, indexReg, remainder);
03834     return;
03835   }
03836 
03837   // We're not folding, so collapse the base, index, and any remainder into the
03838   // destination register.
03839   unsigned TargetReg = getReg(GEPI, MBB, IP);
03840   unsigned basePtrReg = getReg(Src, MBB, IP);
03841 
03842   if ((indexReg == 0) && remainder->isNullValue()) {
03843     BuildMI(*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
03844       .addReg(basePtrReg);
03845     return;
03846   }
03847   if (!remainder->isNullValue()) {
03848     unsigned TmpReg = (indexReg == 0) ? TargetReg : makeAnotherReg(Type::IntTy);
03849     emitBinaryConstOperation(MBB, IP, basePtrReg, remainder, 0, TmpReg);
03850     basePtrReg = TmpReg;
03851   }
03852   if (indexReg != 0)
03853     BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(indexReg)
03854       .addReg(basePtrReg);
03855 }
03856 
03857 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
03858 /// frame manager, otherwise do it the hard way.
03859 ///
03860 void PPC32ISel::visitAllocaInst(AllocaInst &I) {
03861   // If this is a fixed size alloca in the entry block for the function, we
03862   // statically stack allocate the space, so we don't need to do anything here.
03863   //
03864   if (dyn_castFixedAlloca(&I)) return;
03865   
03866   // Find the data size of the alloca inst's getAllocatedType.
03867   const Type *Ty = I.getAllocatedType();
03868   unsigned TySize = TM.getTargetData().getTypeSize(Ty);
03869 
03870   // Create a register to hold the temporary result of multiplying the type size
03871   // constant by the variable amount.
03872   unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
03873   
03874   // TotalSizeReg = mul <numelements>, <TypeSize>
03875   MachineBasicBlock::iterator MBBI = BB->end();
03876   ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
03877   doMultiplyConst(BB, MBBI, TotalSizeReg, I.getArraySize(), CUI);
03878 
03879   // AddedSize = add <TotalSizeReg>, 15
03880   unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
03881   BuildMI(BB, PPC::ADDI, 2, AddedSizeReg).addReg(TotalSizeReg).addSImm(15);
03882 
03883   // AlignedSize = and <AddedSize>, ~15
03884   unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
03885   BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
03886     .addImm(0).addImm(27);
03887   
03888   // Subtract size from stack pointer, thereby allocating some space.
03889   BuildMI(BB, PPC::SUB, 2, PPC::R1).addReg(PPC::R1).addReg(AlignedSize);
03890 
03891   // Put a pointer to the space into the result register, by copying
03892   // the stack pointer.
03893   BuildMI(BB, PPC::OR, 2, getReg(I)).addReg(PPC::R1).addReg(PPC::R1);
03894 
03895   // Inform the Frame Information that we have just allocated a variable-sized
03896   // object.
03897   F->getFrameInfo()->CreateVariableSizedObject();
03898 }
03899 
03900 /// visitMallocInst - Malloc instructions are code generated into direct calls
03901 /// to the library malloc.
03902 ///
03903 void PPC32ISel::visitMallocInst(MallocInst &I) {
03904   unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
03905   unsigned Arg;
03906 
03907   if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
03908     Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
03909   } else {
03910     Arg = makeAnotherReg(Type::UIntTy);
03911     MachineBasicBlock::iterator MBBI = BB->end();
03912     ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, AllocSize);
03913     doMultiplyConst(BB, MBBI, Arg, I.getOperand(0), CUI);
03914   }
03915 
03916   std::vector<ValueRecord> Args;
03917   Args.push_back(ValueRecord(Arg, Type::UIntTy));
03918   MachineInstr *TheCall = 
03919     BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
03920   doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
03921 }
03922 
03923 /// visitFreeInst - Free instructions are code gen'd to call the free libc
03924 /// function.
03925 ///
03926 void PPC32ISel::visitFreeInst(FreeInst &I) {
03927   std::vector<ValueRecord> Args;
03928   Args.push_back(ValueRecord(I.getOperand(0)));
03929   MachineInstr *TheCall = 
03930     BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
03931   doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
03932 }
03933    
03934 /// createPPC32ISelSimple - This pass converts an LLVM function into a machine
03935 /// code representation is a very simple peep-hole fashion.
03936 ///
03937 FunctionPass *llvm::createPPC32ISelSimple(TargetMachine &TM) {
03938   return new PPC32ISel(TM);
03939 }