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SparcV9InstrInfo.h

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00001 //===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -*- C++ -*-===//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This class contains information about individual instructions.
00011 // Also see the SparcV9MachineInstrDesc array, which can be found in
00012 // SparcV9TargetMachine.cpp.
00013 // Other information is computed on demand, and most such functions
00014 // default to member functions in base class TargetInstrInfo. 
00015 //
00016 //===----------------------------------------------------------------------===//
00017 
00018 #ifndef SPARCV9INSTRINFO_H
00019 #define SPARCV9INSTRINFO_H
00020 
00021 #include "llvm/Target/TargetInstrInfo.h"
00022 #include "llvm/CodeGen/MachineInstr.h"
00023 #include "SparcV9Internals.h"
00024 #include "SparcV9RegisterInfo.h"
00025 
00026 namespace llvm {
00027 
00028 /// SparcV9InstrInfo - TargetInstrInfo specialized for the SparcV9 target.
00029 ///
00030 struct SparcV9InstrInfo : public TargetInstrInfo {
00031   const SparcV9RegisterInfo RI;
00032 public:
00033   SparcV9InstrInfo()
00034     : TargetInstrInfo(SparcV9MachineInstrDesc, V9::NUM_TOTAL_OPCODES) { }
00035 
00036   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
00037   /// such, whenever a client has an instance of instruction info, it should
00038   /// always be able to get register info as well (through this method).
00039   ///
00040   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
00041 
00042   // All immediate constants are in position 1 except the
00043   // store instructions and SETxx.
00044   // 
00045   virtual int getImmedConstantPos(MachineOpCode opCode) const {
00046     bool ignore;
00047     if (this->maxImmedConstant(opCode, ignore) != 0) {
00048       // 1st store opcode
00049       assert(! this->isStore((MachineOpCode) V9::STBr - 1));
00050       // last store opcode
00051       assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
00052 
00053       if (opCode == V9::SETHI)
00054         return 0;
00055       if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
00056         return 2;
00057       return 1;
00058     }
00059     else
00060       return -1;
00061   }
00062 
00063   virtual bool hasResultInterlock(MachineOpCode opCode) const
00064   {
00065     // All UltraSPARC instructions have interlocks (note that delay slots
00066     // are not considered here).
00067     // However, instructions that use the result of an FCMP produce a
00068     // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
00069     // Force the compiler to insert a software interlock (i.e., gap of
00070     // 2 other groups, including NOPs if necessary).
00071     return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
00072   }
00073 };
00074 
00075 } // End llvm namespace
00076 
00077 #endif