LLVM API Documentation
00001 //===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the PowerPC64 implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef POWERPC64_INSTRUCTIONINFO_H 00015 #define POWERPC64_INSTRUCTIONINFO_H 00016 00017 #include "PowerPCInstrInfo.h" 00018 #include "PPC64RegisterInfo.h" 00019 00020 namespace llvm { 00021 00022 class PPC64InstrInfo : public TargetInstrInfo { 00023 const PPC64RegisterInfo RI; 00024 public: 00025 PPC64InstrInfo(); 00026 00027 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 00028 /// such, whenever a client has an instance of instruction info, it should 00029 /// always be able to get register info as well (through this method). 00030 /// 00031 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 00032 00033 // 00034 // Return true if the instruction is a register to register move and 00035 // leave the source and dest operands in the passed parameters. 00036 // 00037 virtual bool isMoveInstr(const MachineInstr& MI, 00038 unsigned& sourceReg, 00039 unsigned& destReg) const; 00040 00041 static unsigned invertPPCBranchOpcode(unsigned Opcode) { 00042 switch (Opcode) { 00043 default: assert(0 && "Unknown PPC branch opcode!"); 00044 case PPC::BEQ: return PPC::BNE; 00045 case PPC::BNE: return PPC::BEQ; 00046 case PPC::BLT: return PPC::BGE; 00047 case PPC::BGE: return PPC::BLT; 00048 case PPC::BGT: return PPC::BLE; 00049 case PPC::BLE: return PPC::BGT; 00050 } 00051 } 00052 }; 00053 00054 } 00055 00056 #endif