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X86GenRegisterInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Register Information Source Fragment
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 namespace {     // Register classes...
00012   // R16 Register Class...
00013   const unsigned R16[] = {
00014     X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
00015   };
00016 
00017   struct R16Class : public TargetRegisterClass {
00018     R16Class() : TargetRegisterClass(2, 2, R16, R16 + 8) {}
00019 
00020     iterator allocation_order_end(MachineFunction &MF) const {
00021       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
00022         return end()-2;  // If so, don't allocate SP or BP
00023       else
00024         return end()-1;  // If not, just don't allocate SP
00025     }
00026     } R16Instance;
00027 
00028   // R32 Register Class...
00029   const unsigned R32[] = {
00030     X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
00031   };
00032 
00033   struct R32Class : public TargetRegisterClass {
00034     R32Class() : TargetRegisterClass(4, 4, R32, R32 + 8) {}
00035 
00036     iterator allocation_order_end(MachineFunction &MF) const {
00037       if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
00038         return end()-2;  // If so, don't allocate ESP or EBP
00039       else
00040         return end()-1;  // If not, just don't allocate ESP
00041     }
00042     } R32Instance;
00043 
00044   // R8 Register Class...
00045   const unsigned R8[] = {
00046     X86::AL, X86::AH, X86::CL, X86::CH, X86::DL, X86::DH, X86::BL, X86::BH, 
00047   };
00048 
00049   struct R8Class : public TargetRegisterClass {
00050     R8Class() : TargetRegisterClass(1, 1, R8, R8 + 8) {}
00051   } R8Instance;
00052 
00053   // RFP Register Class...
00054   const unsigned RFP[] = {
00055     X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
00056   };
00057 
00058   struct RFPClass : public TargetRegisterClass {
00059     RFPClass() : TargetRegisterClass(8, 4, RFP, RFP + 7) {}
00060   } RFPInstance;
00061 
00062   // RST Register Class...
00063   const unsigned RST[] = {
00064     X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
00065   };
00066 
00067   struct RSTClass : public TargetRegisterClass {
00068     RSTClass() : TargetRegisterClass(8, 4, RST, RST + 8) {}
00069 
00070     iterator allocation_order_end(MachineFunction &MF) const {
00071       return begin();
00072     }
00073     } RSTInstance;
00074 
00075   const TargetRegisterClass* const RegisterClasses[] = {
00076     &R16Instance,
00077     &R32Instance,
00078     &R8Instance,
00079     &RFPInstance,
00080     &RSTInstance,
00081   };
00082 
00083 
00084   // Register Alias Sets...
00085   const unsigned Empty_AliasSet[] = { 0 };
00086   const unsigned EAX_AliasSet[] = { X86::AX, X86::AL, X86::AH, 0 };
00087   const unsigned ECX_AliasSet[] = { X86::CX, X86::CL, X86::CH, 0 };
00088   const unsigned EDX_AliasSet[] = { X86::DX, X86::DL, X86::DH, 0 };
00089   const unsigned EBX_AliasSet[] = { X86::BX, X86::BL, X86::BH, 0 };
00090   const unsigned ESP_AliasSet[] = { X86::SP, 0 };
00091   const unsigned EBP_AliasSet[] = { X86::BP, 0 };
00092   const unsigned ESI_AliasSet[] = { X86::SI, 0 };
00093   const unsigned EDI_AliasSet[] = { X86::DI, 0 };
00094   const unsigned AX_AliasSet[] = { X86::EAX, X86::AL, X86::AH, 0 };
00095   const unsigned CX_AliasSet[] = { X86::ECX, X86::CL, X86::CH, 0 };
00096   const unsigned DX_AliasSet[] = { X86::EDX, X86::DL, X86::DH, 0 };
00097   const unsigned BX_AliasSet[] = { X86::EBX, X86::BL, X86::BH, 0 };
00098   const unsigned SP_AliasSet[] = { X86::ESP, 0 };
00099   const unsigned BP_AliasSet[] = { X86::EBP, 0 };
00100   const unsigned SI_AliasSet[] = { X86::ESI, 0 };
00101   const unsigned DI_AliasSet[] = { X86::EDI, 0 };
00102   const unsigned AL_AliasSet[] = { X86::EAX, X86::AX, 0 };
00103   const unsigned CL_AliasSet[] = { X86::ECX, X86::CX, 0 };
00104   const unsigned DL_AliasSet[] = { X86::EDX, X86::DX, 0 };
00105   const unsigned BL_AliasSet[] = { X86::EBX, X86::BX, 0 };
00106   const unsigned AH_AliasSet[] = { X86::EAX, X86::AX, 0 };
00107   const unsigned CH_AliasSet[] = { X86::ECX, X86::CX, 0 };
00108   const unsigned DH_AliasSet[] = { X86::EDX, X86::DX, 0 };
00109   const unsigned BH_AliasSet[] = { X86::EBX, X86::BX, 0 };
00110 
00111   const MRegisterDesc RegisterDescriptors[] = { // Descriptors
00112     { "NOREG",  0,    0,  0 },
00113     { "AH", AH_AliasSet,  8, 8 },
00114     { "AL", AL_AliasSet,  8, 8 },
00115     { "AX", AX_AliasSet,  16, 16 },
00116     { "BH", BH_AliasSet,  8, 8 },
00117     { "BL", BL_AliasSet,  8, 8 },
00118     { "BP", BP_AliasSet,  16, 16 },
00119     { "BX", BX_AliasSet,  16, 16 },
00120     { "CH", CH_AliasSet,  8, 8 },
00121     { "CL", CL_AliasSet,  8, 8 },
00122     { "CX", CX_AliasSet,  16, 16 },
00123     { "DH", DH_AliasSet,  8, 8 },
00124     { "DI", DI_AliasSet,  16, 16 },
00125     { "DL", DL_AliasSet,  8, 8 },
00126     { "DX", DX_AliasSet,  16, 16 },
00127     { "EAX",  EAX_AliasSet, 32, 32 },
00128     { "EBP",  EBP_AliasSet, 32, 32 },
00129     { "EBX",  EBX_AliasSet, 32, 32 },
00130     { "ECX",  ECX_AliasSet, 32, 32 },
00131     { "EDI",  EDI_AliasSet, 32, 32 },
00132     { "EDX",  EDX_AliasSet, 32, 32 },
00133     { "ESI",  ESI_AliasSet, 32, 32 },
00134     { "ESP",  ESP_AliasSet, 32, 32 },
00135     { "FP0",  Empty_AliasSet, 64, 32 },
00136     { "FP1",  Empty_AliasSet, 64, 32 },
00137     { "FP2",  Empty_AliasSet, 64, 32 },
00138     { "FP3",  Empty_AliasSet, 64, 32 },
00139     { "FP4",  Empty_AliasSet, 64, 32 },
00140     { "FP5",  Empty_AliasSet, 64, 32 },
00141     { "FP6",  Empty_AliasSet, 64, 32 },
00142     { "SI", SI_AliasSet,  16, 16 },
00143     { "SP", SP_AliasSet,  16, 16 },
00144     { "ST(0)",  Empty_AliasSet, 64, 32 },
00145     { "ST(1)",  Empty_AliasSet, 64, 32 },
00146     { "ST(2)",  Empty_AliasSet, 64, 32 },
00147     { "ST(3)",  Empty_AliasSet, 64, 32 },
00148     { "ST(4)",  Empty_AliasSet, 64, 32 },
00149     { "ST(5)",  Empty_AliasSet, 64, 32 },
00150     { "ST(6)",  Empty_AliasSet, 64, 32 },
00151     { "ST(7)",  Empty_AliasSet, 64, 32 },
00152   };
00153 }
00154 
00155 namespace X86 { // Register classes
00156   TargetRegisterClass *R16RegisterClass = &R16Instance;
00157   TargetRegisterClass *R32RegisterClass = &R32Instance;
00158   TargetRegisterClass *R8RegisterClass = &R8Instance;
00159   TargetRegisterClass *RFPRegisterClass = &RFPInstance;
00160   TargetRegisterClass *RSTRegisterClass = &RSTInstance;
00161 } // end of namespace X86
00162 
00163 X86GenRegisterInfo::X86GenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
00164   : MRegisterInfo(RegisterDescriptors, 40, RegisterClasses, RegisterClasses+5,
00165                   CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
00166 
00167 const unsigned* X86GenRegisterInfo::getCalleeSaveRegs() const {
00168   static const unsigned CalleeSaveRegs[] = {
00169     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
00170   };
00171   return CalleeSaveRegs;
00172 }
00173 
00174 } // End llvm namespace