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SparcV9CodeEmitter.cpp

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00001 //===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // SPARC-specific backend for emitting machine code to memory.
00011 //
00012 // This module also contains the code for lazily resolving the targets
00013 // of call instructions, including the callback used to redirect calls
00014 // to functions for which the code has not yet been generated into the
00015 // JIT compiler.
00016 //
00017 // This file #includes SparcV9CodeEmitter.inc, which contains the code
00018 // for getBinaryCodeForInstr(), a method that converts a MachineInstr
00019 // into the corresponding binary machine code word.
00020 //
00021 //===----------------------------------------------------------------------===//
00022 
00023 #include "llvm/Constants.h"
00024 #include "llvm/Function.h"
00025 #include "llvm/GlobalVariable.h"
00026 #include "llvm/PassManager.h"
00027 #include "llvm/CodeGen/MachineCodeEmitter.h"
00028 #include "llvm/CodeGen/MachineConstantPool.h"
00029 #include "llvm/CodeGen/MachineFunctionPass.h"
00030 #include "llvm/CodeGen/MachineInstr.h"
00031 #include "llvm/Target/TargetMachine.h"
00032 #include "llvm/Target/TargetData.h"
00033 #include "llvm/Support/Debug.h"
00034 #include "SparcV9Internals.h"
00035 #include "SparcV9TargetMachine.h"
00036 #include "SparcV9RegInfo.h"
00037 #include "SparcV9CodeEmitter.h"
00038 #include "SparcV9Relocations.h"
00039 #include "MachineFunctionInfo.h"
00040 using namespace llvm;
00041 
00042 bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
00043                                                       MachineCodeEmitter &MCE) {
00044   PM.add(new SparcV9CodeEmitter(*this, MCE));
00045   PM.add(createSparcV9MachineCodeDestructionPass());
00046   return false;
00047 }
00048 
00049 SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
00050                                        MachineCodeEmitter &M): TM(tm), MCE(M) {}
00051 
00052 void SparcV9CodeEmitter::emitWord(unsigned Val) {
00053   MCE.emitWord(Val);
00054 }
00055 
00056 unsigned 
00057 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
00058                                   MachineInstr &MI) {
00059   const SparcV9RegInfo &RI = *TM.getRegInfo();
00060   unsigned regClass, regType = RI.getRegType(fakeReg);
00061   // At least map fakeReg into its class
00062   fakeReg = RI.getClassRegNum(fakeReg, regClass);
00063 
00064   switch (regClass) {
00065   case SparcV9RegInfo::IntRegClassID: {
00066     // SparcV9 manual, p31
00067     static const unsigned IntRegMap[] = {
00068       // "o0", "o1", "o2", "o3", "o4", "o5",       "o7",
00069       8, 9, 10, 11, 12, 13, 15,
00070       // "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
00071       16, 17, 18, 19, 20, 21, 22, 23,
00072       // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
00073       24, 25, 26, 27, 28, 29, 30, 31,
00074       // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 
00075       0, 1, 2, 3, 4, 5, 6, 7,
00076       // "o6"
00077       14
00078     }; 
00079  
00080     return IntRegMap[fakeReg];
00081     break;
00082   }
00083   case SparcV9RegInfo::FloatRegClassID: {
00084     DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
00085     if (regType == SparcV9RegInfo::FPSingleRegType) {
00086       // only numbered 0-31, hence can already fit into 5 bits (and 6)
00087       DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
00088     } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
00089       // FIXME: This assumes that we only have 5-bit register fields!
00090       // From SparcV9 Manual, page 40.
00091       // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
00092       fakeReg |= (fakeReg >> 5) & 1;
00093       fakeReg &= 0x1f;
00094       DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");      
00095     }
00096     return fakeReg;
00097   }
00098   case SparcV9RegInfo::IntCCRegClassID: {
00099     /*                                   xcc, icc, ccr */
00100     static const unsigned IntCCReg[] = {  6,   4,   2 };
00101     
00102     assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
00103              && "CC register out of bounds for IntCCReg map");      
00104     DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
00105     return IntCCReg[fakeReg];
00106   }
00107   case SparcV9RegInfo::FloatCCRegClassID: {
00108     /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
00109     DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
00110     return fakeReg;
00111   }
00112   case SparcV9RegInfo::SpecialRegClassID: {
00113     // Currently only "special" reg is %fsr, which is encoded as 1 in
00114     // instructions and 0 in SparcV9SpecialRegClass.
00115     static const unsigned SpecialReg[] = {  1 };
00116     assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
00117              && "Special register out of bounds for SpecialReg map");      
00118     DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
00119     return SpecialReg[fakeReg];
00120   }
00121   default:
00122     assert(0 && "Invalid unified register number in getRealRegNum");
00123     return fakeReg;
00124   }
00125 }
00126 
00127 
00128 
00129 int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
00130                                               MachineOperand &MO) {
00131   int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
00132                   // or things that get fixed up later by the JIT.
00133   if (MO.isPCRelativeDisp() || MO.isGlobalAddress()) {
00134     DEBUG(std::cerr << "PCRelativeDisp: ");
00135     Value *V = MO.getVRegValue();
00136     if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
00137       DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
00138       unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
00139       BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
00140     } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00141       // The real target of the branch is CI = PC + (rv * 4)
00142       // So undo that: give the instruction (CI - PC) / 4
00143       rv = (CI->getRawValue() - MCE.getCurrentPCValue()) / 4;
00144     } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
00145       unsigned Reloc = 0;
00146       if (MI.getOpcode() == V9::CALL) {
00147         Reloc = V9::reloc_pcrel_call;
00148       } else if (MI.getOpcode() == V9::SETHI) {
00149         if (MO.isHiBits64())
00150           Reloc = V9::reloc_sethi_hh;
00151         else if (MO.isHiBits32())
00152           Reloc = V9::reloc_sethi_lm;
00153         else
00154           assert(0 && "Unknown relocation!");
00155       } else if (MI.getOpcode() == V9::ORi) {
00156         if (MO.isLoBits32())
00157           Reloc = V9::reloc_or_lo;
00158         else if (MO.isLoBits64())
00159           Reloc = V9::reloc_or_hm;
00160         else
00161           assert(0 && "Unknown relocation!");
00162       } else {
00163         assert(0 && "Unknown relocation!");
00164       }
00165 
00166       MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), Reloc, GV));
00167       rv = 0;
00168     } else {
00169       std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
00170       abort();
00171     }
00172   } else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
00173   {
00174     // This is necessary because the SparcV9 backend doesn't actually lay out
00175     // registers in the real fashion -- it skips those that it chooses not to
00176     // allocate, i.e. those that are the FP, SP, etc.
00177     unsigned fakeReg = MO.getReg();
00178     unsigned realRegByClass = getRealRegNum(fakeReg, MI);
00179     DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
00180                     << realRegByClass << " (LLC: " 
00181                     << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
00182     rv = realRegByClass;
00183   } else if (MO.isImmediate()) {
00184     rv = MO.getImmedValue();
00185     DEBUG(std::cerr << "immed: " << rv << "\n");
00186   } else if (MO.isMachineBasicBlock()) {
00187     // Duplicate code of the above case for VirtualRegister, BasicBlock... 
00188     // It should really hit this case, but SparcV9 backend uses VRegs instead
00189     DEBUG(std::cerr << "Saving reference to MBB\n");
00190     const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
00191     unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
00192     BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
00193   } else if (MO.isExternalSymbol()) {
00194     // SparcV9 backend doesn't generate this (yet...)
00195     std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
00196     abort();
00197   } else if (MO.isFrameIndex()) {
00198     // SparcV9 backend doesn't generate this (yet...)
00199     int FrameIndex = MO.getFrameIndex();
00200     std::cerr << "ERROR: Frame index unhandled.\n";
00201     abort();
00202   } else if (MO.isConstantPoolIndex()) {
00203     unsigned Index = MO.getConstantPoolIndex();
00204     rv = MCE.getConstantPoolEntryAddress(Index);
00205   } else {
00206     std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
00207     abort();
00208   }
00209 
00210   // Finally, deal with the various bitfield-extracting functions that
00211   // are used in SPARC assembly. (Some of these make no sense in combination
00212   // with some of the above; we'll trust that the instruction selector
00213   // will not produce nonsense, and not check for valid combinations here.)
00214   if (MO.isLoBits32()) {          // %lo(val) == %lo() in SparcV9 ABI doc
00215     return rv & 0x03ff;
00216   } else if (MO.isHiBits32()) {   // %lm(val) == %hi() in SparcV9 ABI doc
00217     return (rv >> 10) & 0x03fffff;
00218   } else if (MO.isLoBits64()) {   // %hm(val) == %ulo() in SparcV9 ABI doc
00219     return (rv >> 32) & 0x03ff;
00220   } else if (MO.isHiBits64()) {   // %hh(val) == %uhi() in SparcV9 ABI doc
00221     return rv >> 42;
00222   } else {                        // (unadorned) val
00223     return rv;
00224   }
00225 }
00226 
00227 unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
00228   Val >>= bit;
00229   return (Val & 1);
00230 }
00231 
00232 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
00233   MCE.startFunction(MF);
00234   DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
00235             << ", address: " << "0x" << std::hex 
00236             << (long)MCE.getCurrentPCValue() << "\n");
00237 
00238   MCE.emitConstantPool(MF.getConstantPool());
00239   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
00240     emitBasicBlock(*I);
00241   MCE.finishFunction(MF);
00242 
00243   DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
00244 
00245   // Resolve branches to BasicBlocks for the entire function
00246   for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
00247     long Location = BBLocations[BBRefs[i].first];
00248     unsigned *Ref = BBRefs[i].second.first;
00249     MachineInstr *MI = BBRefs[i].second.second;
00250     DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
00251                     << " in instr: " << std::dec << *MI);
00252     for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
00253       MachineOperand &op = MI->getOperand(ii);
00254       if (op.isPCRelativeDisp()) {
00255         // the instruction's branch target is made such that it branches to
00256         // PC + (branchTarget * 4), so undo that arithmetic here:
00257         // Location is the target of the branch
00258         // Ref is the location of the instruction, and hence the PC
00259         int64_t branchTarget = (Location - (long)Ref) >> 2;
00260         // Save the flags.
00261         bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;   
00262         if (op.isLoBits32()) { loBits32=true; }
00263         if (op.isHiBits32()) { hiBits32=true; }
00264         if (op.isLoBits64()) { loBits64=true; }
00265         if (op.isHiBits64()) { hiBits64=true; }
00266         MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
00267                                    branchTarget);
00268         if (loBits32) { MI->getOperand(ii).markLo32(); }
00269         else if (hiBits32) { MI->getOperand(ii).markHi32(); }
00270         else if (loBits64) { MI->getOperand(ii).markLo64(); }
00271         else if (hiBits64) { MI->getOperand(ii).markHi64(); }
00272         DEBUG(std::cerr << "Rewrote BB ref: ");
00273         unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
00274         MCE.emitWordAt (fixedInstr, Ref);
00275         break;
00276       }
00277     }
00278   }
00279   BBRefs.clear();
00280   BBLocations.clear();
00281 
00282   return false;
00283 }
00284 
00285 void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
00286   currBB = MBB.getBasicBlock();
00287   BBLocations[currBB] = MCE.getCurrentPCValue();
00288   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
00289     if (I->getOpcode() != V9::RDCCR) {
00290       emitWord(getBinaryCodeForInstr(*I));
00291     } else {
00292       // FIXME: The tblgen produced code emitter cannot deal with the fact that
00293       // machine operand #0 of the RDCCR instruction should be ignored.  This is
00294       // really a bug in the representation of the RDCCR instruction (which has
00295       // no need to explicitly represent the CCR dest), but we hack around it
00296       // here.
00297       unsigned RegNo = getMachineOpValue(*I, I->getOperand(1));
00298       RegNo &= (1<<5)-1;
00299       emitWord((RegNo << 25) | 2168487936U);
00300     }
00301 }
00302 
00303 #include "SparcV9CodeEmitter.inc"
00304