LLVM API Documentation
00001 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file describes the target machine instructions to the code generator. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef LLVM_TARGET_TARGETINSTRINFO_H 00015 #define LLVM_TARGET_TARGETINSTRINFO_H 00016 00017 #include "llvm/CodeGen/MachineBasicBlock.h" 00018 #include "llvm/Support/DataTypes.h" 00019 #include <vector> 00020 #include <cassert> 00021 00022 namespace llvm { 00023 00024 class MachineInstr; 00025 class TargetMachine; 00026 class Value; 00027 class Type; 00028 class Instruction; 00029 class Constant; 00030 class Function; 00031 class MachineCodeForInstruction; 00032 00033 //--------------------------------------------------------------------------- 00034 // Data types used to define information about a single machine instruction 00035 //--------------------------------------------------------------------------- 00036 00037 typedef short MachineOpCode; 00038 typedef unsigned InstrSchedClass; 00039 00040 //--------------------------------------------------------------------------- 00041 // struct TargetInstrDescriptor: 00042 // Predefined information about each machine instruction. 00043 // Designed to initialized statically. 00044 // 00045 00046 const unsigned M_NOP_FLAG = 1 << 0; 00047 const unsigned M_BRANCH_FLAG = 1 << 1; 00048 const unsigned M_CALL_FLAG = 1 << 2; 00049 const unsigned M_RET_FLAG = 1 << 3; 00050 const unsigned M_BARRIER_FLAG = 1 << 4; 00051 const unsigned M_DELAY_SLOT_FLAG = 1 << 5; 00052 const unsigned M_CC_FLAG = 1 << 6; 00053 const unsigned M_LOAD_FLAG = 1 << 10; 00054 const unsigned M_STORE_FLAG = 1 << 12; 00055 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 00056 const unsigned M_2_ADDR_FLAG = 1 << 15; 00057 00058 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 00059 // block? Typically this is things like return and branch instructions. 00060 // Various passes use this to insert code into the bottom of a basic block, but 00061 // before control flow occurs. 00062 const unsigned M_TERMINATOR_FLAG = 1 << 16; 00063 00064 class TargetInstrDescriptor { 00065 public: 00066 const char * Name; // Assembly language mnemonic for the opcode. 00067 int numOperands; // Number of args; -1 if variable #args 00068 int resultPos; // Position of the result; -1 if no result 00069 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 00070 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 00071 // smallest -ve value is -(maxImmedConst+1). 00072 unsigned numDelaySlots; // Number of delay slots after instruction 00073 unsigned latency; // Latency in machine cycles 00074 InstrSchedClass schedClass; // enum identifying instr sched class 00075 unsigned Flags; // flags identifying machine instr class 00076 unsigned TSFlags; // Target Specific Flag values 00077 const unsigned *ImplicitUses; // Registers implicitly read by this instr 00078 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 00079 }; 00080 00081 00082 //--------------------------------------------------------------------------- 00083 /// 00084 /// TargetInstrInfo - Interface to description of machine instructions 00085 /// 00086 class TargetInstrInfo { 00087 const TargetInstrDescriptor* desc; // raw array to allow static init'n 00088 unsigned NumOpcodes; // number of entries in the desc array 00089 unsigned numRealOpCodes; // number of non-dummy op codes 00090 00091 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 00092 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 00093 public: 00094 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 00095 virtual ~TargetInstrInfo(); 00096 00097 // Invariant: All instruction sets use opcode #0 as the PHI instruction 00098 enum { PHI = 0 }; 00099 00100 unsigned getNumOpcodes() const { return NumOpcodes; } 00101 00102 /// get - Return the machine instruction descriptor that corresponds to the 00103 /// specified instruction opcode. 00104 /// 00105 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 00106 assert((unsigned)Opcode < NumOpcodes); 00107 return desc[Opcode]; 00108 } 00109 00110 const char *getName(MachineOpCode Opcode) const { 00111 return get(Opcode).Name; 00112 } 00113 00114 int getNumOperands(MachineOpCode Opcode) const { 00115 return get(Opcode).numOperands; 00116 } 00117 00118 00119 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 00120 return get(Opcode).schedClass; 00121 } 00122 00123 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 00124 return get(Opcode).ImplicitUses; 00125 } 00126 00127 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 00128 return get(Opcode).ImplicitDefs; 00129 } 00130 00131 00132 // 00133 // Query instruction class flags according to the machine-independent 00134 // flags listed above. 00135 // 00136 bool isReturn(MachineOpCode Opcode) const { 00137 return get(Opcode).Flags & M_RET_FLAG; 00138 } 00139 00140 bool isTwoAddrInstr(MachineOpCode Opcode) const { 00141 return get(Opcode).Flags & M_2_ADDR_FLAG; 00142 } 00143 bool isTerminatorInstr(unsigned Opcode) const { 00144 return get(Opcode).Flags & M_TERMINATOR_FLAG; 00145 } 00146 00147 /// Return true if the instruction is a register to register move 00148 /// and leave the source and dest operands in the passed parameters. 00149 virtual bool isMoveInstr(const MachineInstr& MI, 00150 unsigned& sourceReg, 00151 unsigned& destReg) const { 00152 return false; 00153 } 00154 00155 /// Insert a goto (unconditional branch) sequence to TMBB, at the 00156 /// end of MBB 00157 virtual void insertGoto(MachineBasicBlock& MBB, 00158 MachineBasicBlock& TMBB) const { 00159 assert(0 && "Target didn't implement insertGoto!"); 00160 } 00161 00162 /// Reverses the branch condition of the MachineInstr pointed by 00163 /// MI. The instruction is replaced and the new MI is returned. 00164 virtual MachineBasicBlock::iterator 00165 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 00166 assert(0 && "Target didn't implement reverseBranchCondition!"); 00167 abort(); 00168 return MI; 00169 } 00170 00171 //------------------------------------------------------------------------- 00172 // Code generation support for creating individual machine instructions 00173 // 00174 // WARNING: These methods are Sparc specific 00175 // 00176 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 00177 // 00178 //------------------------------------------------------------------------- 00179 00180 unsigned getNumDelaySlots(MachineOpCode Opcode) const { 00181 return get(Opcode).numDelaySlots; 00182 } 00183 bool isCCInstr(MachineOpCode Opcode) const { 00184 return get(Opcode).Flags & M_CC_FLAG; 00185 } 00186 bool isNop(MachineOpCode Opcode) const { 00187 return get(Opcode).Flags & M_NOP_FLAG; 00188 } 00189 bool isBranch(MachineOpCode Opcode) const { 00190 return get(Opcode).Flags & M_BRANCH_FLAG; 00191 } 00192 /// isBarrier - Returns true if the specified instruction stops control flow 00193 /// from executing the instruction immediately following it. Examples include 00194 /// unconditional branches and return instructions. 00195 bool isBarrier(MachineOpCode Opcode) const { 00196 return get(Opcode).Flags & M_BARRIER_FLAG; 00197 } 00198 00199 bool isCall(MachineOpCode Opcode) const { 00200 return get(Opcode).Flags & M_CALL_FLAG; 00201 } 00202 bool isLoad(MachineOpCode Opcode) const { 00203 return get(Opcode).Flags & M_LOAD_FLAG; 00204 } 00205 bool isStore(MachineOpCode Opcode) const { 00206 return get(Opcode).Flags & M_STORE_FLAG; 00207 } 00208 00209 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 00210 /// which must be filled by the code generator. 00211 bool hasDelaySlot(unsigned Opcode) const { 00212 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 00213 } 00214 00215 virtual bool hasResultInterlock(MachineOpCode Opcode) const { 00216 return true; 00217 } 00218 00219 // 00220 // Latencies for individual instructions and instruction pairs 00221 // 00222 virtual int minLatency(MachineOpCode Opcode) const { 00223 return get(Opcode).latency; 00224 } 00225 00226 virtual int maxLatency(MachineOpCode Opcode) const { 00227 return get(Opcode).latency; 00228 } 00229 00230 // 00231 // Which operand holds an immediate constant? Returns -1 if none 00232 // 00233 virtual int getImmedConstantPos(MachineOpCode Opcode) const { 00234 return -1; // immediate position is machine specific, so say -1 == "none" 00235 } 00236 00237 // Check if the specified constant fits in the immediate field 00238 // of this machine instruction 00239 // 00240 virtual bool constantFitsInImmedField(MachineOpCode Opcode, 00241 int64_t intValue) const; 00242 00243 // Return the largest positive constant that can be held in the IMMED field 00244 // of this machine instruction. 00245 // isSignExtended is set to true if the value is sign-extended before use 00246 // (this is true for all immediate fields in SPARC instructions). 00247 // Return 0 if the instruction has no IMMED field. 00248 // 00249 virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 00250 bool &isSignExtended) const { 00251 isSignExtended = get(Opcode).immedIsSignExtended; 00252 return get(Opcode).maxImmedConst; 00253 } 00254 }; 00255 00256 } // End llvm namespace 00257 00258 #endif