LLVM API Documentation
00001 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file defines the X86 specific subclass of TargetMachine. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "X86TargetMachine.h" 00015 #include "X86.h" 00016 #include "llvm/Module.h" 00017 #include "llvm/PassManager.h" 00018 #include "llvm/CodeGen/IntrinsicLowering.h" 00019 #include "llvm/CodeGen/MachineFunction.h" 00020 #include "llvm/CodeGen/Passes.h" 00021 #include "llvm/Target/TargetOptions.h" 00022 #include "llvm/Target/TargetMachineRegistry.h" 00023 #include "llvm/Transforms/Scalar.h" 00024 #include "llvm/Support/CommandLine.h" 00025 #include "llvm/ADT/Statistic.h" 00026 using namespace llvm; 00027 00028 X86VectorEnum llvm::X86Vector = NoSSE; 00029 00030 /// X86TargetMachineModule - Note that this is used on hosts that cannot link 00031 /// in a library unless there are references into the library. In particular, 00032 /// it seems that it is not possible to get things to work on Win32 without 00033 /// this. Though it is unused, do not remove it. 00034 extern "C" int X86TargetMachineModule; 00035 int X86TargetMachineModule = 0; 00036 00037 namespace { 00038 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true), 00039 cl::desc("Disable the ssa-based peephole optimizer " 00040 "(defaults to disabled)")); 00041 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden, 00042 cl::desc("Disable the X86 asm printer, for use " 00043 "when profiling the code generator.")); 00044 00045 #if 0 00046 // FIXME: This should eventually be handled with target triples and 00047 // subtarget support! 00048 cl::opt<X86VectorEnum, true> 00049 SSEArg( 00050 cl::desc("Enable SSE support in the X86 target:"), 00051 cl::values( 00052 clEnumValN(SSE, "sse", " Enable SSE support"), 00053 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"), 00054 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"), 00055 clEnumValEnd), 00056 cl::location(X86Vector), cl::init(NoSSE)); 00057 #endif 00058 00059 // Register the target. 00060 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)"); 00061 } 00062 00063 unsigned X86TargetMachine::getJITMatchQuality() { 00064 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 00065 return 10; 00066 #else 00067 return 0; 00068 #endif 00069 } 00070 00071 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) { 00072 if (M.getEndianness() == Module::LittleEndian && 00073 M.getPointerSize() == Module::Pointer32) 00074 return 10; // Direct match 00075 else if (M.getEndianness() != Module::AnyEndianness || 00076 M.getPointerSize() != Module::AnyPointerSize) 00077 return 0; // Match for some other target 00078 00079 return getJITMatchQuality()/2; 00080 } 00081 00082 /// X86TargetMachine ctor - Create an ILP32 architecture model 00083 /// 00084 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL) 00085 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4), 00086 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -4), 00087 JITInfo(*this) { 00088 } 00089 00090 00091 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT 00092 // does to emit statically compiled machine code. 00093 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM, 00094 std::ostream &Out) { 00095 // FIXME: Implement efficient support for garbage collection intrinsics. 00096 PM.add(createLowerGCPass()); 00097 00098 // FIXME: Implement the invoke/unwind instructions! 00099 PM.add(createLowerInvokePass()); 00100 00101 // FIXME: Implement the switch instruction in the instruction selector! 00102 PM.add(createLowerSwitchPass()); 00103 00104 // Make sure that no unreachable blocks are instruction selected. 00105 PM.add(createUnreachableBlockEliminationPass()); 00106 00107 PM.add(createX86SimpleInstructionSelector(*this)); 00108 00109 // Run optional SSA-based machine code optimizations next... 00110 if (!NoSSAPeephole) 00111 PM.add(createX86SSAPeepholeOptimizerPass()); 00112 00113 // Print the instruction selected machine code... 00114 if (PrintMachineCode) 00115 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 00116 00117 // Perform register allocation to convert to a concrete x86 representation 00118 PM.add(createRegisterAllocator()); 00119 00120 if (PrintMachineCode) 00121 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 00122 00123 PM.add(createX86FloatingPointStackifierPass()); 00124 00125 if (PrintMachineCode) 00126 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 00127 00128 // Insert prolog/epilog code. Eliminate abstract frame index references... 00129 PM.add(createPrologEpilogCodeInserter()); 00130 00131 PM.add(createX86PeepholeOptimizerPass()); 00132 00133 if (PrintMachineCode) // Print the register-allocated code 00134 PM.add(createX86CodePrinterPass(std::cerr, *this)); 00135 00136 if (!DisableOutput) 00137 PM.add(createX86CodePrinterPass(Out, *this)); 00138 00139 // Delete machine code for this function 00140 PM.add(createMachineCodeDeleter()); 00141 00142 return false; // success! 00143 } 00144 00145 /// addPassesToJITCompile - Add passes to the specified pass manager to 00146 /// implement a fast dynamic compiler for this target. Return true if this is 00147 /// not supported for this target. 00148 /// 00149 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { 00150 // FIXME: Implement efficient support for garbage collection intrinsics. 00151 PM.add(createLowerGCPass()); 00152 00153 // FIXME: Implement the invoke/unwind instructions! 00154 PM.add(createLowerInvokePass()); 00155 00156 // FIXME: Implement the switch instruction in the instruction selector! 00157 PM.add(createLowerSwitchPass()); 00158 00159 // Make sure that no unreachable blocks are instruction selected. 00160 PM.add(createUnreachableBlockEliminationPass()); 00161 00162 PM.add(createX86SimpleInstructionSelector(TM)); 00163 00164 // Run optional SSA-based machine code optimizations next... 00165 if (!NoSSAPeephole) 00166 PM.add(createX86SSAPeepholeOptimizerPass()); 00167 00168 // FIXME: Add SSA based peephole optimizer here. 00169 00170 // Print the instruction selected machine code... 00171 if (PrintMachineCode) 00172 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 00173 00174 // Perform register allocation to convert to a concrete x86 representation 00175 PM.add(createRegisterAllocator()); 00176 00177 if (PrintMachineCode) 00178 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 00179 00180 PM.add(createX86FloatingPointStackifierPass()); 00181 00182 if (PrintMachineCode) 00183 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 00184 00185 // Insert prolog/epilog code. Eliminate abstract frame index references... 00186 PM.add(createPrologEpilogCodeInserter()); 00187 00188 PM.add(createX86PeepholeOptimizerPass()); 00189 00190 if (PrintMachineCode) // Print the register-allocated code 00191 PM.add(createX86CodePrinterPass(std::cerr, TM)); 00192 } 00193