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MRegisterInfo.cpp

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00001 //===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the MRegisterInfo interface.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "llvm/Target/MRegisterInfo.h"
00015 
00016 namespace llvm {
00017 
00018 MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
00019                              regclass_iterator RCB, regclass_iterator RCE,
00020            int CFSO, int CFDO)
00021   : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
00022   assert(NumRegs < FirstVirtualRegister &&
00023          "Target has too many physical registers!");
00024 
00025   CallFrameSetupOpcode   = CFSO;
00026   CallFrameDestroyOpcode = CFDO;
00027 }
00028 
00029 MRegisterInfo::~MRegisterInfo() {}
00030 
00031 std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
00032   std::vector<bool> Allocatable(NumRegs);
00033   for (MRegisterInfo::regclass_iterator I = regclass_begin(),
00034          E = regclass_end(); I != E; ++I) {
00035     const TargetRegisterClass *RC = *I;
00036     for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
00037            E = RC->allocation_order_end(MF); I != E; ++I)
00038       Allocatable[*I] = true;
00039   }
00040   return Allocatable;
00041 }  
00042 
00043 } // End llvm namespace