LLVM API Documentation
00001 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the declaration of the MachineInstr class, which is the 00011 // basic representation for all target dependent machine instructions used by 00012 // the back end. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #ifndef LLVM_CODEGEN_MACHINEINSTR_H 00017 #define LLVM_CODEGEN_MACHINEINSTR_H 00018 00019 #include "llvm/ADT/iterator" 00020 #include <vector> 00021 #include <cassert> 00022 00023 namespace llvm { 00024 00025 class Value; 00026 class Function; 00027 class MachineBasicBlock; 00028 class TargetMachine; 00029 class GlobalValue; 00030 00031 template <typename T> struct ilist_traits; 00032 template <typename T> struct ilist; 00033 00034 typedef short MachineOpCode; 00035 00036 //===----------------------------------------------------------------------===// 00037 // class MachineOperand 00038 // 00039 // Purpose: 00040 // Representation of each machine instruction operand. 00041 // This class is designed so that you can allocate a vector of operands 00042 // first and initialize each one later. 00043 // 00044 // E.g, for this VM instruction: 00045 // ptr = alloca type, numElements 00046 // we generate 2 machine instructions on the SPARC: 00047 // 00048 // mul Constant, Numelements -> Reg 00049 // add %sp, Reg -> Ptr 00050 // 00051 // Each instruction has 3 operands, listed above. Of those: 00052 // - Reg, NumElements, and Ptr are of operand type MO_Register. 00053 // - Constant is of operand type MO_SignExtendedImmed on the SPARC. 00054 // 00055 // For the register operands, the virtual register type is as follows: 00056 // 00057 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field 00058 // MachineInstr* minstr will point to the instruction that computes reg. 00059 // 00060 // - %sp will be of virtual register type MO_MachineReg. 00061 // The field regNum identifies the machine register. 00062 // 00063 // - NumElements will be of virtual register type MO_VirtualReg. 00064 // The field Value* value identifies the value. 00065 // 00066 // - Ptr will also be of virtual register type MO_VirtualReg. 00067 // Again, the field Value* value identifies the value. 00068 // 00069 //===----------------------------------------------------------------------===// 00070 00071 struct MachineOperand { 00072 private: 00073 // Bit fields of the flags variable used for different operand properties 00074 enum { 00075 DEFFLAG = 0x01, // this is a def of the operand 00076 USEFLAG = 0x02, // this is a use of the operand 00077 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) 00078 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) 00079 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) 00080 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) 00081 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address 00082 }; 00083 00084 public: 00085 // UseType - This enum describes how the machine operand is used by 00086 // the instruction. Note that the MachineInstr/Operator class 00087 // currently uses bool arguments to represent this information 00088 // instead of an enum. Eventually this should change over to use 00089 // this _easier to read_ representation instead. 00090 // 00091 enum UseType { 00092 Use = USEFLAG, /// only read 00093 Def = DEFFLAG, /// only written 00094 UseAndDef = Use | Def /// read AND written 00095 }; 00096 00097 enum MachineOperandType { 00098 MO_VirtualRegister, // virtual register for *value 00099 MO_MachineRegister, // pre-assigned machine register `regNum' 00100 MO_CCRegister, 00101 MO_SignExtendedImmed, 00102 MO_UnextendedImmed, 00103 MO_PCRelativeDisp, 00104 MO_MachineBasicBlock, // MachineBasicBlock reference 00105 MO_FrameIndex, // Abstract Stack Frame Index 00106 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool 00107 MO_ExternalSymbol, // Name of external global symbol 00108 MO_GlobalAddress, // Address of a global value 00109 }; 00110 00111 private: 00112 union { 00113 Value* value; // BasicBlockVal for a label operand. 00114 // ConstantVal for a non-address immediate. 00115 // Virtual register for an SSA operand, 00116 // including hidden operands required for 00117 // the generated machine code. 00118 // LLVM global for MO_GlobalAddress. 00119 00120 int immedVal; // Constant value for an explicit constant 00121 00122 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type 00123 const char *SymbolName; // For MO_ExternalSymbol type 00124 } contents; 00125 00126 char flags; // see bit field definitions above 00127 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. 00128 union { 00129 int regNum; // register number for an explicit register 00130 // will be set for a value after reg allocation 00131 00132 int offset; // Offset to address of global or external, only 00133 // valid for MO_GlobalAddress and MO_ExternalSym 00134 } extra; 00135 00136 void zeroContents () { 00137 memset (&contents, 0, sizeof (contents)); 00138 memset (&extra, 0, sizeof (extra)); 00139 } 00140 00141 MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister) 00142 : flags(0), opType(OpTy) { 00143 zeroContents (); 00144 contents.immedVal = ImmVal; 00145 extra.regNum = -1; 00146 } 00147 00148 MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) 00149 : flags(UseTy), opType(OpTy) { 00150 zeroContents (); 00151 extra.regNum = Reg; 00152 } 00153 00154 MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy, 00155 bool isPCRelative = false) 00156 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { 00157 assert(OpTy != MachineOperand::MO_GlobalAddress); 00158 zeroContents(); 00159 contents.value = V; 00160 extra.regNum = -1; 00161 } 00162 00163 MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy, 00164 bool isPCRelative = false, int Offset = 0) 00165 : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { 00166 assert(OpTy == MachineOperand::MO_GlobalAddress); 00167 zeroContents (); 00168 contents.value = (Value*)V; 00169 extra.offset = Offset; 00170 } 00171 00172 MachineOperand(MachineBasicBlock *mbb) 00173 : flags(0), opType(MO_MachineBasicBlock) { 00174 zeroContents (); 00175 contents.MBB = mbb; 00176 extra.regNum = -1; 00177 } 00178 00179 MachineOperand(const char *SymName, bool isPCRelative, int Offset) 00180 : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) { 00181 zeroContents (); 00182 contents.SymbolName = SymName; 00183 extra.offset = Offset; 00184 } 00185 00186 public: 00187 MachineOperand(const MachineOperand &M) 00188 : flags(M.flags), opType(M.opType) { 00189 zeroContents (); 00190 contents = M.contents; 00191 extra = M.extra; 00192 } 00193 00194 00195 ~MachineOperand() {} 00196 00197 const MachineOperand &operator=(const MachineOperand &MO) { 00198 contents = MO.contents; 00199 flags = MO.flags; 00200 opType = MO.opType; 00201 extra = MO.extra; 00202 return *this; 00203 } 00204 00205 /// getType - Returns the MachineOperandType for this operand. 00206 /// 00207 MachineOperandType getType() const { return opType; } 00208 00209 /// getUseType - Returns the MachineOperandUseType of this operand. 00210 /// 00211 UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } 00212 00213 /// isPCRelative - This returns the value of the PCRELATIVE flag, which 00214 /// indicates whether this operand should be emitted as a PC relative value 00215 /// instead of a global address. This is used for operands of the forms: 00216 /// MachineBasicBlock, GlobalAddress, ExternalSymbol 00217 /// 00218 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } 00219 00220 /// isRegister - Return true if this operand is a register operand. The X86 00221 /// backend currently can't decide whether to use MO_MR or MO_VR to represent 00222 /// them, so we accept both. 00223 /// 00224 /// Note: The sparc backend should not use this method. 00225 /// 00226 bool isRegister() const { 00227 return opType == MO_MachineRegister || opType == MO_VirtualRegister; 00228 } 00229 00230 /// Accessors that tell you what kind of MachineOperand you're looking at. 00231 /// 00232 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } 00233 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } 00234 bool isImmediate() const { 00235 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; 00236 } 00237 bool isFrameIndex() const { return opType == MO_FrameIndex; } 00238 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } 00239 bool isGlobalAddress() const { return opType == MO_GlobalAddress; } 00240 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } 00241 00242 /// getVRegValueOrNull - Get the Value* out of a MachineOperand if it 00243 /// has one. This is deprecated and only used by the SPARC v9 backend. 00244 /// 00245 Value* getVRegValueOrNull() const { 00246 return (opType == MO_VirtualRegister || opType == MO_CCRegister || 00247 isPCRelativeDisp()) ? contents.value : NULL; 00248 } 00249 00250 /// MachineOperand accessors that only work on certain types of 00251 /// MachineOperand... 00252 /// 00253 Value* getVRegValue() const { 00254 assert ((opType == MO_VirtualRegister || opType == MO_CCRegister 00255 || isPCRelativeDisp()) && "Wrong MachineOperand accessor"); 00256 return contents.value; 00257 } 00258 int getMachineRegNum() const { 00259 assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor"); 00260 return extra.regNum; 00261 } 00262 int getImmedValue() const { 00263 assert(isImmediate() && "Wrong MachineOperand accessor"); 00264 return contents.immedVal; 00265 } 00266 MachineBasicBlock *getMachineBasicBlock() const { 00267 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 00268 return contents.MBB; 00269 } 00270 void setMachineBasicBlock(MachineBasicBlock *MBB) { 00271 assert(isMachineBasicBlock() && "Wrong MachineOperand accessor"); 00272 contents.MBB = MBB; 00273 } 00274 int getFrameIndex() const { 00275 assert(isFrameIndex() && "Wrong MachineOperand accessor"); 00276 return contents.immedVal; 00277 } 00278 unsigned getConstantPoolIndex() const { 00279 assert(isConstantPoolIndex() && "Wrong MachineOperand accessor"); 00280 return contents.immedVal; 00281 } 00282 GlobalValue *getGlobal() const { 00283 assert(isGlobalAddress() && "Wrong MachineOperand accessor"); 00284 return (GlobalValue*)contents.value; 00285 } 00286 int getOffset() const { 00287 assert((isGlobalAddress() || isExternalSymbol()) && 00288 "Wrong MachineOperand accessor"); 00289 return extra.offset; 00290 } 00291 const char *getSymbolName() const { 00292 assert(isExternalSymbol() && "Wrong MachineOperand accessor"); 00293 return contents.SymbolName; 00294 } 00295 00296 /// MachineOperand methods for testing that work on any kind of 00297 /// MachineOperand... 00298 /// 00299 bool isUse () const { return flags & USEFLAG; } 00300 MachineOperand& setUse () { flags |= USEFLAG; return *this; } 00301 bool isDef () const { return flags & DEFFLAG; } 00302 MachineOperand& setDef () { flags |= DEFFLAG; return *this; } 00303 bool isHiBits32 () const { return flags & HIFLAG32; } 00304 bool isLoBits32 () const { return flags & LOFLAG32; } 00305 bool isHiBits64 () const { return flags & HIFLAG64; } 00306 bool isLoBits64 () const { return flags & LOFLAG64; } 00307 00308 /// hasAllocatedReg - Returns true iff a machine register has been 00309 /// allocated to this operand. 00310 /// 00311 bool hasAllocatedReg() const { 00312 return (extra.regNum >= 0 && 00313 (opType == MO_VirtualRegister || opType == MO_CCRegister || 00314 opType == MO_MachineRegister)); 00315 } 00316 00317 /// getReg - Returns the register number. It is a runtime error to call this 00318 /// if a register is not allocated. 00319 /// 00320 unsigned getReg() const { 00321 assert(hasAllocatedReg()); 00322 return extra.regNum; 00323 } 00324 00325 /// MachineOperand mutators... 00326 /// 00327 void setReg(unsigned Reg) { 00328 // This method's comment used to say: 'TODO: get rid of this duplicate 00329 // code.' It's not clear where the duplication is. 00330 assert(hasAllocatedReg() && "This operand cannot have a register number!"); 00331 extra.regNum = Reg; 00332 } 00333 00334 void setValueReg(Value *val) { 00335 assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*"); 00336 contents.value = val; 00337 } 00338 00339 void setImmedValue(int immVal) { 00340 assert(isImmediate() && "Wrong MachineOperand mutator"); 00341 contents.immedVal = immVal; 00342 } 00343 00344 void setOffset(int Offset) { 00345 assert((isGlobalAddress() || isExternalSymbol()) && 00346 "Wrong MachineOperand accessor"); 00347 extra.offset = Offset; 00348 } 00349 00350 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); 00351 00352 /// markHi32, markLo32, etc. - These methods are deprecated and only used by 00353 /// the SPARC v9 back-end. 00354 /// 00355 void markHi32() { flags |= HIFLAG32; } 00356 void markLo32() { flags |= LOFLAG32; } 00357 void markHi64() { flags |= HIFLAG64; } 00358 void markLo64() { flags |= LOFLAG64; } 00359 00360 private: 00361 /// setRegForValue - Replaces the Value with its corresponding physical 00362 /// register after register allocation is complete. This is deprecated 00363 /// and only used by the SPARC v9 back-end. 00364 /// 00365 void setRegForValue(int reg) { 00366 assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 00367 opType == MO_MachineRegister); 00368 extra.regNum = reg; 00369 } 00370 00371 friend class MachineInstr; 00372 }; 00373 00374 00375 //===----------------------------------------------------------------------===// 00376 // class MachineInstr 00377 // 00378 // Purpose: 00379 // Representation of each machine instruction. 00380 // 00381 // MachineOpCode must be an enum, defined separately for each target. 00382 // E.g., It is defined in SparcInstructionSelection.h for the SPARC. 00383 // 00384 // There are 2 kinds of operands: 00385 // 00386 // (1) Explicit operands of the machine instruction in vector operands[] 00387 // 00388 // (2) "Implicit operands" are values implicitly used or defined by the 00389 // machine instruction, such as arguments to a CALL, return value of 00390 // a CALL (if any), and return value of a RETURN. 00391 //===----------------------------------------------------------------------===// 00392 00393 class MachineInstr { 00394 short Opcode; // the opcode 00395 unsigned char numImplicitRefs; // number of implicit operands 00396 std::vector<MachineOperand> operands; // the operands 00397 MachineInstr* prev, *next; // links for our intrusive list 00398 MachineBasicBlock* parent; // pointer to the owning basic block 00399 00400 // OperandComplete - Return true if it's illegal to add a new operand 00401 bool OperandsComplete() const; 00402 00403 //Constructor used by clone() method 00404 MachineInstr(const MachineInstr&); 00405 00406 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 00407 00408 // Intrusive list support 00409 // 00410 friend struct ilist_traits<MachineInstr>; 00411 00412 public: 00413 MachineInstr(short Opcode, unsigned numOperands); 00414 00415 /// MachineInstr ctor - This constructor only does a _reserve_ of the 00416 /// operands, not a resize for them. It is expected that if you use this that 00417 /// you call add* methods below to fill up the operands, instead of the Set 00418 /// methods. Eventually, the "resizing" ctors will be phased out. 00419 /// 00420 MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY); 00421 00422 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 00423 /// the MachineInstr is created and added to the end of the specified basic 00424 /// block. 00425 /// 00426 MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps); 00427 00428 ~MachineInstr(); 00429 00430 const MachineBasicBlock* getParent() const { return parent; } 00431 MachineBasicBlock* getParent() { return parent; } 00432 00433 /// getOpcode - Returns the opcode of this MachineInstr. 00434 /// 00435 const int getOpcode() const { return Opcode; } 00436 00437 /// Access to explicit operands of the instruction. 00438 /// 00439 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; } 00440 00441 const MachineOperand& getOperand(unsigned i) const { 00442 assert(i < getNumOperands() && "getOperand() out of range!"); 00443 return operands[i]; 00444 } 00445 MachineOperand& getOperand(unsigned i) { 00446 assert(i < getNumOperands() && "getOperand() out of range!"); 00447 return operands[i]; 00448 } 00449 00450 // 00451 // Access to explicit or implicit operands of the instruction 00452 // This returns the i'th entry in the operand vector. 00453 // That represents the i'th explicit operand or the (i-N)'th implicit operand, 00454 // depending on whether i < N or i >= N. 00455 // 00456 const MachineOperand& getExplOrImplOperand(unsigned i) const { 00457 assert(i < operands.size() && "getExplOrImplOperand() out of range!"); 00458 return (i < getNumOperands()? getOperand(i) 00459 : getImplicitOp(i - getNumOperands())); 00460 } 00461 00462 // 00463 // Access to implicit operands of the instruction 00464 // 00465 unsigned getNumImplicitRefs() const{ return numImplicitRefs; } 00466 00467 MachineOperand& getImplicitOp(unsigned i) { 00468 assert(i < numImplicitRefs && "implicit ref# out of range!"); 00469 return operands[i + operands.size() - numImplicitRefs]; 00470 } 00471 const MachineOperand& getImplicitOp(unsigned i) const { 00472 assert(i < numImplicitRefs && "implicit ref# out of range!"); 00473 return operands[i + operands.size() - numImplicitRefs]; 00474 } 00475 00476 Value* getImplicitRef(unsigned i) { 00477 return getImplicitOp(i).getVRegValue(); 00478 } 00479 const Value* getImplicitRef(unsigned i) const { 00480 return getImplicitOp(i).getVRegValue(); 00481 } 00482 00483 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) { 00484 ++numImplicitRefs; 00485 addRegOperand(V, isDef, isDefAndUse); 00486 } 00487 void setImplicitRef(unsigned i, Value* V) { 00488 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!"); 00489 SetMachineOperandVal(i + getNumOperands(), 00490 MachineOperand::MO_VirtualRegister, V); 00491 } 00492 00493 /// clone - Create a copy of 'this' instruction that is identical in 00494 /// all ways except the the instruction has no parent, prev, or next. 00495 MachineInstr* clone() const; 00496 00497 // 00498 // Debugging support 00499 // 00500 void print(std::ostream &OS, const TargetMachine *TM) const; 00501 void dump() const; 00502 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); 00503 00504 // 00505 // Define iterators to access the Value operands of the Machine Instruction. 00506 // Note that these iterators only enumerate the explicit operands. 00507 // begin() and end() are defined to produce these iterators... 00508 // 00509 template<class _MI, class _V> class ValOpIterator; 00510 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator; 00511 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator; 00512 00513 00514 //===--------------------------------------------------------------------===// 00515 // Accessors to add operands when building up machine instructions 00516 // 00517 00518 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the 00519 /// operands list... 00520 /// 00521 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { 00522 assert(!OperandsComplete() && 00523 "Trying to add an operand to a machine instr that is already done!"); 00524 operands.push_back( 00525 MachineOperand(V, MachineOperand::MO_VirtualRegister, 00526 !isDef ? MachineOperand::Use : 00527 (isDefAndUse ? MachineOperand::UseAndDef : 00528 MachineOperand::Def))); 00529 } 00530 00531 void addRegOperand(Value *V, 00532 MachineOperand::UseType UTy = MachineOperand::Use, 00533 bool isPCRelative = false) { 00534 assert(!OperandsComplete() && 00535 "Trying to add an operand to a machine instr that is already done!"); 00536 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, 00537 UTy, isPCRelative)); 00538 } 00539 00540 void addCCRegOperand(Value *V, 00541 MachineOperand::UseType UTy = MachineOperand::Use) { 00542 assert(!OperandsComplete() && 00543 "Trying to add an operand to a machine instr that is already done!"); 00544 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, 00545 false)); 00546 } 00547 00548 00549 /// addRegOperand - Add a symbolic virtual register reference... 00550 /// 00551 void addRegOperand(int reg, bool isDef) { 00552 assert(!OperandsComplete() && 00553 "Trying to add an operand to a machine instr that is already done!"); 00554 operands.push_back( 00555 MachineOperand(reg, MachineOperand::MO_VirtualRegister, 00556 isDef ? MachineOperand::Def : MachineOperand::Use)); 00557 } 00558 00559 /// addRegOperand - Add a symbolic virtual register reference... 00560 /// 00561 void addRegOperand(int reg, 00562 MachineOperand::UseType UTy = MachineOperand::Use) { 00563 assert(!OperandsComplete() && 00564 "Trying to add an operand to a machine instr that is already done!"); 00565 operands.push_back( 00566 MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); 00567 } 00568 00569 /// addPCDispOperand - Add a PC relative displacement operand to the MI 00570 /// 00571 void addPCDispOperand(Value *V) { 00572 assert(!OperandsComplete() && 00573 "Trying to add an operand to a machine instr that is already done!"); 00574 operands.push_back( 00575 MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use)); 00576 } 00577 00578 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 00579 /// 00580 void addMachineRegOperand(int reg, bool isDef) { 00581 assert(!OperandsComplete() && 00582 "Trying to add an operand to a machine instr that is already done!"); 00583 operands.push_back( 00584 MachineOperand(reg, MachineOperand::MO_MachineRegister, 00585 isDef ? MachineOperand::Def : MachineOperand::Use)); 00586 } 00587 00588 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr 00589 /// 00590 void addMachineRegOperand(int reg, 00591 MachineOperand::UseType UTy = MachineOperand::Use) { 00592 assert(!OperandsComplete() && 00593 "Trying to add an operand to a machine instr that is already done!"); 00594 operands.push_back( 00595 MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy)); 00596 } 00597 00598 /// addZeroExtImmOperand - Add a zero extended constant argument to the 00599 /// machine instruction. 00600 /// 00601 void addZeroExtImmOperand(int intValue) { 00602 assert(!OperandsComplete() && 00603 "Trying to add an operand to a machine instr that is already done!"); 00604 operands.push_back( 00605 MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); 00606 } 00607 00608 /// addSignExtImmOperand - Add a zero extended constant argument to the 00609 /// machine instruction. 00610 /// 00611 void addSignExtImmOperand(int intValue) { 00612 assert(!OperandsComplete() && 00613 "Trying to add an operand to a machine instr that is already done!"); 00614 operands.push_back( 00615 MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed)); 00616 } 00617 00618 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { 00619 assert(!OperandsComplete() && 00620 "Trying to add an operand to a machine instr that is already done!"); 00621 operands.push_back(MachineOperand(MBB)); 00622 } 00623 00624 /// addFrameIndexOperand - Add an abstract frame index to the instruction 00625 /// 00626 void addFrameIndexOperand(unsigned Idx) { 00627 assert(!OperandsComplete() && 00628 "Trying to add an operand to a machine instr that is already done!"); 00629 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); 00630 } 00631 00632 /// addConstantPoolndexOperand - Add a constant pool object index to the 00633 /// instruction. 00634 /// 00635 void addConstantPoolIndexOperand(unsigned I) { 00636 assert(!OperandsComplete() && 00637 "Trying to add an operand to a machine instr that is already done!"); 00638 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); 00639 } 00640 00641 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) { 00642 assert(!OperandsComplete() && 00643 "Trying to add an operand to a machine instr that is already done!"); 00644 operands.push_back( 00645 MachineOperand(GV, MachineOperand::MO_GlobalAddress, 00646 MachineOperand::Use, isPCRelative, Offset)); 00647 } 00648 00649 /// addExternalSymbolOperand - Add an external symbol operand to this instr 00650 /// 00651 void addExternalSymbolOperand(const char *SymName, bool isPCRelative) { 00652 operands.push_back(MachineOperand(SymName, isPCRelative, 0)); 00653 } 00654 00655 //===--------------------------------------------------------------------===// 00656 // Accessors used to modify instructions in place. 00657 // 00658 // FIXME: Move this stuff to MachineOperand itself! 00659 00660 /// replace - Support to rewrite a machine instruction in place: for now, 00661 /// simply replace() and then set new operands with Set.*Operand methods 00662 /// below. 00663 /// 00664 void replace(short Opcode, unsigned numOperands); 00665 00666 /// setOpcode - Replace the opcode of the current instruction with a new one. 00667 /// 00668 void setOpcode(unsigned Op) { Opcode = Op; } 00669 00670 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 00671 /// fewer operand than it started with. 00672 /// 00673 void RemoveOperand(unsigned i) { 00674 operands.erase(operands.begin()+i); 00675 } 00676 00677 // Access to set the operands when building the machine instruction 00678 // 00679 void SetMachineOperandVal(unsigned i, 00680 MachineOperand::MachineOperandType operandType, 00681 Value* V); 00682 00683 void SetMachineOperandConst(unsigned i, 00684 MachineOperand::MachineOperandType operandType, 00685 int intValue); 00686 00687 void SetMachineOperandReg(unsigned i, int regNum); 00688 00689 00690 unsigned substituteValue(const Value* oldVal, Value* newVal, 00691 bool defsOnly, bool notDefsAndUses, 00692 bool& someArgsWereIgnored); 00693 00694 // SetRegForOperand - 00695 // SetRegForImplicitRef - 00696 // Mark an explicit or implicit operand with its allocated physical register. 00697 // 00698 void SetRegForOperand(unsigned i, int regNum); 00699 void SetRegForImplicitRef(unsigned i, int regNum); 00700 00701 // 00702 // Iterator to enumerate machine operands. 00703 // 00704 template<class MITy, class VTy> 00705 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { 00706 unsigned i; 00707 MITy MI; 00708 00709 void skipToNextVal() { 00710 while (i < MI->getNumOperands() && 00711 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister || 00712 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister) 00713 && MI->getOperand(i).getVRegValue() != 0)) 00714 ++i; 00715 } 00716 00717 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) { 00718 skipToNextVal(); 00719 } 00720 00721 public: 00722 typedef ValOpIterator<MITy, VTy> _Self; 00723 00724 inline VTy operator*() const { 00725 return MI->getOperand(i).getVRegValue(); 00726 } 00727 00728 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);} 00729 MachineOperand &getMachineOperand() { return MI->getOperand(i);} 00730 00731 inline VTy operator->() const { return operator*(); } 00732 00733 inline bool isUse() const { return MI->getOperand(i).isUse(); } 00734 inline bool isDef() const { return MI->getOperand(i).isDef(); } 00735 00736 inline _Self& operator++() { i++; skipToNextVal(); return *this; } 00737 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; } 00738 00739 inline bool operator==(const _Self &y) const { 00740 return i == y.i; 00741 } 00742 inline bool operator!=(const _Self &y) const { 00743 return !operator==(y); 00744 } 00745 00746 static _Self begin(MITy MI) { 00747 return _Self(MI, 0); 00748 } 00749 static _Self end(MITy MI) { 00750 return _Self(MI, MI->getNumOperands()); 00751 } 00752 }; 00753 00754 // define begin() and end() 00755 val_op_iterator begin() { return val_op_iterator::begin(this); } 00756 val_op_iterator end() { return val_op_iterator::end(this); } 00757 00758 const_val_op_iterator begin() const { 00759 return const_val_op_iterator::begin(this); 00760 } 00761 const_val_op_iterator end() const { 00762 return const_val_op_iterator::end(this); 00763 } 00764 }; 00765 00766 //===----------------------------------------------------------------------===// 00767 // Debugging Support 00768 00769 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI); 00770 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO); 00771 void PrintMachineInstructions(const Function *F); 00772 00773 } // End llvm namespace 00774 00775 #endif