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SparcV9RegisterInfo.h

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00001 //===- SparcV9RegisterInfo.h - SparcV9 Register Information Impl -*- C++ -*-==//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the SparcV9 implementation of the MRegisterInfo class.
00011 // It also contains stuff needed to instantiate that class, which would
00012 // ordinarily be provided by TableGen.
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #ifndef SPARCV9REGISTERINFO_H
00017 #define SPARCV9REGISTERINFO_H
00018 
00019 #include "llvm/Target/MRegisterInfo.h"
00020 
00021 namespace llvm {
00022 
00023 struct SparcV9RegisterInfo : public MRegisterInfo {
00024   SparcV9RegisterInfo ();
00025   const unsigned *getCalleeSaveRegs() const;
00026 
00027   // The rest of these are stubs... for now.
00028   void storeRegToStackSlot(MachineBasicBlock &MBB,
00029                            MachineBasicBlock::iterator MI,
00030                            unsigned SrcReg, int FrameIndex) const;
00031   void loadRegFromStackSlot(MachineBasicBlock &MBB,
00032                             MachineBasicBlock::iterator MI,
00033                             unsigned DestReg, int FrameIndex) const;
00034   void copyRegToReg(MachineBasicBlock &MBB,
00035                     MachineBasicBlock::iterator MI,
00036                     unsigned DestReg, unsigned SrcReg,
00037                     const TargetRegisterClass *RC) const;
00038   void eliminateFrameIndex (MachineBasicBlock::iterator MI) const;
00039   void emitPrologue (MachineFunction &MF) const;
00040   void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const;
00041 };
00042 
00043 } // End llvm namespace
00044 
00045 //===----------------------------------------------------------------------===//
00046 //
00047 // The second section of this file (immediately following) contains
00048 // a *handwritten* SparcV9 unified register number enumeration, which
00049 // provides a flat namespace containing all the SparcV9 unified
00050 // register numbers.
00051 //
00052 // It would ordinarily be contained in the file SparcV9GenRegisterNames.inc
00053 // if we were using TableGen to generate the register file description
00054 // automatically.
00055 //
00056 //===----------------------------------------------------------------------===//
00057 
00058 namespace llvm {
00059   namespace SparcV9 {
00060     enum {
00061     // FIXME - Register 0 is not a "non-register" like it is on other targets!!
00062 
00063     // SparcV9IntRegClass(IntRegClassID)
00064     // - unified register numbers 0 ... 31 (32 regs)
00065     /* 0  */ o0, o1, o2, o3, o4,
00066     /* 5  */ o5, o7, l0, l1, l2,
00067     /* 10 */ l3, l4, l5, l6, l7,
00068     /* 15 */ i0, i1, i2, i3, i4,
00069     /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero 
00070     /* 25 */ g2, g3, g4, g5, g6,
00071     /* 30 */ g7, o6,             // o6 is stack ptr
00072 
00073     // SparcV9FloatRegClass(FloatRegClassID)
00074     // - regs 32 .. 63 are FPSingleRegType, 64 .. 95 are FPDoubleRegType
00075     // - unified register numbers 32 ... 95 (64 regs)
00076     /* 32 */ f0,  f1,  f2,
00077     /* 35 */ f3,  f4,  f5,  f6,  f7,
00078     /* 40 */ f8,  f9,  f10, f11, f12,
00079     /* 45 */ f13, f14, f15, f16, f17,
00080     /* 50 */ f18, f19, f20, f21, f22,
00081     /* 55 */ f23, f24, f25, f26, f27,
00082     /* 60 */ f28, f29, f30, f31, f32,
00083     /* 65 */ f33, f34, f35, f36, f37,
00084     /* 70 */ f38, f39, f40, f41, f42,
00085     /* 75 */ f43, f44, f45, f46, f47,
00086     /* 80 */ f48, f49, f50, f51, f52,
00087     /* 85 */ f53, f54, f55, f56, f57,
00088     /* 90 */ f58, f59, f60, f61, f62,
00089     /* 95 */ f63,
00090 
00091     // SparcV9IntCCRegClass(IntCCRegClassID) 
00092     // - unified register numbers 96 ... 98 (3 regs)
00093     /* 96 */ xcc, icc, ccr,
00094 
00095     // SparcV9FloatCCRegClass(FloatCCRegClassID)
00096     // - unified register numbers 99 ... 102 (4 regs)
00097     /* 99 */ fcc0, fcc1, fcc2, fcc3,
00098 
00099     // SparcV9SpecialRegClass(SpecialRegClassID)
00100     // - unified register number 103  (1 reg)
00101     /* 103 */ fsr
00102     };
00103   } // end namespace SparcV9
00104 } // end namespace llvm
00105 
00106 #endif // SPARCV9REGISTERINFO_H