LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Assembly Writer Source Fragment 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 /// printInstruction - This method is automatically generated by tablegen 00010 /// from the instruction set description. This method returns true if the 00011 /// machine instruction was sufficiently described to print it, otherwise 00012 /// it returns false. 00013 bool X86IntelAsmPrinter::printInstruction(const MachineInstr *MI) { 00014 switch (MI->getOpcode()) { 00015 default: return false; 00016 case X86::ADC32mi: O << "adc" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00017 case X86::ADC32mi8: O << "adc" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00018 case X86::ADC32mr: O << "adc" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00019 case X86::ADC32ri: O << "adc" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00020 case X86::ADC32ri8: O << "adc" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00021 case X86::ADC32rm: O << "adc" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00022 case X86::ADC32rr: O << "adc" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00023 case X86::ADD16mi: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00024 case X86::ADD16mi8: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00025 case X86::ADD16mr: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00026 case X86::ADD16ri: O << "add" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00027 case X86::ADD16ri8: O << "add" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00028 case X86::ADD16rm: O << "add" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00029 case X86::ADD16rr: O << "add" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00030 case X86::ADD32mi: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00031 case X86::ADD32mi8: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00032 case X86::ADD32mr: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00033 case X86::ADD32ri: O << "add" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00034 case X86::ADD32ri8: O << "add" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00035 case X86::ADD32rm: O << "add" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00036 case X86::ADD32rr: O << "add" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00037 case X86::ADD8mi: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00038 case X86::ADD8mr: O << "add" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00039 case X86::ADD8ri: O << "add" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00040 case X86::ADD8rm: O << "add" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00041 case X86::ADD8rr: O << "add" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00042 case X86::ADJCALLSTACKDOWN: O << "#ADJCALLSTACKDOWN" << '\n'; break; 00043 case X86::ADJCALLSTACKUP: O << "#ADJCALLSTACKUP" << '\n'; break; 00044 case X86::AND16mi: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00045 case X86::AND16mi8: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00046 case X86::AND16mr: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00047 case X86::AND16ri: O << "and" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00048 case X86::AND16ri8: O << "and" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00049 case X86::AND16rm: O << "and" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00050 case X86::AND16rr: O << "and" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00051 case X86::AND32mi: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00052 case X86::AND32mi8: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00053 case X86::AND32mr: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00054 case X86::AND32ri: O << "and" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00055 case X86::AND32ri8: O << "and" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00056 case X86::AND32rm: O << "and" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00057 case X86::AND32rr: O << "and" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00058 case X86::AND8mi: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00059 case X86::AND8mr: O << "and" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00060 case X86::AND8ri: O << "and" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00061 case X86::AND8rm: O << "and" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00062 case X86::AND8rr: O << "and" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00063 case X86::BSWAP32r: O << "bswap" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00064 case X86::CALL32m: O << "call "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00065 case X86::CALL32r: O << "call "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00066 case X86::CALLpcrel32: O << "call "; printCallOperand(MI, 0, MVT::i32); O << '\n'; break; 00067 case X86::CBW: O << "cbw" << '\n'; break; 00068 case X86::CDQ: O << "cdq" << '\n'; break; 00069 case X86::CMOVA16rm: O << "cmova "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00070 case X86::CMOVA16rr: O << "cmova "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00071 case X86::CMOVA32rm: O << "cmova "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00072 case X86::CMOVA32rr: O << "cmova "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00073 case X86::CMOVAE16rm: O << "cmovae "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00074 case X86::CMOVAE16rr: O << "cmovae "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00075 case X86::CMOVAE32rm: O << "cmovae "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00076 case X86::CMOVAE32rr: O << "cmovae "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00077 case X86::CMOVB16rm: O << "cmovb "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00078 case X86::CMOVB16rr: O << "cmovb "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00079 case X86::CMOVB32rm: O << "cmovb "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00080 case X86::CMOVB32rr: O << "cmovb "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00081 case X86::CMOVBE16rm: O << "cmovbe "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00082 case X86::CMOVBE16rr: O << "cmovbe "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00083 case X86::CMOVBE32rm: O << "cmovbe "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00084 case X86::CMOVBE32rr: O << "cmovbe "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00085 case X86::CMOVE16rm: O << "cmove "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00086 case X86::CMOVE16rr: O << "cmove "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00087 case X86::CMOVE32rm: O << "cmove "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00088 case X86::CMOVE32rr: O << "cmove "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00089 case X86::CMOVG16rm: O << "cmovg "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00090 case X86::CMOVG16rr: O << "cmovg "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00091 case X86::CMOVG32rm: O << "cmovg "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00092 case X86::CMOVG32rr: O << "cmovg "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00093 case X86::CMOVGE16rm: O << "cmovge "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00094 case X86::CMOVGE16rr: O << "cmovge "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00095 case X86::CMOVGE32rm: O << "cmovge "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00096 case X86::CMOVGE32rr: O << "cmovge "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00097 case X86::CMOVL16rm: O << "cmovl "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00098 case X86::CMOVL16rr: O << "cmovl "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00099 case X86::CMOVL32rm: O << "cmovl "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00100 case X86::CMOVL32rr: O << "cmovl "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00101 case X86::CMOVLE16rm: O << "cmovle "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00102 case X86::CMOVLE16rr: O << "cmovle "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00103 case X86::CMOVLE32rm: O << "cmovle "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00104 case X86::CMOVLE32rr: O << "cmovle "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00105 case X86::CMOVNE16rm: O << "cmovne "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00106 case X86::CMOVNE16rr: O << "cmovne "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00107 case X86::CMOVNE32rm: O << "cmovne "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00108 case X86::CMOVNE32rr: O << "cmovne "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00109 case X86::CMOVNS16rm: O << "cmovns "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00110 case X86::CMOVNS16rr: O << "cmovns "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00111 case X86::CMOVNS32rm: O << "cmovns "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00112 case X86::CMOVNS32rr: O << "cmovns "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00113 case X86::CMOVS16rm: O << "cmovs "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00114 case X86::CMOVS16rr: O << "cmovs "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00115 case X86::CMOVS32rm: O << "cmovs "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00116 case X86::CMOVS32rr: O << "cmovs "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00117 case X86::CMP16mi: O << "cmp" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00118 case X86::CMP16mr: O << "cmp" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00119 case X86::CMP16ri: O << "cmp" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00120 case X86::CMP16rm: O << "cmp" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00121 case X86::CMP16rr: O << "cmp" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00122 case X86::CMP32mi: O << "cmp" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00123 case X86::CMP32mr: O << "cmp" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00124 case X86::CMP32ri: O << "cmp" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00125 case X86::CMP32rm: O << "cmp" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00126 case X86::CMP32rr: O << "cmp" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00127 case X86::CMP8mi: O << "cmp" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00128 case X86::CMP8mr: O << "cmp" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00129 case X86::CMP8ri: O << "cmp" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00130 case X86::CMP8rm: O << "cmp" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00131 case X86::CMP8rr: O << "cmp" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00132 case X86::CWD: O << "cwd" << '\n'; break; 00133 case X86::DEC16m: O << "dec" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00134 case X86::DEC16r: O << "dec" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00135 case X86::DEC32m: O << "dec" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00136 case X86::DEC32r: O << "dec" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00137 case X86::DEC8m: O << "dec" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00138 case X86::DEC8r: O << "dec" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00139 case X86::DIV16m: O << "div" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00140 case X86::DIV16r: O << "div" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00141 case X86::DIV32m: O << "div" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00142 case X86::DIV32r: O << "div" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00143 case X86::DIV8m: O << "div" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00144 case X86::DIV8r: O << "div" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00145 case X86::FADD32m: O << "fadd" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00146 case X86::FADD64m: O << "fadd" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00147 case X86::FADDPrST0: O << "faddp "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00148 case X86::FADDST0r: O << "fadd "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00149 case X86::FADDrST0: O << "fadd "; printOperand(MI, 0, MVT::f64); O << ", %ST(0)" << '\n'; break; 00150 case X86::FCHS: O << "fchs" << '\n'; break; 00151 case X86::FCMOVA: O << "fcmova " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00152 case X86::FCMOVAE: O << "fcmovae " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00153 case X86::FCMOVB: O << "fcmovb " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00154 case X86::FCMOVBE: O << "fcmovbe " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00155 case X86::FCMOVE: O << "fcmove " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00156 case X86::FCMOVNE: O << "fcmovne " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00157 case X86::FDIV32m: O << "fdiv" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00158 case X86::FDIV64m: O << "fdiv" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00159 case X86::FDIVPrST0: O << "fdiv" << "p "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00160 case X86::FDIVR32m: O << "fdivr" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00161 case X86::FDIVR64m: O << "fdivr" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00162 case X86::FDIVRPrST0: O << "fdiv" << "r" << "p "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00163 case X86::FDIVRST0r: O << "fdivr "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00164 case X86::FDIVRrST0: O << "fdiv" << "r" << " "; printOperand(MI, 0, MVT::f64); O << ", %ST(0)" << '\n'; break; 00165 case X86::FDIVST0r: O << "fdiv "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00166 case X86::FDIVrST0: O << "fdiv" << " "; printOperand(MI, 0, MVT::f64); O << ", %ST(0)" << '\n'; break; 00167 case X86::FILD16m: O << "fild" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00168 case X86::FILD32m: O << "fild" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00169 case X86::FILD64m: O << "fild" << " "; printMemoryOperand(MI, 0, MVT::i64); O << '\n'; break; 00170 case X86::FIST16m: O << "fist" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00171 case X86::FIST32m: O << "fist" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00172 case X86::FISTP16m: O << "fistp" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00173 case X86::FISTP32m: O << "fistp" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00174 case X86::FISTP64m: O << "fistp" << " "; printMemoryOperand(MI, 0, MVT::i64); O << '\n'; break; 00175 case X86::FLD0: O << "fldz" << '\n'; break; 00176 case X86::FLD1: O << "fld1" << '\n'; break; 00177 case X86::FLD32m: O << "fld" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00178 case X86::FLD64m: O << "fld" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00179 case X86::FLD80m: O << "fld" << " "; printMemoryOperand(MI, 0, MVT::f80); O << '\n'; break; 00180 case X86::FLDCW16m: O << "fldcw "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00181 case X86::FLDrr: O << "fld "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00182 case X86::FMUL32m: O << "fmul" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00183 case X86::FMUL64m: O << "fmul" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00184 case X86::FMULPrST0: O << "fmulp "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00185 case X86::FMULST0r: O << "fmul "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00186 case X86::FMULrST0: O << "fmul "; printOperand(MI, 0, MVT::f64); O << ", %ST(0)" << '\n'; break; 00187 case X86::FNSTCW16m: O << "fnstcw "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00188 case X86::FNSTSW8r: O << "fnstsw" << '\n'; break; 00189 case X86::FP_REG_KILL: O << "#FP_REG_KILL" << '\n'; break; 00190 case X86::FST32m: O << "fst" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00191 case X86::FST64m: O << "fst" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00192 case X86::FSTP32m: O << "fstp" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00193 case X86::FSTP64m: O << "fstp" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00194 case X86::FSTP80m: O << "fstp" << " "; printMemoryOperand(MI, 0, MVT::f80); O << '\n'; break; 00195 case X86::FSTPrr: O << "fstp "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00196 case X86::FSTrr: O << "fst "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00197 case X86::FSUB32m: O << "fsub" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00198 case X86::FSUB64m: O << "fsub" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00199 case X86::FSUBPrST0: O << "fsub" << "p "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00200 case X86::FSUBR32m: O << "fsubr" << " "; printMemoryOperand(MI, 0, MVT::f32); O << '\n'; break; 00201 case X86::FSUBR64m: O << "fsubr" << " "; printMemoryOperand(MI, 0, MVT::f64); O << '\n'; break; 00202 case X86::FSUBRPrST0: O << "fsub" << "r" << "p "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00203 case X86::FSUBRST0r: O << "fsubr "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00204 case X86::FSUBRrST0: O << "fsub" << "r" << " "; printOperand(MI, 0, MVT::f64); O << ", %ST(0)" << '\n'; break; 00205 case X86::FSUBST0r: O << "fsub "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00206 case X86::FSUBrST0: O << "fsub" << " "; printOperand(MI, 0, MVT::f64); O << ", %ST(0)" << '\n'; break; 00207 case X86::FTST: O << "ftst" << '\n'; break; 00208 case X86::FUCOMIPr: O << "fucomip " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00209 case X86::FUCOMIr: O << "fucomi " << "%ST(0), "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00210 case X86::FUCOMPPr: O << "fucompp" << '\n'; break; 00211 case X86::FUCOMPr: O << "fucomp "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00212 case X86::FUCOMr: O << "fucom "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00213 case X86::FXCH: O << "fxch "; printOperand(MI, 0, MVT::f64); O << '\n'; break; 00214 case X86::IDIV16m: O << "idiv" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00215 case X86::IDIV16r: O << "idiv" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00216 case X86::IDIV32m: O << "idiv" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00217 case X86::IDIV32r: O << "idiv" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00218 case X86::IDIV8m: O << "idiv" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00219 case X86::IDIV8r: O << "idiv" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00220 case X86::IMPLICIT_DEF: O << "#IMPLICIT_DEF" << '\n'; break; 00221 case X86::IMPLICIT_USE: O << "#IMPLICIT_USE" << '\n'; break; 00222 case X86::IMUL16rm: O << "imul" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00223 case X86::IMUL16rmi: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << ", "; printOperand(MI, 5, MVT::i16); O << '\n'; break; 00224 case X86::IMUL16rmi8: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << ", "; printOperand(MI, 5, MVT::i8); O << '\n'; break; 00225 case X86::IMUL16rr: O << "imul" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00226 case X86::IMUL16rri: O << "imul" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << ", "; printOperand(MI, 2, MVT::i16); O << '\n'; break; 00227 case X86::IMUL16rri8: O << "imul" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << ", "; printOperand(MI, 2, MVT::i8); O << '\n'; break; 00228 case X86::IMUL32rm: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00229 case X86::IMUL32rmi: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << ", "; printOperand(MI, 5, MVT::i32); O << '\n'; break; 00230 case X86::IMUL32rmi8: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << ", "; printOperand(MI, 5, MVT::i8); O << '\n'; break; 00231 case X86::IMUL32rr: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00232 case X86::IMUL32rri: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << ", "; printOperand(MI, 2, MVT::i32); O << '\n'; break; 00233 case X86::IMUL32rri8: O << "imul" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << ", "; printOperand(MI, 2, MVT::i8); O << '\n'; break; 00234 case X86::IN16ri: O << "in" << " " << "AX, "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00235 case X86::IN16rr: O << "in" << " " << "AX, DX" << '\n'; break; 00236 case X86::IN32ri: O << "in" << " " << "EAX, "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00237 case X86::IN32rr: O << "in" << " " << "EAX, DX" << '\n'; break; 00238 case X86::IN8ri: O << "in" << " " << "AL, "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00239 case X86::IN8rr: O << "in" << " " << "AL, DX" << '\n'; break; 00240 case X86::INC16m: O << "inc" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00241 case X86::INC16r: O << "inc" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00242 case X86::INC32m: O << "inc" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00243 case X86::INC32r: O << "inc" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00244 case X86::INC8m: O << "inc" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00245 case X86::INC8r: O << "inc" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00246 case X86::JA: O << "ja "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00247 case X86::JAE: O << "jae "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00248 case X86::JB: O << "jb "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00249 case X86::JBE: O << "jbe "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00250 case X86::JE: O << "je "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00251 case X86::JG: O << "jg "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00252 case X86::JGE: O << "jge "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00253 case X86::JL: O << "jl "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00254 case X86::JLE: O << "jle "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00255 case X86::JMP: O << "jmp "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00256 case X86::JNE: O << "jne "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00257 case X86::JNS: O << "jns "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00258 case X86::JS: O << "js "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00259 case X86::LAHF: O << "lahf" << '\n'; break; 00260 case X86::LEA16r: O << "lea" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00261 case X86::LEA32r: O << "lea" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00262 case X86::LEAVE: O << "leave" << '\n'; break; 00263 case X86::MOV16mi: O << "mov" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00264 case X86::MOV16mr: O << "mov" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00265 case X86::MOV16ri: O << "mov" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00266 case X86::MOV16rm: O << "mov" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00267 case X86::MOV16rr: O << "mov" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00268 case X86::MOV32mi: O << "mov" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00269 case X86::MOV32mr: O << "mov" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00270 case X86::MOV32ri: O << "mov" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00271 case X86::MOV32rm: O << "mov" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00272 case X86::MOV32rr: O << "mov" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00273 case X86::MOV8mi: O << "mov" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00274 case X86::MOV8mr: O << "mov" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00275 case X86::MOV8ri: O << "mov" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00276 case X86::MOV8rm: O << "mov" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00277 case X86::MOV8rr: O << "mov" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00278 case X86::MOVSX16rm8: O << "movs" << "x" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00279 case X86::MOVSX16rr8: O << "movs" << "x" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00280 case X86::MOVSX32rm16: O << "movs" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00281 case X86::MOVSX32rm8: O << "movs" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00282 case X86::MOVSX32rr16: O << "movs" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00283 case X86::MOVSX32rr8: O << "movs" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00284 case X86::MOVZX16rm8: O << "movz" << "x" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00285 case X86::MOVZX16rr8: O << "movz" << "x" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00286 case X86::MOVZX32rm16: O << "movz" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00287 case X86::MOVZX32rm8: O << "movz" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00288 case X86::MOVZX32rr16: O << "movz" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00289 case X86::MOVZX32rr8: O << "movz" << "x" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00290 case X86::MUL16m: O << "mul" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00291 case X86::MUL16r: O << "mul" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00292 case X86::MUL32m: O << "mul" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00293 case X86::MUL32r: O << "mul" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00294 case X86::MUL8m: O << "mul" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00295 case X86::MUL8r: O << "mul" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00296 case X86::NEG16m: O << "neg" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00297 case X86::NEG16r: O << "neg" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00298 case X86::NEG32m: O << "neg" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00299 case X86::NEG32r: O << "neg" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00300 case X86::NEG8m: O << "neg" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00301 case X86::NEG8r: O << "neg" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00302 case X86::NOOP: O << "nop" << '\n'; break; 00303 case X86::NOT16m: O << "not" << " "; printMemoryOperand(MI, 0, MVT::i16); O << '\n'; break; 00304 case X86::NOT16r: O << "not" << " "; printOperand(MI, 0, MVT::i16); O << '\n'; break; 00305 case X86::NOT32m: O << "not" << " "; printMemoryOperand(MI, 0, MVT::i32); O << '\n'; break; 00306 case X86::NOT32r: O << "not" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00307 case X86::NOT8m: O << "not" << " "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00308 case X86::NOT8r: O << "not" << " "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00309 case X86::OR16mi: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00310 case X86::OR16mi8: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00311 case X86::OR16mr: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00312 case X86::OR16ri: O << "or" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00313 case X86::OR16ri8: O << "or" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00314 case X86::OR16rm: O << "or" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00315 case X86::OR16rr: O << "or" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00316 case X86::OR32mi: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00317 case X86::OR32mi8: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00318 case X86::OR32mr: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00319 case X86::OR32ri: O << "or" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00320 case X86::OR32ri8: O << "or" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00321 case X86::OR32rm: O << "or" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00322 case X86::OR32rr: O << "or" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00323 case X86::OR8mi: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00324 case X86::OR8mr: O << "or" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00325 case X86::OR8ri: O << "or" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00326 case X86::OR8rm: O << "or" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00327 case X86::OR8rr: O << "or" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00328 case X86::OUT16ir: O << "out" << " "; printOperand(MI, 0, MVT::i16); O << ", AX" << '\n'; break; 00329 case X86::OUT16rr: O << "out" << " " << "DX, AX" << '\n'; break; 00330 case X86::OUT32ir: O << "out" << " "; printOperand(MI, 0, MVT::i16); O << ", %EAX" << '\n'; break; 00331 case X86::OUT32rr: O << "out" << " " << "DX, EAX" << '\n'; break; 00332 case X86::OUT8ir: O << "out" << " "; printOperand(MI, 0, MVT::i16); O << ", AL" << '\n'; break; 00333 case X86::OUT8rr: O << "out" << " " << "DX, AL" << '\n'; break; 00334 case X86::PHI: O << "PHINODE" << '\n'; break; 00335 case X86::POP32r: O << "pop" << " "; printOperand(MI, 0, MVT::i32); O << '\n'; break; 00336 case X86::REP_MOVSB: O << "rep movsb" << '\n'; break; 00337 case X86::REP_MOVSD: O << "rep movsd" << '\n'; break; 00338 case X86::REP_MOVSW: O << "rep movsw" << '\n'; break; 00339 case X86::REP_STOSB: O << "rep stosb" << '\n'; break; 00340 case X86::REP_STOSD: O << "rep stosd" << '\n'; break; 00341 case X86::REP_STOSW: O << "rep stosw" << '\n'; break; 00342 case X86::RET: O << "ret" << '\n'; break; 00343 case X86::SAHF: O << "sahf" << '\n'; break; 00344 case X86::SAR16mCL: O << "sar" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", %CL" << '\n'; break; 00345 case X86::SAR16mi: O << "sar" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00346 case X86::SAR16rCL: O << "sar" << " "; printOperand(MI, 0, MVT::i16); O << ", %CL" << '\n'; break; 00347 case X86::SAR16ri: O << "sar" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00348 case X86::SAR32mCL: O << "sar" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", %CL" << '\n'; break; 00349 case X86::SAR32mi: O << "sar" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00350 case X86::SAR32rCL: O << "sar" << " "; printOperand(MI, 0, MVT::i32); O << ", %CL" << '\n'; break; 00351 case X86::SAR32ri: O << "sar" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00352 case X86::SAR8mCL: O << "sar" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", %CL" << '\n'; break; 00353 case X86::SAR8mi: O << "sar" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00354 case X86::SAR8rCL: O << "sar" << " "; printOperand(MI, 0, MVT::i8); O << ", %CL" << '\n'; break; 00355 case X86::SAR8ri: O << "sar" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00356 case X86::SBB16mi: O << "sbb" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00357 case X86::SBB16mi8: O << "sbb" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00358 case X86::SBB16ri: O << "sbb" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00359 case X86::SBB16ri8: O << "sbb" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00360 case X86::SBB32mi: O << "sbb" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00361 case X86::SBB32mi8: O << "sbb" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00362 case X86::SBB32mr: O << "sbb" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00363 case X86::SBB32ri: O << "sbb" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00364 case X86::SBB32ri8: O << "sbb" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00365 case X86::SBB32rm: O << "sbb" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00366 case X86::SBB32rr: O << "sbb" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00367 case X86::SBB8mi: O << "sbb" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00368 case X86::SBB8ri: O << "sbb" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00369 case X86::SETAEm: O << "setae "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00370 case X86::SETAEr: O << "setae "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00371 case X86::SETAm: O << "seta "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00372 case X86::SETAr: O << "seta "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00373 case X86::SETBEm: O << "setbe "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00374 case X86::SETBEr: O << "setbe "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00375 case X86::SETBm: O << "setb "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00376 case X86::SETBr: O << "setb "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00377 case X86::SETEm: O << "sete "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00378 case X86::SETEr: O << "sete "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00379 case X86::SETGEm: O << "setge "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00380 case X86::SETGEr: O << "setge "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00381 case X86::SETGm: O << "setg "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00382 case X86::SETGr: O << "setg "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00383 case X86::SETLEm: O << "setle "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00384 case X86::SETLEr: O << "setle "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00385 case X86::SETLm: O << "setl "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00386 case X86::SETLr: O << "setl "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00387 case X86::SETNEm: O << "setne "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00388 case X86::SETNEr: O << "setne "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00389 case X86::SETNSm: O << "setns "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00390 case X86::SETNSr: O << "setns "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00391 case X86::SETPm: O << "setp "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00392 case X86::SETPr: O << "setp "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00393 case X86::SETSm: O << "sets "; printMemoryOperand(MI, 0, MVT::i8); O << '\n'; break; 00394 case X86::SETSr: O << "sets "; printOperand(MI, 0, MVT::i8); O << '\n'; break; 00395 case X86::SHL16mCL: O << "shl" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", %CL" << '\n'; break; 00396 case X86::SHL16mi: O << "shl" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00397 case X86::SHL16rCL: O << "shl" << " "; printOperand(MI, 0, MVT::i16); O << ", %CL" << '\n'; break; 00398 case X86::SHL16ri: O << "shl" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00399 case X86::SHL32mCL: O << "shl" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", %CL" << '\n'; break; 00400 case X86::SHL32mi: O << "shl" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00401 case X86::SHL32rCL: O << "shl" << " "; printOperand(MI, 0, MVT::i32); O << ", %CL" << '\n'; break; 00402 case X86::SHL32ri: O << "shl" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00403 case X86::SHL8mCL: O << "shl" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", %CL" << '\n'; break; 00404 case X86::SHL8mi: O << "shl" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00405 case X86::SHL8rCL: O << "shl" << " "; printOperand(MI, 0, MVT::i8); O << ", %CL" << '\n'; break; 00406 case X86::SHL8ri: O << "shl" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00407 case X86::SHLD32mrCL: O << "shld" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << ", %CL" << '\n'; break; 00408 case X86::SHLD32mri8: O << "shld" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << ", "; printOperand(MI, 5, MVT::i8); O << '\n'; break; 00409 case X86::SHLD32rrCL: O << "shld" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << ", %CL" << '\n'; break; 00410 case X86::SHLD32rri8: O << "shld" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << ", "; printOperand(MI, 2, MVT::i8); O << '\n'; break; 00411 case X86::SHR16mCL: O << "shr" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", %CL" << '\n'; break; 00412 case X86::SHR16mi: O << "shr" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00413 case X86::SHR16rCL: O << "shr" << " "; printOperand(MI, 0, MVT::i16); O << ", %CL" << '\n'; break; 00414 case X86::SHR16ri: O << "shr" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00415 case X86::SHR32mCL: O << "shr" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", %CL" << '\n'; break; 00416 case X86::SHR32mi: O << "shr" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00417 case X86::SHR32rCL: O << "shr" << " "; printOperand(MI, 0, MVT::i32); O << ", %CL" << '\n'; break; 00418 case X86::SHR32ri: O << "shr" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00419 case X86::SHR8mCL: O << "shr" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", %CL" << '\n'; break; 00420 case X86::SHR8mi: O << "shr" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00421 case X86::SHR8rCL: O << "shr" << " "; printOperand(MI, 0, MVT::i8); O << ", %CL" << '\n'; break; 00422 case X86::SHR8ri: O << "shr" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00423 case X86::SHRD32mrCL: O << "shrd" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << ", %CL" << '\n'; break; 00424 case X86::SHRD32mri8: O << "shrd" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << ", "; printOperand(MI, 5, MVT::i8); O << '\n'; break; 00425 case X86::SHRD32rrCL: O << "shrd" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << ", %CL" << '\n'; break; 00426 case X86::SHRD32rri8: O << "shrd" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << ", "; printOperand(MI, 2, MVT::i8); O << '\n'; break; 00427 case X86::SUB16mi: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00428 case X86::SUB16mi8: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00429 case X86::SUB16mr: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00430 case X86::SUB16ri: O << "sub" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00431 case X86::SUB16ri8: O << "sub" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00432 case X86::SUB16rm: O << "sub" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00433 case X86::SUB16rr: O << "sub" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00434 case X86::SUB32mi: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00435 case X86::SUB32mi8: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00436 case X86::SUB32mr: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00437 case X86::SUB32ri: O << "sub" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00438 case X86::SUB32ri8: O << "sub" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00439 case X86::SUB32rm: O << "sub" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00440 case X86::SUB32rr: O << "sub" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00441 case X86::SUB8mi: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00442 case X86::SUB8mr: O << "sub" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00443 case X86::SUB8ri: O << "sub" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00444 case X86::SUB8rm: O << "sub" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00445 case X86::SUB8rr: O << "sub" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00446 case X86::TEST16mi: O << "test" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00447 case X86::TEST16mr: O << "test" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00448 case X86::TEST16ri: O << "test" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00449 case X86::TEST16rm: O << "test" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00450 case X86::TEST16rr: O << "test" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00451 case X86::TEST32mi: O << "test" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00452 case X86::TEST32mr: O << "test" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00453 case X86::TEST32ri: O << "test" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00454 case X86::TEST32rm: O << "test" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00455 case X86::TEST32rr: O << "test" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00456 case X86::TEST8mi: O << "test" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00457 case X86::TEST8mr: O << "test" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00458 case X86::TEST8ri: O << "test" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00459 case X86::TEST8rm: O << "test" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00460 case X86::TEST8rr: O << "test" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00461 case X86::XCHG16mr: O << "xchg" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00462 case X86::XCHG16rm: O << "xchg" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00463 case X86::XCHG16rr: O << "xchg" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00464 case X86::XCHG32mr: O << "xchg" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00465 case X86::XCHG32rm: O << "xchg" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00466 case X86::XCHG32rr: O << "xchg" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00467 case X86::XCHG8mr: O << "xchg" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00468 case X86::XCHG8rm: O << "xchg" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00469 case X86::XCHG8rr: O << "xchg" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00470 case X86::XOR16mi: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00471 case X86::XOR16mi8: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00472 case X86::XOR16mr: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 4, MVT::i16); O << '\n'; break; 00473 case X86::XOR16ri: O << "xor" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00474 case X86::XOR16ri8: O << "xor" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00475 case X86::XOR16rm: O << "xor" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printMemoryOperand(MI, 1, MVT::i16); O << '\n'; break; 00476 case X86::XOR16rr: O << "xor" << " "; printOperand(MI, 0, MVT::i16); O << ", "; printOperand(MI, 1, MVT::i16); O << '\n'; break; 00477 case X86::XOR32mi: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00478 case X86::XOR32mi8: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00479 case X86::XOR32mr: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 4, MVT::i32); O << '\n'; break; 00480 case X86::XOR32ri: O << "xor" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00481 case X86::XOR32ri8: O << "xor" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00482 case X86::XOR32rm: O << "xor" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printMemoryOperand(MI, 1, MVT::i32); O << '\n'; break; 00483 case X86::XOR32rr: O << "xor" << " "; printOperand(MI, 0, MVT::i32); O << ", "; printOperand(MI, 1, MVT::i32); O << '\n'; break; 00484 case X86::XOR8mi: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00485 case X86::XOR8mr: O << "xor" << " "; printMemoryOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 4, MVT::i8); O << '\n'; break; 00486 case X86::XOR8ri: O << "xor" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00487 case X86::XOR8rm: O << "xor" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printMemoryOperand(MI, 1, MVT::i8); O << '\n'; break; 00488 case X86::XOR8rr: O << "xor" << " "; printOperand(MI, 0, MVT::i8); O << ", "; printOperand(MI, 1, MVT::i8); O << '\n'; break; 00489 } 00490 return true; 00491 }