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SparcV9RegisterInfo.cpp

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00001 //===- SparcV9RegisterInfo.cpp - SparcV9 Register Information ---*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the SparcV9 implementation of the MRegisterInfo class.
00011 // It also contains stuff needed to instantiate that class, which would
00012 // ordinarily be provided by TableGen.
00013 //
00014 // This is NOT used by the SparcV9 backend to do register allocation, yet.
00015 //
00016 //===----------------------------------------------------------------------===//
00017 //
00018 // The first section of this file (immediately following) is what
00019 // you would find in SparcV9GenRegisterInfo.inc, if we were using
00020 // TableGen to generate the register file description automatically.
00021 // It consists of register classes and register class instances
00022 // for the SparcV9 target.
00023 // 
00024 // FIXME: the alignments listed here are wild guesses.
00025 //
00026 //===----------------------------------------------------------------------===//
00027 
00028 #include "SparcV9RegisterInfo.h"
00029 #include "llvm/CodeGen/MachineFunction.h"
00030 using namespace llvm;
00031 
00032 namespace llvm {
00033 
00034 namespace {
00035   // IR Register Class...
00036   const unsigned IR[] = {
00037     SparcV9::o0, SparcV9::o1, SparcV9::o2, SparcV9::o3, SparcV9::o4,
00038     SparcV9::o5, SparcV9::o7, SparcV9::l0, SparcV9::l1, SparcV9::l2,
00039     SparcV9::l3, SparcV9::l4, SparcV9::l5, SparcV9::l6, SparcV9::l7,
00040     SparcV9::i0, SparcV9::i1, SparcV9::i2, SparcV9::i3, SparcV9::i4,
00041     SparcV9::i5, SparcV9::i6, SparcV9::i7, SparcV9::g0, SparcV9::g1,
00042     SparcV9::g2, SparcV9::g3, SparcV9::g4, SparcV9::g5, SparcV9::g6,
00043     SparcV9::g7, SparcV9::o6
00044   };
00045   struct IRClass : public TargetRegisterClass {
00046     IRClass() : TargetRegisterClass(8, 8, IR, IR + 32) {}
00047   } IRInstance;
00048 
00049 
00050   // FR Register Class...
00051   const unsigned FR[] = {
00052     SparcV9::f0, SparcV9::f1, SparcV9::f2, SparcV9::f3, SparcV9::f4,
00053     SparcV9::f5, SparcV9::f6, SparcV9::f7, SparcV9::f8, SparcV9::f9,
00054     SparcV9::f10, SparcV9::f11, SparcV9::f12, SparcV9::f13,
00055     SparcV9::f14, SparcV9::f15, SparcV9::f16, SparcV9::f17,
00056     SparcV9::f18, SparcV9::f19, SparcV9::f20, SparcV9::f21,
00057     SparcV9::f22, SparcV9::f23, SparcV9::f24, SparcV9::f25,
00058     SparcV9::f26, SparcV9::f27, SparcV9::f28, SparcV9::f29,
00059     SparcV9::f30, SparcV9::f31, SparcV9::f32, SparcV9::f33,
00060     SparcV9::f34, SparcV9::f35, SparcV9::f36, SparcV9::f37,
00061     SparcV9::f38, SparcV9::f39, SparcV9::f40, SparcV9::f41,
00062     SparcV9::f42, SparcV9::f43, SparcV9::f44, SparcV9::f45,
00063     SparcV9::f46, SparcV9::f47, SparcV9::f48, SparcV9::f49,
00064     SparcV9::f50, SparcV9::f51, SparcV9::f52, SparcV9::f53,
00065     SparcV9::f54, SparcV9::f55, SparcV9::f56, SparcV9::f57,
00066     SparcV9::f58, SparcV9::f59, SparcV9::f60, SparcV9::f61,
00067     SparcV9::f62, SparcV9::f63
00068   };
00069   // FIXME: The size is correct for the first 32 registers. The
00070   // latter 32 do not all really exist; you can only access every other
00071   // one (32, 34, ...), and they must contain double-fp or quad-fp
00072   // values... see below about the aliasing problems.
00073   struct FRClass : public TargetRegisterClass {
00074     FRClass() : TargetRegisterClass(4, 8, FR, FR + 64) {}
00075   } FRInstance;
00076 
00077 
00078   // ICCR Register Class...
00079   const unsigned ICCR[] = {
00080     SparcV9::xcc, SparcV9::icc, SparcV9::ccr
00081   };
00082   struct ICCRClass : public TargetRegisterClass {
00083     ICCRClass() : TargetRegisterClass(1, 8, ICCR, ICCR + 3) {}
00084   } ICCRInstance;
00085 
00086 
00087   // FCCR Register Class...
00088   const unsigned FCCR[] = {
00089     SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
00090   };
00091   struct FCCRClass : public TargetRegisterClass {
00092     FCCRClass() : TargetRegisterClass(1, 8, FCCR, FCCR + 4) {}
00093   } FCCRInstance;
00094 
00095 
00096   // SR Register Class...
00097   const unsigned SR[] = {
00098     SparcV9::fsr
00099   };
00100   struct SRClass : public TargetRegisterClass {
00101     SRClass() : TargetRegisterClass(8, 8, SR, SR + 1) {}
00102   } SRInstance;
00103 
00104 
00105   // Register Classes...
00106   const TargetRegisterClass* const RegisterClasses[] = {
00107     &IRInstance,
00108     &FRInstance,
00109     &ICCRInstance,
00110     &FCCRInstance,
00111     &SRInstance
00112   };
00113 
00114 
00115   // Register Alias Sets...
00116   // FIXME: Note that the SparcV9 backend does not currently abstract
00117   // very well over the way that double-fp and quad-fp values may alias
00118   // single-fp values in registers. Therefore those aliases are NOT
00119   // reflected here.
00120   const unsigned Empty_AliasSet[] = { 0 };
00121   const unsigned fcc3_AliasSet[] = { SparcV9::fsr, 0 };
00122   const unsigned fcc2_AliasSet[] = { SparcV9::fsr, 0 };
00123   const unsigned fcc1_AliasSet[] = { SparcV9::fsr, 0 };
00124   const unsigned fcc0_AliasSet[] = { SparcV9::fsr, 0 };
00125   const unsigned fsr_AliasSet[] = { SparcV9::fcc3, SparcV9::fcc2,
00126                                     SparcV9::fcc1, SparcV9::fcc0, 0 };
00127   const unsigned xcc_AliasSet[] = { SparcV9::ccr, 0 };
00128   const unsigned icc_AliasSet[] = { SparcV9::ccr, 0 };
00129   const unsigned ccr_AliasSet[] = { SparcV9::xcc, SparcV9::icc, 0 };
00130 
00131 const MRegisterDesc RegisterDescriptors[] = { // Descriptors
00132   { "o0", Empty_AliasSet, 0, 0 },
00133   { "o1", Empty_AliasSet, 0, 0 },
00134   { "o2", Empty_AliasSet, 0, 0 },
00135   { "o3", Empty_AliasSet, 0, 0 },
00136   { "o4", Empty_AliasSet, 0, 0 },
00137   { "o5", Empty_AliasSet, 0, 0 },
00138   { "o7", Empty_AliasSet, 0, 0 },
00139   { "l0", Empty_AliasSet, 0, 0 },
00140   { "l1", Empty_AliasSet, 0, 0 },
00141   { "l2", Empty_AliasSet, 0, 0 },
00142   { "l3", Empty_AliasSet, 0, 0 },
00143   { "l4", Empty_AliasSet, 0, 0 },
00144   { "l5", Empty_AliasSet, 0, 0 },
00145   { "l6", Empty_AliasSet, 0, 0 },
00146   { "l7", Empty_AliasSet, 0, 0 },
00147   { "i0", Empty_AliasSet, 0, 0 },
00148   { "i1", Empty_AliasSet, 0, 0 },
00149   { "i2", Empty_AliasSet, 0, 0 },
00150   { "i3", Empty_AliasSet, 0, 0 },
00151   { "i4", Empty_AliasSet, 0, 0 },
00152   { "i5", Empty_AliasSet, 0, 0 },
00153   { "i6", Empty_AliasSet, 0, 0 },
00154   { "i7", Empty_AliasSet, 0, 0 },
00155   { "g0", Empty_AliasSet, 0, 0 },
00156   { "g1", Empty_AliasSet, 0, 0 },
00157   { "g2", Empty_AliasSet, 0, 0 },
00158   { "g3", Empty_AliasSet, 0, 0 },
00159   { "g4", Empty_AliasSet, 0, 0 },
00160   { "g5", Empty_AliasSet, 0, 0 },
00161   { "g6", Empty_AliasSet, 0, 0 },
00162   { "g7", Empty_AliasSet, 0, 0 },
00163   { "o6", Empty_AliasSet, 0, 0 },
00164   { "f0", Empty_AliasSet, 0, 0 },
00165   { "f1", Empty_AliasSet, 0, 0 },
00166   { "f2", Empty_AliasSet, 0, 0 },
00167   { "f3", Empty_AliasSet, 0, 0 },
00168   { "f4", Empty_AliasSet, 0, 0 },
00169   { "f5", Empty_AliasSet, 0, 0 },
00170   { "f6", Empty_AliasSet, 0, 0 },
00171   { "f7", Empty_AliasSet, 0, 0 },
00172   { "f8", Empty_AliasSet, 0, 0 },
00173   { "f9", Empty_AliasSet, 0, 0 },
00174   { "f10", Empty_AliasSet, 0, 0 },
00175   { "f11", Empty_AliasSet, 0, 0 },
00176   { "f12", Empty_AliasSet, 0, 0 },
00177   { "f13", Empty_AliasSet, 0, 0 },
00178   { "f14", Empty_AliasSet, 0, 0 },
00179   { "f15", Empty_AliasSet, 0, 0 },
00180   { "f16", Empty_AliasSet, 0, 0 },
00181   { "f17", Empty_AliasSet, 0, 0 },
00182   { "f18", Empty_AliasSet, 0, 0 },
00183   { "f19", Empty_AliasSet, 0, 0 },
00184   { "f20", Empty_AliasSet, 0, 0 },
00185   { "f21", Empty_AliasSet, 0, 0 },
00186   { "f22", Empty_AliasSet, 0, 0 },
00187   { "f23", Empty_AliasSet, 0, 0 },
00188   { "f24", Empty_AliasSet, 0, 0 },
00189   { "f25", Empty_AliasSet, 0, 0 },
00190   { "f26", Empty_AliasSet, 0, 0 },
00191   { "f27", Empty_AliasSet, 0, 0 },
00192   { "f28", Empty_AliasSet, 0, 0 },
00193   { "f29", Empty_AliasSet, 0, 0 },
00194   { "f30", Empty_AliasSet, 0, 0 },
00195   { "f31", Empty_AliasSet, 0, 0 },
00196   { "f32", Empty_AliasSet, 0, 0 },
00197   { "f33", Empty_AliasSet, 0, 0 },
00198   { "f34", Empty_AliasSet, 0, 0 },
00199   { "f35", Empty_AliasSet, 0, 0 },
00200   { "f36", Empty_AliasSet, 0, 0 },
00201   { "f37", Empty_AliasSet, 0, 0 },
00202   { "f38", Empty_AliasSet, 0, 0 },
00203   { "f39", Empty_AliasSet, 0, 0 },
00204   { "f40", Empty_AliasSet, 0, 0 },
00205   { "f41", Empty_AliasSet, 0, 0 },
00206   { "f42", Empty_AliasSet, 0, 0 },
00207   { "f43", Empty_AliasSet, 0, 0 },
00208   { "f44", Empty_AliasSet, 0, 0 },
00209   { "f45", Empty_AliasSet, 0, 0 },
00210   { "f46", Empty_AliasSet, 0, 0 },
00211   { "f47", Empty_AliasSet, 0, 0 },
00212   { "f48", Empty_AliasSet, 0, 0 },
00213   { "f49", Empty_AliasSet, 0, 0 },
00214   { "f50", Empty_AliasSet, 0, 0 },
00215   { "f51", Empty_AliasSet, 0, 0 },
00216   { "f52", Empty_AliasSet, 0, 0 },
00217   { "f53", Empty_AliasSet, 0, 0 },
00218   { "f54", Empty_AliasSet, 0, 0 },
00219   { "f55", Empty_AliasSet, 0, 0 },
00220   { "f56", Empty_AliasSet, 0, 0 },
00221   { "f57", Empty_AliasSet, 0, 0 },
00222   { "f58", Empty_AliasSet, 0, 0 },
00223   { "f59", Empty_AliasSet, 0, 0 },
00224   { "f60", Empty_AliasSet, 0, 0 },
00225   { "f61", Empty_AliasSet, 0, 0 },
00226   { "f62", Empty_AliasSet, 0, 0 },
00227   { "f63", Empty_AliasSet, 0, 0 },
00228   { "xcc", xcc_AliasSet, 0, 0 },
00229   { "icc", icc_AliasSet, 0, 0 },
00230   { "ccr", ccr_AliasSet, 0, 0 },
00231   { "fcc0", fcc0_AliasSet, 0, 0 },
00232   { "fcc1", fcc1_AliasSet, 0, 0 },
00233   { "fcc2", fcc2_AliasSet, 0, 0 },
00234   { "fcc3", fcc3_AliasSet, 0, 0 },
00235   { "fsr", fsr_AliasSet, 0, 0 },
00236 };
00237 
00238 } // end anonymous namespace
00239 
00240 namespace SparcV9 { // Register classes
00241   TargetRegisterClass *IRRegisterClass = &IRInstance;
00242   TargetRegisterClass *FRRegisterClass = &FRInstance;
00243   TargetRegisterClass *ICCRRegisterClass = &ICCRInstance;
00244   TargetRegisterClass *FCCRRegisterClass = &FCCRInstance;
00245   TargetRegisterClass *SRRegisterClass = &SRInstance;
00246 } // end namespace SparcV9
00247 
00248 const unsigned *SparcV9RegisterInfo::getCalleeSaveRegs() const {
00249   // FIXME: This should be verified against the SparcV9 ABI at some point.
00250   // These are the registers which the SparcV9 backend considers
00251   // "non-volatile".
00252   static const unsigned CalleeSaveRegs[] = {
00253      SparcV9::l0, SparcV9::l1, SparcV9::l2, SparcV9::l3, SparcV9::l4,
00254      SparcV9::l5, SparcV9::l6, SparcV9::l7, SparcV9::i0, SparcV9::i1,
00255      SparcV9::i2, SparcV9::i3, SparcV9::i4, SparcV9::i5, SparcV9::i6,
00256      SparcV9::i7, SparcV9::g0, SparcV9::g1, SparcV9::g2, SparcV9::g3,
00257      SparcV9::g4, SparcV9::g5, SparcV9::g6, SparcV9::g7, SparcV9::o6,
00258      0
00259   };
00260   return CalleeSaveRegs;
00261 }
00262 
00263 } // end namespace llvm
00264 
00265 //===----------------------------------------------------------------------===//
00266 //
00267 // The second section of this file (immediately following) contains the
00268 // SparcV9 implementation of the MRegisterInfo class. It currently consists
00269 // entirely of stub functions, because the SparcV9 target does not use the
00270 // same register allocator that the X86 target uses.
00271 //
00272 //===----------------------------------------------------------------------===//
00273 
00274 SparcV9RegisterInfo::SparcV9RegisterInfo ()
00275   : MRegisterInfo (RegisterDescriptors, 104, RegisterClasses,
00276                    RegisterClasses + 5) {
00277 }
00278 
00279 void SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
00280                                          MachineBasicBlock::iterator MI,
00281                                          unsigned SrcReg, int FrameIndex) const{
00282   abort ();
00283 }
00284 
00285 void SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
00286                                           MachineBasicBlock::iterator MI,
00287                                           unsigned DestReg, int FrameIndex) const {
00288   abort ();
00289 }
00290 
00291 void SparcV9RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
00292                                       MachineBasicBlock::iterator MI,
00293                                       unsigned DestReg, unsigned SrcReg,
00294                                       const TargetRegisterClass *RC) const {
00295   abort ();
00296 }
00297 
00298 void SparcV9RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI) 
00299   const {
00300   abort ();
00301 }
00302 
00303 void SparcV9RegisterInfo::emitPrologue(MachineFunction &MF) const {
00304   abort ();
00305 }
00306 
00307 void SparcV9RegisterInfo::emitEpilogue(MachineFunction &MF,
00308                                        MachineBasicBlock &MBB) const {
00309   abort ();
00310 }