LLVM API Documentation
00001 //===- PPC32RegisterInfo.cpp - PowerPC32 Register Information ---*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the PowerPC32 implementation of the MRegisterInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #define DEBUG_TYPE "reginfo" 00015 #include "PowerPC.h" 00016 #include "PowerPCInstrBuilder.h" 00017 #include "PPC32RegisterInfo.h" 00018 #include "llvm/Constants.h" 00019 #include "llvm/Type.h" 00020 #include "llvm/CodeGen/ValueTypes.h" 00021 #include "llvm/CodeGen/MachineInstrBuilder.h" 00022 #include "llvm/CodeGen/MachineFunction.h" 00023 #include "llvm/CodeGen/MachineFrameInfo.h" 00024 #include "llvm/Target/TargetFrameInfo.h" 00025 #include "llvm/Target/TargetMachine.h" 00026 #include "llvm/Target/TargetOptions.h" 00027 #include "llvm/Support/CommandLine.h" 00028 #include "llvm/Support/Debug.h" 00029 #include "llvm/ADT/STLExtras.h" 00030 #include <cstdlib> 00031 #include <iostream> 00032 using namespace llvm; 00033 00034 namespace llvm { 00035 // Switch toggling compilation for AIX 00036 extern cl::opt<bool> AIX; 00037 } 00038 00039 PPC32RegisterInfo::PPC32RegisterInfo() 00040 : PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 00041 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 00042 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 00043 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 00044 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 00045 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 00046 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 00047 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 00048 ImmToIdxMap[PPC::ADDI] = PPC::ADD; 00049 } 00050 00051 static const TargetRegisterClass *getClass(unsigned SrcReg) { 00052 if (PPC32::FPRCRegisterClass->contains(SrcReg)) 00053 return PPC32::FPRCRegisterClass; 00054 assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR"); 00055 return PPC32::GPRCRegisterClass; 00056 } 00057 00058 static unsigned getIdx(const TargetRegisterClass *RC) { 00059 if (RC == PPC32::GPRCRegisterClass) { 00060 switch (RC->getSize()) { 00061 default: assert(0 && "Invalid data size!"); 00062 case 1: return 0; 00063 case 2: return 1; 00064 case 4: return 2; 00065 } 00066 } else if (RC == PPC32::FPRCRegisterClass) { 00067 switch (RC->getSize()) { 00068 default: assert(0 && "Invalid data size!"); 00069 case 4: return 3; 00070 case 8: return 4; 00071 } 00072 } 00073 std::cerr << "Invalid register class to getIdx()!\n"; 00074 abort(); 00075 } 00076 00077 void 00078 PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 00079 MachineBasicBlock::iterator MI, 00080 unsigned SrcReg, int FrameIdx) const { 00081 static const unsigned Opcode[] = { 00082 PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD 00083 }; 00084 unsigned OC = Opcode[getIdx(getClass(SrcReg))]; 00085 if (SrcReg == PPC::LR) { 00086 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR); 00087 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); 00088 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx); 00089 } else { 00090 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); 00091 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx); 00092 } 00093 } 00094 00095 void 00096 PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 00097 MachineBasicBlock::iterator MI, 00098 unsigned DestReg, int FrameIdx) const{ 00099 static const unsigned Opcode[] = { 00100 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD 00101 }; 00102 unsigned OC = Opcode[getIdx(getClass(DestReg))]; 00103 if (DestReg == PPC::LR) { 00104 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); 00105 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx); 00106 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 00107 } else { 00108 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0); 00109 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx); 00110 } 00111 } 00112 00113 void PPC32RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 00114 MachineBasicBlock::iterator MI, 00115 unsigned DestReg, unsigned SrcReg, 00116 const TargetRegisterClass *RC) const { 00117 MachineInstr *I; 00118 00119 if (RC == PPC32::GPRCRegisterClass) { 00120 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 00121 } else if (RC == PPC32::FPRCRegisterClass) { 00122 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg); 00123 } else { 00124 std::cerr << "Attempt to copy register that is not GPR or FPR"; 00125 abort(); 00126 } 00127 } 00128 00129 //===----------------------------------------------------------------------===// 00130 // Stack Frame Processing methods 00131 //===----------------------------------------------------------------------===// 00132 00133 // hasFP - Return true if the specified function should have a dedicated frame 00134 // pointer register. This is true if the function has variable sized allocas or 00135 // if frame pointer elimination is disabled. 00136 // 00137 static bool hasFP(MachineFunction &MF) { 00138 MachineFrameInfo *MFI = MF.getFrameInfo(); 00139 return MFI->hasVarSizedObjects(); 00140 } 00141 00142 void PPC32RegisterInfo:: 00143 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 00144 MachineBasicBlock::iterator I) const { 00145 if (hasFP(MF)) { 00146 // If we have a frame pointer, convert as follows: 00147 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 00148 // ADJCALLSTACKUP -> addi, r1, r1, amount 00149 MachineInstr *Old = I; 00150 unsigned Amount = Old->getOperand(0).getImmedValue(); 00151 if (Amount != 0) { 00152 // We need to keep the stack aligned properly. To do this, we round the 00153 // amount of space needed for the outgoing arguments up to the next 00154 // alignment boundary. 00155 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 00156 Amount = (Amount+Align-1)/Align*Align; 00157 00158 // Replace the pseudo instruction with a new instruction... 00159 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 00160 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) 00161 .addSImm(-Amount)); 00162 } else { 00163 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 00164 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) 00165 .addSImm(Amount)); 00166 } 00167 } 00168 } 00169 MBB.erase(I); 00170 } 00171 00172 void 00173 PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 00174 unsigned i = 0; 00175 MachineInstr &MI = *II; 00176 MachineBasicBlock &MBB = *MI.getParent(); 00177 MachineFunction &MF = *MBB.getParent(); 00178 00179 while (!MI.getOperand(i).isFrameIndex()) { 00180 ++i; 00181 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 00182 } 00183 00184 int FrameIndex = MI.getOperand(i).getFrameIndex(); 00185 00186 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 00187 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 00188 00189 // Take into account whether it's an add or mem instruction 00190 unsigned OffIdx = (i == 2) ? 1 : 2; 00191 00192 // Now add the frame object offset to the offset from r1. 00193 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 00194 MI.getOperand(OffIdx).getImmedValue(); 00195 00196 // If we're not using a Frame Pointer that has been set to the value of the 00197 // SP before having the stack size subtracted from it, then add the stack size 00198 // to Offset to get the correct offset. 00199 Offset += MF.getFrameInfo()->getStackSize(); 00200 00201 if (Offset > 32767 || Offset < -32768) { 00202 // Insert a set of r0 with the full offset value before the ld, st, or add 00203 MachineBasicBlock *MBB = MI.getParent(); 00204 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16)); 00205 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 00206 .addImm(Offset)); 00207 // convert into indexed form of the instruction 00208 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 00209 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 00210 unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()]; 00211 assert(NewOpcode && "No indexed form of load or store available!"); 00212 MI.setOpcode(NewOpcode); 00213 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 00214 MI.SetMachineOperandReg(2, PPC::R0); 00215 } else { 00216 MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset); 00217 } 00218 } 00219 00220 00221 void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const { 00222 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 00223 MachineBasicBlock::iterator MBBI = MBB.begin(); 00224 MachineFrameInfo *MFI = MF.getFrameInfo(); 00225 MachineInstr *MI; 00226 00227 // Get the number of bytes to allocate from the FrameInfo 00228 unsigned NumBytes = MFI->getStackSize(); 00229 00230 // If we have calls, we cannot use the red zone to store callee save registers 00231 // and we must set up a stack frame, so calculate the necessary size here. 00232 if (MFI->hasCalls()) { 00233 // We reserve argument space for call sites in the function immediately on 00234 // entry to the current function. This eliminates the need for add/sub 00235 // brackets around call sites. 00236 NumBytes += MFI->getMaxCallFrameSize(); 00237 } 00238 00239 // Do we need to allocate space on the stack? 00240 if (NumBytes == 0) return; 00241 00242 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 00243 // of the stack and round the size to a multiple of the alignment. 00244 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 00245 unsigned GPRSize = getSpillSize(PPC::R1)/8; 00246 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize; 00247 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 00248 00249 // Update frame info to pretend that this is part of the stack... 00250 MFI->setStackSize(NumBytes); 00251 00252 // adjust stack pointer: r1 -= numbytes 00253 if (NumBytes <= 32768) { 00254 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 00255 MBB.insert(MBBI, MI); 00256 } else { 00257 int NegNumbytes = -NumBytes; 00258 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 00259 MBB.insert(MBBI, MI); 00260 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 00261 .addImm(NegNumbytes & 0xFFFF); 00262 MBB.insert(MBBI, MI); 00263 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 00264 MBB.insert(MBBI, MI); 00265 } 00266 00267 if (hasFP(MF)) { 00268 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 00269 MBB.insert(MBBI, MI); 00270 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 00271 MBB.insert(MBBI, MI); 00272 } 00273 } 00274 00275 void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF, 00276 MachineBasicBlock &MBB) const { 00277 const MachineFrameInfo *MFI = MF.getFrameInfo(); 00278 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 00279 MachineInstr *MI; 00280 assert(MBBI->getOpcode() == PPC::BLR && 00281 "Can only insert epilog into returning blocks"); 00282 00283 // Get the number of bytes allocated from the FrameInfo... 00284 unsigned NumBytes = MFI->getStackSize(); 00285 unsigned GPRSize = getSpillSize(PPC::R31)/8; 00286 00287 if (NumBytes != 0) { 00288 if (hasFP(MF)) { 00289 MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31); 00290 MBB.insert(MBBI, MI); 00291 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31); 00292 MBB.insert(MBBI, MI); 00293 } 00294 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); 00295 MBB.insert(MBBI, MI); 00296 } 00297 } 00298 00299 #include "PPC32GenRegisterInfo.inc" 00300 00301 const TargetRegisterClass* 00302 PPC32RegisterInfo::getRegClassForType(const Type* Ty) const { 00303 switch (Ty->getTypeID()) { 00304 default: assert(0 && "Invalid type to getClass!"); 00305 case Type::LongTyID: 00306 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); 00307 case Type::BoolTyID: 00308 case Type::SByteTyID: 00309 case Type::UByteTyID: 00310 case Type::ShortTyID: 00311 case Type::UShortTyID: 00312 case Type::IntTyID: 00313 case Type::UIntTyID: 00314 case Type::PointerTyID: return &GPRCInstance; 00315 00316 case Type::FloatTyID: 00317 case Type::DoubleTyID: return &FPRCInstance; 00318 } 00319 } 00320