LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Machine Code Emitter 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 unsigned PPC32CodeEmitter::getBinaryCodeForInstr(MachineInstr &MI) { 00012 unsigned Value = 0; 00013 DEBUG(std::cerr << MI); 00014 switch (MI.getOpcode()) { 00015 case PPC::ADD: { 00016 DEBUG(std::cerr << "Emitting ADD\n"); 00017 Value = 2080375316U; 00018 00019 // op0: RT 00020 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00021 op0 &= (1<<5) - 1; 00022 op0 <<= 21; 00023 Value |= op0; 00024 // op1: RA 00025 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00026 op1 &= (1<<5) - 1; 00027 op1 <<= 16; 00028 Value |= op1; 00029 // op2: RB 00030 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00031 op2 &= (1<<5) - 1; 00032 op2 <<= 11; 00033 Value |= op2; 00034 break; 00035 } 00036 case PPC::ADDC: { 00037 DEBUG(std::cerr << "Emitting ADDC\n"); 00038 Value = 2080374804U; 00039 00040 // op0: RT 00041 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00042 op0 &= (1<<5) - 1; 00043 op0 <<= 21; 00044 Value |= op0; 00045 // op1: RA 00046 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00047 op1 &= (1<<5) - 1; 00048 op1 <<= 16; 00049 Value |= op1; 00050 // op2: RB 00051 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00052 op2 &= (1<<5) - 1; 00053 op2 <<= 11; 00054 Value |= op2; 00055 break; 00056 } 00057 case PPC::ADDE: { 00058 DEBUG(std::cerr << "Emitting ADDE\n"); 00059 Value = 2080375060U; 00060 00061 // op0: RT 00062 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00063 op0 &= (1<<5) - 1; 00064 op0 <<= 21; 00065 Value |= op0; 00066 // op1: RA 00067 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00068 op1 &= (1<<5) - 1; 00069 op1 <<= 16; 00070 Value |= op1; 00071 // op2: RB 00072 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00073 op2 &= (1<<5) - 1; 00074 op2 <<= 11; 00075 Value |= op2; 00076 break; 00077 } 00078 case PPC::ADDI: { 00079 DEBUG(std::cerr << "Emitting ADDI\n"); 00080 Value = 939524096U; 00081 00082 // op0: A 00083 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00084 op0 &= (1<<5) - 1; 00085 op0 <<= 21; 00086 Value |= op0; 00087 // op1: B 00088 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00089 op1 &= (1<<5) - 1; 00090 op1 <<= 16; 00091 Value |= op1; 00092 // op2: C 00093 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00094 op2 &= (1<<16) - 1; 00095 Value |= op2; 00096 break; 00097 } 00098 case PPC::ADDIC: { 00099 DEBUG(std::cerr << "Emitting ADDIC\n"); 00100 Value = 805306368U; 00101 00102 // op0: A 00103 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00104 op0 &= (1<<5) - 1; 00105 op0 <<= 21; 00106 Value |= op0; 00107 // op1: B 00108 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00109 op1 &= (1<<5) - 1; 00110 op1 <<= 16; 00111 Value |= op1; 00112 // op2: C 00113 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00114 op2 &= (1<<16) - 1; 00115 Value |= op2; 00116 break; 00117 } 00118 case PPC::ADDICo: { 00119 DEBUG(std::cerr << "Emitting ADDICo\n"); 00120 Value = 872415232U; 00121 00122 // op0: A 00123 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00124 op0 &= (1<<5) - 1; 00125 op0 <<= 21; 00126 Value |= op0; 00127 // op1: B 00128 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00129 op1 &= (1<<5) - 1; 00130 op1 <<= 16; 00131 Value |= op1; 00132 // op2: C 00133 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00134 op2 &= (1<<16) - 1; 00135 Value |= op2; 00136 break; 00137 } 00138 case PPC::ADDIS: { 00139 DEBUG(std::cerr << "Emitting ADDIS\n"); 00140 Value = 1006632960U; 00141 00142 // op0: A 00143 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00144 op0 &= (1<<5) - 1; 00145 op0 <<= 21; 00146 Value |= op0; 00147 // op1: B 00148 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00149 op1 &= (1<<5) - 1; 00150 op1 <<= 16; 00151 Value |= op1; 00152 // op2: C 00153 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00154 op2 &= (1<<16) - 1; 00155 Value |= op2; 00156 break; 00157 } 00158 case PPC::ADDME: { 00159 DEBUG(std::cerr << "Emitting ADDME\n"); 00160 Value = 2080375252U; 00161 00162 // op0: RT 00163 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00164 op0 &= (1<<5) - 1; 00165 op0 <<= 21; 00166 Value |= op0; 00167 // op1: RA 00168 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00169 op1 &= (1<<5) - 1; 00170 op1 <<= 16; 00171 Value |= op1; 00172 break; 00173 } 00174 case PPC::ADDZE: { 00175 DEBUG(std::cerr << "Emitting ADDZE\n"); 00176 Value = 2080375188U; 00177 00178 // op0: RT 00179 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00180 op0 &= (1<<5) - 1; 00181 op0 <<= 21; 00182 Value |= op0; 00183 // op1: RA 00184 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00185 op1 &= (1<<5) - 1; 00186 op1 <<= 16; 00187 Value |= op1; 00188 break; 00189 } 00190 case PPC::ADJCALLSTACKDOWN: { 00191 DEBUG(std::cerr << "Emitting ADJCALLSTACKDOWN\n"); 00192 Value = 0U; 00193 00194 break; 00195 } 00196 case PPC::ADJCALLSTACKUP: { 00197 DEBUG(std::cerr << "Emitting ADJCALLSTACKUP\n"); 00198 Value = 0U; 00199 00200 break; 00201 } 00202 case PPC::AND: { 00203 DEBUG(std::cerr << "Emitting AND\n"); 00204 Value = 2080374840U; 00205 00206 // op0: A 00207 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00208 op0 &= (1<<5) - 1; 00209 op0 <<= 16; 00210 Value |= op0; 00211 // op1: RST 00212 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00213 op1 &= (1<<5) - 1; 00214 op1 <<= 21; 00215 Value |= op1; 00216 // op2: B 00217 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00218 op2 &= (1<<5) - 1; 00219 op2 <<= 11; 00220 Value |= op2; 00221 break; 00222 } 00223 case PPC::ANDC: { 00224 DEBUG(std::cerr << "Emitting ANDC\n"); 00225 Value = 2080374904U; 00226 00227 // op0: A 00228 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00229 op0 &= (1<<5) - 1; 00230 op0 <<= 16; 00231 Value |= op0; 00232 // op1: RST 00233 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00234 op1 &= (1<<5) - 1; 00235 op1 <<= 21; 00236 Value |= op1; 00237 // op2: B 00238 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00239 op2 &= (1<<5) - 1; 00240 op2 <<= 11; 00241 Value |= op2; 00242 break; 00243 } 00244 case PPC::ANDISo: { 00245 DEBUG(std::cerr << "Emitting ANDISo\n"); 00246 Value = 1946157056U; 00247 00248 // op0: B 00249 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00250 op0 &= (1<<5) - 1; 00251 op0 <<= 16; 00252 Value |= op0; 00253 // op1: A 00254 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00255 op1 &= (1<<5) - 1; 00256 op1 <<= 21; 00257 Value |= op1; 00258 // op2: C 00259 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00260 op2 &= (1<<16) - 1; 00261 Value |= op2; 00262 break; 00263 } 00264 case PPC::ANDIo: { 00265 DEBUG(std::cerr << "Emitting ANDIo\n"); 00266 Value = 1879048192U; 00267 00268 // op0: B 00269 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00270 op0 &= (1<<5) - 1; 00271 op0 <<= 16; 00272 Value |= op0; 00273 // op1: A 00274 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00275 op1 &= (1<<5) - 1; 00276 op1 <<= 21; 00277 Value |= op1; 00278 // op2: C 00279 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00280 op2 &= (1<<16) - 1; 00281 Value |= op2; 00282 break; 00283 } 00284 case PPC::B: { 00285 DEBUG(std::cerr << "Emitting B\n"); 00286 Value = 1207959552U; 00287 00288 // op0: LI 00289 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00290 op0 &= (1<<24) - 1; 00291 op0 <<= 2; 00292 Value |= op0; 00293 break; 00294 } 00295 case PPC::BCTR: { 00296 DEBUG(std::cerr << "Emitting BCTR\n"); 00297 Value = 1317012512U; 00298 00299 break; 00300 } 00301 case PPC::BEQ: { 00302 DEBUG(std::cerr << "Emitting BEQ\n"); 00303 Value = 1099038720U; 00304 00305 // op0: CRNum 00306 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00307 op0 &= (1<<3) - 1; 00308 op0 <<= 18; 00309 Value |= op0; 00310 // op1: BD 00311 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00312 op1 &= (1<<14) - 1; 00313 op1 <<= 2; 00314 Value |= op1; 00315 break; 00316 } 00317 case PPC::BGE: { 00318 DEBUG(std::cerr << "Emitting BGE\n"); 00319 Value = 1082130432U; 00320 00321 // op0: CRNum 00322 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00323 op0 &= (1<<3) - 1; 00324 op0 <<= 18; 00325 Value |= op0; 00326 // op1: BD 00327 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00328 op1 &= (1<<14) - 1; 00329 op1 <<= 2; 00330 Value |= op1; 00331 break; 00332 } 00333 case PPC::BGT: { 00334 DEBUG(std::cerr << "Emitting BGT\n"); 00335 Value = 1098973184U; 00336 00337 // op0: CRNum 00338 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00339 op0 &= (1<<3) - 1; 00340 op0 <<= 18; 00341 Value |= op0; 00342 // op1: BD 00343 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00344 op1 &= (1<<14) - 1; 00345 op1 <<= 2; 00346 Value |= op1; 00347 break; 00348 } 00349 case PPC::BL: { 00350 DEBUG(std::cerr << "Emitting BL\n"); 00351 Value = 1207959553U; 00352 00353 // op0: LI 00354 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00355 op0 &= (1<<24) - 1; 00356 op0 <<= 2; 00357 Value |= op0; 00358 break; 00359 } 00360 case PPC::BLE: { 00361 DEBUG(std::cerr << "Emitting BLE\n"); 00362 Value = 1082195968U; 00363 00364 // op0: CRNum 00365 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00366 op0 &= (1<<3) - 1; 00367 op0 <<= 18; 00368 Value |= op0; 00369 // op1: BD 00370 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00371 op1 &= (1<<14) - 1; 00372 op1 <<= 2; 00373 Value |= op1; 00374 break; 00375 } 00376 case PPC::BLR: { 00377 DEBUG(std::cerr << "Emitting BLR\n"); 00378 Value = 1317011488U; 00379 00380 break; 00381 } 00382 case PPC::BLT: { 00383 DEBUG(std::cerr << "Emitting BLT\n"); 00384 Value = 1098907648U; 00385 00386 // op0: CRNum 00387 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00388 op0 &= (1<<3) - 1; 00389 op0 <<= 18; 00390 Value |= op0; 00391 // op1: BD 00392 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00393 op1 &= (1<<14) - 1; 00394 op1 <<= 2; 00395 Value |= op1; 00396 break; 00397 } 00398 case PPC::BNE: { 00399 DEBUG(std::cerr << "Emitting BNE\n"); 00400 Value = 1082261504U; 00401 00402 // op0: CRNum 00403 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00404 op0 &= (1<<3) - 1; 00405 op0 <<= 18; 00406 Value |= op0; 00407 // op1: BD 00408 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00409 op1 &= (1<<14) - 1; 00410 op1 <<= 2; 00411 Value |= op1; 00412 break; 00413 } 00414 case PPC::CALLindirect: { 00415 DEBUG(std::cerr << "Emitting CALLindirect\n"); 00416 Value = 1317012513U; 00417 00418 break; 00419 } 00420 case PPC::CALLpcrel: { 00421 DEBUG(std::cerr << "Emitting CALLpcrel\n"); 00422 Value = 1207959553U; 00423 00424 // op0: LI 00425 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00426 op0 &= (1<<24) - 1; 00427 op0 <<= 2; 00428 Value |= op0; 00429 break; 00430 } 00431 case PPC::CMP: { 00432 DEBUG(std::cerr << "Emitting CMP\n"); 00433 Value = 2080374784U; 00434 00435 // op0: BF 00436 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00437 op0 &= (1<<3) - 1; 00438 op0 <<= 23; 00439 Value |= op0; 00440 // op1: L 00441 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00442 op1 &= (1<<1) - 1; 00443 op1 <<= 21; 00444 Value |= op1; 00445 // op2: RA 00446 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00447 op2 &= (1<<5) - 1; 00448 op2 <<= 16; 00449 Value |= op2; 00450 // op3: RB 00451 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 00452 op3 &= (1<<5) - 1; 00453 op3 <<= 11; 00454 Value |= op3; 00455 break; 00456 } 00457 case PPC::CMPD: { 00458 DEBUG(std::cerr << "Emitting CMPD\n"); 00459 Value = 2082471936U; 00460 00461 // op0: BF 00462 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00463 op0 &= (1<<3) - 1; 00464 op0 <<= 23; 00465 Value |= op0; 00466 // op1: RA 00467 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00468 op1 &= (1<<5) - 1; 00469 op1 <<= 16; 00470 Value |= op1; 00471 // op2: RB 00472 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00473 op2 &= (1<<5) - 1; 00474 op2 <<= 11; 00475 Value |= op2; 00476 break; 00477 } 00478 case PPC::CMPDI: { 00479 DEBUG(std::cerr << "Emitting CMPDI\n"); 00480 Value = 740294656U; 00481 00482 // op0: BF 00483 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00484 op0 &= (1<<3) - 1; 00485 op0 <<= 23; 00486 Value |= op0; 00487 // op1: RA 00488 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00489 op1 &= (1<<5) - 1; 00490 op1 <<= 16; 00491 Value |= op1; 00492 // op2: I 00493 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00494 op2 &= (1<<16) - 1; 00495 Value |= op2; 00496 break; 00497 } 00498 case PPC::CMPI: { 00499 DEBUG(std::cerr << "Emitting CMPI\n"); 00500 Value = 738197504U; 00501 00502 // op0: BF 00503 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00504 op0 &= (1<<3) - 1; 00505 op0 <<= 23; 00506 Value |= op0; 00507 // op1: L 00508 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00509 op1 &= (1<<1) - 1; 00510 op1 <<= 21; 00511 Value |= op1; 00512 // op2: RA 00513 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00514 op2 &= (1<<5) - 1; 00515 op2 <<= 16; 00516 Value |= op2; 00517 // op3: I 00518 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 00519 op3 &= (1<<16) - 1; 00520 Value |= op3; 00521 break; 00522 } 00523 case PPC::CMPL: { 00524 DEBUG(std::cerr << "Emitting CMPL\n"); 00525 Value = 2080374848U; 00526 00527 // op0: BF 00528 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00529 op0 &= (1<<3) - 1; 00530 op0 <<= 23; 00531 Value |= op0; 00532 // op1: L 00533 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00534 op1 &= (1<<1) - 1; 00535 op1 <<= 21; 00536 Value |= op1; 00537 // op2: RA 00538 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00539 op2 &= (1<<5) - 1; 00540 op2 <<= 16; 00541 Value |= op2; 00542 // op3: RB 00543 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 00544 op3 &= (1<<5) - 1; 00545 op3 <<= 11; 00546 Value |= op3; 00547 break; 00548 } 00549 case PPC::CMPLD: { 00550 DEBUG(std::cerr << "Emitting CMPLD\n"); 00551 Value = 2082472000U; 00552 00553 // op0: BF 00554 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00555 op0 &= (1<<3) - 1; 00556 op0 <<= 23; 00557 Value |= op0; 00558 // op1: RA 00559 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00560 op1 &= (1<<5) - 1; 00561 op1 <<= 16; 00562 Value |= op1; 00563 // op2: RB 00564 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00565 op2 &= (1<<5) - 1; 00566 op2 <<= 11; 00567 Value |= op2; 00568 break; 00569 } 00570 case PPC::CMPLDI: { 00571 DEBUG(std::cerr << "Emitting CMPLDI\n"); 00572 Value = 673185792U; 00573 00574 // op0: BF 00575 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00576 op0 &= (1<<3) - 1; 00577 op0 <<= 23; 00578 Value |= op0; 00579 // op1: RA 00580 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00581 op1 &= (1<<5) - 1; 00582 op1 <<= 16; 00583 Value |= op1; 00584 // op2: I 00585 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00586 op2 &= (1<<16) - 1; 00587 Value |= op2; 00588 break; 00589 } 00590 case PPC::CMPLI: { 00591 DEBUG(std::cerr << "Emitting CMPLI\n"); 00592 Value = 671088640U; 00593 00594 // op0: BF 00595 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00596 op0 &= (1<<3) - 1; 00597 op0 <<= 23; 00598 Value |= op0; 00599 // op1: L 00600 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00601 op1 &= (1<<1) - 1; 00602 op1 <<= 21; 00603 Value |= op1; 00604 // op2: RA 00605 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00606 op2 &= (1<<5) - 1; 00607 op2 <<= 16; 00608 Value |= op2; 00609 // op3: I 00610 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 00611 op3 &= (1<<16) - 1; 00612 Value |= op3; 00613 break; 00614 } 00615 case PPC::CMPLW: { 00616 DEBUG(std::cerr << "Emitting CMPLW\n"); 00617 Value = 2080374848U; 00618 00619 // op0: BF 00620 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00621 op0 &= (1<<3) - 1; 00622 op0 <<= 23; 00623 Value |= op0; 00624 // op1: RA 00625 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00626 op1 &= (1<<5) - 1; 00627 op1 <<= 16; 00628 Value |= op1; 00629 // op2: RB 00630 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00631 op2 &= (1<<5) - 1; 00632 op2 <<= 11; 00633 Value |= op2; 00634 break; 00635 } 00636 case PPC::CMPLWI: { 00637 DEBUG(std::cerr << "Emitting CMPLWI\n"); 00638 Value = 671088640U; 00639 00640 // op0: BF 00641 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00642 op0 &= (1<<3) - 1; 00643 op0 <<= 23; 00644 Value |= op0; 00645 // op1: RA 00646 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00647 op1 &= (1<<5) - 1; 00648 op1 <<= 16; 00649 Value |= op1; 00650 // op2: I 00651 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00652 op2 &= (1<<16) - 1; 00653 Value |= op2; 00654 break; 00655 } 00656 case PPC::CMPW: { 00657 DEBUG(std::cerr << "Emitting CMPW\n"); 00658 Value = 2080374784U; 00659 00660 // op0: BF 00661 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00662 op0 &= (1<<3) - 1; 00663 op0 <<= 23; 00664 Value |= op0; 00665 // op1: RA 00666 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00667 op1 &= (1<<5) - 1; 00668 op1 <<= 16; 00669 Value |= op1; 00670 // op2: RB 00671 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00672 op2 &= (1<<5) - 1; 00673 op2 <<= 11; 00674 Value |= op2; 00675 break; 00676 } 00677 case PPC::CMPWI: { 00678 DEBUG(std::cerr << "Emitting CMPWI\n"); 00679 Value = 738197504U; 00680 00681 // op0: BF 00682 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00683 op0 &= (1<<3) - 1; 00684 op0 <<= 23; 00685 Value |= op0; 00686 // op1: RA 00687 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00688 op1 &= (1<<5) - 1; 00689 op1 <<= 16; 00690 Value |= op1; 00691 // op2: I 00692 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00693 op2 &= (1<<16) - 1; 00694 Value |= op2; 00695 break; 00696 } 00697 case PPC::CNTLZW: { 00698 DEBUG(std::cerr << "Emitting CNTLZW\n"); 00699 Value = 2080374836U; 00700 00701 // op0: A 00702 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00703 op0 &= (1<<5) - 1; 00704 op0 <<= 16; 00705 Value |= op0; 00706 // op1: RST 00707 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00708 op1 &= (1<<5) - 1; 00709 op1 <<= 21; 00710 Value |= op1; 00711 break; 00712 } 00713 case PPC::COND_BRANCH: { 00714 DEBUG(std::cerr << "Emitting COND_BRANCH\n"); 00715 Value = 0U; 00716 00717 break; 00718 } 00719 case PPC::CRAND: { 00720 DEBUG(std::cerr << "Emitting CRAND\n"); 00721 Value = 1275068930U; 00722 00723 // op0: RST 00724 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00725 op0 &= (1<<5) - 1; 00726 op0 <<= 21; 00727 Value |= op0; 00728 // op1: A 00729 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00730 op1 &= (1<<5) - 1; 00731 op1 <<= 16; 00732 Value |= op1; 00733 // op2: B 00734 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00735 op2 &= (1<<5) - 1; 00736 op2 <<= 11; 00737 Value |= op2; 00738 break; 00739 } 00740 case PPC::CRANDC: { 00741 DEBUG(std::cerr << "Emitting CRANDC\n"); 00742 Value = 1275068674U; 00743 00744 // op0: RST 00745 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00746 op0 &= (1<<5) - 1; 00747 op0 <<= 21; 00748 Value |= op0; 00749 // op1: A 00750 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00751 op1 &= (1<<5) - 1; 00752 op1 <<= 16; 00753 Value |= op1; 00754 // op2: B 00755 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00756 op2 &= (1<<5) - 1; 00757 op2 <<= 11; 00758 Value |= op2; 00759 break; 00760 } 00761 case PPC::CRNOR: { 00762 DEBUG(std::cerr << "Emitting CRNOR\n"); 00763 Value = 1275068482U; 00764 00765 // op0: RST 00766 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00767 op0 &= (1<<5) - 1; 00768 op0 <<= 21; 00769 Value |= op0; 00770 // op1: A 00771 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00772 op1 &= (1<<5) - 1; 00773 op1 <<= 16; 00774 Value |= op1; 00775 // op2: B 00776 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00777 op2 &= (1<<5) - 1; 00778 op2 <<= 11; 00779 Value |= op2; 00780 break; 00781 } 00782 case PPC::CROR: { 00783 DEBUG(std::cerr << "Emitting CROR\n"); 00784 Value = 1275069314U; 00785 00786 // op0: RST 00787 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00788 op0 &= (1<<5) - 1; 00789 op0 <<= 21; 00790 Value |= op0; 00791 // op1: A 00792 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00793 op1 &= (1<<5) - 1; 00794 op1 <<= 16; 00795 Value |= op1; 00796 // op2: B 00797 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00798 op2 &= (1<<5) - 1; 00799 op2 <<= 11; 00800 Value |= op2; 00801 break; 00802 } 00803 case PPC::DIVD: { 00804 DEBUG(std::cerr << "Emitting DIVD\n"); 00805 Value = 2080375762U; 00806 00807 // op0: RT 00808 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00809 op0 &= (1<<5) - 1; 00810 op0 <<= 21; 00811 Value |= op0; 00812 // op1: RA 00813 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00814 op1 &= (1<<5) - 1; 00815 op1 <<= 16; 00816 Value |= op1; 00817 // op2: RB 00818 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00819 op2 &= (1<<5) - 1; 00820 op2 <<= 11; 00821 Value |= op2; 00822 break; 00823 } 00824 case PPC::DIVDU: { 00825 DEBUG(std::cerr << "Emitting DIVDU\n"); 00826 Value = 2080375698U; 00827 00828 // op0: RT 00829 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00830 op0 &= (1<<5) - 1; 00831 op0 <<= 21; 00832 Value |= op0; 00833 // op1: RA 00834 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00835 op1 &= (1<<5) - 1; 00836 op1 <<= 16; 00837 Value |= op1; 00838 // op2: RB 00839 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00840 op2 &= (1<<5) - 1; 00841 op2 <<= 11; 00842 Value |= op2; 00843 break; 00844 } 00845 case PPC::DIVW: { 00846 DEBUG(std::cerr << "Emitting DIVW\n"); 00847 Value = 2080375766U; 00848 00849 // op0: RT 00850 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00851 op0 &= (1<<5) - 1; 00852 op0 <<= 21; 00853 Value |= op0; 00854 // op1: RA 00855 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00856 op1 &= (1<<5) - 1; 00857 op1 <<= 16; 00858 Value |= op1; 00859 // op2: RB 00860 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00861 op2 &= (1<<5) - 1; 00862 op2 <<= 11; 00863 Value |= op2; 00864 break; 00865 } 00866 case PPC::DIVWU: { 00867 DEBUG(std::cerr << "Emitting DIVWU\n"); 00868 Value = 2080375702U; 00869 00870 // op0: RT 00871 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00872 op0 &= (1<<5) - 1; 00873 op0 <<= 21; 00874 Value |= op0; 00875 // op1: RA 00876 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00877 op1 &= (1<<5) - 1; 00878 op1 <<= 16; 00879 Value |= op1; 00880 // op2: RB 00881 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00882 op2 &= (1<<5) - 1; 00883 op2 <<= 11; 00884 Value |= op2; 00885 break; 00886 } 00887 case PPC::EQV: { 00888 DEBUG(std::cerr << "Emitting EQV\n"); 00889 Value = 2080375352U; 00890 00891 // op0: A 00892 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00893 op0 &= (1<<5) - 1; 00894 op0 <<= 16; 00895 Value |= op0; 00896 // op1: RST 00897 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00898 op1 &= (1<<5) - 1; 00899 op1 <<= 21; 00900 Value |= op1; 00901 // op2: B 00902 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00903 op2 &= (1<<5) - 1; 00904 op2 <<= 11; 00905 Value |= op2; 00906 break; 00907 } 00908 case PPC::EXTSB: { 00909 DEBUG(std::cerr << "Emitting EXTSB\n"); 00910 Value = 2080376692U; 00911 00912 // op0: A 00913 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00914 op0 &= (1<<5) - 1; 00915 op0 <<= 16; 00916 Value |= op0; 00917 // op1: RST 00918 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00919 op1 &= (1<<5) - 1; 00920 op1 <<= 21; 00921 Value |= op1; 00922 break; 00923 } 00924 case PPC::EXTSH: { 00925 DEBUG(std::cerr << "Emitting EXTSH\n"); 00926 Value = 2080376628U; 00927 00928 // op0: A 00929 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00930 op0 &= (1<<5) - 1; 00931 op0 <<= 16; 00932 Value |= op0; 00933 // op1: RST 00934 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00935 op1 &= (1<<5) - 1; 00936 op1 <<= 21; 00937 Value |= op1; 00938 break; 00939 } 00940 case PPC::EXTSW: { 00941 DEBUG(std::cerr << "Emitting EXTSW\n"); 00942 Value = 2080376756U; 00943 00944 // op0: A 00945 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00946 op0 &= (1<<5) - 1; 00947 op0 <<= 16; 00948 Value |= op0; 00949 // op1: RST 00950 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00951 op1 &= (1<<5) - 1; 00952 op1 <<= 21; 00953 Value |= op1; 00954 break; 00955 } 00956 case PPC::FADD: { 00957 DEBUG(std::cerr << "Emitting FADD\n"); 00958 Value = 4227858474U; 00959 00960 // op0: FRT 00961 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00962 op0 &= (1<<5) - 1; 00963 op0 <<= 21; 00964 Value |= op0; 00965 // op1: FRA 00966 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00967 op1 &= (1<<5) - 1; 00968 op1 <<= 16; 00969 Value |= op1; 00970 // op2: FRB 00971 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00972 op2 &= (1<<5) - 1; 00973 op2 <<= 11; 00974 Value |= op2; 00975 break; 00976 } 00977 case PPC::FADDS: { 00978 DEBUG(std::cerr << "Emitting FADDS\n"); 00979 Value = 3959423018U; 00980 00981 // op0: FRT 00982 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00983 op0 &= (1<<5) - 1; 00984 op0 <<= 21; 00985 Value |= op0; 00986 // op1: FRA 00987 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00988 op1 &= (1<<5) - 1; 00989 op1 <<= 16; 00990 Value |= op1; 00991 // op2: FRB 00992 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00993 op2 &= (1<<5) - 1; 00994 op2 <<= 11; 00995 Value |= op2; 00996 break; 00997 } 00998 case PPC::FCFID: { 00999 DEBUG(std::cerr << "Emitting FCFID\n"); 01000 Value = 4227860124U; 01001 01002 // op0: RST 01003 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01004 op0 &= (1<<5) - 1; 01005 op0 <<= 21; 01006 Value |= op0; 01007 // op1: B 01008 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01009 op1 &= (1<<5) - 1; 01010 op1 <<= 11; 01011 Value |= op1; 01012 break; 01013 } 01014 case PPC::FCMPU: { 01015 DEBUG(std::cerr << "Emitting FCMPU\n"); 01016 Value = 4227858432U; 01017 01018 // op0: BF 01019 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01020 op0 &= (1<<3) - 1; 01021 op0 <<= 23; 01022 Value |= op0; 01023 // op1: FRA 01024 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01025 op1 &= (1<<5) - 1; 01026 op1 <<= 16; 01027 Value |= op1; 01028 // op2: FRB 01029 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01030 op2 &= (1<<5) - 1; 01031 op2 <<= 11; 01032 Value |= op2; 01033 break; 01034 } 01035 case PPC::FCTIDZ: { 01036 DEBUG(std::cerr << "Emitting FCTIDZ\n"); 01037 Value = 4227860062U; 01038 01039 // op0: RST 01040 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01041 op0 &= (1<<5) - 1; 01042 op0 <<= 21; 01043 Value |= op0; 01044 // op1: B 01045 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01046 op1 &= (1<<5) - 1; 01047 op1 <<= 11; 01048 Value |= op1; 01049 break; 01050 } 01051 case PPC::FCTIWZ: { 01052 DEBUG(std::cerr << "Emitting FCTIWZ\n"); 01053 Value = 4227858462U; 01054 01055 // op0: RST 01056 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01057 op0 &= (1<<5) - 1; 01058 op0 <<= 21; 01059 Value |= op0; 01060 // op1: B 01061 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01062 op1 &= (1<<5) - 1; 01063 op1 <<= 11; 01064 Value |= op1; 01065 break; 01066 } 01067 case PPC::FDIV: { 01068 DEBUG(std::cerr << "Emitting FDIV\n"); 01069 Value = 4227858468U; 01070 01071 // op0: FRT 01072 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01073 op0 &= (1<<5) - 1; 01074 op0 <<= 21; 01075 Value |= op0; 01076 // op1: FRA 01077 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01078 op1 &= (1<<5) - 1; 01079 op1 <<= 16; 01080 Value |= op1; 01081 // op2: FRB 01082 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01083 op2 &= (1<<5) - 1; 01084 op2 <<= 11; 01085 Value |= op2; 01086 break; 01087 } 01088 case PPC::FDIVS: { 01089 DEBUG(std::cerr << "Emitting FDIVS\n"); 01090 Value = 3959423012U; 01091 01092 // op0: FRT 01093 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01094 op0 &= (1<<5) - 1; 01095 op0 <<= 21; 01096 Value |= op0; 01097 // op1: FRA 01098 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01099 op1 &= (1<<5) - 1; 01100 op1 <<= 16; 01101 Value |= op1; 01102 // op2: FRB 01103 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01104 op2 &= (1<<5) - 1; 01105 op2 <<= 11; 01106 Value |= op2; 01107 break; 01108 } 01109 case PPC::FMADD: { 01110 DEBUG(std::cerr << "Emitting FMADD\n"); 01111 Value = 4227858490U; 01112 01113 // op0: FRT 01114 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01115 op0 &= (1<<5) - 1; 01116 op0 <<= 21; 01117 Value |= op0; 01118 // op1: FRA 01119 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01120 op1 &= (1<<5) - 1; 01121 op1 <<= 16; 01122 Value |= op1; 01123 // op2: FRC 01124 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01125 op2 &= (1<<5) - 1; 01126 op2 <<= 6; 01127 Value |= op2; 01128 // op3: FRB 01129 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 01130 op3 &= (1<<5) - 1; 01131 op3 <<= 11; 01132 Value |= op3; 01133 break; 01134 } 01135 case PPC::FMR: { 01136 DEBUG(std::cerr << "Emitting FMR\n"); 01137 Value = 4227858576U; 01138 01139 // op0: RST 01140 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01141 op0 &= (1<<5) - 1; 01142 op0 <<= 21; 01143 Value |= op0; 01144 // op1: B 01145 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01146 op1 &= (1<<5) - 1; 01147 op1 <<= 11; 01148 Value |= op1; 01149 break; 01150 } 01151 case PPC::FMUL: { 01152 DEBUG(std::cerr << "Emitting FMUL\n"); 01153 Value = 4227858482U; 01154 01155 // op0: FRT 01156 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01157 op0 &= (1<<5) - 1; 01158 op0 <<= 21; 01159 Value |= op0; 01160 // op1: FRA 01161 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01162 op1 &= (1<<5) - 1; 01163 op1 <<= 16; 01164 Value |= op1; 01165 // op2: FRC 01166 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01167 op2 &= (1<<5) - 1; 01168 op2 <<= 6; 01169 Value |= op2; 01170 break; 01171 } 01172 case PPC::FMULS: { 01173 DEBUG(std::cerr << "Emitting FMULS\n"); 01174 Value = 3959423026U; 01175 01176 // op0: FRT 01177 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01178 op0 &= (1<<5) - 1; 01179 op0 <<= 21; 01180 Value |= op0; 01181 // op1: FRA 01182 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01183 op1 &= (1<<5) - 1; 01184 op1 <<= 16; 01185 Value |= op1; 01186 // op2: FRC 01187 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01188 op2 &= (1<<5) - 1; 01189 op2 <<= 6; 01190 Value |= op2; 01191 break; 01192 } 01193 case PPC::FNEG: { 01194 DEBUG(std::cerr << "Emitting FNEG\n"); 01195 Value = 4227858512U; 01196 01197 // op0: RST 01198 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01199 op0 &= (1<<5) - 1; 01200 op0 <<= 21; 01201 Value |= op0; 01202 // op1: B 01203 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01204 op1 &= (1<<5) - 1; 01205 op1 <<= 11; 01206 Value |= op1; 01207 break; 01208 } 01209 case PPC::FRSP: { 01210 DEBUG(std::cerr << "Emitting FRSP\n"); 01211 Value = 4227858456U; 01212 01213 // op0: RST 01214 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01215 op0 &= (1<<5) - 1; 01216 op0 <<= 21; 01217 Value |= op0; 01218 // op1: B 01219 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01220 op1 &= (1<<5) - 1; 01221 op1 <<= 11; 01222 Value |= op1; 01223 break; 01224 } 01225 case PPC::FSEL: { 01226 DEBUG(std::cerr << "Emitting FSEL\n"); 01227 Value = 4227858478U; 01228 01229 // op0: FRT 01230 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01231 op0 &= (1<<5) - 1; 01232 op0 <<= 21; 01233 Value |= op0; 01234 // op1: FRA 01235 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01236 op1 &= (1<<5) - 1; 01237 op1 <<= 16; 01238 Value |= op1; 01239 // op2: FRC 01240 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01241 op2 &= (1<<5) - 1; 01242 op2 <<= 6; 01243 Value |= op2; 01244 // op3: FRB 01245 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 01246 op3 &= (1<<5) - 1; 01247 op3 <<= 11; 01248 Value |= op3; 01249 break; 01250 } 01251 case PPC::FSUB: { 01252 DEBUG(std::cerr << "Emitting FSUB\n"); 01253 Value = 4227858472U; 01254 01255 // op0: FRT 01256 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01257 op0 &= (1<<5) - 1; 01258 op0 <<= 21; 01259 Value |= op0; 01260 // op1: FRA 01261 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01262 op1 &= (1<<5) - 1; 01263 op1 <<= 16; 01264 Value |= op1; 01265 // op2: FRB 01266 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01267 op2 &= (1<<5) - 1; 01268 op2 <<= 11; 01269 Value |= op2; 01270 break; 01271 } 01272 case PPC::FSUBS: { 01273 DEBUG(std::cerr << "Emitting FSUBS\n"); 01274 Value = 3959423016U; 01275 01276 // op0: FRT 01277 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01278 op0 &= (1<<5) - 1; 01279 op0 <<= 21; 01280 Value |= op0; 01281 // op1: FRA 01282 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01283 op1 &= (1<<5) - 1; 01284 op1 <<= 16; 01285 Value |= op1; 01286 // op2: FRB 01287 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01288 op2 &= (1<<5) - 1; 01289 op2 <<= 11; 01290 Value |= op2; 01291 break; 01292 } 01293 case PPC::IMPLICIT_DEF: { 01294 DEBUG(std::cerr << "Emitting IMPLICIT_DEF\n"); 01295 Value = 0U; 01296 01297 break; 01298 } 01299 case PPC::LA: { 01300 DEBUG(std::cerr << "Emitting LA\n"); 01301 Value = 939524096U; 01302 01303 // op0: A 01304 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01305 op0 &= (1<<5) - 1; 01306 op0 <<= 21; 01307 Value |= op0; 01308 // op1: B 01309 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01310 op1 &= (1<<5) - 1; 01311 op1 <<= 16; 01312 Value |= op1; 01313 // op2: C 01314 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01315 op2 &= (1<<16) - 1; 01316 Value |= op2; 01317 break; 01318 } 01319 case PPC::LBZ: { 01320 DEBUG(std::cerr << "Emitting LBZ\n"); 01321 Value = 2281701376U; 01322 01323 // op0: A 01324 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01325 op0 &= (1<<5) - 1; 01326 op0 <<= 21; 01327 Value |= op0; 01328 // op1: C 01329 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01330 op1 &= (1<<16) - 1; 01331 Value |= op1; 01332 // op2: B 01333 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01334 op2 &= (1<<5) - 1; 01335 op2 <<= 16; 01336 Value |= op2; 01337 break; 01338 } 01339 case PPC::LBZX: { 01340 DEBUG(std::cerr << "Emitting LBZX\n"); 01341 Value = 2080374958U; 01342 01343 // op0: RST 01344 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01345 op0 &= (1<<5) - 1; 01346 op0 <<= 21; 01347 Value |= op0; 01348 // op1: A 01349 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01350 op1 &= (1<<5) - 1; 01351 op1 <<= 16; 01352 Value |= op1; 01353 // op2: B 01354 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01355 op2 &= (1<<5) - 1; 01356 op2 <<= 11; 01357 Value |= op2; 01358 break; 01359 } 01360 case PPC::LD: { 01361 DEBUG(std::cerr << "Emitting LD\n"); 01362 Value = 3892314112U; 01363 01364 // op0: RST 01365 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01366 op0 &= (1<<5) - 1; 01367 op0 <<= 21; 01368 Value |= op0; 01369 // op1: DS 01370 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01371 op1 &= (1<<14) - 1; 01372 op1 <<= 2; 01373 Value |= op1; 01374 // op2: RA 01375 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01376 op2 &= (1<<5) - 1; 01377 op2 <<= 16; 01378 Value |= op2; 01379 break; 01380 } 01381 case PPC::LDX: { 01382 DEBUG(std::cerr << "Emitting LDX\n"); 01383 Value = 2080374826U; 01384 01385 // op0: RST 01386 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01387 op0 &= (1<<5) - 1; 01388 op0 <<= 21; 01389 Value |= op0; 01390 // op1: A 01391 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01392 op1 &= (1<<5) - 1; 01393 op1 <<= 16; 01394 Value |= op1; 01395 // op2: B 01396 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01397 op2 &= (1<<5) - 1; 01398 op2 <<= 11; 01399 Value |= op2; 01400 break; 01401 } 01402 case PPC::LFD: { 01403 DEBUG(std::cerr << "Emitting LFD\n"); 01404 Value = 3355443200U; 01405 01406 // op0: A 01407 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01408 op0 &= (1<<5) - 1; 01409 op0 <<= 21; 01410 Value |= op0; 01411 // op1: C 01412 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01413 op1 &= (1<<16) - 1; 01414 Value |= op1; 01415 // op2: B 01416 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01417 op2 &= (1<<5) - 1; 01418 op2 <<= 16; 01419 Value |= op2; 01420 break; 01421 } 01422 case PPC::LFDX: { 01423 DEBUG(std::cerr << "Emitting LFDX\n"); 01424 Value = 2080375982U; 01425 01426 // op0: RST 01427 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01428 op0 &= (1<<5) - 1; 01429 op0 <<= 21; 01430 Value |= op0; 01431 // op1: A 01432 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01433 op1 &= (1<<5) - 1; 01434 op1 <<= 16; 01435 Value |= op1; 01436 // op2: B 01437 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01438 op2 &= (1<<5) - 1; 01439 op2 <<= 11; 01440 Value |= op2; 01441 break; 01442 } 01443 case PPC::LFS: { 01444 DEBUG(std::cerr << "Emitting LFS\n"); 01445 Value = 3221225472U; 01446 01447 // op0: A 01448 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01449 op0 &= (1<<5) - 1; 01450 op0 <<= 21; 01451 Value |= op0; 01452 // op1: C 01453 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01454 op1 &= (1<<16) - 1; 01455 Value |= op1; 01456 // op2: B 01457 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01458 op2 &= (1<<5) - 1; 01459 op2 <<= 16; 01460 Value |= op2; 01461 break; 01462 } 01463 case PPC::LFSX: { 01464 DEBUG(std::cerr << "Emitting LFSX\n"); 01465 Value = 2080375854U; 01466 01467 // op0: RST 01468 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01469 op0 &= (1<<5) - 1; 01470 op0 <<= 21; 01471 Value |= op0; 01472 // op1: A 01473 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01474 op1 &= (1<<5) - 1; 01475 op1 <<= 16; 01476 Value |= op1; 01477 // op2: B 01478 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01479 op2 &= (1<<5) - 1; 01480 op2 <<= 11; 01481 Value |= op2; 01482 break; 01483 } 01484 case PPC::LHA: { 01485 DEBUG(std::cerr << "Emitting LHA\n"); 01486 Value = 2818572288U; 01487 01488 // op0: A 01489 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01490 op0 &= (1<<5) - 1; 01491 op0 <<= 21; 01492 Value |= op0; 01493 // op1: C 01494 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01495 op1 &= (1<<16) - 1; 01496 Value |= op1; 01497 // op2: B 01498 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01499 op2 &= (1<<5) - 1; 01500 op2 <<= 16; 01501 Value |= op2; 01502 break; 01503 } 01504 case PPC::LHAX: { 01505 DEBUG(std::cerr << "Emitting LHAX\n"); 01506 Value = 2080375470U; 01507 01508 // op0: RST 01509 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01510 op0 &= (1<<5) - 1; 01511 op0 <<= 21; 01512 Value |= op0; 01513 // op1: A 01514 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01515 op1 &= (1<<5) - 1; 01516 op1 <<= 16; 01517 Value |= op1; 01518 // op2: B 01519 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01520 op2 &= (1<<5) - 1; 01521 op2 <<= 11; 01522 Value |= op2; 01523 break; 01524 } 01525 case PPC::LHZ: { 01526 DEBUG(std::cerr << "Emitting LHZ\n"); 01527 Value = 2684354560U; 01528 01529 // op0: A 01530 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01531 op0 &= (1<<5) - 1; 01532 op0 <<= 21; 01533 Value |= op0; 01534 // op1: C 01535 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01536 op1 &= (1<<16) - 1; 01537 Value |= op1; 01538 // op2: B 01539 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01540 op2 &= (1<<5) - 1; 01541 op2 <<= 16; 01542 Value |= op2; 01543 break; 01544 } 01545 case PPC::LHZX: { 01546 DEBUG(std::cerr << "Emitting LHZX\n"); 01547 Value = 2080375342U; 01548 01549 // op0: RST 01550 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01551 op0 &= (1<<5) - 1; 01552 op0 <<= 21; 01553 Value |= op0; 01554 // op1: A 01555 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01556 op1 &= (1<<5) - 1; 01557 op1 <<= 16; 01558 Value |= op1; 01559 // op2: B 01560 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01561 op2 &= (1<<5) - 1; 01562 op2 <<= 11; 01563 Value |= op2; 01564 break; 01565 } 01566 case PPC::LI: { 01567 DEBUG(std::cerr << "Emitting LI\n"); 01568 Value = 939524096U; 01569 01570 // op0: A 01571 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01572 op0 &= (1<<5) - 1; 01573 op0 <<= 21; 01574 Value |= op0; 01575 // op1: B 01576 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01577 op1 &= (1<<16) - 1; 01578 Value |= op1; 01579 break; 01580 } 01581 case PPC::LIS: { 01582 DEBUG(std::cerr << "Emitting LIS\n"); 01583 Value = 1006632960U; 01584 01585 // op0: A 01586 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01587 op0 &= (1<<5) - 1; 01588 op0 <<= 21; 01589 Value |= op0; 01590 // op1: B 01591 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01592 op1 &= (1<<16) - 1; 01593 Value |= op1; 01594 break; 01595 } 01596 case PPC::LMW: { 01597 DEBUG(std::cerr << "Emitting LMW\n"); 01598 Value = 3087007744U; 01599 01600 // op0: A 01601 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01602 op0 &= (1<<5) - 1; 01603 op0 <<= 21; 01604 Value |= op0; 01605 // op1: C 01606 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01607 op1 &= (1<<16) - 1; 01608 Value |= op1; 01609 // op2: B 01610 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01611 op2 &= (1<<5) - 1; 01612 op2 <<= 16; 01613 Value |= op2; 01614 break; 01615 } 01616 case PPC::LOADHiAddr: { 01617 DEBUG(std::cerr << "Emitting LOADHiAddr\n"); 01618 Value = 1006632960U; 01619 01620 // op0: A 01621 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01622 op0 &= (1<<5) - 1; 01623 op0 <<= 21; 01624 Value |= op0; 01625 // op1: B 01626 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01627 op1 &= (1<<5) - 1; 01628 op1 <<= 16; 01629 Value |= op1; 01630 // op2: C 01631 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01632 op2 &= (1<<16) - 1; 01633 Value |= op2; 01634 break; 01635 } 01636 case PPC::LWA: { 01637 DEBUG(std::cerr << "Emitting LWA\n"); 01638 Value = 3892314114U; 01639 01640 // op0: RST 01641 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01642 op0 &= (1<<5) - 1; 01643 op0 <<= 21; 01644 Value |= op0; 01645 // op1: DS 01646 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01647 op1 &= (1<<14) - 1; 01648 op1 <<= 2; 01649 Value |= op1; 01650 // op2: RA 01651 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01652 op2 &= (1<<5) - 1; 01653 op2 <<= 16; 01654 Value |= op2; 01655 break; 01656 } 01657 case PPC::LWAX: { 01658 DEBUG(std::cerr << "Emitting LWAX\n"); 01659 Value = 2080375466U; 01660 01661 // op0: RST 01662 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01663 op0 &= (1<<5) - 1; 01664 op0 <<= 21; 01665 Value |= op0; 01666 // op1: A 01667 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01668 op1 &= (1<<5) - 1; 01669 op1 <<= 16; 01670 Value |= op1; 01671 // op2: B 01672 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01673 op2 &= (1<<5) - 1; 01674 op2 <<= 11; 01675 Value |= op2; 01676 break; 01677 } 01678 case PPC::LWZ: { 01679 DEBUG(std::cerr << "Emitting LWZ\n"); 01680 Value = 2147483648U; 01681 01682 // op0: A 01683 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01684 op0 &= (1<<5) - 1; 01685 op0 <<= 21; 01686 Value |= op0; 01687 // op1: C 01688 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01689 op1 &= (1<<16) - 1; 01690 Value |= op1; 01691 // op2: B 01692 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01693 op2 &= (1<<5) - 1; 01694 op2 <<= 16; 01695 Value |= op2; 01696 break; 01697 } 01698 case PPC::LWZU: { 01699 DEBUG(std::cerr << "Emitting LWZU\n"); 01700 Value = 2348810240U; 01701 01702 // op0: A 01703 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01704 op0 &= (1<<5) - 1; 01705 op0 <<= 21; 01706 Value |= op0; 01707 // op1: C 01708 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01709 op1 &= (1<<16) - 1; 01710 Value |= op1; 01711 // op2: B 01712 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01713 op2 &= (1<<5) - 1; 01714 op2 <<= 16; 01715 Value |= op2; 01716 break; 01717 } 01718 case PPC::LWZX: { 01719 DEBUG(std::cerr << "Emitting LWZX\n"); 01720 Value = 2080374830U; 01721 01722 // op0: RST 01723 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01724 op0 &= (1<<5) - 1; 01725 op0 <<= 21; 01726 Value |= op0; 01727 // op1: A 01728 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01729 op1 &= (1<<5) - 1; 01730 op1 <<= 16; 01731 Value |= op1; 01732 // op2: B 01733 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01734 op2 &= (1<<5) - 1; 01735 op2 <<= 11; 01736 Value |= op2; 01737 break; 01738 } 01739 case PPC::MFCR: { 01740 DEBUG(std::cerr << "Emitting MFCR\n"); 01741 Value = 2080374822U; 01742 01743 // op0: RST 01744 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01745 op0 &= (1<<5) - 1; 01746 op0 <<= 21; 01747 Value |= op0; 01748 break; 01749 } 01750 case PPC::MFCTR: { 01751 DEBUG(std::cerr << "Emitting MFCTR\n"); 01752 Value = 2080965286U; 01753 01754 // op0: ST 01755 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01756 op0 &= (1<<5) - 1; 01757 op0 <<= 21; 01758 Value |= op0; 01759 break; 01760 } 01761 case PPC::MFLR: { 01762 DEBUG(std::cerr << "Emitting MFLR\n"); 01763 Value = 2080899750U; 01764 01765 // op0: ST 01766 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01767 op0 &= (1<<5) - 1; 01768 op0 <<= 21; 01769 Value |= op0; 01770 break; 01771 } 01772 case PPC::MTCTR: { 01773 DEBUG(std::cerr << "Emitting MTCTR\n"); 01774 Value = 2080965542U; 01775 01776 // op0: ST 01777 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01778 op0 &= (1<<5) - 1; 01779 op0 <<= 21; 01780 Value |= op0; 01781 break; 01782 } 01783 case PPC::MTLR: { 01784 DEBUG(std::cerr << "Emitting MTLR\n"); 01785 Value = 2080900006U; 01786 01787 // op0: ST 01788 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01789 op0 &= (1<<5) - 1; 01790 op0 <<= 21; 01791 Value |= op0; 01792 break; 01793 } 01794 case PPC::MULHWU: { 01795 DEBUG(std::cerr << "Emitting MULHWU\n"); 01796 Value = 2080374806U; 01797 01798 // op0: RT 01799 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01800 op0 &= (1<<5) - 1; 01801 op0 <<= 21; 01802 Value |= op0; 01803 // op1: RA 01804 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01805 op1 &= (1<<5) - 1; 01806 op1 <<= 16; 01807 Value |= op1; 01808 // op2: RB 01809 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01810 op2 &= (1<<5) - 1; 01811 op2 <<= 11; 01812 Value |= op2; 01813 break; 01814 } 01815 case PPC::MULLD: { 01816 DEBUG(std::cerr << "Emitting MULLD\n"); 01817 Value = 2080375250U; 01818 01819 // op0: RT 01820 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01821 op0 &= (1<<5) - 1; 01822 op0 <<= 21; 01823 Value |= op0; 01824 // op1: RA 01825 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01826 op1 &= (1<<5) - 1; 01827 op1 <<= 16; 01828 Value |= op1; 01829 // op2: RB 01830 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01831 op2 &= (1<<5) - 1; 01832 op2 <<= 11; 01833 Value |= op2; 01834 break; 01835 } 01836 case PPC::MULLI: { 01837 DEBUG(std::cerr << "Emitting MULLI\n"); 01838 Value = 469762048U; 01839 01840 // op0: A 01841 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01842 op0 &= (1<<5) - 1; 01843 op0 <<= 21; 01844 Value |= op0; 01845 // op1: B 01846 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01847 op1 &= (1<<5) - 1; 01848 op1 <<= 16; 01849 Value |= op1; 01850 // op2: C 01851 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01852 op2 &= (1<<16) - 1; 01853 Value |= op2; 01854 break; 01855 } 01856 case PPC::MULLW: { 01857 DEBUG(std::cerr << "Emitting MULLW\n"); 01858 Value = 2080375254U; 01859 01860 // op0: RT 01861 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01862 op0 &= (1<<5) - 1; 01863 op0 <<= 21; 01864 Value |= op0; 01865 // op1: RA 01866 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01867 op1 &= (1<<5) - 1; 01868 op1 <<= 16; 01869 Value |= op1; 01870 // op2: RB 01871 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01872 op2 &= (1<<5) - 1; 01873 op2 <<= 11; 01874 Value |= op2; 01875 break; 01876 } 01877 case PPC::MovePCtoLR: { 01878 DEBUG(std::cerr << "Emitting MovePCtoLR\n"); 01879 Value = 0U; 01880 01881 break; 01882 } 01883 case PPC::NAND: { 01884 DEBUG(std::cerr << "Emitting NAND\n"); 01885 Value = 2080375736U; 01886 01887 // op0: A 01888 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01889 op0 &= (1<<5) - 1; 01890 op0 <<= 16; 01891 Value |= op0; 01892 // op1: RST 01893 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01894 op1 &= (1<<5) - 1; 01895 op1 <<= 21; 01896 Value |= op1; 01897 // op2: B 01898 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01899 op2 &= (1<<5) - 1; 01900 op2 <<= 11; 01901 Value |= op2; 01902 break; 01903 } 01904 case PPC::NEG: { 01905 DEBUG(std::cerr << "Emitting NEG\n"); 01906 Value = 2080374992U; 01907 01908 // op0: RT 01909 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01910 op0 &= (1<<5) - 1; 01911 op0 <<= 21; 01912 Value |= op0; 01913 // op1: RA 01914 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01915 op1 &= (1<<5) - 1; 01916 op1 <<= 16; 01917 Value |= op1; 01918 break; 01919 } 01920 case PPC::NOP: { 01921 DEBUG(std::cerr << "Emitting NOP\n"); 01922 Value = 1610612736U; 01923 01924 break; 01925 } 01926 case PPC::NOR: { 01927 DEBUG(std::cerr << "Emitting NOR\n"); 01928 Value = 2080375032U; 01929 01930 // op0: A 01931 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01932 op0 &= (1<<5) - 1; 01933 op0 <<= 16; 01934 Value |= op0; 01935 // op1: RST 01936 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01937 op1 &= (1<<5) - 1; 01938 op1 <<= 21; 01939 Value |= op1; 01940 // op2: B 01941 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01942 op2 &= (1<<5) - 1; 01943 op2 <<= 11; 01944 Value |= op2; 01945 break; 01946 } 01947 case PPC::OR: { 01948 DEBUG(std::cerr << "Emitting OR\n"); 01949 Value = 2080375672U; 01950 01951 // op0: A 01952 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01953 op0 &= (1<<5) - 1; 01954 op0 <<= 16; 01955 Value |= op0; 01956 // op1: RST 01957 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01958 op1 &= (1<<5) - 1; 01959 op1 <<= 21; 01960 Value |= op1; 01961 // op2: B 01962 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01963 op2 &= (1<<5) - 1; 01964 op2 <<= 11; 01965 Value |= op2; 01966 break; 01967 } 01968 case PPC::ORC: { 01969 DEBUG(std::cerr << "Emitting ORC\n"); 01970 Value = 2080375608U; 01971 01972 // op0: A 01973 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01974 op0 &= (1<<5) - 1; 01975 op0 <<= 16; 01976 Value |= op0; 01977 // op1: RST 01978 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01979 op1 &= (1<<5) - 1; 01980 op1 <<= 21; 01981 Value |= op1; 01982 // op2: B 01983 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01984 op2 &= (1<<5) - 1; 01985 op2 <<= 11; 01986 Value |= op2; 01987 break; 01988 } 01989 case PPC::ORI: { 01990 DEBUG(std::cerr << "Emitting ORI\n"); 01991 Value = 1610612736U; 01992 01993 // op0: B 01994 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01995 op0 &= (1<<5) - 1; 01996 op0 <<= 16; 01997 Value |= op0; 01998 // op1: A 01999 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02000 op1 &= (1<<5) - 1; 02001 op1 <<= 21; 02002 Value |= op1; 02003 // op2: C 02004 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02005 op2 &= (1<<16) - 1; 02006 Value |= op2; 02007 break; 02008 } 02009 case PPC::ORIS: { 02010 DEBUG(std::cerr << "Emitting ORIS\n"); 02011 Value = 1677721600U; 02012 02013 // op0: B 02014 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02015 op0 &= (1<<5) - 1; 02016 op0 <<= 16; 02017 Value |= op0; 02018 // op1: A 02019 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02020 op1 &= (1<<5) - 1; 02021 op1 <<= 21; 02022 Value |= op1; 02023 // op2: C 02024 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02025 op2 &= (1<<16) - 1; 02026 Value |= op2; 02027 break; 02028 } 02029 case PPC::ORo: { 02030 DEBUG(std::cerr << "Emitting ORo\n"); 02031 Value = 2080375673U; 02032 02033 // op0: A 02034 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02035 op0 &= (1<<5) - 1; 02036 op0 <<= 16; 02037 Value |= op0; 02038 // op1: RST 02039 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02040 op1 &= (1<<5) - 1; 02041 op1 <<= 21; 02042 Value |= op1; 02043 // op2: B 02044 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02045 op2 &= (1<<5) - 1; 02046 op2 <<= 11; 02047 Value |= op2; 02048 break; 02049 } 02050 case PPC::PHI: { 02051 DEBUG(std::cerr << "Emitting PHI\n"); 02052 Value = 0U; 02053 02054 break; 02055 } 02056 case PPC::RLDICL: { 02057 DEBUG(std::cerr << "Emitting RLDICL\n"); 02058 Value = 2013265920U; 02059 02060 // op0: RS 02061 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02062 op0 &= (1<<5) - 1; 02063 op0 <<= 21; 02064 Value |= op0; 02065 // op1: RA 02066 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02067 op1 &= (1<<5) - 1; 02068 op1 <<= 16; 02069 Value |= op1; 02070 // op2: SH 02071 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02072 // op3: MBE 02073 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 02074 op3 &= (1<<6) - 1; 02075 op3 <<= 5; 02076 Value |= op3; 02077 Value |= getValueBit(op2, 0) << 30; 02078 Value |= getValueBit(op2, 5) << 20; 02079 Value |= getValueBit(op2, 4) << 19; 02080 Value |= getValueBit(op2, 3) << 18; 02081 Value |= getValueBit(op2, 2) << 17; 02082 Value |= getValueBit(op2, 1) << 16; 02083 break; 02084 } 02085 case PPC::RLDICR: { 02086 DEBUG(std::cerr << "Emitting RLDICR\n"); 02087 Value = 2013265924U; 02088 02089 // op0: RS 02090 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02091 op0 &= (1<<5) - 1; 02092 op0 <<= 21; 02093 Value |= op0; 02094 // op1: RA 02095 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02096 op1 &= (1<<5) - 1; 02097 op1 <<= 16; 02098 Value |= op1; 02099 // op2: SH 02100 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02101 // op3: MBE 02102 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 02103 op3 &= (1<<6) - 1; 02104 op3 <<= 5; 02105 Value |= op3; 02106 Value |= getValueBit(op2, 0) << 30; 02107 Value |= getValueBit(op2, 5) << 20; 02108 Value |= getValueBit(op2, 4) << 19; 02109 Value |= getValueBit(op2, 3) << 18; 02110 Value |= getValueBit(op2, 2) << 17; 02111 Value |= getValueBit(op2, 1) << 16; 02112 break; 02113 } 02114 case PPC::RLWIMI: { 02115 DEBUG(std::cerr << "Emitting RLWIMI\n"); 02116 Value = 1342177280U; 02117 02118 // op0: RA 02119 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02120 op0 &= (1<<5) - 1; 02121 op0 <<= 16; 02122 Value |= op0; 02123 // op1: RS 02124 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02125 op1 &= (1<<5) - 1; 02126 op1 <<= 21; 02127 Value |= op1; 02128 // op2: RB 02129 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02130 op2 &= (1<<5) - 1; 02131 op2 <<= 11; 02132 Value |= op2; 02133 // op3: MB 02134 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 02135 op3 &= (1<<5) - 1; 02136 op3 <<= 6; 02137 Value |= op3; 02138 // op4: ME 02139 int64_t op4 = getMachineOpValue(MI, MI.getOperand(4)); 02140 op4 &= (1<<5) - 1; 02141 op4 <<= 1; 02142 Value |= op4; 02143 break; 02144 } 02145 case PPC::RLWINM: { 02146 DEBUG(std::cerr << "Emitting RLWINM\n"); 02147 Value = 1409286144U; 02148 02149 // op0: RA 02150 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02151 op0 &= (1<<5) - 1; 02152 op0 <<= 16; 02153 Value |= op0; 02154 // op1: RS 02155 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02156 op1 &= (1<<5) - 1; 02157 op1 <<= 21; 02158 Value |= op1; 02159 // op2: RB 02160 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02161 op2 &= (1<<5) - 1; 02162 op2 <<= 11; 02163 Value |= op2; 02164 // op3: MB 02165 int64_t op3 = getMachineOpValue(MI, MI.getOperand(3)); 02166 op3 &= (1<<5) - 1; 02167 op3 <<= 6; 02168 Value |= op3; 02169 // op4: ME 02170 int64_t op4 = getMachineOpValue(MI, MI.getOperand(4)); 02171 op4 &= (1<<5) - 1; 02172 op4 <<= 1; 02173 Value |= op4; 02174 break; 02175 } 02176 case PPC::SLD: { 02177 DEBUG(std::cerr << "Emitting SLD\n"); 02178 Value = 2080374838U; 02179 02180 // op0: A 02181 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02182 op0 &= (1<<5) - 1; 02183 op0 <<= 16; 02184 Value |= op0; 02185 // op1: RST 02186 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02187 op1 &= (1<<5) - 1; 02188 op1 <<= 21; 02189 Value |= op1; 02190 // op2: B 02191 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02192 op2 &= (1<<5) - 1; 02193 op2 <<= 11; 02194 Value |= op2; 02195 break; 02196 } 02197 case PPC::SLW: { 02198 DEBUG(std::cerr << "Emitting SLW\n"); 02199 Value = 2080374832U; 02200 02201 // op0: A 02202 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02203 op0 &= (1<<5) - 1; 02204 op0 <<= 16; 02205 Value |= op0; 02206 // op1: RST 02207 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02208 op1 &= (1<<5) - 1; 02209 op1 <<= 21; 02210 Value |= op1; 02211 // op2: B 02212 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02213 op2 &= (1<<5) - 1; 02214 op2 <<= 11; 02215 Value |= op2; 02216 break; 02217 } 02218 case PPC::SRAD: { 02219 DEBUG(std::cerr << "Emitting SRAD\n"); 02220 Value = 2080376372U; 02221 02222 // op0: A 02223 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02224 op0 &= (1<<5) - 1; 02225 op0 <<= 16; 02226 Value |= op0; 02227 // op1: RST 02228 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02229 op1 &= (1<<5) - 1; 02230 op1 <<= 21; 02231 Value |= op1; 02232 // op2: B 02233 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02234 op2 &= (1<<5) - 1; 02235 op2 <<= 11; 02236 Value |= op2; 02237 break; 02238 } 02239 case PPC::SRADI: { 02240 DEBUG(std::cerr << "Emitting SRADI\n"); 02241 Value = 2080376436U; 02242 02243 // op0: RS 02244 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02245 op0 &= (1<<5) - 1; 02246 op0 <<= 21; 02247 Value |= op0; 02248 // op1: A 02249 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02250 op1 &= (1<<5) - 1; 02251 op1 <<= 16; 02252 Value |= op1; 02253 // op2: SH 02254 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02255 Value |= getValueBit(op2, 0) << 30; 02256 Value |= getValueBit(op2, 5) << 20; 02257 Value |= getValueBit(op2, 4) << 19; 02258 Value |= getValueBit(op2, 3) << 18; 02259 Value |= getValueBit(op2, 2) << 17; 02260 Value |= getValueBit(op2, 1) << 16; 02261 break; 02262 } 02263 case PPC::SRAW: { 02264 DEBUG(std::cerr << "Emitting SRAW\n"); 02265 Value = 2080376368U; 02266 02267 // op0: A 02268 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02269 op0 &= (1<<5) - 1; 02270 op0 <<= 16; 02271 Value |= op0; 02272 // op1: RST 02273 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02274 op1 &= (1<<5) - 1; 02275 op1 <<= 21; 02276 Value |= op1; 02277 // op2: B 02278 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02279 op2 &= (1<<5) - 1; 02280 op2 <<= 11; 02281 Value |= op2; 02282 break; 02283 } 02284 case PPC::SRAWI: { 02285 DEBUG(std::cerr << "Emitting SRAWI\n"); 02286 Value = 2080376432U; 02287 02288 // op0: A 02289 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02290 op0 &= (1<<5) - 1; 02291 op0 <<= 16; 02292 Value |= op0; 02293 // op1: RST 02294 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02295 op1 &= (1<<5) - 1; 02296 op1 <<= 21; 02297 Value |= op1; 02298 // op2: B 02299 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02300 op2 &= (1<<5) - 1; 02301 op2 <<= 11; 02302 Value |= op2; 02303 break; 02304 } 02305 case PPC::SRD: { 02306 DEBUG(std::cerr << "Emitting SRD\n"); 02307 Value = 2080375862U; 02308 02309 // op0: A 02310 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02311 op0 &= (1<<5) - 1; 02312 op0 <<= 16; 02313 Value |= op0; 02314 // op1: RST 02315 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02316 op1 &= (1<<5) - 1; 02317 op1 <<= 21; 02318 Value |= op1; 02319 // op2: B 02320 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02321 op2 &= (1<<5) - 1; 02322 op2 <<= 11; 02323 Value |= op2; 02324 break; 02325 } 02326 case PPC::SRW: { 02327 DEBUG(std::cerr << "Emitting SRW\n"); 02328 Value = 2080375856U; 02329 02330 // op0: A 02331 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02332 op0 &= (1<<5) - 1; 02333 op0 <<= 16; 02334 Value |= op0; 02335 // op1: RST 02336 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02337 op1 &= (1<<5) - 1; 02338 op1 <<= 21; 02339 Value |= op1; 02340 // op2: B 02341 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02342 op2 &= (1<<5) - 1; 02343 op2 <<= 11; 02344 Value |= op2; 02345 break; 02346 } 02347 case PPC::STB: { 02348 DEBUG(std::cerr << "Emitting STB\n"); 02349 Value = 2550136832U; 02350 02351 // op0: A 02352 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02353 op0 &= (1<<5) - 1; 02354 op0 <<= 21; 02355 Value |= op0; 02356 // op1: C 02357 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02358 op1 &= (1<<16) - 1; 02359 Value |= op1; 02360 // op2: B 02361 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02362 op2 &= (1<<5) - 1; 02363 op2 <<= 16; 02364 Value |= op2; 02365 break; 02366 } 02367 case PPC::STBX: { 02368 DEBUG(std::cerr << "Emitting STBX\n"); 02369 Value = 2080375214U; 02370 02371 // op0: RST 02372 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02373 op0 &= (1<<5) - 1; 02374 op0 <<= 21; 02375 Value |= op0; 02376 // op1: A 02377 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02378 op1 &= (1<<5) - 1; 02379 op1 <<= 16; 02380 Value |= op1; 02381 // op2: B 02382 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02383 op2 &= (1<<5) - 1; 02384 op2 <<= 11; 02385 Value |= op2; 02386 break; 02387 } 02388 case PPC::STD: { 02389 DEBUG(std::cerr << "Emitting STD\n"); 02390 Value = 4160749568U; 02391 02392 // op0: RST 02393 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02394 op0 &= (1<<5) - 1; 02395 op0 <<= 21; 02396 Value |= op0; 02397 // op1: DS 02398 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02399 op1 &= (1<<14) - 1; 02400 op1 <<= 2; 02401 Value |= op1; 02402 // op2: RA 02403 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02404 op2 &= (1<<5) - 1; 02405 op2 <<= 16; 02406 Value |= op2; 02407 break; 02408 } 02409 case PPC::STDU: { 02410 DEBUG(std::cerr << "Emitting STDU\n"); 02411 Value = 4160749569U; 02412 02413 // op0: RST 02414 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02415 op0 &= (1<<5) - 1; 02416 op0 <<= 21; 02417 Value |= op0; 02418 // op1: DS 02419 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02420 op1 &= (1<<14) - 1; 02421 op1 <<= 2; 02422 Value |= op1; 02423 // op2: RA 02424 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02425 op2 &= (1<<5) - 1; 02426 op2 <<= 16; 02427 Value |= op2; 02428 break; 02429 } 02430 case PPC::STDUX: { 02431 DEBUG(std::cerr << "Emitting STDUX\n"); 02432 Value = 2080375146U; 02433 02434 // op0: RST 02435 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02436 op0 &= (1<<5) - 1; 02437 op0 <<= 21; 02438 Value |= op0; 02439 // op1: A 02440 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02441 op1 &= (1<<5) - 1; 02442 op1 <<= 16; 02443 Value |= op1; 02444 // op2: B 02445 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02446 op2 &= (1<<5) - 1; 02447 op2 <<= 11; 02448 Value |= op2; 02449 break; 02450 } 02451 case PPC::STDX: { 02452 DEBUG(std::cerr << "Emitting STDX\n"); 02453 Value = 2080375082U; 02454 02455 // op0: RST 02456 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02457 op0 &= (1<<5) - 1; 02458 op0 <<= 21; 02459 Value |= op0; 02460 // op1: A 02461 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02462 op1 &= (1<<5) - 1; 02463 op1 <<= 16; 02464 Value |= op1; 02465 // op2: B 02466 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02467 op2 &= (1<<5) - 1; 02468 op2 <<= 11; 02469 Value |= op2; 02470 break; 02471 } 02472 case PPC::STFD: { 02473 DEBUG(std::cerr << "Emitting STFD\n"); 02474 Value = 3623878656U; 02475 02476 // op0: A 02477 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02478 op0 &= (1<<5) - 1; 02479 op0 <<= 21; 02480 Value |= op0; 02481 // op1: C 02482 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02483 op1 &= (1<<16) - 1; 02484 Value |= op1; 02485 // op2: B 02486 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02487 op2 &= (1<<5) - 1; 02488 op2 <<= 16; 02489 Value |= op2; 02490 break; 02491 } 02492 case PPC::STFDX: { 02493 DEBUG(std::cerr << "Emitting STFDX\n"); 02494 Value = 2080376238U; 02495 02496 // op0: RST 02497 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02498 op0 &= (1<<5) - 1; 02499 op0 <<= 21; 02500 Value |= op0; 02501 // op1: A 02502 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02503 op1 &= (1<<5) - 1; 02504 op1 <<= 16; 02505 Value |= op1; 02506 // op2: B 02507 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02508 op2 &= (1<<5) - 1; 02509 op2 <<= 11; 02510 Value |= op2; 02511 break; 02512 } 02513 case PPC::STFS: { 02514 DEBUG(std::cerr << "Emitting STFS\n"); 02515 Value = 3489660928U; 02516 02517 // op0: A 02518 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02519 op0 &= (1<<5) - 1; 02520 op0 <<= 21; 02521 Value |= op0; 02522 // op1: C 02523 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02524 op1 &= (1<<16) - 1; 02525 Value |= op1; 02526 // op2: B 02527 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02528 op2 &= (1<<5) - 1; 02529 op2 <<= 16; 02530 Value |= op2; 02531 break; 02532 } 02533 case PPC::STFSX: { 02534 DEBUG(std::cerr << "Emitting STFSX\n"); 02535 Value = 2080376110U; 02536 02537 // op0: RST 02538 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02539 op0 &= (1<<5) - 1; 02540 op0 <<= 21; 02541 Value |= op0; 02542 // op1: A 02543 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02544 op1 &= (1<<5) - 1; 02545 op1 <<= 16; 02546 Value |= op1; 02547 // op2: B 02548 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02549 op2 &= (1<<5) - 1; 02550 op2 <<= 11; 02551 Value |= op2; 02552 break; 02553 } 02554 case PPC::STH: { 02555 DEBUG(std::cerr << "Emitting STH\n"); 02556 Value = 2952790016U; 02557 02558 // op0: A 02559 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02560 op0 &= (1<<5) - 1; 02561 op0 <<= 21; 02562 Value |= op0; 02563 // op1: C 02564 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02565 op1 &= (1<<16) - 1; 02566 Value |= op1; 02567 // op2: B 02568 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02569 op2 &= (1<<5) - 1; 02570 op2 <<= 16; 02571 Value |= op2; 02572 break; 02573 } 02574 case PPC::STHX: { 02575 DEBUG(std::cerr << "Emitting STHX\n"); 02576 Value = 2080375598U; 02577 02578 // op0: RST 02579 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02580 op0 &= (1<<5) - 1; 02581 op0 <<= 21; 02582 Value |= op0; 02583 // op1: A 02584 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02585 op1 &= (1<<5) - 1; 02586 op1 <<= 16; 02587 Value |= op1; 02588 // op2: B 02589 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02590 op2 &= (1<<5) - 1; 02591 op2 <<= 11; 02592 Value |= op2; 02593 break; 02594 } 02595 case PPC::STMW: { 02596 DEBUG(std::cerr << "Emitting STMW\n"); 02597 Value = 3154116608U; 02598 02599 // op0: A 02600 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02601 op0 &= (1<<5) - 1; 02602 op0 <<= 21; 02603 Value |= op0; 02604 // op1: C 02605 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02606 op1 &= (1<<16) - 1; 02607 Value |= op1; 02608 // op2: B 02609 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02610 op2 &= (1<<5) - 1; 02611 op2 <<= 16; 02612 Value |= op2; 02613 break; 02614 } 02615 case PPC::STW: { 02616 DEBUG(std::cerr << "Emitting STW\n"); 02617 Value = 2415919104U; 02618 02619 // op0: A 02620 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02621 op0 &= (1<<5) - 1; 02622 op0 <<= 21; 02623 Value |= op0; 02624 // op1: C 02625 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02626 op1 &= (1<<16) - 1; 02627 Value |= op1; 02628 // op2: B 02629 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02630 op2 &= (1<<5) - 1; 02631 op2 <<= 16; 02632 Value |= op2; 02633 break; 02634 } 02635 case PPC::STWU: { 02636 DEBUG(std::cerr << "Emitting STWU\n"); 02637 Value = 2483027968U; 02638 02639 // op0: A 02640 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02641 op0 &= (1<<5) - 1; 02642 op0 <<= 21; 02643 Value |= op0; 02644 // op1: C 02645 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02646 op1 &= (1<<16) - 1; 02647 Value |= op1; 02648 // op2: B 02649 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02650 op2 &= (1<<5) - 1; 02651 op2 <<= 16; 02652 Value |= op2; 02653 break; 02654 } 02655 case PPC::STWUX: { 02656 DEBUG(std::cerr << "Emitting STWUX\n"); 02657 Value = 2080375150U; 02658 02659 // op0: RST 02660 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02661 op0 &= (1<<5) - 1; 02662 op0 <<= 21; 02663 Value |= op0; 02664 // op1: A 02665 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02666 op1 &= (1<<5) - 1; 02667 op1 <<= 16; 02668 Value |= op1; 02669 // op2: B 02670 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02671 op2 &= (1<<5) - 1; 02672 op2 <<= 11; 02673 Value |= op2; 02674 break; 02675 } 02676 case PPC::STWX: { 02677 DEBUG(std::cerr << "Emitting STWX\n"); 02678 Value = 2080375086U; 02679 02680 // op0: RST 02681 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02682 op0 &= (1<<5) - 1; 02683 op0 <<= 21; 02684 Value |= op0; 02685 // op1: A 02686 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02687 op1 &= (1<<5) - 1; 02688 op1 <<= 16; 02689 Value |= op1; 02690 // op2: B 02691 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02692 op2 &= (1<<5) - 1; 02693 op2 <<= 11; 02694 Value |= op2; 02695 break; 02696 } 02697 case PPC::SUB: { 02698 DEBUG(std::cerr << "Emitting SUB\n"); 02699 Value = 2080374864U; 02700 02701 // op0: RT 02702 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02703 op0 &= (1<<5) - 1; 02704 op0 <<= 21; 02705 Value |= op0; 02706 // op1: RA 02707 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02708 op1 &= (1<<5) - 1; 02709 op1 <<= 11; 02710 Value |= op1; 02711 // op2: RB 02712 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02713 op2 &= (1<<5) - 1; 02714 op2 <<= 16; 02715 Value |= op2; 02716 break; 02717 } 02718 case PPC::SUBC: { 02719 DEBUG(std::cerr << "Emitting SUBC\n"); 02720 Value = 2080374800U; 02721 02722 // op0: RT 02723 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02724 op0 &= (1<<5) - 1; 02725 op0 <<= 21; 02726 Value |= op0; 02727 // op1: RA 02728 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02729 op1 &= (1<<5) - 1; 02730 op1 <<= 11; 02731 Value |= op1; 02732 // op2: RB 02733 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02734 op2 &= (1<<5) - 1; 02735 op2 <<= 16; 02736 Value |= op2; 02737 break; 02738 } 02739 case PPC::SUBF: { 02740 DEBUG(std::cerr << "Emitting SUBF\n"); 02741 Value = 2080374864U; 02742 02743 // op0: RT 02744 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02745 op0 &= (1<<5) - 1; 02746 op0 <<= 21; 02747 Value |= op0; 02748 // op1: RA 02749 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02750 op1 &= (1<<5) - 1; 02751 op1 <<= 16; 02752 Value |= op1; 02753 // op2: RB 02754 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02755 op2 &= (1<<5) - 1; 02756 op2 <<= 11; 02757 Value |= op2; 02758 break; 02759 } 02760 case PPC::SUBFC: { 02761 DEBUG(std::cerr << "Emitting SUBFC\n"); 02762 Value = 2080374800U; 02763 02764 // op0: RT 02765 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02766 op0 &= (1<<5) - 1; 02767 op0 <<= 21; 02768 Value |= op0; 02769 // op1: RA 02770 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02771 op1 &= (1<<5) - 1; 02772 op1 <<= 16; 02773 Value |= op1; 02774 // op2: RB 02775 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02776 op2 &= (1<<5) - 1; 02777 op2 <<= 11; 02778 Value |= op2; 02779 break; 02780 } 02781 case PPC::SUBFE: { 02782 DEBUG(std::cerr << "Emitting SUBFE\n"); 02783 Value = 2080375056U; 02784 02785 // op0: RT 02786 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02787 op0 &= (1<<5) - 1; 02788 op0 <<= 21; 02789 Value |= op0; 02790 // op1: RA 02791 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02792 op1 &= (1<<5) - 1; 02793 op1 <<= 16; 02794 Value |= op1; 02795 // op2: RB 02796 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02797 op2 &= (1<<5) - 1; 02798 op2 <<= 11; 02799 Value |= op2; 02800 break; 02801 } 02802 case PPC::SUBFIC: { 02803 DEBUG(std::cerr << "Emitting SUBFIC\n"); 02804 Value = 536870912U; 02805 02806 // op0: A 02807 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02808 op0 &= (1<<5) - 1; 02809 op0 <<= 21; 02810 Value |= op0; 02811 // op1: B 02812 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02813 op1 &= (1<<5) - 1; 02814 op1 <<= 16; 02815 Value |= op1; 02816 // op2: C 02817 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02818 op2 &= (1<<16) - 1; 02819 Value |= op2; 02820 break; 02821 } 02822 case PPC::SUBFZE: { 02823 DEBUG(std::cerr << "Emitting SUBFZE\n"); 02824 Value = 2080375184U; 02825 02826 // op0: RT 02827 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02828 op0 &= (1<<5) - 1; 02829 op0 <<= 21; 02830 Value |= op0; 02831 // op1: RA 02832 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02833 op1 &= (1<<5) - 1; 02834 op1 <<= 16; 02835 Value |= op1; 02836 break; 02837 } 02838 case PPC::XOR: { 02839 DEBUG(std::cerr << "Emitting XOR\n"); 02840 Value = 2080375416U; 02841 02842 // op0: A 02843 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02844 op0 &= (1<<5) - 1; 02845 op0 <<= 16; 02846 Value |= op0; 02847 // op1: RST 02848 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02849 op1 &= (1<<5) - 1; 02850 op1 <<= 21; 02851 Value |= op1; 02852 // op2: B 02853 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02854 op2 &= (1<<5) - 1; 02855 op2 <<= 11; 02856 Value |= op2; 02857 break; 02858 } 02859 case PPC::XORI: { 02860 DEBUG(std::cerr << "Emitting XORI\n"); 02861 Value = 1744830464U; 02862 02863 // op0: B 02864 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02865 op0 &= (1<<5) - 1; 02866 op0 <<= 16; 02867 Value |= op0; 02868 // op1: A 02869 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02870 op1 &= (1<<5) - 1; 02871 op1 <<= 21; 02872 Value |= op1; 02873 // op2: C 02874 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02875 op2 &= (1<<16) - 1; 02876 Value |= op2; 02877 break; 02878 } 02879 case PPC::XORIS: { 02880 DEBUG(std::cerr << "Emitting XORIS\n"); 02881 Value = 1811939328U; 02882 02883 // op0: B 02884 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02885 op0 &= (1<<5) - 1; 02886 op0 <<= 16; 02887 Value |= op0; 02888 // op1: A 02889 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02890 op1 &= (1<<5) - 1; 02891 op1 <<= 21; 02892 Value |= op1; 02893 // op2: C 02894 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02895 op2 &= (1<<16) - 1; 02896 Value |= op2; 02897 break; 02898 } 02899 default: 02900 std::cerr << "Not supported instr: " << MI << "\n"; 02901 abort(); 02902 } 02903 return Value; 02904 } 02905 02906 } // End llvm namespace