LLVM API Documentation

Main Page | Namespace List | Class Hierarchy | Alphabetical List | Class List | Directories | File List | Namespace Members | Class Members | File Members | Related Pages

SparcV9RegClassInfo.h

Go to the documentation of this file.
00001 //===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 -*- C++ -*-=//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the register classes used by the SparcV9 target. It
00011 // implicitly defines (using enums) the "class register numbers" used in
00012 // the SparcV9 target, which are converted using a formula in the SparcV9RegInfo
00013 // class to "unified register numbers".
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #ifndef SPARCV9REGCLASSINFO_H
00018 #define SPARCV9REGCLASSINFO_H
00019 
00020 #include "SparcV9RegInfo.h"
00021 
00022 namespace llvm {
00023 
00024 //-----------------------------------------------------------------------------
00025 // Integer Register Class
00026 //-----------------------------------------------------------------------------
00027 
00028 struct SparcV9IntRegClass : public TargetRegClassInfo {
00029   SparcV9IntRegClass(unsigned ID) 
00030     : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {  }
00031 
00032   void colorIGNode(IGNode *Node,
00033                    const std::vector<bool> &IsColorUsedArr) const;
00034 
00035   inline bool isRegVolatile(int Reg) const {
00036     return (Reg < (int)StartOfNonVolatileRegs); 
00037   }
00038 
00039   inline bool modifiedByCall(int Reg) const {
00040     return Reg==(int)ModifiedByCall;
00041   }
00042 
00043   enum {   // colors possible for a LR (in preferred order)
00044      // --- following colors are volatile across function calls
00045      // %g0 can't be used for coloring - always 0
00046      o0, o1, o2, o3, o4, o5, o7,  // %o0-%o5, 
00047 
00048      // %o6 is sp, 
00049      // all %0's can get modified by a call
00050 
00051      // --- following colors are NON-volatile across function calls
00052      l0, l1, l2, l3, l4, l5, l6, l7,    //  %l0-%l7
00053      i0, i1, i2, i3, i4, i5,         // %i0-%i5: i's need not be preserved 
00054       
00055      // %i6 is the fp - so not allocated
00056      // %i7 is the ret address by convention - can be used for others
00057 
00058      // max # of colors reg coloring  can allocate (NumOfAvailRegs)
00059 
00060      // --- following colors are not available for allocation within this phase
00061      // --- but can appear for pre-colored ranges 
00062 
00063      i6, i7, g0,  g1, g2, g3, g4, g5, g6, g7, o6,
00064 
00065      NumOfAllRegs,  // Must be first AFTER registers...
00066      
00067      //*** NOTE: If we decide to use some %g regs, they are volatile
00068      // (see sparc64ABI)
00069      // Move the %g regs from the end of the enumeration to just above the
00070      // enumeration of %o0 (change StartOfAllRegs below)
00071      // change isRegVloatile method below
00072      // Also change IntRegNames above.
00073 
00074      // max # of colors reg coloring  can allocate
00075      NumOfAvailRegs = i6,
00076 
00077      StartOfNonVolatileRegs = l0,
00078      StartOfAllRegs = o0,
00079      
00080      ModifiedByCall = o7,
00081   };
00082 
00083   const char * const getRegName(unsigned reg) const;
00084 };
00085 
00086 
00087 //-----------------------------------------------------------------------------
00088 // Float Register Class
00089 //-----------------------------------------------------------------------------
00090 
00091 class SparcV9FloatRegClass : public TargetRegClassInfo {
00092   int findFloatColor(const LiveRange *LR, unsigned Start,
00093          unsigned End,
00094                      const std::vector<bool> &IsColorUsedArr) const;
00095 public:
00096   SparcV9FloatRegClass(unsigned ID) 
00097     : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
00098 
00099   // This method marks the registers used for a given register number.
00100   // This marks a single register for Float regs, but the R,R+1 pair
00101   // for double-precision registers.
00102   // 
00103   virtual void markColorsUsed(unsigned RegInClass,
00104                               int UserRegType,
00105                               int RegTypeWanted,
00106                               std::vector<bool> &IsColorUsedArr) const;
00107   
00108   // This method finds unused registers of the specified register type,
00109   // using the given "used" flag array IsColorUsedArr.  It checks a single
00110   // entry in the array directly for float regs, and checks the pair [R,R+1]
00111   // for double-precision registers
00112   // It returns -1 if no unused color is found.
00113   // 
00114   virtual int findUnusedColor(int RegTypeWanted,
00115                               const std::vector<bool> &IsColorUsedArr) const;
00116 
00117   void colorIGNode(IGNode *Node,
00118                    const std::vector<bool> &IsColorUsedArr) const;
00119 
00120   // according to  SparcV9 64 ABI, all %fp regs are volatile
00121   inline bool isRegVolatile(int Reg) const { return true; }
00122 
00123   enum {
00124     f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, 
00125     f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
00126     f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
00127     f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
00128     f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
00129     f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
00130     f60, f61, f62, f63,
00131 
00132     // there are 64 regs alltogether but only 32 regs can be allocated at
00133     // a time.
00134     //
00135     NumOfAvailRegs = 32,
00136     NumOfAllRegs = 64,
00137 
00138     StartOfNonVolatileRegs = f32,
00139     StartOfAllRegs = f0,
00140   };
00141 
00142   const char * const getRegName(unsigned reg) const;
00143 };
00144 
00145 
00146 //-----------------------------------------------------------------------------
00147 // Int CC Register Class
00148 // Only one integer cc register is available. However, this register is
00149 // referred to as %xcc or %icc when instructions like subcc are executed but 
00150 // referred to as %ccr (i.e., %xcc . %icc") when this register is moved
00151 // into an integer register using RD or WR instrcutions. So, three ids are
00152 // allocated for the three names.
00153 //-----------------------------------------------------------------------------
00154 
00155 struct SparcV9IntCCRegClass : public TargetRegClassInfo {
00156   SparcV9IntCCRegClass(unsigned ID) 
00157     : TargetRegClassInfo(ID, 1, 3) {  }
00158   
00159   void colorIGNode(IGNode *Node,
00160                    const std::vector<bool> &IsColorUsedArr) const;
00161 
00162   // according to the 64-bit SparcV9 ABI, all integer CC regs are
00163   // volatile.
00164   inline bool isRegVolatile(int Reg) const { return true; }
00165 
00166   enum {
00167     xcc, icc, ccr   // only one is available - see the note above
00168   };
00169 
00170   const char * const getRegName(unsigned reg) const;
00171 };
00172 
00173 
00174 //-----------------------------------------------------------------------------
00175 // Float CC Register Class
00176 // Only 4 Float CC registers are available for allocation.
00177 //-----------------------------------------------------------------------------
00178 
00179 struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
00180   SparcV9FloatCCRegClass(unsigned ID) 
00181     : TargetRegClassInfo(ID, 4, 4) {  }
00182 
00183   void colorIGNode(IGNode *Node,
00184                    const std::vector<bool> &IsColorUsedArr) const;
00185   
00186   // according to the 64-bit SparcV9 ABI, all floating-point CC regs are
00187   // volatile.
00188   inline bool isRegVolatile(int Reg) const { return true; }
00189 
00190   enum {
00191     fcc0, fcc1, fcc2, fcc3
00192   };
00193   
00194   const char * const getRegName(unsigned reg) const;
00195 };
00196 
00197 
00198 //-----------------------------------------------------------------------------
00199 // SparcV9 special register class.  These registers are not used for allocation
00200 // but are used as arguments of some instructions.
00201 //-----------------------------------------------------------------------------
00202 
00203 struct SparcV9SpecialRegClass : public TargetRegClassInfo {
00204   SparcV9SpecialRegClass(unsigned ID) 
00205     : TargetRegClassInfo(ID, 0, 1) {  }
00206 
00207   void colorIGNode(IGNode *Node,
00208                    const std::vector<bool> &IsColorUsedArr) const {
00209     assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
00210   }
00211   
00212   // all currently included special regs are volatile
00213   inline bool isRegVolatile(int Reg) const { return true; }
00214 
00215   enum {
00216     fsr                                 // floating point state register
00217   };
00218 
00219   const char * const getRegName(unsigned reg) const;
00220 };
00221 
00222 } // End llvm namespace
00223 
00224 #endif