LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Target Instruction Descriptors 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 static const unsigned EmptyImpUses[] = { 0 }; 00012 static const unsigned EmptyImpDefs[] = { 0 }; 00013 static const unsigned CALL32mImpDefs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, 0 }; 00014 static const unsigned CALL32rImpDefs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, 0 }; 00015 static const unsigned CALLpcrel32ImpDefs[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, 0 }; 00016 static const unsigned CBWImpUses[] = { X86::AL, 0 }; 00017 static const unsigned CBWImpDefs[] = { X86::AH, 0 }; 00018 static const unsigned CDQImpUses[] = { X86::EAX, 0 }; 00019 static const unsigned CDQImpDefs[] = { X86::EDX, 0 }; 00020 static const unsigned CWDImpUses[] = { X86::AX, 0 }; 00021 static const unsigned CWDImpDefs[] = { X86::DX, 0 }; 00022 static const unsigned DIV16mImpUses[] = { X86::AX, X86::DX, 0 }; 00023 static const unsigned DIV16mImpDefs[] = { X86::AX, X86::DX, 0 }; 00024 static const unsigned DIV16rImpUses[] = { X86::AX, X86::DX, 0 }; 00025 static const unsigned DIV16rImpDefs[] = { X86::AX, X86::DX, 0 }; 00026 static const unsigned DIV32mImpUses[] = { X86::EAX, X86::EDX, 0 }; 00027 static const unsigned DIV32mImpDefs[] = { X86::EAX, X86::EDX, 0 }; 00028 static const unsigned DIV32rImpUses[] = { X86::EAX, X86::EDX, 0 }; 00029 static const unsigned DIV32rImpDefs[] = { X86::EAX, X86::EDX, 0 }; 00030 static const unsigned DIV8mImpUses[] = { X86::AX, 0 }; 00031 static const unsigned DIV8mImpDefs[] = { X86::AX, 0 }; 00032 static const unsigned DIV8rImpUses[] = { X86::AX, 0 }; 00033 static const unsigned DIV8rImpDefs[] = { X86::AX, 0 }; 00034 static const unsigned FADDPrST0ImpUses[] = { X86::ST0, 0 }; 00035 static const unsigned FADDST0rImpUses[] = { X86::ST0, 0 }; 00036 static const unsigned FADDST0rImpDefs[] = { X86::ST0, 0 }; 00037 static const unsigned FADDrST0ImpUses[] = { X86::ST0, 0 }; 00038 static const unsigned FCMOVAImpUses[] = { X86::ST0, 0 }; 00039 static const unsigned FCMOVAImpDefs[] = { X86::ST0, 0 }; 00040 static const unsigned FCMOVAEImpUses[] = { X86::ST0, 0 }; 00041 static const unsigned FCMOVAEImpDefs[] = { X86::ST0, 0 }; 00042 static const unsigned FCMOVBImpUses[] = { X86::ST0, 0 }; 00043 static const unsigned FCMOVBImpDefs[] = { X86::ST0, 0 }; 00044 static const unsigned FCMOVBEImpUses[] = { X86::ST0, 0 }; 00045 static const unsigned FCMOVBEImpDefs[] = { X86::ST0, 0 }; 00046 static const unsigned FCMOVEImpUses[] = { X86::ST0, 0 }; 00047 static const unsigned FCMOVEImpDefs[] = { X86::ST0, 0 }; 00048 static const unsigned FCMOVNEImpUses[] = { X86::ST0, 0 }; 00049 static const unsigned FCMOVNEImpDefs[] = { X86::ST0, 0 }; 00050 static const unsigned FDIVPrST0ImpUses[] = { X86::ST0, 0 }; 00051 static const unsigned FDIVRPrST0ImpUses[] = { X86::ST0, 0 }; 00052 static const unsigned FDIVRST0rImpUses[] = { X86::ST0, 0 }; 00053 static const unsigned FDIVRST0rImpDefs[] = { X86::ST0, 0 }; 00054 static const unsigned FDIVRrST0ImpUses[] = { X86::ST0, 0 }; 00055 static const unsigned FDIVST0rImpUses[] = { X86::ST0, 0 }; 00056 static const unsigned FDIVST0rImpDefs[] = { X86::ST0, 0 }; 00057 static const unsigned FDIVrST0ImpUses[] = { X86::ST0, 0 }; 00058 static const unsigned FMULPrST0ImpUses[] = { X86::ST0, 0 }; 00059 static const unsigned FMULST0rImpUses[] = { X86::ST0, 0 }; 00060 static const unsigned FMULST0rImpDefs[] = { X86::ST0, 0 }; 00061 static const unsigned FMULrST0ImpUses[] = { X86::ST0, 0 }; 00062 static const unsigned FNSTSW8rImpDefs[] = { X86::AX, 0 }; 00063 static const unsigned FP_REG_KILLImpDefs[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 }; 00064 static const unsigned FSUBPrST0ImpUses[] = { X86::ST0, 0 }; 00065 static const unsigned FSUBRPrST0ImpUses[] = { X86::ST0, 0 }; 00066 static const unsigned FSUBRST0rImpUses[] = { X86::ST0, 0 }; 00067 static const unsigned FSUBRST0rImpDefs[] = { X86::ST0, 0 }; 00068 static const unsigned FSUBRrST0ImpUses[] = { X86::ST0, 0 }; 00069 static const unsigned FSUBST0rImpUses[] = { X86::ST0, 0 }; 00070 static const unsigned FSUBST0rImpDefs[] = { X86::ST0, 0 }; 00071 static const unsigned FSUBrST0ImpUses[] = { X86::ST0, 0 }; 00072 static const unsigned FUCOMIPrImpUses[] = { X86::ST0, 0 }; 00073 static const unsigned FUCOMIrImpUses[] = { X86::ST0, 0 }; 00074 static const unsigned FUCOMPPrImpUses[] = { X86::ST0, 0 }; 00075 static const unsigned FUCOMPrImpUses[] = { X86::ST0, 0 }; 00076 static const unsigned FUCOMrImpUses[] = { X86::ST0, 0 }; 00077 static const unsigned FpGETRESULTImpUses[] = { X86::ST0, 0 }; 00078 static const unsigned FpSETRESULTImpDefs[] = { X86::ST0, 0 }; 00079 static const unsigned IDIV16mImpUses[] = { X86::AX, X86::DX, 0 }; 00080 static const unsigned IDIV16mImpDefs[] = { X86::AX, X86::DX, 0 }; 00081 static const unsigned IDIV16rImpUses[] = { X86::AX, X86::DX, 0 }; 00082 static const unsigned IDIV16rImpDefs[] = { X86::AX, X86::DX, 0 }; 00083 static const unsigned IDIV32mImpUses[] = { X86::EAX, X86::EDX, 0 }; 00084 static const unsigned IDIV32mImpDefs[] = { X86::EAX, X86::EDX, 0 }; 00085 static const unsigned IDIV32rImpUses[] = { X86::EAX, X86::EDX, 0 }; 00086 static const unsigned IDIV32rImpDefs[] = { X86::EAX, X86::EDX, 0 }; 00087 static const unsigned IDIV8mImpUses[] = { X86::AX, 0 }; 00088 static const unsigned IDIV8mImpDefs[] = { X86::AX, 0 }; 00089 static const unsigned IDIV8rImpUses[] = { X86::AX, 0 }; 00090 static const unsigned IDIV8rImpDefs[] = { X86::AX, 0 }; 00091 static const unsigned IN16riImpDefs[] = { X86::AX, 0 }; 00092 static const unsigned IN16rrImpUses[] = { X86::DX, 0 }; 00093 static const unsigned IN16rrImpDefs[] = { X86::AX, 0 }; 00094 static const unsigned IN32riImpDefs[] = { X86::EAX, 0 }; 00095 static const unsigned IN32rrImpUses[] = { X86::DX, 0 }; 00096 static const unsigned IN32rrImpDefs[] = { X86::EAX, 0 }; 00097 static const unsigned IN8riImpDefs[] = { X86::AL, 0 }; 00098 static const unsigned IN8rrImpUses[] = { X86::DX, 0 }; 00099 static const unsigned IN8rrImpDefs[] = { X86::AL, 0 }; 00100 static const unsigned LAHFImpDefs[] = { X86::AH, 0 }; 00101 static const unsigned LEAVEImpUses[] = { X86::EBP, X86::ESP, 0 }; 00102 static const unsigned LEAVEImpDefs[] = { X86::EBP, X86::ESP, 0 }; 00103 static const unsigned MUL16mImpUses[] = { X86::AX, 0 }; 00104 static const unsigned MUL16mImpDefs[] = { X86::AX, X86::DX, 0 }; 00105 static const unsigned MUL16rImpUses[] = { X86::AX, 0 }; 00106 static const unsigned MUL16rImpDefs[] = { X86::AX, X86::DX, 0 }; 00107 static const unsigned MUL32mImpUses[] = { X86::EAX, 0 }; 00108 static const unsigned MUL32mImpDefs[] = { X86::EAX, X86::EDX, 0 }; 00109 static const unsigned MUL32rImpUses[] = { X86::EAX, 0 }; 00110 static const unsigned MUL32rImpDefs[] = { X86::EAX, X86::EDX, 0 }; 00111 static const unsigned MUL8mImpUses[] = { X86::AL, 0 }; 00112 static const unsigned MUL8mImpDefs[] = { X86::AX, 0 }; 00113 static const unsigned MUL8rImpUses[] = { X86::AL, 0 }; 00114 static const unsigned MUL8rImpDefs[] = { X86::AX, 0 }; 00115 static const unsigned OUT16irImpUses[] = { X86::AX, 0 }; 00116 static const unsigned OUT16rrImpUses[] = { X86::DX, X86::AX, 0 }; 00117 static const unsigned OUT32irImpUses[] = { X86::EAX, 0 }; 00118 static const unsigned OUT32rrImpUses[] = { X86::DX, X86::EAX, 0 }; 00119 static const unsigned OUT8irImpUses[] = { X86::AL, 0 }; 00120 static const unsigned OUT8rrImpUses[] = { X86::DX, X86::AL, 0 }; 00121 static const unsigned POP32rImpUses[] = { X86::ESP, 0 }; 00122 static const unsigned POP32rImpDefs[] = { X86::ESP, 0 }; 00123 static const unsigned REP_MOVSBImpUses[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00124 static const unsigned REP_MOVSBImpDefs[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00125 static const unsigned REP_MOVSDImpUses[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00126 static const unsigned REP_MOVSDImpDefs[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00127 static const unsigned REP_MOVSWImpUses[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00128 static const unsigned REP_MOVSWImpDefs[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; 00129 static const unsigned REP_STOSBImpUses[] = { X86::AL, X86::ECX, X86::EDI, 0 }; 00130 static const unsigned REP_STOSBImpDefs[] = { X86::ECX, X86::EDI, 0 }; 00131 static const unsigned REP_STOSDImpUses[] = { X86::EAX, X86::ECX, X86::EDI, 0 }; 00132 static const unsigned REP_STOSDImpDefs[] = { X86::ECX, X86::EDI, 0 }; 00133 static const unsigned REP_STOSWImpUses[] = { X86::AX, X86::ECX, X86::EDI, 0 }; 00134 static const unsigned REP_STOSWImpDefs[] = { X86::ECX, X86::EDI, 0 }; 00135 static const unsigned SAHFImpUses[] = { X86::AH, 0 }; 00136 static const unsigned SAR16mCLImpUses[] = { X86::CL, 0 }; 00137 static const unsigned SAR16rCLImpUses[] = { X86::CL, 0 }; 00138 static const unsigned SAR32mCLImpUses[] = { X86::CL, 0 }; 00139 static const unsigned SAR32rCLImpUses[] = { X86::CL, 0 }; 00140 static const unsigned SAR8mCLImpUses[] = { X86::CL, 0 }; 00141 static const unsigned SAR8rCLImpUses[] = { X86::CL, 0 }; 00142 static const unsigned SHL16mCLImpUses[] = { X86::CL, 0 }; 00143 static const unsigned SHL16rCLImpUses[] = { X86::CL, 0 }; 00144 static const unsigned SHL32mCLImpUses[] = { X86::CL, 0 }; 00145 static const unsigned SHL32rCLImpUses[] = { X86::CL, 0 }; 00146 static const unsigned SHL8mCLImpUses[] = { X86::CL, 0 }; 00147 static const unsigned SHL8rCLImpUses[] = { X86::CL, 0 }; 00148 static const unsigned SHLD32mrCLImpUses[] = { X86::CL, 0 }; 00149 static const unsigned SHLD32rrCLImpUses[] = { X86::CL, 0 }; 00150 static const unsigned SHR16mCLImpUses[] = { X86::CL, 0 }; 00151 static const unsigned SHR16rCLImpUses[] = { X86::CL, 0 }; 00152 static const unsigned SHR32mCLImpUses[] = { X86::CL, 0 }; 00153 static const unsigned SHR32rCLImpUses[] = { X86::CL, 0 }; 00154 static const unsigned SHR8mCLImpUses[] = { X86::CL, 0 }; 00155 static const unsigned SHR8rCLImpUses[] = { X86::CL, 0 }; 00156 static const unsigned SHRD32mrCLImpUses[] = { X86::CL, 0 }; 00157 static const unsigned SHRD32rrCLImpUses[] = { X86::CL, 0 }; 00158 00159 static const TargetInstrDescriptor X86Insts[] = { 00160 { "PHI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs }, // Inst #0 = PHI 00161 { "ADC32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #1 = ADC32mi 00162 { "ADC32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #2 = ADC32mi8 00163 { "ADC32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(17<<16), EmptyImpUses, EmptyImpDefs }, // Inst #3 = ADC32mr 00164 { "ADC32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(18<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #4 = ADC32ri 00165 { "ADC32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(18<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #5 = ADC32ri8 00166 { "ADC32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(19<<16), EmptyImpUses, EmptyImpDefs }, // Inst #6 = ADC32rm 00167 { "ADC32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(17<<16), EmptyImpUses, EmptyImpDefs }, // Inst #7 = ADC32rr 00168 { "ADD16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #8 = ADD16mi 00169 { "ADD16mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #9 = ADD16mi8 00170 { "ADD16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(1<<16), EmptyImpUses, EmptyImpDefs }, // Inst #10 = ADD16mr 00171 { "ADD16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #11 = ADD16ri 00172 { "ADD16ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #12 = ADD16ri8 00173 { "ADD16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(3<<16), EmptyImpUses, EmptyImpDefs }, // Inst #13 = ADD16rm 00174 { "ADD16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<5)|(1<<16), EmptyImpUses, EmptyImpDefs }, // Inst #14 = ADD16rr 00175 { "ADD32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #15 = ADD32mi 00176 { "ADD32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #16 = ADD32mi8 00177 { "ADD32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<16), EmptyImpUses, EmptyImpDefs }, // Inst #17 = ADD32mr 00178 { "ADD32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #18 = ADD32ri 00179 { "ADD32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #19 = ADD32ri8 00180 { "ADD32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(3<<16), EmptyImpUses, EmptyImpDefs }, // Inst #20 = ADD32rm 00181 { "ADD32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<16), EmptyImpUses, EmptyImpDefs }, // Inst #21 = ADD32rr 00182 { "ADD8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #22 = ADD8mi 00183 { "ADD8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0), EmptyImpUses, EmptyImpDefs }, // Inst #23 = ADD8mr 00184 { "ADD8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #24 = ADD8ri 00185 { "ADD8rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(2<<16), EmptyImpUses, EmptyImpDefs }, // Inst #25 = ADD8rm 00186 { "ADD8rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0), EmptyImpUses, EmptyImpDefs }, // Inst #26 = ADD8rr 00187 { "ADJCALLSTACKDOWN", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs }, // Inst #27 = ADJCALLSTACKDOWN 00188 { "ADJCALLSTACKUP", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs }, // Inst #28 = ADJCALLSTACKUP 00189 { "AND16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #29 = AND16mi 00190 { "AND16mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #30 = AND16mi8 00191 { "AND16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(33<<16), EmptyImpUses, EmptyImpDefs }, // Inst #31 = AND16mr 00192 { "AND16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #32 = AND16ri 00193 { "AND16ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #33 = AND16ri8 00194 { "AND16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(35<<16), EmptyImpUses, EmptyImpDefs }, // Inst #34 = AND16rm 00195 { "AND16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<5)|(33<<16), EmptyImpUses, EmptyImpDefs }, // Inst #35 = AND16rr 00196 { "AND32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #36 = AND32mi 00197 { "AND32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #37 = AND32mi8 00198 { "AND32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(33<<16), EmptyImpUses, EmptyImpDefs }, // Inst #38 = AND32mr 00199 { "AND32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #39 = AND32ri 00200 { "AND32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #40 = AND32ri8 00201 { "AND32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(35<<16), EmptyImpUses, EmptyImpDefs }, // Inst #41 = AND32rm 00202 { "AND32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(33<<16), EmptyImpUses, EmptyImpDefs }, // Inst #42 = AND32rr 00203 { "AND8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #43 = AND8mi 00204 { "AND8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(32<<16), EmptyImpUses, EmptyImpDefs }, // Inst #44 = AND8mr 00205 { "AND8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #45 = AND8ri 00206 { "AND8rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(34<<16), EmptyImpUses, EmptyImpDefs }, // Inst #46 = AND8rm 00207 { "AND8rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(32<<16), EmptyImpUses, EmptyImpDefs }, // Inst #47 = AND8rr 00208 { "BSWAP32r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(1<<6)|(200<<16), EmptyImpUses, EmptyImpDefs }, // Inst #48 = BSWAP32r 00209 { "CALL32m", -1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|(26<<0)|(255<<16), EmptyImpUses, CALL32mImpDefs }, // Inst #49 = CALL32m 00210 { "CALL32r", -1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|(18<<0)|(255<<16), EmptyImpUses, CALL32rImpDefs }, // Inst #50 = CALL32r 00211 { "CALLpcrel32", -1, -1, 0, false, 0, 0, 0, 0|M_CALL_FLAG, 0|(1<<0)|(232<<16), EmptyImpUses, CALLpcrel32ImpDefs }, // Inst #51 = CALLpcrel32 00212 { "CBW", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(152<<16), CBWImpUses, CBWImpDefs }, // Inst #52 = CBW 00213 { "CDQ", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(153<<16), CDQImpUses, CDQImpDefs }, // Inst #53 = CDQ 00214 { "CMOVA16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(71<<16), EmptyImpUses, EmptyImpDefs }, // Inst #54 = CMOVA16rm 00215 { "CMOVA16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(71<<16), EmptyImpUses, EmptyImpDefs }, // Inst #55 = CMOVA16rr 00216 { "CMOVA32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(71<<16), EmptyImpUses, EmptyImpDefs }, // Inst #56 = CMOVA32rm 00217 { "CMOVA32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(71<<16), EmptyImpUses, EmptyImpDefs }, // Inst #57 = CMOVA32rr 00218 { "CMOVAE16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(67<<16), EmptyImpUses, EmptyImpDefs }, // Inst #58 = CMOVAE16rm 00219 { "CMOVAE16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(67<<16), EmptyImpUses, EmptyImpDefs }, // Inst #59 = CMOVAE16rr 00220 { "CMOVAE32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(67<<16), EmptyImpUses, EmptyImpDefs }, // Inst #60 = CMOVAE32rm 00221 { "CMOVAE32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(67<<16), EmptyImpUses, EmptyImpDefs }, // Inst #61 = CMOVAE32rr 00222 { "CMOVB16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(66<<16), EmptyImpUses, EmptyImpDefs }, // Inst #62 = CMOVB16rm 00223 { "CMOVB16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(66<<16), EmptyImpUses, EmptyImpDefs }, // Inst #63 = CMOVB16rr 00224 { "CMOVB32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(66<<16), EmptyImpUses, EmptyImpDefs }, // Inst #64 = CMOVB32rm 00225 { "CMOVB32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(66<<16), EmptyImpUses, EmptyImpDefs }, // Inst #65 = CMOVB32rr 00226 { "CMOVBE16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(70<<16), EmptyImpUses, EmptyImpDefs }, // Inst #66 = CMOVBE16rm 00227 { "CMOVBE16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(70<<16), EmptyImpUses, EmptyImpDefs }, // Inst #67 = CMOVBE16rr 00228 { "CMOVBE32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(70<<16), EmptyImpUses, EmptyImpDefs }, // Inst #68 = CMOVBE32rm 00229 { "CMOVBE32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(70<<16), EmptyImpUses, EmptyImpDefs }, // Inst #69 = CMOVBE32rr 00230 { "CMOVE16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(68<<16), EmptyImpUses, EmptyImpDefs }, // Inst #70 = CMOVE16rm 00231 { "CMOVE16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(68<<16), EmptyImpUses, EmptyImpDefs }, // Inst #71 = CMOVE16rr 00232 { "CMOVE32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(68<<16), EmptyImpUses, EmptyImpDefs }, // Inst #72 = CMOVE32rm 00233 { "CMOVE32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(68<<16), EmptyImpUses, EmptyImpDefs }, // Inst #73 = CMOVE32rr 00234 { "CMOVG16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(79<<16), EmptyImpUses, EmptyImpDefs }, // Inst #74 = CMOVG16rm 00235 { "CMOVG16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(79<<16), EmptyImpUses, EmptyImpDefs }, // Inst #75 = CMOVG16rr 00236 { "CMOVG32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(79<<16), EmptyImpUses, EmptyImpDefs }, // Inst #76 = CMOVG32rm 00237 { "CMOVG32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(79<<16), EmptyImpUses, EmptyImpDefs }, // Inst #77 = CMOVG32rr 00238 { "CMOVGE16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(77<<16), EmptyImpUses, EmptyImpDefs }, // Inst #78 = CMOVGE16rm 00239 { "CMOVGE16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(77<<16), EmptyImpUses, EmptyImpDefs }, // Inst #79 = CMOVGE16rr 00240 { "CMOVGE32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(77<<16), EmptyImpUses, EmptyImpDefs }, // Inst #80 = CMOVGE32rm 00241 { "CMOVGE32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(77<<16), EmptyImpUses, EmptyImpDefs }, // Inst #81 = CMOVGE32rr 00242 { "CMOVL16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(76<<16), EmptyImpUses, EmptyImpDefs }, // Inst #82 = CMOVL16rm 00243 { "CMOVL16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(76<<16), EmptyImpUses, EmptyImpDefs }, // Inst #83 = CMOVL16rr 00244 { "CMOVL32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(76<<16), EmptyImpUses, EmptyImpDefs }, // Inst #84 = CMOVL32rm 00245 { "CMOVL32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(76<<16), EmptyImpUses, EmptyImpDefs }, // Inst #85 = CMOVL32rr 00246 { "CMOVLE16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(78<<16), EmptyImpUses, EmptyImpDefs }, // Inst #86 = CMOVLE16rm 00247 { "CMOVLE16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(78<<16), EmptyImpUses, EmptyImpDefs }, // Inst #87 = CMOVLE16rr 00248 { "CMOVLE32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(78<<16), EmptyImpUses, EmptyImpDefs }, // Inst #88 = CMOVLE32rm 00249 { "CMOVLE32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(78<<16), EmptyImpUses, EmptyImpDefs }, // Inst #89 = CMOVLE32rr 00250 { "CMOVNE16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(69<<16), EmptyImpUses, EmptyImpDefs }, // Inst #90 = CMOVNE16rm 00251 { "CMOVNE16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(69<<16), EmptyImpUses, EmptyImpDefs }, // Inst #91 = CMOVNE16rr 00252 { "CMOVNE32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(69<<16), EmptyImpUses, EmptyImpDefs }, // Inst #92 = CMOVNE32rm 00253 { "CMOVNE32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(69<<16), EmptyImpUses, EmptyImpDefs }, // Inst #93 = CMOVNE32rr 00254 { "CMOVNS16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(73<<16), EmptyImpUses, EmptyImpDefs }, // Inst #94 = CMOVNS16rm 00255 { "CMOVNS16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(73<<16), EmptyImpUses, EmptyImpDefs }, // Inst #95 = CMOVNS16rr 00256 { "CMOVNS32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(73<<16), EmptyImpUses, EmptyImpDefs }, // Inst #96 = CMOVNS32rm 00257 { "CMOVNS32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(73<<16), EmptyImpUses, EmptyImpDefs }, // Inst #97 = CMOVNS32rr 00258 { "CMOVS16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(72<<16), EmptyImpUses, EmptyImpDefs }, // Inst #98 = CMOVS16rm 00259 { "CMOVS16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(72<<16), EmptyImpUses, EmptyImpDefs }, // Inst #99 = CMOVS16rr 00260 { "CMOVS32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(72<<16), EmptyImpUses, EmptyImpDefs }, // Inst #100 = CMOVS32rm 00261 { "CMOVS32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(72<<16), EmptyImpUses, EmptyImpDefs }, // Inst #101 = CMOVS32rr 00262 { "CMP16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #102 = CMP16mi 00263 { "CMP16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(57<<16), EmptyImpUses, EmptyImpDefs }, // Inst #103 = CMP16mr 00264 { "CMP16ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(23<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #104 = CMP16ri 00265 { "CMP16rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(59<<16), EmptyImpUses, EmptyImpDefs }, // Inst #105 = CMP16rm 00266 { "CMP16rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(1<<5)|(57<<16), EmptyImpUses, EmptyImpDefs }, // Inst #106 = CMP16rr 00267 { "CMP32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #107 = CMP32mi 00268 { "CMP32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(57<<16), EmptyImpUses, EmptyImpDefs }, // Inst #108 = CMP32mr 00269 { "CMP32ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(23<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #109 = CMP32ri 00270 { "CMP32rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(59<<16), EmptyImpUses, EmptyImpDefs }, // Inst #110 = CMP32rm 00271 { "CMP32rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(57<<16), EmptyImpUses, EmptyImpDefs }, // Inst #111 = CMP32rr 00272 { "CMP8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #112 = CMP8mi 00273 { "CMP8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(56<<16), EmptyImpUses, EmptyImpDefs }, // Inst #113 = CMP8mr 00274 { "CMP8ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(23<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #114 = CMP8ri 00275 { "CMP8rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(58<<16), EmptyImpUses, EmptyImpDefs }, // Inst #115 = CMP8rm 00276 { "CMP8rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(56<<16), EmptyImpUses, EmptyImpDefs }, // Inst #116 = CMP8rr 00277 { "CWD", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(153<<16), CWDImpUses, CWDImpDefs }, // Inst #117 = CWD 00278 { "DEC16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(1<<5)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #118 = DEC16m 00279 { "DEC16r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(1<<5)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #119 = DEC16r 00280 { "DEC32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #120 = DEC32m 00281 { "DEC32r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #121 = DEC32r 00282 { "DEC8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(254<<16), EmptyImpUses, EmptyImpDefs }, // Inst #122 = DEC8m 00283 { "DEC8r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(254<<16), EmptyImpUses, EmptyImpDefs }, // Inst #123 = DEC8r 00284 { "DIV16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(1<<5)|(247<<16), DIV16mImpUses, DIV16mImpDefs }, // Inst #124 = DIV16m 00285 { "DIV16r", -1, -1, 0, false, 0, 0, 0, 0, 0|(22<<0)|(1<<5)|(247<<16), DIV16rImpUses, DIV16rImpDefs }, // Inst #125 = DIV16r 00286 { "DIV32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(247<<16), DIV32mImpUses, DIV32mImpDefs }, // Inst #126 = DIV32m 00287 { "DIV32r", -1, -1, 0, false, 0, 0, 0, 0, 0|(22<<0)|(247<<16), DIV32rImpUses, DIV32rImpDefs }, // Inst #127 = DIV32r 00288 { "DIV8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(246<<16), DIV8mImpUses, DIV8mImpDefs }, // Inst #128 = DIV8m 00289 { "DIV8r", -1, -1, 0, false, 0, 0, 0, 0, 0|(22<<0)|(246<<16), DIV8rImpUses, DIV8rImpDefs }, // Inst #129 = DIV8r 00290 { "FADD32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(3<<12)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #130 = FADD32m 00291 { "FADD64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(3<<12)|(220<<16), EmptyImpUses, EmptyImpDefs }, // Inst #131 = FADD64m 00292 { "FADDPrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(9<<6)|(192<<16), FADDPrST0ImpUses, EmptyImpDefs }, // Inst #132 = FADDPrST0 00293 { "FADDST0r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<6)|(192<<16), FADDST0rImpUses, FADDST0rImpDefs }, // Inst #133 = FADDST0r 00294 { "FADDrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(7<<6)|(192<<16), FADDrST0ImpUses, EmptyImpDefs }, // Inst #134 = FADDrST0 00295 { "FCHS", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(4<<6)|(3<<12)|(224<<16), EmptyImpUses, EmptyImpDefs }, // Inst #135 = FCHS 00296 { "FCMOVA", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(6<<6)|(6<<12)|(208<<16), FCMOVAImpUses, FCMOVAImpDefs }, // Inst #136 = FCMOVA 00297 { "FCMOVAE", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(6<<6)|(6<<12)|(192<<16), FCMOVAEImpUses, FCMOVAEImpDefs }, // Inst #137 = FCMOVAE 00298 { "FCMOVB", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(5<<6)|(6<<12)|(192<<16), FCMOVBImpUses, FCMOVBImpDefs }, // Inst #138 = FCMOVB 00299 { "FCMOVBE", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(5<<6)|(6<<12)|(208<<16), FCMOVBEImpUses, FCMOVBEImpDefs }, // Inst #139 = FCMOVBE 00300 { "FCMOVE", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(5<<6)|(6<<12)|(200<<16), FCMOVEImpUses, FCMOVEImpDefs }, // Inst #140 = FCMOVE 00301 { "FCMOVNE", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(2<<0)|(6<<6)|(6<<12)|(200<<16), FCMOVNEImpUses, FCMOVNEImpDefs }, // Inst #141 = FCMOVNE 00302 { "FDIV32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(3<<12)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #142 = FDIV32m 00303 { "FDIV64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(3<<12)|(220<<16), EmptyImpUses, EmptyImpDefs }, // Inst #143 = FDIV64m 00304 { "FDIVPrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(9<<6)|(248<<16), FDIVPrST0ImpUses, EmptyImpDefs }, // Inst #144 = FDIVPrST0 00305 { "FDIVR32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(3<<12)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #145 = FDIVR32m 00306 { "FDIVR64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(3<<12)|(220<<16), EmptyImpUses, EmptyImpDefs }, // Inst #146 = FDIVR64m 00307 { "FDIVRPrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(9<<6)|(240<<16), FDIVRPrST0ImpUses, EmptyImpDefs }, // Inst #147 = FDIVRPrST0 00308 { "FDIVRST0r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<6)|(248<<16), FDIVRST0rImpUses, FDIVRST0rImpDefs }, // Inst #148 = FDIVRST0r 00309 { "FDIVRrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(7<<6)|(240<<16), FDIVRrST0ImpUses, EmptyImpDefs }, // Inst #149 = FDIVRrST0 00310 { "FDIVST0r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<6)|(240<<16), FDIVST0rImpUses, FDIVST0rImpDefs }, // Inst #150 = FDIVST0r 00311 { "FDIVrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(7<<6)|(248<<16), FDIVrST0ImpUses, EmptyImpDefs }, // Inst #151 = FDIVrST0 00312 { "FILD16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<12)|(223<<16), EmptyImpUses, EmptyImpDefs }, // Inst #152 = FILD16m 00313 { "FILD32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<12)|(219<<16), EmptyImpUses, EmptyImpDefs }, // Inst #153 = FILD32m 00314 { "FILD64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<12)|(223<<16), EmptyImpUses, EmptyImpDefs }, // Inst #154 = FILD64m 00315 { "FIST16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(2<<12)|(223<<16), EmptyImpUses, EmptyImpDefs }, // Inst #155 = FIST16m 00316 { "FIST32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(2<<12)|(219<<16), EmptyImpUses, EmptyImpDefs }, // Inst #156 = FIST32m 00317 { "FISTP16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(223<<16), EmptyImpUses, EmptyImpDefs }, // Inst #157 = FISTP16m 00318 { "FISTP32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(219<<16), EmptyImpUses, EmptyImpDefs }, // Inst #158 = FISTP32m 00319 { "FISTP64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(2<<12)|(223<<16), EmptyImpUses, EmptyImpDefs }, // Inst #159 = FISTP64m 00320 { "FLD0", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(4<<6)|(1<<12)|(238<<16), EmptyImpUses, EmptyImpDefs }, // Inst #160 = FLD0 00321 { "FLD1", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(4<<6)|(1<<12)|(232<<16), EmptyImpUses, EmptyImpDefs }, // Inst #161 = FLD1 00322 { "FLD32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<12)|(217<<16), EmptyImpUses, EmptyImpDefs }, // Inst #162 = FLD32m 00323 { "FLD64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<12)|(221<<16), EmptyImpUses, EmptyImpDefs }, // Inst #163 = FLD64m 00324 { "FLD80m", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<12)|(219<<16), EmptyImpUses, EmptyImpDefs }, // Inst #164 = FLD80m 00325 { "FLDCW16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(217<<16), EmptyImpUses, EmptyImpDefs }, // Inst #165 = FLDCW16m 00326 { "FLDrr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(4<<6)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #166 = FLDrr 00327 { "FMUL32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(3<<12)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #167 = FMUL32m 00328 { "FMUL64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(3<<12)|(220<<16), EmptyImpUses, EmptyImpDefs }, // Inst #168 = FMUL64m 00329 { "FMULPrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(9<<6)|(200<<16), FMULPrST0ImpUses, EmptyImpDefs }, // Inst #169 = FMULPrST0 00330 { "FMULST0r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<6)|(200<<16), FMULST0rImpUses, FMULST0rImpDefs }, // Inst #170 = FMULST0r 00331 { "FMULrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(7<<6)|(200<<16), FMULrST0ImpUses, EmptyImpDefs }, // Inst #171 = FMULrST0 00332 { "FNSTCW16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(217<<16), EmptyImpUses, EmptyImpDefs }, // Inst #172 = FNSTCW16m 00333 { "FNSTSW8r", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(10<<6)|(224<<16), EmptyImpUses, FNSTSW8rImpDefs }, // Inst #173 = FNSTSW8r 00334 { "FP_REG_KILL", -1, -1, 0, false, 0, 0, 0, 0|M_TERMINATOR_FLAG, 0, EmptyImpUses, FP_REG_KILLImpDefs }, // Inst #174 = FP_REG_KILL 00335 { "FST32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(2<<12)|(217<<16), EmptyImpUses, EmptyImpDefs }, // Inst #175 = FST32m 00336 { "FST64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(2<<12)|(221<<16), EmptyImpUses, EmptyImpDefs }, // Inst #176 = FST64m 00337 { "FSTP32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(2<<12)|(217<<16), EmptyImpUses, EmptyImpDefs }, // Inst #177 = FSTP32m 00338 { "FSTP64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(2<<12)|(221<<16), EmptyImpUses, EmptyImpDefs }, // Inst #178 = FSTP64m 00339 { "FSTP80m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(2<<12)|(219<<16), EmptyImpUses, EmptyImpDefs }, // Inst #179 = FSTP80m 00340 { "FSTPrr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(8<<6)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #180 = FSTPrr 00341 { "FSTrr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(8<<6)|(208<<16), EmptyImpUses, EmptyImpDefs }, // Inst #181 = FSTrr 00342 { "FSUB32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(3<<12)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #182 = FSUB32m 00343 { "FSUB64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(3<<12)|(220<<16), EmptyImpUses, EmptyImpDefs }, // Inst #183 = FSUB64m 00344 { "FSUBPrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(9<<6)|(232<<16), FSUBPrST0ImpUses, EmptyImpDefs }, // Inst #184 = FSUBPrST0 00345 { "FSUBR32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(3<<12)|(216<<16), EmptyImpUses, EmptyImpDefs }, // Inst #185 = FSUBR32m 00346 { "FSUBR64m", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(3<<12)|(220<<16), EmptyImpUses, EmptyImpDefs }, // Inst #186 = FSUBR64m 00347 { "FSUBRPrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(9<<6)|(224<<16), FSUBRPrST0ImpUses, EmptyImpDefs }, // Inst #187 = FSUBRPrST0 00348 { "FSUBRST0r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<6)|(232<<16), FSUBRST0rImpUses, FSUBRST0rImpDefs }, // Inst #188 = FSUBRST0r 00349 { "FSUBRrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(7<<6)|(224<<16), FSUBRrST0ImpUses, EmptyImpDefs }, // Inst #189 = FSUBRrST0 00350 { "FSUBST0r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<6)|(224<<16), FSUBST0rImpUses, FSUBST0rImpDefs }, // Inst #190 = FSUBST0r 00351 { "FSUBrST0", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(7<<6)|(232<<16), FSUBrST0ImpUses, EmptyImpDefs }, // Inst #191 = FSUBrST0 00352 { "FTST", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(4<<6)|(2<<12)|(228<<16), EmptyImpUses, EmptyImpDefs }, // Inst #192 = FTST 00353 { "FUCOMIPr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(10<<6)|(232<<16), FUCOMIPrImpUses, EmptyImpDefs }, // Inst #193 = FUCOMIPr 00354 { "FUCOMIr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(6<<6)|(5<<12)|(232<<16), FUCOMIrImpUses, EmptyImpDefs }, // Inst #194 = FUCOMIr 00355 { "FUCOMPPr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(5<<6)|(233<<16), FUCOMPPrImpUses, EmptyImpDefs }, // Inst #195 = FUCOMPPr 00356 { "FUCOMPr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(8<<6)|(232<<16), FUCOMPrImpUses, EmptyImpDefs }, // Inst #196 = FUCOMPr 00357 { "FUCOMr", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(8<<6)|(5<<12)|(224<<16), FUCOMrImpUses, EmptyImpDefs }, // Inst #197 = FUCOMr 00358 { "FXCH", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(4<<6)|(200<<16), EmptyImpUses, EmptyImpDefs }, // Inst #198 = FXCH 00359 { "FpADD", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<12), EmptyImpUses, EmptyImpDefs }, // Inst #199 = FpADD 00360 { "FpDIV", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<12), EmptyImpUses, EmptyImpDefs }, // Inst #200 = FpDIV 00361 { "FpGETRESULT", -1, -1, 0, false, 0, 0, 0, 0, 0|(7<<12), FpGETRESULTImpUses, EmptyImpDefs }, // Inst #201 = FpGETRESULT 00362 { "FpMOV", -1, -1, 0, false, 0, 0, 0, 0, 0|(7<<12), EmptyImpUses, EmptyImpDefs }, // Inst #202 = FpMOV 00363 { "FpMUL", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<12), EmptyImpUses, EmptyImpDefs }, // Inst #203 = FpMUL 00364 { "FpSETRESULT", -1, -1, 0, false, 0, 0, 0, 0, 0|(7<<12), EmptyImpUses, FpSETRESULTImpDefs }, // Inst #204 = FpSETRESULT 00365 { "FpSUB", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<12), EmptyImpUses, EmptyImpDefs }, // Inst #205 = FpSUB 00366 { "IDIV16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<5)|(247<<16), IDIV16mImpUses, IDIV16mImpDefs }, // Inst #206 = IDIV16m 00367 { "IDIV16r", -1, -1, 0, false, 0, 0, 0, 0, 0|(23<<0)|(1<<5)|(247<<16), IDIV16rImpUses, IDIV16rImpDefs }, // Inst #207 = IDIV16r 00368 { "IDIV32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(247<<16), IDIV32mImpUses, IDIV32mImpDefs }, // Inst #208 = IDIV32m 00369 { "IDIV32r", -1, -1, 0, false, 0, 0, 0, 0, 0|(23<<0)|(247<<16), IDIV32rImpUses, IDIV32rImpDefs }, // Inst #209 = IDIV32r 00370 { "IDIV8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(246<<16), IDIV8mImpUses, IDIV8mImpDefs }, // Inst #210 = IDIV8m 00371 { "IDIV8r", -1, -1, 0, false, 0, 0, 0, 0, 0|(23<<0)|(246<<16), IDIV8rImpUses, IDIV8rImpDefs }, // Inst #211 = IDIV8r 00372 { "IMPLICIT_DEF", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs }, // Inst #212 = IMPLICIT_DEF 00373 { "IMPLICIT_USE", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs }, // Inst #213 = IMPLICIT_USE 00374 { "IMUL16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(1<<6)|(175<<16), EmptyImpUses, EmptyImpDefs }, // Inst #214 = IMUL16rm 00375 { "IMUL16rmi", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(2<<10)|(105<<16), EmptyImpUses, EmptyImpDefs }, // Inst #215 = IMUL16rmi 00376 { "IMUL16rmi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(1<<10)|(107<<16), EmptyImpUses, EmptyImpDefs }, // Inst #216 = IMUL16rmi8 00377 { "IMUL16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<5)|(1<<6)|(175<<16), EmptyImpUses, EmptyImpDefs }, // Inst #217 = IMUL16rr 00378 { "IMUL16rri", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<5)|(2<<10)|(105<<16), EmptyImpUses, EmptyImpDefs }, // Inst #218 = IMUL16rri 00379 { "IMUL16rri8", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<5)|(1<<10)|(107<<16), EmptyImpUses, EmptyImpDefs }, // Inst #219 = IMUL16rri8 00380 { "IMUL32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<6)|(175<<16), EmptyImpUses, EmptyImpDefs }, // Inst #220 = IMUL32rm 00381 { "IMUL32rmi", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(3<<10)|(105<<16), EmptyImpUses, EmptyImpDefs }, // Inst #221 = IMUL32rmi 00382 { "IMUL32rmi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<10)|(107<<16), EmptyImpUses, EmptyImpDefs }, // Inst #222 = IMUL32rmi8 00383 { "IMUL32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(5<<0)|(1<<6)|(175<<16), EmptyImpUses, EmptyImpDefs }, // Inst #223 = IMUL32rr 00384 { "IMUL32rri", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(3<<10)|(105<<16), EmptyImpUses, EmptyImpDefs }, // Inst #224 = IMUL32rri 00385 { "IMUL32rri8", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<10)|(107<<16), EmptyImpUses, EmptyImpDefs }, // Inst #225 = IMUL32rri8 00386 { "IN16ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(1<<5)|(2<<10)|(229<<16), EmptyImpUses, IN16riImpDefs }, // Inst #226 = IN16ri 00387 { "IN16rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(1<<5)|(237<<16), IN16rrImpUses, IN16rrImpDefs }, // Inst #227 = IN16rr 00388 { "IN32ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<10)|(229<<16), EmptyImpUses, IN32riImpDefs }, // Inst #228 = IN32ri 00389 { "IN32rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(237<<16), IN32rrImpUses, IN32rrImpDefs }, // Inst #229 = IN32rr 00390 { "IN8ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<10)|(228<<16), EmptyImpUses, IN8riImpDefs }, // Inst #230 = IN8ri 00391 { "IN8rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(236<<16), IN8rrImpUses, IN8rrImpDefs }, // Inst #231 = IN8rr 00392 { "INC16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<5)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #232 = INC16m 00393 { "INC16r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(1<<5)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #233 = INC16r 00394 { "INC32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #234 = INC32m 00395 { "INC32r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(255<<16), EmptyImpUses, EmptyImpDefs }, // Inst #235 = INC32r 00396 { "INC8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(254<<16), EmptyImpUses, EmptyImpDefs }, // Inst #236 = INC8m 00397 { "INC8r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(16<<0)|(254<<16), EmptyImpUses, EmptyImpDefs }, // Inst #237 = INC8r 00398 { "JA", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #238 = JA 00399 { "JAE", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #239 = JAE 00400 { "JB", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(130<<16), EmptyImpUses, EmptyImpDefs }, // Inst #240 = JB 00401 { "JBE", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(134<<16), EmptyImpUses, EmptyImpDefs }, // Inst #241 = JBE 00402 { "JE", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(132<<16), EmptyImpUses, EmptyImpDefs }, // Inst #242 = JE 00403 { "JG", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(143<<16), EmptyImpUses, EmptyImpDefs }, // Inst #243 = JG 00404 { "JGE", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(141<<16), EmptyImpUses, EmptyImpDefs }, // Inst #244 = JGE 00405 { "JL", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(140<<16), EmptyImpUses, EmptyImpDefs }, // Inst #245 = JL 00406 { "JLE", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(142<<16), EmptyImpUses, EmptyImpDefs }, // Inst #246 = JLE 00407 { "JMP", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(233<<16), EmptyImpUses, EmptyImpDefs }, // Inst #247 = JMP 00408 { "JNE", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #248 = JNE 00409 { "JNS", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(137<<16), EmptyImpUses, EmptyImpDefs }, // Inst #249 = JNS 00410 { "JS", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(1<<6)|(136<<16), EmptyImpUses, EmptyImpDefs }, // Inst #250 = JS 00411 { "LAHF", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(159<<16), EmptyImpUses, LAHFImpDefs }, // Inst #251 = LAHF 00412 { "LEA16r", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(141<<16), EmptyImpUses, EmptyImpDefs }, // Inst #252 = LEA16r 00413 { "LEA32r", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(141<<16), EmptyImpUses, EmptyImpDefs }, // Inst #253 = LEA32r 00414 { "LEAVE", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(201<<16), LEAVEImpUses, LEAVEImpDefs }, // Inst #254 = LEAVE 00415 { "MOV16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<5)|(2<<10)|(199<<16), EmptyImpUses, EmptyImpDefs }, // Inst #255 = MOV16mi 00416 { "MOV16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(137<<16), EmptyImpUses, EmptyImpDefs }, // Inst #256 = MOV16mr 00417 { "MOV16ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(1<<5)|(2<<10)|(184<<16), EmptyImpUses, EmptyImpDefs }, // Inst #257 = MOV16ri 00418 { "MOV16rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(139<<16), EmptyImpUses, EmptyImpDefs }, // Inst #258 = MOV16rm 00419 { "MOV16rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(1<<5)|(137<<16), EmptyImpUses, EmptyImpDefs }, // Inst #259 = MOV16rr 00420 { "MOV32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(3<<10)|(199<<16), EmptyImpUses, EmptyImpDefs }, // Inst #260 = MOV32mi 00421 { "MOV32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(137<<16), EmptyImpUses, EmptyImpDefs }, // Inst #261 = MOV32mr 00422 { "MOV32ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(3<<10)|(184<<16), EmptyImpUses, EmptyImpDefs }, // Inst #262 = MOV32ri 00423 { "MOV32rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(139<<16), EmptyImpUses, EmptyImpDefs }, // Inst #263 = MOV32rm 00424 { "MOV32rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(137<<16), EmptyImpUses, EmptyImpDefs }, // Inst #264 = MOV32rr 00425 { "MOV8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<10)|(198<<16), EmptyImpUses, EmptyImpDefs }, // Inst #265 = MOV8mi 00426 { "MOV8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(136<<16), EmptyImpUses, EmptyImpDefs }, // Inst #266 = MOV8mr 00427 { "MOV8ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(1<<10)|(176<<16), EmptyImpUses, EmptyImpDefs }, // Inst #267 = MOV8ri 00428 { "MOV8rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(138<<16), EmptyImpUses, EmptyImpDefs }, // Inst #268 = MOV8rm 00429 { "MOV8rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(136<<16), EmptyImpUses, EmptyImpDefs }, // Inst #269 = MOV8rr 00430 { "MOVSX16rm8", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(1<<6)|(190<<16), EmptyImpUses, EmptyImpDefs }, // Inst #270 = MOVSX16rm8 00431 { "MOVSX16rr8", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<5)|(1<<6)|(190<<16), EmptyImpUses, EmptyImpDefs }, // Inst #271 = MOVSX16rr8 00432 { "MOVSX32rm16", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<6)|(191<<16), EmptyImpUses, EmptyImpDefs }, // Inst #272 = MOVSX32rm16 00433 { "MOVSX32rm8", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<6)|(190<<16), EmptyImpUses, EmptyImpDefs }, // Inst #273 = MOVSX32rm8 00434 { "MOVSX32rr16", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<6)|(191<<16), EmptyImpUses, EmptyImpDefs }, // Inst #274 = MOVSX32rr16 00435 { "MOVSX32rr8", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<6)|(190<<16), EmptyImpUses, EmptyImpDefs }, // Inst #275 = MOVSX32rr8 00436 { "MOVZX16rm8", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(1<<6)|(182<<16), EmptyImpUses, EmptyImpDefs }, // Inst #276 = MOVZX16rm8 00437 { "MOVZX16rr8", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<5)|(1<<6)|(182<<16), EmptyImpUses, EmptyImpDefs }, // Inst #277 = MOVZX16rr8 00438 { "MOVZX32rm16", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<6)|(183<<16), EmptyImpUses, EmptyImpDefs }, // Inst #278 = MOVZX32rm16 00439 { "MOVZX32rm8", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<6)|(182<<16), EmptyImpUses, EmptyImpDefs }, // Inst #279 = MOVZX32rm8 00440 { "MOVZX32rr16", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<6)|(183<<16), EmptyImpUses, EmptyImpDefs }, // Inst #280 = MOVZX32rr16 00441 { "MOVZX32rr8", -1, -1, 0, false, 0, 0, 0, 0, 0|(5<<0)|(1<<6)|(182<<16), EmptyImpUses, EmptyImpDefs }, // Inst #281 = MOVZX32rr8 00442 { "MUL16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<5)|(247<<16), MUL16mImpUses, MUL16mImpDefs }, // Inst #282 = MUL16m 00443 { "MUL16r", -1, -1, 0, false, 0, 0, 0, 0, 0|(20<<0)|(1<<5)|(247<<16), MUL16rImpUses, MUL16rImpDefs }, // Inst #283 = MUL16r 00444 { "MUL32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(247<<16), MUL32mImpUses, MUL32mImpDefs }, // Inst #284 = MUL32m 00445 { "MUL32r", -1, -1, 0, false, 0, 0, 0, 0, 0|(20<<0)|(247<<16), MUL32rImpUses, MUL32rImpDefs }, // Inst #285 = MUL32r 00446 { "MUL8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(246<<16), MUL8mImpUses, MUL8mImpDefs }, // Inst #286 = MUL8m 00447 { "MUL8r", -1, -1, 0, false, 0, 0, 0, 0, 0|(20<<0)|(246<<16), MUL8rImpUses, MUL8rImpDefs }, // Inst #287 = MUL8r 00448 { "NEG16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(1<<5)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #288 = NEG16m 00449 { "NEG16r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(1<<5)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #289 = NEG16r 00450 { "NEG32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #290 = NEG32m 00451 { "NEG32r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #291 = NEG32r 00452 { "NEG8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(246<<16), EmptyImpUses, EmptyImpDefs }, // Inst #292 = NEG8m 00453 { "NEG8r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(246<<16), EmptyImpUses, EmptyImpDefs }, // Inst #293 = NEG8r 00454 { "NOOP", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(144<<16), EmptyImpUses, EmptyImpDefs }, // Inst #294 = NOOP 00455 { "NOT16m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(1<<5)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #295 = NOT16m 00456 { "NOT16r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(18<<0)|(1<<5)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #296 = NOT16r 00457 { "NOT32m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #297 = NOT32m 00458 { "NOT32r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(18<<0)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #298 = NOT32r 00459 { "NOT8m", -1, -1, 0, false, 0, 0, 0, 0, 0|(26<<0)|(246<<16), EmptyImpUses, EmptyImpDefs }, // Inst #299 = NOT8m 00460 { "NOT8r", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(18<<0)|(246<<16), EmptyImpUses, EmptyImpDefs }, // Inst #300 = NOT8r 00461 { "OR16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #301 = OR16mi 00462 { "OR16mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #302 = OR16mi8 00463 { "OR16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(9<<16), EmptyImpUses, EmptyImpDefs }, // Inst #303 = OR16mr 00464 { "OR16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #304 = OR16ri 00465 { "OR16ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #305 = OR16ri8 00466 { "OR16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(11<<16), EmptyImpUses, EmptyImpDefs }, // Inst #306 = OR16rm 00467 { "OR16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<5)|(9<<16), EmptyImpUses, EmptyImpDefs }, // Inst #307 = OR16rr 00468 { "OR32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #308 = OR32mi 00469 { "OR32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #309 = OR32mi8 00470 { "OR32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(9<<16), EmptyImpUses, EmptyImpDefs }, // Inst #310 = OR32mr 00471 { "OR32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #311 = OR32ri 00472 { "OR32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #312 = OR32ri8 00473 { "OR32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(11<<16), EmptyImpUses, EmptyImpDefs }, // Inst #313 = OR32rm 00474 { "OR32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(9<<16), EmptyImpUses, EmptyImpDefs }, // Inst #314 = OR32rr 00475 { "OR8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(25<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #315 = OR8mi 00476 { "OR8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(8<<16), EmptyImpUses, EmptyImpDefs }, // Inst #316 = OR8mr 00477 { "OR8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(17<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #317 = OR8ri 00478 { "OR8rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(10<<16), EmptyImpUses, EmptyImpDefs }, // Inst #318 = OR8rm 00479 { "OR8rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(8<<16), EmptyImpUses, EmptyImpDefs }, // Inst #319 = OR8rr 00480 { "OUT16ir", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(1<<5)|(2<<10)|(231<<16), OUT16irImpUses, EmptyImpDefs }, // Inst #320 = OUT16ir 00481 { "OUT16rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(1<<5)|(239<<16), OUT16rrImpUses, EmptyImpDefs }, // Inst #321 = OUT16rr 00482 { "OUT32ir", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<10)|(231<<16), OUT32irImpUses, EmptyImpDefs }, // Inst #322 = OUT32ir 00483 { "OUT32rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(239<<16), OUT32rrImpUses, EmptyImpDefs }, // Inst #323 = OUT32rr 00484 { "OUT8ir", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<10)|(230<<16), OUT8irImpUses, EmptyImpDefs }, // Inst #324 = OUT8ir 00485 { "OUT8rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(238<<16), OUT8rrImpUses, EmptyImpDefs }, // Inst #325 = OUT8rr 00486 { "POP32r", -1, -1, 0, false, 0, 0, 0, 0, 0|(2<<0)|(88<<16), POP32rImpUses, POP32rImpDefs }, // Inst #326 = POP32r 00487 { "REP_MOVSB", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<6)|(164<<16), REP_MOVSBImpUses, REP_MOVSBImpDefs }, // Inst #327 = REP_MOVSB 00488 { "REP_MOVSD", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<6)|(165<<16), REP_MOVSDImpUses, REP_MOVSDImpDefs }, // Inst #328 = REP_MOVSD 00489 { "REP_MOVSW", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(1<<5)|(2<<6)|(165<<16), REP_MOVSWImpUses, REP_MOVSWImpDefs }, // Inst #329 = REP_MOVSW 00490 { "REP_STOSB", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<6)|(170<<16), REP_STOSBImpUses, REP_STOSBImpDefs }, // Inst #330 = REP_STOSB 00491 { "REP_STOSD", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(2<<6)|(171<<16), REP_STOSDImpUses, REP_STOSDImpDefs }, // Inst #331 = REP_STOSD 00492 { "REP_STOSW", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(1<<5)|(2<<6)|(171<<16), REP_STOSWImpUses, REP_STOSWImpDefs }, // Inst #332 = REP_STOSW 00493 { "RET", -1, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_BARRIER_FLAG|M_TERMINATOR_FLAG, 0|(1<<0)|(195<<16), EmptyImpUses, EmptyImpDefs }, // Inst #333 = RET 00494 { "SAHF", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<0)|(158<<16), SAHFImpUses, EmptyImpDefs }, // Inst #334 = SAHF 00495 { "SAR16mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<5)|(211<<16), SAR16mCLImpUses, EmptyImpDefs }, // Inst #335 = SAR16mCL 00496 { "SAR16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<5)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #336 = SAR16mi 00497 { "SAR16rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(23<<0)|(1<<5)|(211<<16), SAR16rCLImpUses, EmptyImpDefs }, // Inst #337 = SAR16rCL 00498 { "SAR16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(23<<0)|(1<<5)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #338 = SAR16ri 00499 { "SAR32mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(211<<16), SAR32mCLImpUses, EmptyImpDefs }, // Inst #339 = SAR32mCL 00500 { "SAR32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #340 = SAR32mi 00501 { "SAR32rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(23<<0)|(211<<16), SAR32rCLImpUses, EmptyImpDefs }, // Inst #341 = SAR32rCL 00502 { "SAR32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(23<<0)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #342 = SAR32ri 00503 { "SAR8mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(210<<16), SAR8mCLImpUses, EmptyImpDefs }, // Inst #343 = SAR8mCL 00504 { "SAR8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(31<<0)|(1<<10)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #344 = SAR8mi 00505 { "SAR8rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(23<<0)|(210<<16), SAR8rCLImpUses, EmptyImpDefs }, // Inst #345 = SAR8rCL 00506 { "SAR8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(23<<0)|(1<<10)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #346 = SAR8ri 00507 { "SBB16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(1<<5)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #347 = SBB16mi 00508 { "SBB16mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #348 = SBB16mi8 00509 { "SBB16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #349 = SBB16ri 00510 { "SBB16ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #350 = SBB16ri8 00511 { "SBB32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #351 = SBB32mi 00512 { "SBB32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #352 = SBB32mi8 00513 { "SBB32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(25<<16), EmptyImpUses, EmptyImpDefs }, // Inst #353 = SBB32mr 00514 { "SBB32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #354 = SBB32ri 00515 { "SBB32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #355 = SBB32ri8 00516 { "SBB32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(27<<16), EmptyImpUses, EmptyImpDefs }, // Inst #356 = SBB32rm 00517 { "SBB32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(25<<16), EmptyImpUses, EmptyImpDefs }, // Inst #357 = SBB32rr 00518 { "SBB8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(27<<0)|(3<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #358 = SBB8mi 00519 { "SBB8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(19<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #359 = SBB8ri 00520 { "SETAEm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(147<<16), EmptyImpUses, EmptyImpDefs }, // Inst #360 = SETAEm 00521 { "SETAEr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(147<<16), EmptyImpUses, EmptyImpDefs }, // Inst #361 = SETAEr 00522 { "SETAm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(151<<16), EmptyImpUses, EmptyImpDefs }, // Inst #362 = SETAm 00523 { "SETAr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(151<<16), EmptyImpUses, EmptyImpDefs }, // Inst #363 = SETAr 00524 { "SETBEm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(150<<16), EmptyImpUses, EmptyImpDefs }, // Inst #364 = SETBEm 00525 { "SETBEr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(150<<16), EmptyImpUses, EmptyImpDefs }, // Inst #365 = SETBEr 00526 { "SETBm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(146<<16), EmptyImpUses, EmptyImpDefs }, // Inst #366 = SETBm 00527 { "SETBr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(146<<16), EmptyImpUses, EmptyImpDefs }, // Inst #367 = SETBr 00528 { "SETEm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(148<<16), EmptyImpUses, EmptyImpDefs }, // Inst #368 = SETEm 00529 { "SETEr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(148<<16), EmptyImpUses, EmptyImpDefs }, // Inst #369 = SETEr 00530 { "SETGEm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(157<<16), EmptyImpUses, EmptyImpDefs }, // Inst #370 = SETGEm 00531 { "SETGEr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(157<<16), EmptyImpUses, EmptyImpDefs }, // Inst #371 = SETGEr 00532 { "SETGm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(159<<16), EmptyImpUses, EmptyImpDefs }, // Inst #372 = SETGm 00533 { "SETGr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(159<<16), EmptyImpUses, EmptyImpDefs }, // Inst #373 = SETGr 00534 { "SETLEm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(158<<16), EmptyImpUses, EmptyImpDefs }, // Inst #374 = SETLEm 00535 { "SETLEr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(158<<16), EmptyImpUses, EmptyImpDefs }, // Inst #375 = SETLEr 00536 { "SETLm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(156<<16), EmptyImpUses, EmptyImpDefs }, // Inst #376 = SETLm 00537 { "SETLr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(156<<16), EmptyImpUses, EmptyImpDefs }, // Inst #377 = SETLr 00538 { "SETNEm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(149<<16), EmptyImpUses, EmptyImpDefs }, // Inst #378 = SETNEm 00539 { "SETNEr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(149<<16), EmptyImpUses, EmptyImpDefs }, // Inst #379 = SETNEr 00540 { "SETNSm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(153<<16), EmptyImpUses, EmptyImpDefs }, // Inst #380 = SETNSm 00541 { "SETNSr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(153<<16), EmptyImpUses, EmptyImpDefs }, // Inst #381 = SETNSr 00542 { "SETPm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(154<<16), EmptyImpUses, EmptyImpDefs }, // Inst #382 = SETPm 00543 { "SETPr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(154<<16), EmptyImpUses, EmptyImpDefs }, // Inst #383 = SETPr 00544 { "SETSm", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<6)|(152<<16), EmptyImpUses, EmptyImpDefs }, // Inst #384 = SETSm 00545 { "SETSr", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<6)|(152<<16), EmptyImpUses, EmptyImpDefs }, // Inst #385 = SETSr 00546 { "SHL16mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<5)|(211<<16), SHL16mCLImpUses, EmptyImpDefs }, // Inst #386 = SHL16mCL 00547 { "SHL16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<5)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #387 = SHL16mi 00548 { "SHL16rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<5)|(211<<16), SHL16rCLImpUses, EmptyImpDefs }, // Inst #388 = SHL16rCL 00549 { "SHL16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<5)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #389 = SHL16ri 00550 { "SHL32mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(211<<16), SHL32mCLImpUses, EmptyImpDefs }, // Inst #390 = SHL32mCL 00551 { "SHL32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #391 = SHL32mi 00552 { "SHL32rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(211<<16), SHL32rCLImpUses, EmptyImpDefs }, // Inst #392 = SHL32rCL 00553 { "SHL32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #393 = SHL32ri 00554 { "SHL8mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(210<<16), SHL8mCLImpUses, EmptyImpDefs }, // Inst #394 = SHL8mCL 00555 { "SHL8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(28<<0)|(1<<10)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #395 = SHL8mi 00556 { "SHL8rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(210<<16), SHL8rCLImpUses, EmptyImpDefs }, // Inst #396 = SHL8rCL 00557 { "SHL8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(20<<0)|(1<<10)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #397 = SHL8ri 00558 { "SHLD32mrCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<6)|(165<<16), SHLD32mrCLImpUses, EmptyImpDefs }, // Inst #398 = SHLD32mrCL 00559 { "SHLD32mri8", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<6)|(1<<10)|(164<<16), EmptyImpUses, EmptyImpDefs }, // Inst #399 = SHLD32mri8 00560 { "SHLD32rrCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<6)|(165<<16), SHLD32rrCLImpUses, EmptyImpDefs }, // Inst #400 = SHLD32rrCL 00561 { "SHLD32rri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<6)|(1<<10)|(164<<16), EmptyImpUses, EmptyImpDefs }, // Inst #401 = SHLD32rri8 00562 { "SHR16mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<5)|(211<<16), SHR16mCLImpUses, EmptyImpDefs }, // Inst #402 = SHR16mCL 00563 { "SHR16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<5)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #403 = SHR16mi 00564 { "SHR16rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<5)|(211<<16), SHR16rCLImpUses, EmptyImpDefs }, // Inst #404 = SHR16rCL 00565 { "SHR16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<5)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #405 = SHR16ri 00566 { "SHR32mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(211<<16), SHR32mCLImpUses, EmptyImpDefs }, // Inst #406 = SHR32mCL 00567 { "SHR32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #407 = SHR32mi 00568 { "SHR32rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(211<<16), SHR32rCLImpUses, EmptyImpDefs }, // Inst #408 = SHR32rCL 00569 { "SHR32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<10)|(193<<16), EmptyImpUses, EmptyImpDefs }, // Inst #409 = SHR32ri 00570 { "SHR8mCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(210<<16), SHR8mCLImpUses, EmptyImpDefs }, // Inst #410 = SHR8mCL 00571 { "SHR8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<10)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #411 = SHR8mi 00572 { "SHR8rCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(210<<16), SHR8rCLImpUses, EmptyImpDefs }, // Inst #412 = SHR8rCL 00573 { "SHR8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<10)|(192<<16), EmptyImpUses, EmptyImpDefs }, // Inst #413 = SHR8ri 00574 { "SHRD32mrCL", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<6)|(173<<16), SHRD32mrCLImpUses, EmptyImpDefs }, // Inst #414 = SHRD32mrCL 00575 { "SHRD32mri8", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<6)|(1<<10)|(172<<16), EmptyImpUses, EmptyImpDefs }, // Inst #415 = SHRD32mri8 00576 { "SHRD32rrCL", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<6)|(173<<16), SHRD32rrCLImpUses, EmptyImpDefs }, // Inst #416 = SHRD32rrCL 00577 { "SHRD32rri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<6)|(1<<10)|(172<<16), EmptyImpUses, EmptyImpDefs }, // Inst #417 = SHRD32rri8 00578 { "SUB16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #418 = SUB16mi 00579 { "SUB16mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #419 = SUB16mi8 00580 { "SUB16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(41<<16), EmptyImpUses, EmptyImpDefs }, // Inst #420 = SUB16mr 00581 { "SUB16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #421 = SUB16ri 00582 { "SUB16ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #422 = SUB16ri8 00583 { "SUB16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(43<<16), EmptyImpUses, EmptyImpDefs }, // Inst #423 = SUB16rm 00584 { "SUB16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<5)|(41<<16), EmptyImpUses, EmptyImpDefs }, // Inst #424 = SUB16rr 00585 { "SUB32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #425 = SUB32mi 00586 { "SUB32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #426 = SUB32mi8 00587 { "SUB32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(41<<16), EmptyImpUses, EmptyImpDefs }, // Inst #427 = SUB32mr 00588 { "SUB32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #428 = SUB32ri 00589 { "SUB32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #429 = SUB32ri8 00590 { "SUB32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(43<<16), EmptyImpUses, EmptyImpDefs }, // Inst #430 = SUB32rm 00591 { "SUB32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(41<<16), EmptyImpUses, EmptyImpDefs }, // Inst #431 = SUB32rr 00592 { "SUB8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(29<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #432 = SUB8mi 00593 { "SUB8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(40<<16), EmptyImpUses, EmptyImpDefs }, // Inst #433 = SUB8mr 00594 { "SUB8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(21<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #434 = SUB8ri 00595 { "SUB8rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(42<<16), EmptyImpUses, EmptyImpDefs }, // Inst #435 = SUB8rm 00596 { "SUB8rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(40<<16), EmptyImpUses, EmptyImpDefs }, // Inst #436 = SUB8rr 00597 { "TEST16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<5)|(2<<10)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #437 = TEST16mi 00598 { "TEST16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #438 = TEST16mr 00599 { "TEST16ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<5)|(2<<10)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #439 = TEST16ri 00600 { "TEST16rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #440 = TEST16rm 00601 { "TEST16rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(1<<5)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #441 = TEST16rr 00602 { "TEST32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(3<<10)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #442 = TEST32mi 00603 { "TEST32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #443 = TEST32mr 00604 { "TEST32ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(3<<10)|(247<<16), EmptyImpUses, EmptyImpDefs }, // Inst #444 = TEST32ri 00605 { "TEST32rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #445 = TEST32rm 00606 { "TEST32rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(133<<16), EmptyImpUses, EmptyImpDefs }, // Inst #446 = TEST32rr 00607 { "TEST8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(24<<0)|(1<<10)|(246<<16), EmptyImpUses, EmptyImpDefs }, // Inst #447 = TEST8mi 00608 { "TEST8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(132<<16), EmptyImpUses, EmptyImpDefs }, // Inst #448 = TEST8mr 00609 { "TEST8ri", -1, -1, 0, false, 0, 0, 0, 0, 0|(16<<0)|(1<<10)|(246<<16), EmptyImpUses, EmptyImpDefs }, // Inst #449 = TEST8ri 00610 { "TEST8rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(132<<16), EmptyImpUses, EmptyImpDefs }, // Inst #450 = TEST8rm 00611 { "TEST8rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(132<<16), EmptyImpUses, EmptyImpDefs }, // Inst #451 = TEST8rr 00612 { "XCHG16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #452 = XCHG16mr 00613 { "XCHG16rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(1<<5)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #453 = XCHG16rm 00614 { "XCHG16rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(1<<5)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #454 = XCHG16rr 00615 { "XCHG32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #455 = XCHG32mr 00616 { "XCHG32rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #456 = XCHG32rm 00617 { "XCHG32rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(135<<16), EmptyImpUses, EmptyImpDefs }, // Inst #457 = XCHG32rr 00618 { "XCHG8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(134<<16), EmptyImpUses, EmptyImpDefs }, // Inst #458 = XCHG8mr 00619 { "XCHG8rm", -1, -1, 0, false, 0, 0, 0, 0, 0|(6<<0)|(134<<16), EmptyImpUses, EmptyImpDefs }, // Inst #459 = XCHG8rm 00620 { "XCHG8rr", -1, -1, 0, false, 0, 0, 0, 0, 0|(3<<0)|(134<<16), EmptyImpUses, EmptyImpDefs }, // Inst #460 = XCHG8rr 00621 { "XOR16mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #461 = XOR16mi 00622 { "XOR16mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #462 = XOR16mi8 00623 { "XOR16mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(1<<5)|(49<<16), EmptyImpUses, EmptyImpDefs }, // Inst #463 = XOR16mr 00624 { "XOR16ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(22<<0)|(1<<5)|(2<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #464 = XOR16ri 00625 { "XOR16ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(22<<0)|(1<<5)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #465 = XOR16ri8 00626 { "XOR16rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(1<<5)|(51<<16), EmptyImpUses, EmptyImpDefs }, // Inst #466 = XOR16rm 00627 { "XOR16rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(1<<5)|(49<<16), EmptyImpUses, EmptyImpDefs }, // Inst #467 = XOR16rr 00628 { "XOR32mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #468 = XOR32mi 00629 { "XOR32mi8", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #469 = XOR32mi8 00630 { "XOR32mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(49<<16), EmptyImpUses, EmptyImpDefs }, // Inst #470 = XOR32mr 00631 { "XOR32ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(22<<0)|(3<<10)|(129<<16), EmptyImpUses, EmptyImpDefs }, // Inst #471 = XOR32ri 00632 { "XOR32ri8", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(22<<0)|(1<<10)|(131<<16), EmptyImpUses, EmptyImpDefs }, // Inst #472 = XOR32ri8 00633 { "XOR32rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(51<<16), EmptyImpUses, EmptyImpDefs }, // Inst #473 = XOR32rm 00634 { "XOR32rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(49<<16), EmptyImpUses, EmptyImpDefs }, // Inst #474 = XOR32rr 00635 { "XOR8mi", -1, -1, 0, false, 0, 0, 0, 0, 0|(30<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #475 = XOR8mi 00636 { "XOR8mr", -1, -1, 0, false, 0, 0, 0, 0, 0|(4<<0)|(48<<16), EmptyImpUses, EmptyImpDefs }, // Inst #476 = XOR8mr 00637 { "XOR8ri", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(22<<0)|(1<<10)|(128<<16), EmptyImpUses, EmptyImpDefs }, // Inst #477 = XOR8ri 00638 { "XOR8rm", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(6<<0)|(50<<16), EmptyImpUses, EmptyImpDefs }, // Inst #478 = XOR8rm 00639 { "XOR8rr", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0|(3<<0)|(48<<16), EmptyImpUses, EmptyImpDefs }, // Inst #479 = XOR8rr 00640 }; 00641 } // End llvm namespace