LLVM API Documentation
00001 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the X86 implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef X86INSTRUCTIONINFO_H 00015 #define X86INSTRUCTIONINFO_H 00016 00017 #include "llvm/Target/TargetInstrInfo.h" 00018 #include "X86RegisterInfo.h" 00019 00020 namespace llvm { 00021 00022 /// X86II - This namespace holds all of the target specific flags that 00023 /// instruction info tracks. 00024 /// 00025 namespace X86II { 00026 enum { 00027 //===------------------------------------------------------------------===// 00028 // Instruction types. These are the standard/most common forms for X86 00029 // instructions. 00030 // 00031 00032 // PseudoFrm - This represents an instruction that is a pseudo instruction 00033 // or one that has not been implemented yet. It is illegal to code generate 00034 // it, but tolerated for intermediate implementation stages. 00035 Pseudo = 0, 00036 00037 /// Raw - This form is for instructions that don't have any operands, so 00038 /// they are just a fixed opcode value, like 'leave'. 00039 RawFrm = 1, 00040 00041 /// AddRegFrm - This form is used for instructions like 'push r32' that have 00042 /// their one register operand added to their opcode. 00043 AddRegFrm = 2, 00044 00045 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 00046 /// to specify a destination, which in this case is a register. 00047 /// 00048 MRMDestReg = 3, 00049 00050 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 00051 /// to specify a destination, which in this case is memory. 00052 /// 00053 MRMDestMem = 4, 00054 00055 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 00056 /// to specify a source, which in this case is a register. 00057 /// 00058 MRMSrcReg = 5, 00059 00060 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 00061 /// to specify a source, which in this case is memory. 00062 /// 00063 MRMSrcMem = 6, 00064 00065 /// MRM[0-7][rm] - These forms are used to represent instructions that use 00066 /// a Mod/RM byte, and use the middle field to hold extended opcode 00067 /// information. In the intel manual these are represented as /0, /1, ... 00068 /// 00069 00070 // First, instructions that operate on a register r/m operand... 00071 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 00072 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 00073 00074 // Next, instructions that operate on a memory r/m operand... 00075 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 00076 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 00077 00078 FormMask = 31, 00079 00080 //===------------------------------------------------------------------===// 00081 // Actual flags... 00082 00083 // OpSize - Set if this instruction requires an operand size prefix (0x66), 00084 // which most often indicates that the instruction operates on 16 bit data 00085 // instead of 32 bit data. 00086 OpSize = 1 << 5, 00087 00088 // Op0Mask - There are several prefix bytes that are used to form two byte 00089 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 00090 // used to obtain the setting of this field. If no bits in this field is 00091 // set, there is no prefix byte for obtaining a multibyte opcode. 00092 // 00093 Op0Shift = 6, 00094 Op0Mask = 0xF << Op0Shift, 00095 00096 // TB - TwoByte - Set if this instruction has a two byte opcode, which 00097 // starts with a 0x0F byte before the real opcode. 00098 TB = 1 << Op0Shift, 00099 00100 // REP - The 0xF3 prefix byte indicating repetition of the following 00101 // instruction. 00102 REP = 2 << Op0Shift, 00103 00104 // D8-DF - These escape opcodes are used by the floating point unit. These 00105 // values must remain sequential. 00106 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 00107 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 00108 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 00109 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 00110 00111 //===------------------------------------------------------------------===// 00112 // This two-bit field describes the size of an immediate operand. Zero is 00113 // unused so that we can tell if we forgot to set a value. 00114 ImmShift = 10, 00115 ImmMask = 7 << ImmShift, 00116 Imm8 = 1 << ImmShift, 00117 Imm16 = 2 << ImmShift, 00118 Imm32 = 3 << ImmShift, 00119 00120 //===------------------------------------------------------------------===// 00121 // FP Instruction Classification... Zero is non-fp instruction. 00122 00123 // FPTypeMask - Mask for all of the FP types... 00124 FPTypeShift = 12, 00125 FPTypeMask = 7 << FPTypeShift, 00126 00127 // NotFP - The default, set for instructions that do not use FP registers. 00128 NotFP = 0 << FPTypeShift, 00129 00130 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 00131 ZeroArgFP = 1 << FPTypeShift, 00132 00133 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 00134 OneArgFP = 2 << FPTypeShift, 00135 00136 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 00137 // result back to ST(0). For example, fcos, fsqrt, etc. 00138 // 00139 OneArgFPRW = 3 << FPTypeShift, 00140 00141 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 00142 // explicit argument, storing the result to either ST(0) or the implicit 00143 // argument. For example: fadd, fsub, fmul, etc... 00144 TwoArgFP = 4 << FPTypeShift, 00145 00146 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 00147 // explicit argument, but have no destination. Example: fucom, fucomi, ... 00148 CompareFP = 5 << FPTypeShift, 00149 00150 // CondMovFP - "2 operand" floating point conditional move instructions. 00151 CondMovFP = 6 << FPTypeShift, 00152 00153 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 00154 SpecialFP = 7 << FPTypeShift, 00155 00156 // Bit 15 is unused. 00157 OpcodeShift = 16, 00158 OpcodeMask = 0xFF << OpcodeShift, 00159 // Bits 24 -> 31 are unused 00160 }; 00161 } 00162 00163 class X86InstrInfo : public TargetInstrInfo { 00164 const X86RegisterInfo RI; 00165 public: 00166 X86InstrInfo(); 00167 00168 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 00169 /// such, whenever a client has an instance of instruction info, it should 00170 /// always be able to get register info as well (through this method). 00171 /// 00172 virtual const MRegisterInfo &getRegisterInfo() const { return RI; } 00173 00174 // 00175 // Return true if the instruction is a register to register move and 00176 // leave the source and dest operands in the passed parameters. 00177 // 00178 virtual bool isMoveInstr(const MachineInstr& MI, 00179 unsigned& sourceReg, 00180 unsigned& destReg) const; 00181 00182 /// Insert a goto (unconditional branch) sequence to TMBB, at the 00183 /// end of MBB 00184 virtual void insertGoto(MachineBasicBlock& MBB, 00185 MachineBasicBlock& TMBB) const; 00186 00187 /// Reverses the branch condition of the MachineInstr pointed by 00188 /// MI. The instruction is replaced and the new MI is returned. 00189 virtual MachineBasicBlock::iterator 00190 reverseBranchCondition(MachineBasicBlock::iterator MI) const; 00191 00192 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 00193 // specified opcode number. 00194 // 00195 unsigned char getBaseOpcodeFor(unsigned Opcode) const { 00196 return get(Opcode).TSFlags >> X86II::OpcodeShift; 00197 } 00198 }; 00199 00200 } // End llvm namespace 00201 00202 #endif