LLVM API Documentation

Main Page | Namespace List | Class Hierarchy | Alphabetical List | Class List | Directories | File List | Namespace Members | Class Members | File Members | Related Pages

X86InstrInfo.cpp

Go to the documentation of this file.
00001 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
00002 // 
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 // 
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "X86InstrInfo.h"
00015 #include "X86.h"
00016 #include "llvm/CodeGen/MachineInstrBuilder.h"
00017 #include "X86GenInstrInfo.inc"
00018 using namespace llvm;
00019 
00020 X86InstrInfo::X86InstrInfo()
00021   : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
00022 }
00023 
00024 
00025 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
00026                                unsigned& sourceReg,
00027                                unsigned& destReg) const {
00028   MachineOpCode oc = MI.getOpcode();
00029   if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
00030       oc == X86::FpMOV) {
00031       assert(MI.getNumOperands() == 2 &&
00032              MI.getOperand(0).isRegister() &&
00033              MI.getOperand(1).isRegister() &&
00034              "invalid register-register move instruction");
00035       sourceReg = MI.getOperand(1).getReg();
00036       destReg = MI.getOperand(0).getReg();
00037       return true;
00038   }
00039   return false;
00040 }
00041 
00042 void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
00043                               MachineBasicBlock& TMBB) const {
00044   BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
00045 }
00046 
00047 MachineBasicBlock::iterator
00048 X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
00049   unsigned Opcode = MI->getOpcode();
00050   assert(isBranch(Opcode) && "MachineInstr must be a branch");
00051   unsigned ROpcode;
00052   switch (Opcode) {
00053   default: assert(0 && "Cannot reverse unconditional branches!");
00054   case X86::JB:  ROpcode = X86::JAE; break;
00055   case X86::JAE: ROpcode = X86::JB;  break;
00056   case X86::JE:  ROpcode = X86::JNE; break;
00057   case X86::JNE: ROpcode = X86::JE;  break;
00058   case X86::JBE: ROpcode = X86::JA;  break;
00059   case X86::JA:  ROpcode = X86::JBE; break;
00060   case X86::JS:  ROpcode = X86::JNS; break;
00061   case X86::JNS: ROpcode = X86::JS;  break;
00062   case X86::JL:  ROpcode = X86::JGE; break;
00063   case X86::JGE: ROpcode = X86::JL;  break;
00064   case X86::JLE: ROpcode = X86::JG;  break;
00065   case X86::JG:  ROpcode = X86::JLE; break;
00066   }
00067   MachineBasicBlock* MBB = MI->getParent();
00068   MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
00069   return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
00070 }