LLVM API Documentation
00001 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file describes an abstract interface used to get information about a 00011 // target machines register file. This information is used for a variety of 00012 // purposed, especially register allocation. 00013 // 00014 //===----------------------------------------------------------------------===// 00015 00016 #ifndef LLVM_TARGET_MREGISTERINFO_H 00017 #define LLVM_TARGET_MREGISTERINFO_H 00018 00019 #include "llvm/CodeGen/MachineBasicBlock.h" 00020 #include <cassert> 00021 #include <functional> 00022 00023 namespace llvm { 00024 00025 class Type; 00026 class MachineFunction; 00027 class MachineInstr; 00028 00029 /// MRegisterDesc - This record contains all of the information known about a 00030 /// particular register. The AliasSet field (if not null) contains a pointer to 00031 /// a Zero terminated array of registers that this register aliases. This is 00032 /// needed for architectures like X86 which have AL alias AX alias EAX. 00033 /// Registers that this does not apply to simply should set this to null. 00034 /// 00035 struct MRegisterDesc { 00036 const char *Name; // Assembly language name for the register 00037 const unsigned *AliasSet; // Register Alias Set, described above 00038 unsigned char SpillSize; // Size of this register in bytes 00039 unsigned char SpillAlignment; // Alignment of stack slot for this reg 00040 }; 00041 00042 class TargetRegisterClass { 00043 public: 00044 typedef const unsigned* iterator; 00045 typedef const unsigned* const_iterator; 00046 00047 private: 00048 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 00049 const iterator RegsBegin, RegsEnd; 00050 public: 00051 TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE) 00052 : RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {} 00053 virtual ~TargetRegisterClass() {} // Allow subclasses 00054 00055 // begin/end - Return all of the registers in this class. 00056 iterator begin() const { return RegsBegin; } 00057 iterator end() const { return RegsEnd; } 00058 00059 // getNumRegs - Return the number of registers in this class 00060 unsigned getNumRegs() const { return RegsEnd-RegsBegin; } 00061 00062 // getRegister - Return the specified register in the class 00063 unsigned getRegister(unsigned i) const { 00064 assert(i < getNumRegs() && "Register number out of range!"); 00065 return RegsBegin[i]; 00066 } 00067 00068 /// contains - Return true if the specified register is included in this 00069 /// register class. 00070 bool contains(unsigned Reg) const { 00071 for (iterator I = begin(), E = end(); I != E; ++I) 00072 if (*I == Reg) return true; 00073 return false; 00074 } 00075 00076 /// allocation_order_begin/end - These methods define a range of registers 00077 /// which specify the registers in this class that are valid to register 00078 /// allocate, and the preferred order to allocate them in. For example, 00079 /// callee saved registers should be at the end of the list, because it is 00080 /// cheaper to allocate caller saved registers. 00081 /// 00082 /// These methods take a MachineFunction argument, which can be used to tune 00083 /// the allocatable registers based on the characteristics of the function. 00084 /// One simple example is that the frame pointer register can be used if 00085 /// frame-pointer-elimination is performed. 00086 /// 00087 /// By default, these methods return all registers in the class. 00088 /// 00089 virtual iterator allocation_order_begin(MachineFunction &MF) const { 00090 return begin(); 00091 } 00092 virtual iterator allocation_order_end(MachineFunction &MF) const { 00093 return end(); 00094 } 00095 00096 00097 00098 /// getSize - Return the size of the register in bytes, which is also the size 00099 /// of a stack slot allocated to hold a spilled copy of this register. 00100 unsigned getSize() const { return RegSize; } 00101 00102 /// getAlignment - Return the minimum required alignment for a register of 00103 /// this class. 00104 unsigned getAlignment() const { return Alignment; } 00105 }; 00106 00107 00108 /// MRegisterInfo base class - We assume that the target defines a static array 00109 /// of MRegisterDesc objects that represent all of the machine registers that 00110 /// the target has. As such, we simply have to track a pointer to this array so 00111 /// that we can turn register number into a register descriptor. 00112 /// 00113 class MRegisterInfo { 00114 public: 00115 typedef const TargetRegisterClass * const * regclass_iterator; 00116 private: 00117 const MRegisterDesc *Desc; // Pointer to the descriptor array 00118 unsigned NumRegs; // Number of entries in the array 00119 00120 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 00121 00122 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 00123 protected: 00124 MRegisterInfo(const MRegisterDesc *D, unsigned NR, 00125 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, 00126 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1); 00127 virtual ~MRegisterInfo(); 00128 public: 00129 00130 enum { // Define some target independent constants 00131 /// NoRegister - This 'hard' register is a 'noop' register for all backends. 00132 /// This is used as the destination register for instructions that do not 00133 /// produce a value. Some frontends may use this as an operand register to 00134 /// mean special things, for example, the Sparc backend uses R0 to mean %g0 00135 /// which always PRODUCES the value 0. The X86 backend does not use this 00136 /// value as an operand register, except for memory references. 00137 /// 00138 NoRegister = 0, 00139 00140 /// FirstVirtualRegister - This is the first register number that is 00141 /// considered to be a 'virtual' register, which is part of the SSA 00142 /// namespace. This must be the same for all targets, which means that each 00143 /// target is limited to 1024 registers. 00144 /// 00145 FirstVirtualRegister = 1024, 00146 }; 00147 00148 /// isPhysicalRegister - Return true if the specified register number is in 00149 /// the physical register namespace. 00150 static bool isPhysicalRegister(unsigned Reg) { 00151 assert(Reg && "this is not a register!"); 00152 return Reg < FirstVirtualRegister; 00153 } 00154 00155 /// isVirtualRegister - Return true if the specified register number is in 00156 /// the virtual register namespace. 00157 static bool isVirtualRegister(unsigned Reg) { 00158 assert(Reg && "this is not a register!"); 00159 return Reg >= FirstVirtualRegister; 00160 } 00161 00162 /// getAllocatableSet - Returns a bitset indexed by register number 00163 /// indicating if a register is allocatable or not. 00164 std::vector<bool> getAllocatableSet(MachineFunction &MF) const; 00165 00166 const MRegisterDesc &operator[](unsigned RegNo) const { 00167 assert(RegNo < NumRegs && 00168 "Attempting to access record for invalid register number!"); 00169 return Desc[RegNo]; 00170 } 00171 00172 /// Provide a get method, equivalent to [], but more useful if we have a 00173 /// pointer to this object. 00174 /// 00175 const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); } 00176 00177 /// getAliasSet - Return the set of registers aliased by the specified 00178 /// register, or a null list of there are none. The list returned is zero 00179 /// terminated. 00180 /// 00181 const unsigned *getAliasSet(unsigned RegNo) const { 00182 return get(RegNo).AliasSet; 00183 } 00184 00185 /// getName - Return the symbolic target specific name for the specified 00186 /// physical register. 00187 const char *getName(unsigned RegNo) const { 00188 return get(RegNo).Name; 00189 } 00190 00191 /// getSpillSize - Return the size in bits required of a stack slot used to 00192 /// spill register into. 00193 unsigned getSpillSize(unsigned RegNo) const { 00194 return get(RegNo).SpillSize; 00195 } 00196 00197 /// getSpillAlignment - Return the alignment required by a stack slot used to 00198 /// spill register into. 00199 unsigned getSpillAlignment(unsigned RegNo) const { 00200 return get(RegNo).SpillAlignment; 00201 } 00202 00203 /// getNumRegs - Return the number of registers this target has 00204 /// (useful for sizing arrays holding per register information) 00205 unsigned getNumRegs() const { 00206 return NumRegs; 00207 } 00208 00209 /// areAliases - Returns true if the two registers alias each other, 00210 /// false otherwise 00211 bool areAliases(unsigned regA, unsigned regB) const { 00212 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) 00213 if (*Alias == regB) return true; 00214 return false; 00215 } 00216 00217 virtual const unsigned* getCalleeSaveRegs() const = 0; 00218 00219 00220 //===--------------------------------------------------------------------===// 00221 // Register Class Information 00222 // 00223 00224 /// Register class iterators 00225 /// 00226 regclass_iterator regclass_begin() const { return RegClassBegin; } 00227 regclass_iterator regclass_end() const { return RegClassEnd; } 00228 00229 unsigned getNumRegClasses() const { 00230 return regclass_end()-regclass_begin(); 00231 } 00232 00233 //===--------------------------------------------------------------------===// 00234 // Interfaces used by the register allocator and stack frame 00235 // manipulation passes to move data around between registers, 00236 // immediates and memory. The return value is the number of 00237 // instructions added to (negative if removed from) the basic block. 00238 // 00239 00240 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 00241 MachineBasicBlock::iterator MI, 00242 unsigned SrcReg, int FrameIndex) const = 0; 00243 00244 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 00245 MachineBasicBlock::iterator MI, 00246 unsigned DestReg, int FrameIndex) const = 0; 00247 00248 virtual void copyRegToReg(MachineBasicBlock &MBB, 00249 MachineBasicBlock::iterator MI, 00250 unsigned DestReg, unsigned SrcReg, 00251 const TargetRegisterClass *RC) const = 0; 00252 00253 00254 /// foldMemoryOperand - Attempt to fold a load or store of the 00255 /// specified stack slot into the specified machine instruction for 00256 /// the specified operand. If this is possible, a new instruction 00257 /// is returned with the specified operand folded, otherwise NULL is 00258 /// returned. The client is responsible for removing the old 00259 /// instruction and adding the new one in the instruction stream 00260 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 00261 unsigned OpNum, 00262 int FrameIndex) const { 00263 return 0; 00264 } 00265 00266 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 00267 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 00268 /// targets use pseudo instructions in order to abstract away the difference 00269 /// between operating with a frame pointer and operating without, through the 00270 /// use of these two instructions. 00271 /// 00272 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 00273 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 00274 00275 00276 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 00277 /// code insertion to eliminate call frame setup and destroy pseudo 00278 /// instructions (but only if the Target is using them). It is responsible 00279 /// for eliminating these instructions, replacing them with concrete 00280 /// instructions. This method need only be implemented if using call frame 00281 /// setup/destroy pseudo instructions. 00282 /// 00283 virtual void 00284 eliminateCallFramePseudoInstr(MachineFunction &MF, 00285 MachineBasicBlock &MBB, 00286 MachineBasicBlock::iterator MI) const { 00287 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 00288 "eliminateCallFramePseudoInstr must be implemented if using" 00289 " call frame setup/destroy pseudo instructions!"); 00290 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 00291 } 00292 00293 /// processFunctionBeforeFrameFinalized - This method is called immediately 00294 /// before the specified functions frame layout (MF.getFrameInfo()) is 00295 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 00296 /// replaced with direct constants. This method is optional. The return value 00297 /// is the number of instructions added to (negative if removed from) the 00298 /// basic block 00299 /// 00300 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 00301 } 00302 00303 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 00304 /// frame indices from instructions which may use them. The instruction 00305 /// referenced by the iterator contains an MO_FrameIndex operand which must be 00306 /// eliminated by this method. This method may modify or replace the 00307 /// specified instruction, as long as it keeps the iterator pointing the the 00308 /// finished product. The return value is the number of instructions 00309 /// added to (negative if removed from) the basic block. 00310 /// 00311 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0; 00312 00313 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 00314 /// the function. The return value is the number of instructions 00315 /// added to (negative if removed from) the basic block (entry for prologue). 00316 /// 00317 virtual void emitPrologue(MachineFunction &MF) const = 0; 00318 virtual void emitEpilogue(MachineFunction &MF, 00319 MachineBasicBlock &MBB) const = 0; 00320 }; 00321 00322 // This is useful when building DenseMaps keyed on virtual registers 00323 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 00324 unsigned operator()(unsigned Reg) const { 00325 return Reg - MRegisterInfo::FirstVirtualRegister; 00326 } 00327 }; 00328 00329 } // End llvm namespace 00330 00331 #endif