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PPC32GenInstrInfo.inc

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00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===//
00002 //
00003 // Target Instruction Descriptors
00004 //
00005 // Automatically generated file, do not edit!
00006 //
00007 //===----------------------------------------------------------------------===//
00008 
00009 namespace llvm {
00010 
00011 static const unsigned EmptyImpUses[] = { 0 };
00012 static const unsigned EmptyImpDefs[] = { 0 };
00013 static const unsigned CALLindirectImpDefs[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::LR, PPC::XER, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
00014 static const unsigned CALLpcrelImpDefs[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::LR, PPC::XER, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
00015 
00016 static const TargetInstrDescriptor PPC32Insts[] = {
00017   { "PHI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #0 = PHI
00018   { "ADD",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #1 = ADD
00019   { "ADDC", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #2 = ADDC
00020   { "ADDE", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #3 = ADDE
00021   { "ADDI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #4 = ADDI
00022   { "ADDIC",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #5 = ADDIC
00023   { "ADDICo", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #6 = ADDICo
00024   { "ADDIS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #7 = ADDIS
00025   { "ADDME",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #8 = ADDME
00026   { "ADDZE",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #9 = ADDZE
00027   { "ADJCALLSTACKDOWN", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #10 = ADJCALLSTACKDOWN
00028   { "ADJCALLSTACKUP", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #11 = ADJCALLSTACKUP
00029   { "AND",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #12 = AND
00030   { "ANDC", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #13 = ANDC
00031   { "ANDISo", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #14 = ANDISo
00032   { "ANDIo",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #15 = ANDIo
00033   { "B",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #16 = B
00034   { "BCTR", -1, -1, 0, false, 0, 0, 0, 0|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #17 = BCTR
00035   { "BEQ",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #18 = BEQ
00036   { "BGE",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #19 = BGE
00037   { "BGT",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #20 = BGT
00038   { "BL", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #21 = BL
00039   { "BLE",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #22 = BLE
00040   { "BLR",  -1, -1, 0, false, 0, 0, 0, 0|M_RET_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #23 = BLR
00041   { "BLT",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #24 = BLT
00042   { "BNE",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #25 = BNE
00043   { "CALLindirect", -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, CALLindirectImpDefs  },  // Inst #26 = CALLindirect
00044   { "CALLpcrel",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_CALL_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, CALLpcrelImpDefs  },  // Inst #27 = CALLpcrel
00045   { "CMP",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #28 = CMP
00046   { "CMPD", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #29 = CMPD
00047   { "CMPDI",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #30 = CMPDI
00048   { "CMPI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #31 = CMPI
00049   { "CMPL", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #32 = CMPL
00050   { "CMPLD",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #33 = CMPLD
00051   { "CMPLDI", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #34 = CMPLDI
00052   { "CMPLI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #35 = CMPLI
00053   { "CMPLW",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #36 = CMPLW
00054   { "CMPLWI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #37 = CMPLWI
00055   { "CMPW", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #38 = CMPW
00056   { "CMPWI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #39 = CMPWI
00057   { "CNTLZW", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #40 = CNTLZW
00058   { "COND_BRANCH",  -1, -1, 0, false, 0, 0, 0, 0|M_BRANCH_FLAG|M_TERMINATOR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #41 = COND_BRANCH
00059   { "CRAND",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #42 = CRAND
00060   { "CRANDC", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #43 = CRANDC
00061   { "CRNOR",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #44 = CRNOR
00062   { "CROR", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #45 = CROR
00063   { "DIVD", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #46 = DIVD
00064   { "DIVDU",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #47 = DIVDU
00065   { "DIVW", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #48 = DIVW
00066   { "DIVWU",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #49 = DIVWU
00067   { "EQV",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #50 = EQV
00068   { "EXTSB",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #51 = EXTSB
00069   { "EXTSH",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #52 = EXTSH
00070   { "EXTSW",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #53 = EXTSW
00071   { "FADD", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #54 = FADD
00072   { "FADDS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #55 = FADDS
00073   { "FCFID",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #56 = FCFID
00074   { "FCMPU",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #57 = FCMPU
00075   { "FCTIDZ", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #58 = FCTIDZ
00076   { "FCTIWZ", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #59 = FCTIWZ
00077   { "FDIV", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #60 = FDIV
00078   { "FDIVS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #61 = FDIVS
00079   { "FMADD",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #62 = FMADD
00080   { "FMR",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #63 = FMR
00081   { "FMUL", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #64 = FMUL
00082   { "FMULS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #65 = FMULS
00083   { "FNEG", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #66 = FNEG
00084   { "FRSP", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #67 = FRSP
00085   { "FSEL", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #68 = FSEL
00086   { "FSUB", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #69 = FSUB
00087   { "FSUBS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #70 = FSUBS
00088   { "IMPLICIT_DEF", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #71 = IMPLICIT_DEF
00089   { "LA", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #72 = LA
00090   { "LBZ",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #73 = LBZ
00091   { "LBZX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #74 = LBZX
00092   { "LD", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #75 = LD
00093   { "LDX",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #76 = LDX
00094   { "LFD",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #77 = LFD
00095   { "LFDX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #78 = LFDX
00096   { "LFS",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #79 = LFS
00097   { "LFSX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #80 = LFSX
00098   { "LHA",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #81 = LHA
00099   { "LHAX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #82 = LHAX
00100   { "LHZ",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #83 = LHZ
00101   { "LHZX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #84 = LHZX
00102   { "LI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #85 = LI
00103   { "LIS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #86 = LIS
00104   { "LMW",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #87 = LMW
00105   { "LOADHiAddr", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #88 = LOADHiAddr
00106   { "LWA",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #89 = LWA
00107   { "LWAX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #90 = LWAX
00108   { "LWZ",  -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #91 = LWZ
00109   { "LWZU", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #92 = LWZU
00110   { "LWZX", -1, -1, 0, false, 0, 0, 0, 0|M_LOAD_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #93 = LWZX
00111   { "MFCR", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #94 = MFCR
00112   { "MFCTR",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #95 = MFCTR
00113   { "MFLR", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #96 = MFLR
00114   { "MTCTR",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #97 = MTCTR
00115   { "MTLR", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #98 = MTLR
00116   { "MULHWU", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #99 = MULHWU
00117   { "MULLD",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #100 = MULLD
00118   { "MULLI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #101 = MULLI
00119   { "MULLW",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #102 = MULLW
00120   { "MovePCtoLR", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #103 = MovePCtoLR
00121   { "NAND", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #104 = NAND
00122   { "NEG",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #105 = NEG
00123   { "NOP",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #106 = NOP
00124   { "NOR",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #107 = NOR
00125   { "OR", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #108 = OR
00126   { "ORC",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #109 = ORC
00127   { "ORI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #110 = ORI
00128   { "ORIS", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #111 = ORIS
00129   { "ORo",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #112 = ORo
00130   { "RLDICL", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #113 = RLDICL
00131   { "RLDICR", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #114 = RLDICR
00132   { "RLWIMI", -1, -1, 0, false, 0, 0, 0, 0|M_2_ADDR_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #115 = RLWIMI
00133   { "RLWINM", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #116 = RLWINM
00134   { "SLD",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #117 = SLD
00135   { "SLW",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #118 = SLW
00136   { "SRAD", -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #119 = SRAD
00137   { "SRADI",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #120 = SRADI
00138   { "SRAW", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #121 = SRAW
00139   { "SRAWI",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #122 = SRAWI
00140   { "SRD",  -1, -1, 0, false, 0, 0, 0, 0, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #123 = SRD
00141   { "SRW",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #124 = SRW
00142   { "STB",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #125 = STB
00143   { "STBX", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #126 = STBX
00144   { "STD",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #127 = STD
00145   { "STDU", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #128 = STDU
00146   { "STDUX",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #129 = STDUX
00147   { "STDX", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0|(1<<1), EmptyImpUses, EmptyImpDefs  },  // Inst #130 = STDX
00148   { "STFD", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #131 = STFD
00149   { "STFDX",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #132 = STFDX
00150   { "STFS", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #133 = STFS
00151   { "STFSX",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #134 = STFSX
00152   { "STH",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #135 = STH
00153   { "STHX", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #136 = STHX
00154   { "STMW", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #137 = STMW
00155   { "STW",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #138 = STW
00156   { "STWU", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #139 = STWU
00157   { "STWUX",  -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #140 = STWUX
00158   { "STWX", -1, -1, 0, false, 0, 0, 0, 0|M_STORE_FLAG, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #141 = STWX
00159   { "SUB",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #142 = SUB
00160   { "SUBC", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #143 = SUBC
00161   { "SUBF", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #144 = SUBF
00162   { "SUBFC",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #145 = SUBFC
00163   { "SUBFE",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #146 = SUBFE
00164   { "SUBFIC", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #147 = SUBFIC
00165   { "SUBFZE", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #148 = SUBFZE
00166   { "XOR",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #149 = XOR
00167   { "XORI", -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #150 = XORI
00168   { "XORIS",  -1, -1, 0, false, 0, 0, 0, 0, 0, EmptyImpUses, EmptyImpDefs  },  // Inst #151 = XORIS
00169 };
00170 } // End llvm namespace