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X86RegisterInfo.cpp

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00001 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file was developed by the LLVM research group and is distributed under
00006 // the University of Illinois Open Source License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of the MRegisterInfo class.  This
00011 // file is responsible for the frame pointer elimination optimization on X86.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "X86.h"
00016 #include "X86RegisterInfo.h"
00017 #include "X86InstrBuilder.h"
00018 #include "llvm/Constants.h"
00019 #include "llvm/Type.h"
00020 #include "llvm/CodeGen/ValueTypes.h"
00021 #include "llvm/CodeGen/MachineInstrBuilder.h"
00022 #include "llvm/CodeGen/MachineFunction.h"
00023 #include "llvm/CodeGen/MachineFrameInfo.h"
00024 #include "llvm/Target/TargetFrameInfo.h"
00025 #include "llvm/Target/TargetMachine.h"
00026 #include "llvm/Target/TargetOptions.h"
00027 #include "llvm/Support/CommandLine.h"
00028 #include "llvm/ADT/STLExtras.h"
00029 #include <iostream>
00030 
00031 using namespace llvm;
00032 
00033 namespace {
00034   cl::opt<bool>
00035   NoFusing("disable-spill-fusing",
00036            cl::desc("Disable fusing of spill code into instructions"));
00037   cl::opt<bool>
00038   PrintFailedFusing("print-failed-fuse-candidates",
00039                     cl::desc("Print instructions that the allocator wants to"
00040                              " fuse, but the X86 backend currently can't"),
00041                     cl::Hidden);
00042 }
00043 
00044 X86RegisterInfo::X86RegisterInfo()
00045   : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
00046 
00047 static unsigned getIdx(unsigned SpillSize) {
00048   switch (SpillSize) {
00049   default: assert(0 && "Invalid data size!");
00050   case 8:  return 0;
00051   case 16: return 1;
00052   case 32: return 2;
00053   case 64: return 3;   // FP in 64-bit spill mode.
00054   case 80: return 4;   // FP in 80-bit spill mode.
00055   }
00056 }
00057 
00058 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
00059                                           MachineBasicBlock::iterator MI,
00060                                           unsigned SrcReg, int FrameIdx) const {
00061   static const unsigned Opcode[] =
00062     { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST64m, X86::FSTP80m };
00063   unsigned Idx = getIdx(getSpillSize(SrcReg));
00064   addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 5), FrameIdx).addReg(SrcReg);
00065 }
00066 
00067 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
00068                                            MachineBasicBlock::iterator MI,
00069                                            unsigned DestReg, int FrameIdx)const{
00070   static const unsigned Opcode[] =
00071     { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD64m, X86::FLD80m };
00072   unsigned Idx = getIdx(getSpillSize(DestReg));
00073   addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 4, DestReg), FrameIdx);
00074 }
00075 
00076 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
00077                                    MachineBasicBlock::iterator MI,
00078                                    unsigned DestReg, unsigned SrcReg,
00079                                    const TargetRegisterClass *RC) const {
00080   static const unsigned Opcode[] =
00081     { X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::FpMOV };
00082   BuildMI(MBB, MI, Opcode[getIdx(RC->getSize()*8)], 1, DestReg).addReg(SrcReg);
00083 }
00084 
00085 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
00086                                MachineInstr *MI) {
00087   return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
00088 }
00089 
00090 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
00091                                 MachineInstr *MI) {
00092   return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
00093                  .addReg(MI->getOperand(1).getReg());
00094 }
00095 
00096 static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
00097                                  MachineInstr *MI) {
00098   return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
00099       .addReg(MI->getOperand(1).getReg())
00100       .addZImm(MI->getOperand(2).getImmedValue());
00101 }
00102 
00103 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
00104                                 MachineInstr *MI) {
00105   if (MI->getOperand(1).isImmediate())
00106     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
00107       .addZImm(MI->getOperand(1).getImmedValue());
00108   else if (MI->getOperand(1).isGlobalAddress())
00109     return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
00110       .addGlobalAddress(MI->getOperand(1).getGlobal());
00111   assert(0 && "Unknown operand for MakeMI!");
00112   return 0;
00113 }
00114 
00115 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
00116                                 MachineInstr *MI) {
00117   const MachineOperand& op = MI->getOperand(0);
00118   return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
00119                            FrameIndex);
00120 }
00121 
00122 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
00123                                  MachineInstr *MI) {
00124   const MachineOperand& op = MI->getOperand(0);
00125   return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
00126                         FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
00127 }
00128 
00129 
00130 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
00131                                                  unsigned i,
00132                                                  int FrameIndex) const {
00133   if (NoFusing) return NULL;
00134 
00135   /// FIXME: This should obviously be autogenerated by tablegen when patterns
00136   /// are available!
00137   MachineBasicBlock& MBB = *MI->getParent();
00138   if (i == 0) {
00139     switch(MI->getOpcode()) {
00140     case X86::XCHG8rr:   return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
00141     case X86::XCHG16rr:  return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
00142     case X86::XCHG32rr:  return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
00143     case X86::MOV8rr:    return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
00144     case X86::MOV16rr:   return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
00145     case X86::MOV32rr:   return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
00146     case X86::MOV8ri:    return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
00147     case X86::MOV16ri:   return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
00148     case X86::MOV32ri:   return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
00149     case X86::MUL8r:     return MakeMInst( X86::MUL8m ,  FrameIndex, MI);
00150     case X86::MUL16r:    return MakeMInst( X86::MUL16m,  FrameIndex, MI);
00151     case X86::MUL32r:    return MakeMInst( X86::MUL32m,  FrameIndex, MI);
00152     case X86::DIV8r:     return MakeMInst( X86::DIV8m ,  FrameIndex, MI);
00153     case X86::DIV16r:    return MakeMInst( X86::DIV16m,  FrameIndex, MI);
00154     case X86::DIV32r:    return MakeMInst( X86::DIV32m,  FrameIndex, MI);
00155     case X86::IDIV8r:    return MakeMInst( X86::IDIV8m , FrameIndex, MI);
00156     case X86::IDIV16r:   return MakeMInst( X86::IDIV16m, FrameIndex, MI);
00157     case X86::IDIV32r:   return MakeMInst( X86::IDIV32m, FrameIndex, MI);
00158     case X86::NEG8r:     return MakeMInst( X86::NEG8m ,  FrameIndex, MI);
00159     case X86::NEG16r:    return MakeMInst( X86::NEG16m,  FrameIndex, MI);
00160     case X86::NEG32r:    return MakeMInst( X86::NEG32m,  FrameIndex, MI);
00161     case X86::NOT8r:     return MakeMInst( X86::NOT8m ,  FrameIndex, MI);
00162     case X86::NOT16r:    return MakeMInst( X86::NOT16m,  FrameIndex, MI);
00163     case X86::NOT32r:    return MakeMInst( X86::NOT32m,  FrameIndex, MI);
00164     case X86::INC8r:     return MakeMInst( X86::INC8m ,  FrameIndex, MI);
00165     case X86::INC16r:    return MakeMInst( X86::INC16m,  FrameIndex, MI);
00166     case X86::INC32r:    return MakeMInst( X86::INC32m,  FrameIndex, MI);
00167     case X86::DEC8r:     return MakeMInst( X86::DEC8m ,  FrameIndex, MI);
00168     case X86::DEC16r:    return MakeMInst( X86::DEC16m,  FrameIndex, MI);
00169     case X86::DEC32r:    return MakeMInst( X86::DEC32m,  FrameIndex, MI);
00170     case X86::ADD8rr:    return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
00171     case X86::ADD16rr:   return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
00172     case X86::ADD32rr:   return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
00173     case X86::ADC32rr:   return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
00174     case X86::ADC32ri:   return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
00175     case X86::ADD8ri:    return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
00176     case X86::ADD16ri:   return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
00177     case X86::ADD32ri:   return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
00178     case X86::SUB8rr:    return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
00179     case X86::SUB16rr:   return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
00180     case X86::SUB32rr:   return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
00181     case X86::SBB32rr:   return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
00182     case X86::SBB8ri:    return MakeMIInst(X86::SBB8mi,  FrameIndex, MI);
00183     case X86::SBB16ri:   return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
00184     case X86::SBB32ri:   return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
00185     case X86::SUB8ri:    return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
00186     case X86::SUB16ri:   return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
00187     case X86::SUB32ri:   return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
00188     case X86::AND8rr:    return MakeMRInst(X86::AND8mr , FrameIndex, MI);
00189     case X86::AND16rr:   return MakeMRInst(X86::AND16mr, FrameIndex, MI);
00190     case X86::AND32rr:   return MakeMRInst(X86::AND32mr, FrameIndex, MI);
00191     case X86::AND8ri:    return MakeMIInst(X86::AND8mi , FrameIndex, MI);
00192     case X86::AND16ri:   return MakeMIInst(X86::AND16mi, FrameIndex, MI);
00193     case X86::AND32ri:   return MakeMIInst(X86::AND32mi, FrameIndex, MI);
00194     case X86::OR8rr:     return MakeMRInst(X86::OR8mr ,  FrameIndex, MI);
00195     case X86::OR16rr:    return MakeMRInst(X86::OR16mr,  FrameIndex, MI);
00196     case X86::OR32rr:    return MakeMRInst(X86::OR32mr,  FrameIndex, MI);
00197     case X86::OR8ri:     return MakeMIInst(X86::OR8mi ,  FrameIndex, MI);
00198     case X86::OR16ri:    return MakeMIInst(X86::OR16mi,  FrameIndex, MI);
00199     case X86::OR32ri:    return MakeMIInst(X86::OR32mi,  FrameIndex, MI);
00200     case X86::XOR8rr:    return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
00201     case X86::XOR16rr:   return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
00202     case X86::XOR32rr:   return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
00203     case X86::XOR8ri:    return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
00204     case X86::XOR16ri:   return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
00205     case X86::XOR32ri:   return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
00206     case X86::SHL8rCL:   return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
00207     case X86::SHL16rCL:  return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
00208     case X86::SHL32rCL:  return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
00209     case X86::SHL8ri:    return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
00210     case X86::SHL16ri:   return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
00211     case X86::SHL32ri:   return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
00212     case X86::SHR8rCL:   return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
00213     case X86::SHR16rCL:  return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
00214     case X86::SHR32rCL:  return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
00215     case X86::SHR8ri:    return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
00216     case X86::SHR16ri:   return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
00217     case X86::SHR32ri:   return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
00218     case X86::SAR8rCL:   return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
00219     case X86::SAR16rCL:  return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
00220     case X86::SAR32rCL:  return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
00221     case X86::SAR8ri:    return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
00222     case X86::SAR16ri:   return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
00223     case X86::SAR32ri:   return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
00224     case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
00225     case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
00226     case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
00227     case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
00228     case X86::SETBr:     return MakeMInst( X86::SETBm,   FrameIndex, MI);
00229     case X86::SETAEr:    return MakeMInst( X86::SETAEm,  FrameIndex, MI);
00230     case X86::SETEr:     return MakeMInst( X86::SETEm,   FrameIndex, MI);
00231     case X86::SETNEr:    return MakeMInst( X86::SETNEm,  FrameIndex, MI);
00232     case X86::SETBEr:    return MakeMInst( X86::SETBEm,  FrameIndex, MI);
00233     case X86::SETAr:     return MakeMInst( X86::SETAm,   FrameIndex, MI);
00234     case X86::SETSr:     return MakeMInst( X86::SETSm,   FrameIndex, MI);
00235     case X86::SETNSr:    return MakeMInst( X86::SETNSm,  FrameIndex, MI);
00236     case X86::SETPr:     return MakeMInst( X86::SETPm,   FrameIndex, MI);
00237     case X86::SETLr:     return MakeMInst( X86::SETLm,   FrameIndex, MI);
00238     case X86::SETGEr:    return MakeMInst( X86::SETGEm,  FrameIndex, MI);
00239     case X86::SETLEr:    return MakeMInst( X86::SETLEm,  FrameIndex, MI);
00240     case X86::SETGr:     return MakeMInst( X86::SETGm,   FrameIndex, MI);
00241     case X86::TEST8rr:   return MakeMRInst(X86::TEST8mr ,FrameIndex, MI);
00242     case X86::TEST16rr:  return MakeMRInst(X86::TEST16mr,FrameIndex, MI);
00243     case X86::TEST32rr:  return MakeMRInst(X86::TEST32mr,FrameIndex, MI);
00244     case X86::TEST8ri:   return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
00245     case X86::TEST16ri:  return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
00246     case X86::TEST32ri:  return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
00247     case X86::CMP8rr:    return MakeMRInst(X86::CMP8mr , FrameIndex, MI);
00248     case X86::CMP16rr:   return MakeMRInst(X86::CMP16mr, FrameIndex, MI);
00249     case X86::CMP32rr:   return MakeMRInst(X86::CMP32mr, FrameIndex, MI);
00250     case X86::CMP8ri:    return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
00251     case X86::CMP16ri:   return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
00252     case X86::CMP32ri:   return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
00253     }
00254   } else if (i == 1) {
00255     switch(MI->getOpcode()) {
00256     case X86::XCHG8rr:   return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
00257     case X86::XCHG16rr:  return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
00258     case X86::XCHG32rr:  return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
00259     case X86::MOV8rr:    return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
00260     case X86::MOV16rr:   return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
00261     case X86::MOV32rr:   return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
00262     case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
00263     case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
00264     case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
00265     case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
00266     case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
00267     case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
00268     case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
00269     case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
00270     case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
00271     case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
00272     case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
00273     case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
00274     case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
00275     case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
00276     case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
00277     case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
00278     case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
00279     case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
00280     case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
00281     case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
00282     case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
00283     case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
00284     case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
00285     case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
00286     case X86::ADD8rr:    return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
00287     case X86::ADD16rr:   return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
00288     case X86::ADD32rr:   return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
00289     case X86::ADC32rr:   return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
00290     case X86::SUB8rr:    return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
00291     case X86::SUB16rr:   return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
00292     case X86::SUB32rr:   return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
00293     case X86::SBB32rr:   return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
00294     case X86::AND8rr:    return MakeRMInst(X86::AND8rm , FrameIndex, MI);
00295     case X86::AND16rr:   return MakeRMInst(X86::AND16rm, FrameIndex, MI);
00296     case X86::AND32rr:   return MakeRMInst(X86::AND32rm, FrameIndex, MI);
00297     case X86::OR8rr:     return MakeRMInst(X86::OR8rm ,  FrameIndex, MI);
00298     case X86::OR16rr:    return MakeRMInst(X86::OR16rm,  FrameIndex, MI);
00299     case X86::OR32rr:    return MakeRMInst(X86::OR32rm,  FrameIndex, MI);
00300     case X86::XOR8rr:    return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
00301     case X86::XOR16rr:   return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
00302     case X86::XOR32rr:   return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
00303     case X86::TEST8rr:   return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
00304     case X86::TEST16rr:  return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
00305     case X86::TEST32rr:  return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
00306     case X86::IMUL16rr:  return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
00307     case X86::IMUL32rr:  return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
00308     case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
00309     case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
00310     case X86::CMP8rr:    return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
00311     case X86::CMP16rr:   return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
00312     case X86::CMP32rr:   return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
00313     case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
00314     case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
00315     case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
00316     case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
00317     case X86::MOVZX32rr8:  return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
00318     case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
00319     }
00320   }
00321   if (PrintFailedFusing)
00322     std::cerr << "We failed to fuse: " << *MI;
00323   return NULL;
00324 }
00325 
00326 //===----------------------------------------------------------------------===//
00327 // Stack Frame Processing methods
00328 //===----------------------------------------------------------------------===//
00329 
00330 // hasFP - Return true if the specified function should have a dedicated frame
00331 // pointer register.  This is true if the function has variable sized allocas or
00332 // if frame pointer elimination is disabled.
00333 //
00334 static bool hasFP(MachineFunction &MF) {
00335   return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
00336 }
00337 
00338 void X86RegisterInfo::
00339 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
00340                               MachineBasicBlock::iterator I) const {
00341   if (hasFP(MF)) {
00342     // If we have a frame pointer, turn the adjcallstackup instruction into a
00343     // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
00344     // <amt>'
00345     MachineInstr *Old = I;
00346     unsigned Amount = Old->getOperand(0).getImmedValue();
00347     if (Amount != 0) {
00348       // We need to keep the stack aligned properly.  To do this, we round the
00349       // amount of space needed for the outgoing arguments up to the next
00350       // alignment boundary.
00351       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
00352       Amount = (Amount+Align-1)/Align*Align;
00353 
00354       MachineInstr *New;
00355       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
00356   New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
00357               .addZImm(Amount);
00358       } else {
00359   assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
00360   New=BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
00361               .addZImm(Amount);
00362       }
00363 
00364       // Replace the pseudo instruction with a new instruction...
00365       MBB.insert(I, New);
00366     }
00367   }
00368 
00369   MBB.erase(I);
00370 }
00371 
00372 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
00373   unsigned i = 0;
00374   MachineInstr &MI = *II;
00375   MachineFunction &MF = *MI.getParent()->getParent();
00376   while (!MI.getOperand(i).isFrameIndex()) {
00377     ++i;
00378     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
00379   }
00380 
00381   int FrameIndex = MI.getOperand(i).getFrameIndex();
00382 
00383   // This must be part of a four operand memory reference.  Replace the
00384   // FrameIndex with base register with EBP.  Add add an offset to the offset.
00385   MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
00386 
00387   // Now add the frame object offset to the offset from EBP.
00388   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
00389                MI.getOperand(i+3).getImmedValue()+4;
00390 
00391   if (!hasFP(MF))
00392     Offset += MF.getFrameInfo()->getStackSize();
00393   else
00394     Offset += 4;  // Skip the saved EBP
00395 
00396   MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
00397 }
00398 
00399 void
00400 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
00401   if (hasFP(MF)) {
00402     // Create a frame entry for the EBP register that must be saved.
00403     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
00404     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
00405            "Slot for EBP register must be last in order to be found!");
00406   }
00407 }
00408 
00409 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
00410   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
00411   MachineBasicBlock::iterator MBBI = MBB.begin();
00412   MachineFrameInfo *MFI = MF.getFrameInfo();
00413   MachineInstr *MI;
00414 
00415   // Get the number of bytes to allocate from the FrameInfo
00416   unsigned NumBytes = MFI->getStackSize();
00417   if (hasFP(MF)) {
00418     // Get the offset of the stack slot for the EBP register... which is
00419     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
00420     int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
00421 
00422     if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
00423       MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
00424             .addZImm(NumBytes);
00425       MBB.insert(MBBI, MI);
00426     }
00427 
00428     // Save EBP into the appropriate stack slot...
00429     MI = addRegOffset(BuildMI(X86::MOV32mr, 5),    // mov [ESP-<offset>], EBP
00430           X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
00431     MBB.insert(MBBI, MI);
00432 
00433     // Update EBP with the new base value...
00434     if (NumBytes == 4)    // mov EBP, ESP
00435       MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
00436     else                  // lea EBP, [ESP+StackSize]
00437       MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
00438 
00439     MBB.insert(MBBI, MI);
00440 
00441   } else {
00442     if (MFI->hasCalls()) {
00443       // When we have no frame pointer, we reserve argument space for call sites
00444       // in the function immediately on entry to the current function.  This
00445       // eliminates the need for add/sub ESP brackets around call sites.
00446       //
00447       NumBytes += MFI->getMaxCallFrameSize();
00448 
00449       // Round the size to a multiple of the alignment (don't forget the 4 byte
00450       // offset though).
00451       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
00452       NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
00453     }
00454 
00455     // Update frame info to pretend that this is part of the stack...
00456     MFI->setStackSize(NumBytes);
00457 
00458     if (NumBytes) {
00459       // adjust stack pointer: ESP -= numbytes
00460       MI= BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
00461             .addZImm(NumBytes);
00462       MBB.insert(MBBI, MI);
00463     }
00464   }
00465 }
00466 
00467 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
00468                                    MachineBasicBlock &MBB) const {
00469   const MachineFrameInfo *MFI = MF.getFrameInfo();
00470   MachineBasicBlock::iterator MBBI = prior(MBB.end());
00471   MachineInstr *MI;
00472   assert(MBBI->getOpcode() == X86::RET &&
00473          "Can only insert epilog into returning blocks");
00474 
00475   if (hasFP(MF)) {
00476     // Get the offset of the stack slot for the EBP register... which is
00477     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
00478     int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
00479 
00480     // mov ESP, EBP
00481     MI = BuildMI(X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
00482     MBB.insert(MBBI, MI);
00483 
00484     // pop EBP
00485     MI = BuildMI(X86::POP32r, 0, X86::EBP);
00486     MBB.insert(MBBI, MI);
00487   } else {
00488     // Get the number of bytes allocated from the FrameInfo...
00489     unsigned NumBytes = MFI->getStackSize();
00490 
00491     if (NumBytes) {    // adjust stack pointer back: ESP += numbytes
00492       MI =BuildMI(X86::ADD32ri, 1, X86::ESP, MachineOperand::UseAndDef)
00493             .addZImm(NumBytes);
00494       MBB.insert(MBBI, MI);
00495     }
00496   }
00497 }
00498 
00499 #include "X86GenRegisterInfo.inc"
00500 
00501 const TargetRegisterClass*
00502 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
00503   switch (Ty->getTypeID()) {
00504   case Type::LongTyID:
00505   case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
00506   default:              assert(0 && "Invalid type to getClass!");
00507   case Type::BoolTyID:
00508   case Type::SByteTyID:
00509   case Type::UByteTyID:   return &R8Instance;
00510   case Type::ShortTyID:
00511   case Type::UShortTyID:  return &R16Instance;
00512   case Type::IntTyID:
00513   case Type::UIntTyID:
00514   case Type::PointerTyID: return &R32Instance;
00515 
00516   case Type::FloatTyID:
00517   case Type::DoubleTyID: return &RFPInstance;
00518   }
00519 }