LLVM API Documentation
00001 //===- TableGen'erated file -------------------------------------*- C++ -*-===// 00002 // 00003 // Machine Code Emitter 00004 // 00005 // Automatically generated file, do not edit! 00006 // 00007 //===----------------------------------------------------------------------===// 00008 00009 namespace llvm { 00010 00011 unsigned SparcV9CodeEmitter::getBinaryCodeForInstr(MachineInstr &MI) { 00012 unsigned Value = 0; 00013 DEBUG(std::cerr << MI); 00014 switch (MI.getOpcode()) { 00015 case V9::ADDCcci: { 00016 DEBUG(std::cerr << "Emitting ADDCcci\n"); 00017 Value = 2160074752U; 00018 00019 // op0: rs1 00020 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00021 op0 &= (1<<5) - 1; 00022 op0 <<= 14; 00023 Value |= op0; 00024 // op1: simm13 00025 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00026 op1 &= (1<<13) - 1; 00027 Value |= op1; 00028 // op2: rd 00029 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00030 op2 &= (1<<5) - 1; 00031 op2 <<= 25; 00032 Value |= op2; 00033 break; 00034 } 00035 case V9::ADDCccr: { 00036 DEBUG(std::cerr << "Emitting ADDCccr\n"); 00037 Value = 2160066560U; 00038 00039 // op0: rs1 00040 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00041 op0 &= (1<<5) - 1; 00042 op0 <<= 14; 00043 Value |= op0; 00044 // op1: rs2 00045 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00046 op1 &= (1<<5) - 1; 00047 Value |= op1; 00048 // op2: rd 00049 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00050 op2 &= (1<<5) - 1; 00051 op2 <<= 25; 00052 Value |= op2; 00053 break; 00054 } 00055 case V9::ADDCi: { 00056 DEBUG(std::cerr << "Emitting ADDCi\n"); 00057 Value = 2151686144U; 00058 00059 // op0: rs1 00060 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00061 op0 &= (1<<5) - 1; 00062 op0 <<= 14; 00063 Value |= op0; 00064 // op1: simm13 00065 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00066 op1 &= (1<<13) - 1; 00067 Value |= op1; 00068 // op2: rd 00069 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00070 op2 &= (1<<5) - 1; 00071 op2 <<= 25; 00072 Value |= op2; 00073 break; 00074 } 00075 case V9::ADDCr: { 00076 DEBUG(std::cerr << "Emitting ADDCr\n"); 00077 Value = 2151677952U; 00078 00079 // op0: rs1 00080 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00081 op0 &= (1<<5) - 1; 00082 op0 <<= 14; 00083 Value |= op0; 00084 // op1: rs2 00085 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00086 op1 &= (1<<5) - 1; 00087 Value |= op1; 00088 // op2: rd 00089 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00090 op2 &= (1<<5) - 1; 00091 op2 <<= 25; 00092 Value |= op2; 00093 break; 00094 } 00095 case V9::ADDcci: { 00096 DEBUG(std::cerr << "Emitting ADDcci\n"); 00097 Value = 2155880448U; 00098 00099 // op0: rs1 00100 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00101 op0 &= (1<<5) - 1; 00102 op0 <<= 14; 00103 Value |= op0; 00104 // op1: simm13 00105 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00106 op1 &= (1<<13) - 1; 00107 Value |= op1; 00108 // op2: rd 00109 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00110 op2 &= (1<<5) - 1; 00111 op2 <<= 25; 00112 Value |= op2; 00113 break; 00114 } 00115 case V9::ADDccr: { 00116 DEBUG(std::cerr << "Emitting ADDccr\n"); 00117 Value = 2155872256U; 00118 00119 // op0: rs1 00120 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00121 op0 &= (1<<5) - 1; 00122 op0 <<= 14; 00123 Value |= op0; 00124 // op1: rs2 00125 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00126 op1 &= (1<<5) - 1; 00127 Value |= op1; 00128 // op2: rd 00129 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00130 op2 &= (1<<5) - 1; 00131 op2 <<= 25; 00132 Value |= op2; 00133 break; 00134 } 00135 case V9::ADDi: { 00136 DEBUG(std::cerr << "Emitting ADDi\n"); 00137 Value = 2147491840U; 00138 00139 // op0: rs1 00140 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00141 op0 &= (1<<5) - 1; 00142 op0 <<= 14; 00143 Value |= op0; 00144 // op1: simm13 00145 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00146 op1 &= (1<<13) - 1; 00147 Value |= op1; 00148 // op2: rd 00149 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00150 op2 &= (1<<5) - 1; 00151 op2 <<= 25; 00152 Value |= op2; 00153 break; 00154 } 00155 case V9::ADDr: { 00156 DEBUG(std::cerr << "Emitting ADDr\n"); 00157 Value = 2147483648U; 00158 00159 // op0: rs1 00160 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00161 op0 &= (1<<5) - 1; 00162 op0 <<= 14; 00163 Value |= op0; 00164 // op1: rs2 00165 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00166 op1 &= (1<<5) - 1; 00167 Value |= op1; 00168 // op2: rd 00169 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00170 op2 &= (1<<5) - 1; 00171 op2 <<= 25; 00172 Value |= op2; 00173 break; 00174 } 00175 case V9::ANDNcci: { 00176 DEBUG(std::cerr << "Emitting ANDNcci\n"); 00177 Value = 2158501888U; 00178 00179 // op0: rs1 00180 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00181 op0 &= (1<<5) - 1; 00182 op0 <<= 14; 00183 Value |= op0; 00184 // op1: simm13 00185 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00186 op1 &= (1<<13) - 1; 00187 Value |= op1; 00188 // op2: rd 00189 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00190 op2 &= (1<<5) - 1; 00191 op2 <<= 25; 00192 Value |= op2; 00193 break; 00194 } 00195 case V9::ANDNccr: { 00196 DEBUG(std::cerr << "Emitting ANDNccr\n"); 00197 Value = 2158493696U; 00198 00199 // op0: rs1 00200 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00201 op0 &= (1<<5) - 1; 00202 op0 <<= 14; 00203 Value |= op0; 00204 // op1: rs2 00205 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00206 op1 &= (1<<5) - 1; 00207 Value |= op1; 00208 // op2: rd 00209 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00210 op2 &= (1<<5) - 1; 00211 op2 <<= 25; 00212 Value |= op2; 00213 break; 00214 } 00215 case V9::ANDNi: { 00216 DEBUG(std::cerr << "Emitting ANDNi\n"); 00217 Value = 2150113280U; 00218 00219 // op0: rs1 00220 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00221 op0 &= (1<<5) - 1; 00222 op0 <<= 14; 00223 Value |= op0; 00224 // op1: simm13 00225 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00226 op1 &= (1<<13) - 1; 00227 Value |= op1; 00228 // op2: rd 00229 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00230 op2 &= (1<<5) - 1; 00231 op2 <<= 25; 00232 Value |= op2; 00233 break; 00234 } 00235 case V9::ANDNr: { 00236 DEBUG(std::cerr << "Emitting ANDNr\n"); 00237 Value = 2150105088U; 00238 00239 // op0: rs1 00240 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00241 op0 &= (1<<5) - 1; 00242 op0 <<= 14; 00243 Value |= op0; 00244 // op1: rs2 00245 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00246 op1 &= (1<<5) - 1; 00247 Value |= op1; 00248 // op2: rd 00249 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00250 op2 &= (1<<5) - 1; 00251 op2 <<= 25; 00252 Value |= op2; 00253 break; 00254 } 00255 case V9::ANDcci: { 00256 DEBUG(std::cerr << "Emitting ANDcci\n"); 00257 Value = 2156404736U; 00258 00259 // op0: rs1 00260 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00261 op0 &= (1<<5) - 1; 00262 op0 <<= 14; 00263 Value |= op0; 00264 // op1: simm13 00265 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00266 op1 &= (1<<13) - 1; 00267 Value |= op1; 00268 // op2: rd 00269 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00270 op2 &= (1<<5) - 1; 00271 op2 <<= 25; 00272 Value |= op2; 00273 break; 00274 } 00275 case V9::ANDccr: { 00276 DEBUG(std::cerr << "Emitting ANDccr\n"); 00277 Value = 2156396544U; 00278 00279 // op0: rs1 00280 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00281 op0 &= (1<<5) - 1; 00282 op0 <<= 14; 00283 Value |= op0; 00284 // op1: rs2 00285 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00286 op1 &= (1<<5) - 1; 00287 Value |= op1; 00288 // op2: rd 00289 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00290 op2 &= (1<<5) - 1; 00291 op2 <<= 25; 00292 Value |= op2; 00293 break; 00294 } 00295 case V9::ANDi: { 00296 DEBUG(std::cerr << "Emitting ANDi\n"); 00297 Value = 2148016128U; 00298 00299 // op0: rs1 00300 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00301 op0 &= (1<<5) - 1; 00302 op0 <<= 14; 00303 Value |= op0; 00304 // op1: simm13 00305 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00306 op1 &= (1<<13) - 1; 00307 Value |= op1; 00308 // op2: rd 00309 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00310 op2 &= (1<<5) - 1; 00311 op2 <<= 25; 00312 Value |= op2; 00313 break; 00314 } 00315 case V9::ANDr: { 00316 DEBUG(std::cerr << "Emitting ANDr\n"); 00317 Value = 2148007936U; 00318 00319 // op0: rs1 00320 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00321 op0 &= (1<<5) - 1; 00322 op0 <<= 14; 00323 Value |= op0; 00324 // op1: rs2 00325 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00326 op1 &= (1<<5) - 1; 00327 Value |= op1; 00328 // op2: rd 00329 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00330 op2 &= (1<<5) - 1; 00331 op2 <<= 25; 00332 Value |= op2; 00333 break; 00334 } 00335 case V9::BA: { 00336 DEBUG(std::cerr << "Emitting BA\n"); 00337 Value = 273154048U; 00338 00339 // op0: disp 00340 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00341 op0 &= (1<<19) - 1; 00342 Value |= op0; 00343 break; 00344 } 00345 case V9::BCC: { 00346 DEBUG(std::cerr << "Emitting BCC\n"); 00347 Value = 440926208U; 00348 00349 // op0: cc 00350 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00351 op0 &= (1<<2) - 1; 00352 op0 <<= 20; 00353 Value |= op0; 00354 // op1: disp 00355 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00356 op1 &= (1<<19) - 1; 00357 Value |= op1; 00358 break; 00359 } 00360 case V9::BCS: { 00361 DEBUG(std::cerr << "Emitting BCS\n"); 00362 Value = 172490752U; 00363 00364 // op0: cc 00365 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00366 op0 &= (1<<2) - 1; 00367 op0 <<= 20; 00368 Value |= op0; 00369 // op1: disp 00370 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00371 op1 &= (1<<19) - 1; 00372 Value |= op1; 00373 break; 00374 } 00375 case V9::BE: { 00376 DEBUG(std::cerr << "Emitting BE\n"); 00377 Value = 38273024U; 00378 00379 // op0: cc 00380 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00381 op0 &= (1<<2) - 1; 00382 op0 <<= 20; 00383 Value |= op0; 00384 // op1: disp 00385 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00386 op1 &= (1<<19) - 1; 00387 Value |= op1; 00388 break; 00389 } 00390 case V9::BG: { 00391 DEBUG(std::cerr << "Emitting BG\n"); 00392 Value = 340262912U; 00393 00394 // op0: cc 00395 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00396 op0 &= (1<<2) - 1; 00397 op0 <<= 20; 00398 Value |= op0; 00399 // op1: disp 00400 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00401 op1 &= (1<<19) - 1; 00402 Value |= op1; 00403 break; 00404 } 00405 case V9::BGE: { 00406 DEBUG(std::cerr << "Emitting BGE\n"); 00407 Value = 373817344U; 00408 00409 // op0: cc 00410 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00411 op0 &= (1<<2) - 1; 00412 op0 <<= 20; 00413 Value |= op0; 00414 // op1: disp 00415 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00416 op1 &= (1<<19) - 1; 00417 Value |= op1; 00418 break; 00419 } 00420 case V9::BGU: { 00421 DEBUG(std::cerr << "Emitting BGU\n"); 00422 Value = 407371776U; 00423 00424 // op0: cc 00425 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00426 op0 &= (1<<2) - 1; 00427 op0 <<= 20; 00428 Value |= op0; 00429 // op1: disp 00430 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00431 op1 &= (1<<19) - 1; 00432 Value |= op1; 00433 break; 00434 } 00435 case V9::BL: { 00436 DEBUG(std::cerr << "Emitting BL\n"); 00437 Value = 105381888U; 00438 00439 // op0: cc 00440 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00441 op0 &= (1<<2) - 1; 00442 op0 <<= 20; 00443 Value |= op0; 00444 // op1: disp 00445 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00446 op1 &= (1<<19) - 1; 00447 Value |= op1; 00448 break; 00449 } 00450 case V9::BLE: { 00451 DEBUG(std::cerr << "Emitting BLE\n"); 00452 Value = 71827456U; 00453 00454 // op0: cc 00455 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00456 op0 &= (1<<2) - 1; 00457 op0 <<= 20; 00458 Value |= op0; 00459 // op1: disp 00460 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00461 op1 &= (1<<19) - 1; 00462 Value |= op1; 00463 break; 00464 } 00465 case V9::BLEU: { 00466 DEBUG(std::cerr << "Emitting BLEU\n"); 00467 Value = 138936320U; 00468 00469 // op0: cc 00470 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00471 op0 &= (1<<2) - 1; 00472 op0 <<= 20; 00473 Value |= op0; 00474 // op1: disp 00475 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00476 op1 &= (1<<19) - 1; 00477 Value |= op1; 00478 break; 00479 } 00480 case V9::BN: { 00481 DEBUG(std::cerr << "Emitting BN\n"); 00482 Value = 4718592U; 00483 00484 // op0: disp 00485 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00486 op0 &= (1<<19) - 1; 00487 Value |= op0; 00488 break; 00489 } 00490 case V9::BNE: { 00491 DEBUG(std::cerr << "Emitting BNE\n"); 00492 Value = 306708480U; 00493 00494 // op0: cc 00495 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00496 op0 &= (1<<2) - 1; 00497 op0 <<= 20; 00498 Value |= op0; 00499 // op1: disp 00500 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00501 op1 &= (1<<19) - 1; 00502 Value |= op1; 00503 break; 00504 } 00505 case V9::BNEG: { 00506 DEBUG(std::cerr << "Emitting BNEG\n"); 00507 Value = 206045184U; 00508 00509 // op0: cc 00510 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00511 op0 &= (1<<2) - 1; 00512 op0 <<= 20; 00513 Value |= op0; 00514 // op1: disp 00515 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00516 op1 &= (1<<19) - 1; 00517 Value |= op1; 00518 break; 00519 } 00520 case V9::BPOS: { 00521 DEBUG(std::cerr << "Emitting BPOS\n"); 00522 Value = 474480640U; 00523 00524 // op0: cc 00525 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00526 op0 &= (1<<2) - 1; 00527 op0 <<= 20; 00528 Value |= op0; 00529 // op1: disp 00530 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00531 op1 &= (1<<19) - 1; 00532 Value |= op1; 00533 break; 00534 } 00535 case V9::BRGEZ: { 00536 DEBUG(std::cerr << "Emitting BRGEZ\n"); 00537 Value = 247988224U; 00538 00539 // op0: rs1 00540 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00541 op0 &= (1<<5) - 1; 00542 op0 <<= 14; 00543 Value |= op0; 00544 // op1: disp 00545 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00546 Value |= getValueBit(op1, 15) << 21; 00547 Value |= getValueBit(op1, 14) << 20; 00548 Value |= getValueBit(op1, 13) << 13; 00549 Value |= getValueBit(op1, 12) << 12; 00550 Value |= getValueBit(op1, 11) << 11; 00551 Value |= getValueBit(op1, 10) << 10; 00552 Value |= getValueBit(op1, 9) << 9; 00553 Value |= getValueBit(op1, 8) << 8; 00554 Value |= getValueBit(op1, 7) << 7; 00555 Value |= getValueBit(op1, 6) << 6; 00556 Value |= getValueBit(op1, 5) << 5; 00557 Value |= getValueBit(op1, 4) << 4; 00558 Value |= getValueBit(op1, 3) << 3; 00559 Value |= getValueBit(op1, 2) << 2; 00560 Value |= getValueBit(op1, 1) << 1; 00561 Value |= getValueBit(op1, 0) << 0; 00562 break; 00563 } 00564 case V9::BRGZ: { 00565 DEBUG(std::cerr << "Emitting BRGZ\n"); 00566 Value = 214433792U; 00567 00568 // op0: rs1 00569 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00570 op0 &= (1<<5) - 1; 00571 op0 <<= 14; 00572 Value |= op0; 00573 // op1: disp 00574 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00575 Value |= getValueBit(op1, 15) << 21; 00576 Value |= getValueBit(op1, 14) << 20; 00577 Value |= getValueBit(op1, 13) << 13; 00578 Value |= getValueBit(op1, 12) << 12; 00579 Value |= getValueBit(op1, 11) << 11; 00580 Value |= getValueBit(op1, 10) << 10; 00581 Value |= getValueBit(op1, 9) << 9; 00582 Value |= getValueBit(op1, 8) << 8; 00583 Value |= getValueBit(op1, 7) << 7; 00584 Value |= getValueBit(op1, 6) << 6; 00585 Value |= getValueBit(op1, 5) << 5; 00586 Value |= getValueBit(op1, 4) << 4; 00587 Value |= getValueBit(op1, 3) << 3; 00588 Value |= getValueBit(op1, 2) << 2; 00589 Value |= getValueBit(op1, 1) << 1; 00590 Value |= getValueBit(op1, 0) << 0; 00591 break; 00592 } 00593 case V9::BRLEZ: { 00594 DEBUG(std::cerr << "Emitting BRLEZ\n"); 00595 Value = 80216064U; 00596 00597 // op0: rs1 00598 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00599 op0 &= (1<<5) - 1; 00600 op0 <<= 14; 00601 Value |= op0; 00602 // op1: disp 00603 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00604 Value |= getValueBit(op1, 15) << 21; 00605 Value |= getValueBit(op1, 14) << 20; 00606 Value |= getValueBit(op1, 13) << 13; 00607 Value |= getValueBit(op1, 12) << 12; 00608 Value |= getValueBit(op1, 11) << 11; 00609 Value |= getValueBit(op1, 10) << 10; 00610 Value |= getValueBit(op1, 9) << 9; 00611 Value |= getValueBit(op1, 8) << 8; 00612 Value |= getValueBit(op1, 7) << 7; 00613 Value |= getValueBit(op1, 6) << 6; 00614 Value |= getValueBit(op1, 5) << 5; 00615 Value |= getValueBit(op1, 4) << 4; 00616 Value |= getValueBit(op1, 3) << 3; 00617 Value |= getValueBit(op1, 2) << 2; 00618 Value |= getValueBit(op1, 1) << 1; 00619 Value |= getValueBit(op1, 0) << 0; 00620 break; 00621 } 00622 case V9::BRLZ: { 00623 DEBUG(std::cerr << "Emitting BRLZ\n"); 00624 Value = 113770496U; 00625 00626 // op0: rs1 00627 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00628 op0 &= (1<<5) - 1; 00629 op0 <<= 14; 00630 Value |= op0; 00631 // op1: disp 00632 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00633 Value |= getValueBit(op1, 15) << 21; 00634 Value |= getValueBit(op1, 14) << 20; 00635 Value |= getValueBit(op1, 13) << 13; 00636 Value |= getValueBit(op1, 12) << 12; 00637 Value |= getValueBit(op1, 11) << 11; 00638 Value |= getValueBit(op1, 10) << 10; 00639 Value |= getValueBit(op1, 9) << 9; 00640 Value |= getValueBit(op1, 8) << 8; 00641 Value |= getValueBit(op1, 7) << 7; 00642 Value |= getValueBit(op1, 6) << 6; 00643 Value |= getValueBit(op1, 5) << 5; 00644 Value |= getValueBit(op1, 4) << 4; 00645 Value |= getValueBit(op1, 3) << 3; 00646 Value |= getValueBit(op1, 2) << 2; 00647 Value |= getValueBit(op1, 1) << 1; 00648 Value |= getValueBit(op1, 0) << 0; 00649 break; 00650 } 00651 case V9::BRNZ: { 00652 DEBUG(std::cerr << "Emitting BRNZ\n"); 00653 Value = 180879360U; 00654 00655 // op0: rs1 00656 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00657 op0 &= (1<<5) - 1; 00658 op0 <<= 14; 00659 Value |= op0; 00660 // op1: disp 00661 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00662 Value |= getValueBit(op1, 15) << 21; 00663 Value |= getValueBit(op1, 14) << 20; 00664 Value |= getValueBit(op1, 13) << 13; 00665 Value |= getValueBit(op1, 12) << 12; 00666 Value |= getValueBit(op1, 11) << 11; 00667 Value |= getValueBit(op1, 10) << 10; 00668 Value |= getValueBit(op1, 9) << 9; 00669 Value |= getValueBit(op1, 8) << 8; 00670 Value |= getValueBit(op1, 7) << 7; 00671 Value |= getValueBit(op1, 6) << 6; 00672 Value |= getValueBit(op1, 5) << 5; 00673 Value |= getValueBit(op1, 4) << 4; 00674 Value |= getValueBit(op1, 3) << 3; 00675 Value |= getValueBit(op1, 2) << 2; 00676 Value |= getValueBit(op1, 1) << 1; 00677 Value |= getValueBit(op1, 0) << 0; 00678 break; 00679 } 00680 case V9::BRZ: { 00681 DEBUG(std::cerr << "Emitting BRZ\n"); 00682 Value = 46661632U; 00683 00684 // op0: rs1 00685 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00686 op0 &= (1<<5) - 1; 00687 op0 <<= 14; 00688 Value |= op0; 00689 // op1: disp 00690 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00691 Value |= getValueBit(op1, 15) << 21; 00692 Value |= getValueBit(op1, 14) << 20; 00693 Value |= getValueBit(op1, 13) << 13; 00694 Value |= getValueBit(op1, 12) << 12; 00695 Value |= getValueBit(op1, 11) << 11; 00696 Value |= getValueBit(op1, 10) << 10; 00697 Value |= getValueBit(op1, 9) << 9; 00698 Value |= getValueBit(op1, 8) << 8; 00699 Value |= getValueBit(op1, 7) << 7; 00700 Value |= getValueBit(op1, 6) << 6; 00701 Value |= getValueBit(op1, 5) << 5; 00702 Value |= getValueBit(op1, 4) << 4; 00703 Value |= getValueBit(op1, 3) << 3; 00704 Value |= getValueBit(op1, 2) << 2; 00705 Value |= getValueBit(op1, 1) << 1; 00706 Value |= getValueBit(op1, 0) << 0; 00707 break; 00708 } 00709 case V9::BVC: { 00710 DEBUG(std::cerr << "Emitting BVC\n"); 00711 Value = 508035072U; 00712 00713 // op0: cc 00714 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00715 op0 &= (1<<2) - 1; 00716 op0 <<= 20; 00717 Value |= op0; 00718 // op1: disp 00719 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00720 op1 &= (1<<19) - 1; 00721 Value |= op1; 00722 break; 00723 } 00724 case V9::BVS: { 00725 DEBUG(std::cerr << "Emitting BVS\n"); 00726 Value = 239599616U; 00727 00728 // op0: cc 00729 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00730 op0 &= (1<<2) - 1; 00731 op0 <<= 20; 00732 Value |= op0; 00733 // op1: disp 00734 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00735 op1 &= (1<<19) - 1; 00736 Value |= op1; 00737 break; 00738 } 00739 case V9::CALL: { 00740 DEBUG(std::cerr << "Emitting CALL\n"); 00741 Value = 1073741824U; 00742 00743 // op0: disp 00744 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00745 op0 &= (1<<30) - 1; 00746 Value |= op0; 00747 break; 00748 } 00749 case V9::FABSD: { 00750 DEBUG(std::cerr << "Emitting FABSD\n"); 00751 Value = 2174746944U; 00752 00753 // op0: rs2 00754 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00755 op0 &= (1<<5) - 1; 00756 Value |= op0; 00757 // op1: rd 00758 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00759 op1 &= (1<<5) - 1; 00760 op1 <<= 25; 00761 Value |= op1; 00762 break; 00763 } 00764 case V9::FABSS: { 00765 DEBUG(std::cerr << "Emitting FABSS\n"); 00766 Value = 2174746912U; 00767 00768 // op0: rs2 00769 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00770 op0 &= (1<<5) - 1; 00771 Value |= op0; 00772 // op1: rd 00773 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00774 op1 &= (1<<5) - 1; 00775 op1 <<= 25; 00776 Value |= op1; 00777 break; 00778 } 00779 case V9::FADDD: { 00780 DEBUG(std::cerr << "Emitting FADDD\n"); 00781 Value = 2174748736U; 00782 00783 // op0: rs1 00784 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00785 op0 &= (1<<5) - 1; 00786 op0 <<= 14; 00787 Value |= op0; 00788 // op1: rs2 00789 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00790 op1 &= (1<<5) - 1; 00791 Value |= op1; 00792 // op2: rd 00793 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00794 op2 &= (1<<5) - 1; 00795 op2 <<= 25; 00796 Value |= op2; 00797 break; 00798 } 00799 case V9::FADDQ: { 00800 DEBUG(std::cerr << "Emitting FADDQ\n"); 00801 Value = 2174748768U; 00802 00803 // op0: rs1 00804 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00805 op0 &= (1<<5) - 1; 00806 op0 <<= 14; 00807 Value |= op0; 00808 // op1: rs2 00809 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00810 op1 &= (1<<5) - 1; 00811 Value |= op1; 00812 // op2: rd 00813 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00814 op2 &= (1<<5) - 1; 00815 op2 <<= 25; 00816 Value |= op2; 00817 break; 00818 } 00819 case V9::FADDS: { 00820 DEBUG(std::cerr << "Emitting FADDS\n"); 00821 Value = 2174748704U; 00822 00823 // op0: rs1 00824 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00825 op0 &= (1<<5) - 1; 00826 op0 <<= 14; 00827 Value |= op0; 00828 // op1: rs2 00829 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00830 op1 &= (1<<5) - 1; 00831 Value |= op1; 00832 // op2: rd 00833 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 00834 op2 &= (1<<5) - 1; 00835 op2 <<= 25; 00836 Value |= op2; 00837 break; 00838 } 00839 case V9::FBA: { 00840 DEBUG(std::cerr << "Emitting FBA\n"); 00841 Value = 289931264U; 00842 00843 // op0: cc 00844 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00845 op0 &= (1<<2) - 1; 00846 op0 <<= 20; 00847 Value |= op0; 00848 // op1: disp 00849 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00850 op1 &= (1<<19) - 1; 00851 Value |= op1; 00852 break; 00853 } 00854 case V9::FBE: { 00855 DEBUG(std::cerr << "Emitting FBE\n"); 00856 Value = 323485696U; 00857 00858 // op0: cc 00859 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00860 op0 &= (1<<2) - 1; 00861 op0 <<= 20; 00862 Value |= op0; 00863 // op1: disp 00864 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00865 op1 &= (1<<19) - 1; 00866 Value |= op1; 00867 break; 00868 } 00869 case V9::FBG: { 00870 DEBUG(std::cerr << "Emitting FBG\n"); 00871 Value = 222822400U; 00872 00873 // op0: cc 00874 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00875 op0 &= (1<<2) - 1; 00876 op0 <<= 20; 00877 Value |= op0; 00878 // op1: disp 00879 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00880 op1 &= (1<<19) - 1; 00881 Value |= op1; 00882 break; 00883 } 00884 case V9::FBGE: { 00885 DEBUG(std::cerr << "Emitting FBGE\n"); 00886 Value = 390594560U; 00887 00888 // op0: cc 00889 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00890 op0 &= (1<<2) - 1; 00891 op0 <<= 20; 00892 Value |= op0; 00893 // op1: disp 00894 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00895 op1 &= (1<<19) - 1; 00896 Value |= op1; 00897 break; 00898 } 00899 case V9::FBL: { 00900 DEBUG(std::cerr << "Emitting FBL\n"); 00901 Value = 155713536U; 00902 00903 // op0: cc 00904 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00905 op0 &= (1<<2) - 1; 00906 op0 <<= 20; 00907 Value |= op0; 00908 // op1: disp 00909 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00910 op1 &= (1<<19) - 1; 00911 Value |= op1; 00912 break; 00913 } 00914 case V9::FBLE: { 00915 DEBUG(std::cerr << "Emitting FBLE\n"); 00916 Value = 457703424U; 00917 00918 // op0: cc 00919 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00920 op0 &= (1<<2) - 1; 00921 op0 <<= 20; 00922 Value |= op0; 00923 // op1: disp 00924 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00925 op1 &= (1<<19) - 1; 00926 Value |= op1; 00927 break; 00928 } 00929 case V9::FBLG: { 00930 DEBUG(std::cerr << "Emitting FBLG\n"); 00931 Value = 88604672U; 00932 00933 // op0: cc 00934 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00935 op0 &= (1<<2) - 1; 00936 op0 <<= 20; 00937 Value |= op0; 00938 // op1: disp 00939 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00940 op1 &= (1<<19) - 1; 00941 Value |= op1; 00942 break; 00943 } 00944 case V9::FBN: { 00945 DEBUG(std::cerr << "Emitting FBN\n"); 00946 Value = 21495808U; 00947 00948 // op0: cc 00949 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00950 op0 &= (1<<2) - 1; 00951 op0 <<= 20; 00952 Value |= op0; 00953 // op1: disp 00954 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00955 op1 &= (1<<19) - 1; 00956 Value |= op1; 00957 break; 00958 } 00959 case V9::FBNE: { 00960 DEBUG(std::cerr << "Emitting FBNE\n"); 00961 Value = 55050240U; 00962 00963 // op0: cc 00964 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00965 op0 &= (1<<2) - 1; 00966 op0 <<= 20; 00967 Value |= op0; 00968 // op1: disp 00969 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00970 op1 &= (1<<19) - 1; 00971 Value |= op1; 00972 break; 00973 } 00974 case V9::FBO: { 00975 DEBUG(std::cerr << "Emitting FBO\n"); 00976 Value = 524812288U; 00977 00978 // op0: cc 00979 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00980 op0 &= (1<<2) - 1; 00981 op0 <<= 20; 00982 Value |= op0; 00983 // op1: disp 00984 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 00985 op1 &= (1<<19) - 1; 00986 Value |= op1; 00987 break; 00988 } 00989 case V9::FBU: { 00990 DEBUG(std::cerr << "Emitting FBU\n"); 00991 Value = 256376832U; 00992 00993 // op0: cc 00994 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 00995 op0 &= (1<<2) - 1; 00996 op0 <<= 20; 00997 Value |= op0; 00998 // op1: disp 00999 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01000 op1 &= (1<<19) - 1; 01001 Value |= op1; 01002 break; 01003 } 01004 case V9::FBUE: { 01005 DEBUG(std::cerr << "Emitting FBUE\n"); 01006 Value = 357040128U; 01007 01008 // op0: cc 01009 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01010 op0 &= (1<<2) - 1; 01011 op0 <<= 20; 01012 Value |= op0; 01013 // op1: disp 01014 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01015 op1 &= (1<<19) - 1; 01016 Value |= op1; 01017 break; 01018 } 01019 case V9::FBUG: { 01020 DEBUG(std::cerr << "Emitting FBUG\n"); 01021 Value = 189267968U; 01022 01023 // op0: cc 01024 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01025 op0 &= (1<<2) - 1; 01026 op0 <<= 20; 01027 Value |= op0; 01028 // op1: disp 01029 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01030 op1 &= (1<<19) - 1; 01031 Value |= op1; 01032 break; 01033 } 01034 case V9::FBUGE: { 01035 DEBUG(std::cerr << "Emitting FBUGE\n"); 01036 Value = 424148992U; 01037 01038 // op0: cc 01039 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01040 op0 &= (1<<2) - 1; 01041 op0 <<= 20; 01042 Value |= op0; 01043 // op1: disp 01044 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01045 op1 &= (1<<19) - 1; 01046 Value |= op1; 01047 break; 01048 } 01049 case V9::FBUL: { 01050 DEBUG(std::cerr << "Emitting FBUL\n"); 01051 Value = 122159104U; 01052 01053 // op0: cc 01054 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01055 op0 &= (1<<2) - 1; 01056 op0 <<= 20; 01057 Value |= op0; 01058 // op1: disp 01059 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01060 op1 &= (1<<19) - 1; 01061 Value |= op1; 01062 break; 01063 } 01064 case V9::FBULE: { 01065 DEBUG(std::cerr << "Emitting FBULE\n"); 01066 Value = 491257856U; 01067 01068 // op0: cc 01069 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01070 op0 &= (1<<2) - 1; 01071 op0 <<= 20; 01072 Value |= op0; 01073 // op1: disp 01074 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01075 op1 &= (1<<19) - 1; 01076 Value |= op1; 01077 break; 01078 } 01079 case V9::FCMPD: { 01080 DEBUG(std::cerr << "Emitting FCMPD\n"); 01081 Value = 2175273536U; 01082 01083 // op0: cc 01084 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01085 op0 &= (1<<2) - 1; 01086 op0 <<= 25; 01087 Value |= op0; 01088 // op1: rs1 01089 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01090 op1 &= (1<<5) - 1; 01091 op1 <<= 14; 01092 Value |= op1; 01093 // op2: rs2 01094 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01095 op2 &= (1<<5) - 1; 01096 Value |= op2; 01097 break; 01098 } 01099 case V9::FCMPQ: { 01100 DEBUG(std::cerr << "Emitting FCMPQ\n"); 01101 Value = 2175273568U; 01102 01103 // op0: cc 01104 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01105 op0 &= (1<<2) - 1; 01106 op0 <<= 25; 01107 Value |= op0; 01108 // op1: rs1 01109 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01110 op1 &= (1<<5) - 1; 01111 op1 <<= 14; 01112 Value |= op1; 01113 // op2: rs2 01114 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01115 op2 &= (1<<5) - 1; 01116 Value |= op2; 01117 break; 01118 } 01119 case V9::FCMPS: { 01120 DEBUG(std::cerr << "Emitting FCMPS\n"); 01121 Value = 2175273504U; 01122 01123 // op0: cc 01124 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01125 op0 &= (1<<2) - 1; 01126 op0 <<= 25; 01127 Value |= op0; 01128 // op1: rs1 01129 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01130 op1 &= (1<<5) - 1; 01131 op1 <<= 14; 01132 Value |= op1; 01133 // op2: rs2 01134 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01135 op2 &= (1<<5) - 1; 01136 Value |= op2; 01137 break; 01138 } 01139 case V9::FDIVD: { 01140 DEBUG(std::cerr << "Emitting FDIVD\n"); 01141 Value = 2174749120U; 01142 01143 // op0: rs1 01144 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01145 op0 &= (1<<5) - 1; 01146 op0 <<= 14; 01147 Value |= op0; 01148 // op1: rs2 01149 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01150 op1 &= (1<<5) - 1; 01151 Value |= op1; 01152 // op2: rd 01153 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01154 op2 &= (1<<5) - 1; 01155 op2 <<= 25; 01156 Value |= op2; 01157 break; 01158 } 01159 case V9::FDIVQ: { 01160 DEBUG(std::cerr << "Emitting FDIVQ\n"); 01161 Value = 2174749152U; 01162 01163 // op0: rs1 01164 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01165 op0 &= (1<<5) - 1; 01166 op0 <<= 14; 01167 Value |= op0; 01168 // op1: rs2 01169 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01170 op1 &= (1<<5) - 1; 01171 Value |= op1; 01172 // op2: rd 01173 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01174 op2 &= (1<<5) - 1; 01175 op2 <<= 25; 01176 Value |= op2; 01177 break; 01178 } 01179 case V9::FDIVS: { 01180 DEBUG(std::cerr << "Emitting FDIVS\n"); 01181 Value = 2174749088U; 01182 01183 // op0: rs1 01184 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01185 op0 &= (1<<5) - 1; 01186 op0 <<= 14; 01187 Value |= op0; 01188 // op1: rs2 01189 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01190 op1 &= (1<<5) - 1; 01191 Value |= op1; 01192 // op2: rd 01193 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01194 op2 &= (1<<5) - 1; 01195 op2 <<= 25; 01196 Value |= op2; 01197 break; 01198 } 01199 case V9::FDMULQ: { 01200 DEBUG(std::cerr << "Emitting FDMULQ\n"); 01201 Value = 2174750144U; 01202 01203 // op0: rs1 01204 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01205 op0 &= (1<<5) - 1; 01206 op0 <<= 14; 01207 Value |= op0; 01208 // op1: rs2 01209 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01210 op1 &= (1<<5) - 1; 01211 Value |= op1; 01212 // op2: rd 01213 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01214 op2 &= (1<<5) - 1; 01215 op2 <<= 25; 01216 Value |= op2; 01217 break; 01218 } 01219 case V9::FDTOI: { 01220 DEBUG(std::cerr << "Emitting FDTOI\n"); 01221 Value = 2174753344U; 01222 01223 // op0: rs2 01224 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01225 op0 &= (1<<5) - 1; 01226 Value |= op0; 01227 // op1: rd 01228 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01229 op1 &= (1<<5) - 1; 01230 op1 <<= 25; 01231 Value |= op1; 01232 break; 01233 } 01234 case V9::FDTOQ: { 01235 DEBUG(std::cerr << "Emitting FDTOQ\n"); 01236 Value = 2174753216U; 01237 01238 // op0: rs2 01239 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01240 op0 &= (1<<5) - 1; 01241 Value |= op0; 01242 // op1: rd 01243 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01244 op1 &= (1<<5) - 1; 01245 op1 <<= 25; 01246 Value |= op1; 01247 break; 01248 } 01249 case V9::FDTOS: { 01250 DEBUG(std::cerr << "Emitting FDTOS\n"); 01251 Value = 2174752960U; 01252 01253 // op0: rs2 01254 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01255 op0 &= (1<<5) - 1; 01256 Value |= op0; 01257 // op1: rd 01258 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01259 op1 &= (1<<5) - 1; 01260 op1 <<= 25; 01261 Value |= op1; 01262 break; 01263 } 01264 case V9::FDTOX: { 01265 DEBUG(std::cerr << "Emitting FDTOX\n"); 01266 Value = 2174750784U; 01267 01268 // op0: rs2 01269 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01270 op0 &= (1<<5) - 1; 01271 Value |= op0; 01272 // op1: rd 01273 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01274 op1 &= (1<<5) - 1; 01275 op1 <<= 25; 01276 Value |= op1; 01277 break; 01278 } 01279 case V9::FITOD: { 01280 DEBUG(std::cerr << "Emitting FITOD\n"); 01281 Value = 2174753024U; 01282 01283 // op0: rs2 01284 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01285 op0 &= (1<<5) - 1; 01286 Value |= op0; 01287 // op1: rd 01288 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01289 op1 &= (1<<5) - 1; 01290 op1 <<= 25; 01291 Value |= op1; 01292 break; 01293 } 01294 case V9::FITOQ: { 01295 DEBUG(std::cerr << "Emitting FITOQ\n"); 01296 Value = 2174753152U; 01297 01298 // op0: rs2 01299 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01300 op0 &= (1<<5) - 1; 01301 Value |= op0; 01302 // op1: rd 01303 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01304 op1 &= (1<<5) - 1; 01305 op1 <<= 25; 01306 Value |= op1; 01307 break; 01308 } 01309 case V9::FITOS: { 01310 DEBUG(std::cerr << "Emitting FITOS\n"); 01311 Value = 2174752896U; 01312 01313 // op0: rs2 01314 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01315 op0 &= (1<<5) - 1; 01316 Value |= op0; 01317 // op1: rd 01318 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01319 op1 &= (1<<5) - 1; 01320 op1 <<= 25; 01321 Value |= op1; 01322 break; 01323 } 01324 case V9::FMOVD: { 01325 DEBUG(std::cerr << "Emitting FMOVD\n"); 01326 Value = 2174746688U; 01327 01328 // op0: rs2 01329 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01330 op0 &= (1<<5) - 1; 01331 Value |= op0; 01332 // op1: rd 01333 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01334 op1 &= (1<<5) - 1; 01335 op1 <<= 25; 01336 Value |= op1; 01337 break; 01338 } 01339 case V9::FMOVDA: { 01340 DEBUG(std::cerr << "Emitting FMOVDA\n"); 01341 Value = 2175402048U; 01342 01343 // op0: cc 01344 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01345 op0 &= (1<<3) - 1; 01346 op0 <<= 11; 01347 Value |= op0; 01348 // op1: rs2 01349 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01350 op1 &= (1<<5) - 1; 01351 Value |= op1; 01352 // op2: rd 01353 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01354 op2 &= (1<<5) - 1; 01355 op2 <<= 25; 01356 Value |= op2; 01357 break; 01358 } 01359 case V9::FMOVDCC: { 01360 DEBUG(std::cerr << "Emitting FMOVDCC\n"); 01361 Value = 2175483968U; 01362 01363 // op0: cc 01364 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01365 op0 &= (1<<3) - 1; 01366 op0 <<= 11; 01367 Value |= op0; 01368 // op1: rs2 01369 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01370 op1 &= (1<<5) - 1; 01371 Value |= op1; 01372 // op2: rd 01373 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01374 op2 &= (1<<5) - 1; 01375 op2 <<= 25; 01376 Value |= op2; 01377 break; 01378 } 01379 case V9::FMOVDCS: { 01380 DEBUG(std::cerr << "Emitting FMOVDCS\n"); 01381 Value = 2175352896U; 01382 01383 // op0: cc 01384 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01385 op0 &= (1<<3) - 1; 01386 op0 <<= 11; 01387 Value |= op0; 01388 // op1: rs2 01389 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01390 op1 &= (1<<5) - 1; 01391 Value |= op1; 01392 // op2: rd 01393 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01394 op2 &= (1<<5) - 1; 01395 op2 <<= 25; 01396 Value |= op2; 01397 break; 01398 } 01399 case V9::FMOVDE: { 01400 DEBUG(std::cerr << "Emitting FMOVDE\n"); 01401 Value = 2175270976U; 01402 01403 // op0: cc 01404 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01405 op0 &= (1<<3) - 1; 01406 op0 <<= 11; 01407 Value |= op0; 01408 // op1: rs2 01409 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01410 op1 &= (1<<5) - 1; 01411 Value |= op1; 01412 // op2: rd 01413 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01414 op2 &= (1<<5) - 1; 01415 op2 <<= 25; 01416 Value |= op2; 01417 break; 01418 } 01419 case V9::FMOVDFA: { 01420 DEBUG(std::cerr << "Emitting FMOVDFA\n"); 01421 Value = 2175336512U; 01422 01423 // op0: cc 01424 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01425 op0 &= (1<<3) - 1; 01426 op0 <<= 11; 01427 Value |= op0; 01428 // op1: rs2 01429 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01430 op1 &= (1<<5) - 1; 01431 Value |= op1; 01432 // op2: rd 01433 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01434 op2 &= (1<<5) - 1; 01435 op2 <<= 25; 01436 Value |= op2; 01437 break; 01438 } 01439 case V9::FMOVDFE: { 01440 DEBUG(std::cerr << "Emitting FMOVDFE\n"); 01441 Value = 2175418432U; 01442 01443 // op0: cc 01444 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01445 op0 &= (1<<3) - 1; 01446 op0 <<= 11; 01447 Value |= op0; 01448 // op1: rs2 01449 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01450 op1 &= (1<<5) - 1; 01451 Value |= op1; 01452 // op2: rd 01453 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01454 op2 &= (1<<5) - 1; 01455 op2 <<= 25; 01456 Value |= op2; 01457 break; 01458 } 01459 case V9::FMOVDFG: { 01460 DEBUG(std::cerr << "Emitting FMOVDFG\n"); 01461 Value = 2175369280U; 01462 01463 // op0: cc 01464 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01465 op0 &= (1<<3) - 1; 01466 op0 <<= 11; 01467 Value |= op0; 01468 // op1: rs2 01469 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01470 op1 &= (1<<5) - 1; 01471 Value |= op1; 01472 // op2: rd 01473 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01474 op2 &= (1<<5) - 1; 01475 op2 <<= 25; 01476 Value |= op2; 01477 break; 01478 } 01479 case V9::FMOVDFGE: { 01480 DEBUG(std::cerr << "Emitting FMOVDFGE\n"); 01481 Value = 2175451200U; 01482 01483 // op0: cc 01484 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01485 op0 &= (1<<3) - 1; 01486 op0 <<= 11; 01487 Value |= op0; 01488 // op1: rs2 01489 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01490 op1 &= (1<<5) - 1; 01491 Value |= op1; 01492 // op2: rd 01493 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01494 op2 &= (1<<5) - 1; 01495 op2 <<= 25; 01496 Value |= op2; 01497 break; 01498 } 01499 case V9::FMOVDFL: { 01500 DEBUG(std::cerr << "Emitting FMOVDFL\n"); 01501 Value = 2175336512U; 01502 01503 // op0: cc 01504 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01505 op0 &= (1<<3) - 1; 01506 op0 <<= 11; 01507 Value |= op0; 01508 // op1: rs2 01509 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01510 op1 &= (1<<5) - 1; 01511 Value |= op1; 01512 // op2: rd 01513 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01514 op2 &= (1<<5) - 1; 01515 op2 <<= 25; 01516 Value |= op2; 01517 break; 01518 } 01519 case V9::FMOVDFLE: { 01520 DEBUG(std::cerr << "Emitting FMOVDFLE\n"); 01521 Value = 2175483968U; 01522 01523 // op0: cc 01524 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01525 op0 &= (1<<3) - 1; 01526 op0 <<= 11; 01527 Value |= op0; 01528 // op1: rs2 01529 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01530 op1 &= (1<<5) - 1; 01531 Value |= op1; 01532 // op2: rd 01533 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01534 op2 &= (1<<5) - 1; 01535 op2 <<= 25; 01536 Value |= op2; 01537 break; 01538 } 01539 case V9::FMOVDFLG: { 01540 DEBUG(std::cerr << "Emitting FMOVDFLG\n"); 01541 Value = 2175303744U; 01542 01543 // op0: cc 01544 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01545 op0 &= (1<<3) - 1; 01546 op0 <<= 11; 01547 Value |= op0; 01548 // op1: rs2 01549 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01550 op1 &= (1<<5) - 1; 01551 Value |= op1; 01552 // op2: rd 01553 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01554 op2 &= (1<<5) - 1; 01555 op2 <<= 25; 01556 Value |= op2; 01557 break; 01558 } 01559 case V9::FMOVDFN: { 01560 DEBUG(std::cerr << "Emitting FMOVDFN\n"); 01561 Value = 2175270976U; 01562 01563 // op0: cc 01564 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01565 op0 &= (1<<3) - 1; 01566 op0 <<= 11; 01567 Value |= op0; 01568 // op1: rs2 01569 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01570 op1 &= (1<<5) - 1; 01571 Value |= op1; 01572 // op2: rd 01573 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01574 op2 &= (1<<5) - 1; 01575 op2 <<= 25; 01576 Value |= op2; 01577 break; 01578 } 01579 case V9::FMOVDFNE: { 01580 DEBUG(std::cerr << "Emitting FMOVDFNE\n"); 01581 Value = 2175287360U; 01582 01583 // op0: cc 01584 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01585 op0 &= (1<<3) - 1; 01586 op0 <<= 11; 01587 Value |= op0; 01588 // op1: rs2 01589 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01590 op1 &= (1<<5) - 1; 01591 Value |= op1; 01592 // op2: rd 01593 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01594 op2 &= (1<<5) - 1; 01595 op2 <<= 25; 01596 Value |= op2; 01597 break; 01598 } 01599 case V9::FMOVDFO: { 01600 DEBUG(std::cerr << "Emitting FMOVDFO\n"); 01601 Value = 2175516736U; 01602 01603 // op0: cc 01604 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01605 op0 &= (1<<3) - 1; 01606 op0 <<= 11; 01607 Value |= op0; 01608 // op1: rs2 01609 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01610 op1 &= (1<<5) - 1; 01611 Value |= op1; 01612 // op2: rd 01613 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01614 op2 &= (1<<5) - 1; 01615 op2 <<= 25; 01616 Value |= op2; 01617 break; 01618 } 01619 case V9::FMOVDFU: { 01620 DEBUG(std::cerr << "Emitting FMOVDFU\n"); 01621 Value = 2175385664U; 01622 01623 // op0: cc 01624 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01625 op0 &= (1<<3) - 1; 01626 op0 <<= 11; 01627 Value |= op0; 01628 // op1: rs2 01629 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01630 op1 &= (1<<5) - 1; 01631 Value |= op1; 01632 // op2: rd 01633 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01634 op2 &= (1<<5) - 1; 01635 op2 <<= 25; 01636 Value |= op2; 01637 break; 01638 } 01639 case V9::FMOVDFUE: { 01640 DEBUG(std::cerr << "Emitting FMOVDFUE\n"); 01641 Value = 2175434816U; 01642 01643 // op0: cc 01644 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01645 op0 &= (1<<3) - 1; 01646 op0 <<= 11; 01647 Value |= op0; 01648 // op1: rs2 01649 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01650 op1 &= (1<<5) - 1; 01651 Value |= op1; 01652 // op2: rd 01653 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01654 op2 &= (1<<5) - 1; 01655 op2 <<= 25; 01656 Value |= op2; 01657 break; 01658 } 01659 case V9::FMOVDFUG: { 01660 DEBUG(std::cerr << "Emitting FMOVDFUG\n"); 01661 Value = 2175352896U; 01662 01663 // op0: cc 01664 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01665 op0 &= (1<<3) - 1; 01666 op0 <<= 11; 01667 Value |= op0; 01668 // op1: rs2 01669 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01670 op1 &= (1<<5) - 1; 01671 Value |= op1; 01672 // op2: rd 01673 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01674 op2 &= (1<<5) - 1; 01675 op2 <<= 25; 01676 Value |= op2; 01677 break; 01678 } 01679 case V9::FMOVDFUGE: { 01680 DEBUG(std::cerr << "Emitting FMOVDFUGE\n"); 01681 Value = 2175467584U; 01682 01683 // op0: cc 01684 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01685 op0 &= (1<<3) - 1; 01686 op0 <<= 11; 01687 Value |= op0; 01688 // op1: rs2 01689 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01690 op1 &= (1<<5) - 1; 01691 Value |= op1; 01692 // op2: rd 01693 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01694 op2 &= (1<<5) - 1; 01695 op2 <<= 25; 01696 Value |= op2; 01697 break; 01698 } 01699 case V9::FMOVDFUL: { 01700 DEBUG(std::cerr << "Emitting FMOVDFUL\n"); 01701 Value = 2175320128U; 01702 01703 // op0: cc 01704 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01705 op0 &= (1<<3) - 1; 01706 op0 <<= 11; 01707 Value |= op0; 01708 // op1: rs2 01709 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01710 op1 &= (1<<5) - 1; 01711 Value |= op1; 01712 // op2: rd 01713 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01714 op2 &= (1<<5) - 1; 01715 op2 <<= 25; 01716 Value |= op2; 01717 break; 01718 } 01719 case V9::FMOVDFULE: { 01720 DEBUG(std::cerr << "Emitting FMOVDFULE\n"); 01721 Value = 2175500352U; 01722 01723 // op0: cc 01724 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01725 op0 &= (1<<3) - 1; 01726 op0 <<= 11; 01727 Value |= op0; 01728 // op1: rs2 01729 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01730 op1 &= (1<<5) - 1; 01731 Value |= op1; 01732 // op2: rd 01733 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01734 op2 &= (1<<5) - 1; 01735 op2 <<= 25; 01736 Value |= op2; 01737 break; 01738 } 01739 case V9::FMOVDG: { 01740 DEBUG(std::cerr << "Emitting FMOVDG\n"); 01741 Value = 2175434816U; 01742 01743 // op0: cc 01744 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01745 op0 &= (1<<3) - 1; 01746 op0 <<= 11; 01747 Value |= op0; 01748 // op1: rs2 01749 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01750 op1 &= (1<<5) - 1; 01751 Value |= op1; 01752 // op2: rd 01753 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01754 op2 &= (1<<5) - 1; 01755 op2 <<= 25; 01756 Value |= op2; 01757 break; 01758 } 01759 case V9::FMOVDGE: { 01760 DEBUG(std::cerr << "Emitting FMOVDGE\n"); 01761 Value = 2175451200U; 01762 01763 // op0: cc 01764 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01765 op0 &= (1<<3) - 1; 01766 op0 <<= 11; 01767 Value |= op0; 01768 // op1: rs2 01769 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01770 op1 &= (1<<5) - 1; 01771 Value |= op1; 01772 // op2: rd 01773 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01774 op2 &= (1<<5) - 1; 01775 op2 <<= 25; 01776 Value |= op2; 01777 break; 01778 } 01779 case V9::FMOVDGU: { 01780 DEBUG(std::cerr << "Emitting FMOVDGU\n"); 01781 Value = 2175467584U; 01782 01783 // op0: cc 01784 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01785 op0 &= (1<<3) - 1; 01786 op0 <<= 11; 01787 Value |= op0; 01788 // op1: rs2 01789 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01790 op1 &= (1<<5) - 1; 01791 Value |= op1; 01792 // op2: rd 01793 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01794 op2 &= (1<<5) - 1; 01795 op2 <<= 25; 01796 Value |= op2; 01797 break; 01798 } 01799 case V9::FMOVDL: { 01800 DEBUG(std::cerr << "Emitting FMOVDL\n"); 01801 Value = 2175320128U; 01802 01803 // op0: cc 01804 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01805 op0 &= (1<<3) - 1; 01806 op0 <<= 11; 01807 Value |= op0; 01808 // op1: rs2 01809 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01810 op1 &= (1<<5) - 1; 01811 Value |= op1; 01812 // op2: rd 01813 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01814 op2 &= (1<<5) - 1; 01815 op2 <<= 25; 01816 Value |= op2; 01817 break; 01818 } 01819 case V9::FMOVDLE: { 01820 DEBUG(std::cerr << "Emitting FMOVDLE\n"); 01821 Value = 2175270976U; 01822 01823 // op0: cc 01824 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01825 op0 &= (1<<3) - 1; 01826 op0 <<= 11; 01827 Value |= op0; 01828 // op1: rs2 01829 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01830 op1 &= (1<<5) - 1; 01831 Value |= op1; 01832 // op2: rd 01833 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01834 op2 &= (1<<5) - 1; 01835 op2 <<= 25; 01836 Value |= op2; 01837 break; 01838 } 01839 case V9::FMOVDLEU: { 01840 DEBUG(std::cerr << "Emitting FMOVDLEU\n"); 01841 Value = 2175336512U; 01842 01843 // op0: cc 01844 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01845 op0 &= (1<<3) - 1; 01846 op0 <<= 11; 01847 Value |= op0; 01848 // op1: rs2 01849 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01850 op1 &= (1<<5) - 1; 01851 Value |= op1; 01852 // op2: rd 01853 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01854 op2 &= (1<<5) - 1; 01855 op2 <<= 25; 01856 Value |= op2; 01857 break; 01858 } 01859 case V9::FMOVDN: { 01860 DEBUG(std::cerr << "Emitting FMOVDN\n"); 01861 Value = 2175270976U; 01862 01863 // op0: cc 01864 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01865 op0 &= (1<<3) - 1; 01866 op0 <<= 11; 01867 Value |= op0; 01868 // op1: rs2 01869 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01870 op1 &= (1<<5) - 1; 01871 Value |= op1; 01872 // op2: rd 01873 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01874 op2 &= (1<<5) - 1; 01875 op2 <<= 25; 01876 Value |= op2; 01877 break; 01878 } 01879 case V9::FMOVDNE: { 01880 DEBUG(std::cerr << "Emitting FMOVDNE\n"); 01881 Value = 2175418432U; 01882 01883 // op0: cc 01884 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01885 op0 &= (1<<3) - 1; 01886 op0 <<= 11; 01887 Value |= op0; 01888 // op1: rs2 01889 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01890 op1 &= (1<<5) - 1; 01891 Value |= op1; 01892 // op2: rd 01893 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01894 op2 &= (1<<5) - 1; 01895 op2 <<= 25; 01896 Value |= op2; 01897 break; 01898 } 01899 case V9::FMOVDNEG: { 01900 DEBUG(std::cerr << "Emitting FMOVDNEG\n"); 01901 Value = 2175369280U; 01902 01903 // op0: cc 01904 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01905 op0 &= (1<<3) - 1; 01906 op0 <<= 11; 01907 Value |= op0; 01908 // op1: rs2 01909 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01910 op1 &= (1<<5) - 1; 01911 Value |= op1; 01912 // op2: rd 01913 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01914 op2 &= (1<<5) - 1; 01915 op2 <<= 25; 01916 Value |= op2; 01917 break; 01918 } 01919 case V9::FMOVDPOS: { 01920 DEBUG(std::cerr << "Emitting FMOVDPOS\n"); 01921 Value = 2175500352U; 01922 01923 // op0: cc 01924 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01925 op0 &= (1<<3) - 1; 01926 op0 <<= 11; 01927 Value |= op0; 01928 // op1: rs2 01929 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01930 op1 &= (1<<5) - 1; 01931 Value |= op1; 01932 // op2: rd 01933 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01934 op2 &= (1<<5) - 1; 01935 op2 <<= 25; 01936 Value |= op2; 01937 break; 01938 } 01939 case V9::FMOVDVC: { 01940 DEBUG(std::cerr << "Emitting FMOVDVC\n"); 01941 Value = 2175516736U; 01942 01943 // op0: cc 01944 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01945 op0 &= (1<<3) - 1; 01946 op0 <<= 11; 01947 Value |= op0; 01948 // op1: rs2 01949 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01950 op1 &= (1<<5) - 1; 01951 Value |= op1; 01952 // op2: rd 01953 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01954 op2 &= (1<<5) - 1; 01955 op2 <<= 25; 01956 Value |= op2; 01957 break; 01958 } 01959 case V9::FMOVDVS: { 01960 DEBUG(std::cerr << "Emitting FMOVDVS\n"); 01961 Value = 2175385664U; 01962 01963 // op0: cc 01964 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01965 op0 &= (1<<3) - 1; 01966 op0 <<= 11; 01967 Value |= op0; 01968 // op1: rs2 01969 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01970 op1 &= (1<<5) - 1; 01971 Value |= op1; 01972 // op2: rd 01973 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01974 op2 &= (1<<5) - 1; 01975 op2 <<= 25; 01976 Value |= op2; 01977 break; 01978 } 01979 case V9::FMOVQA: { 01980 DEBUG(std::cerr << "Emitting FMOVQA\n"); 01981 Value = 2175402080U; 01982 01983 // op0: cc 01984 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 01985 op0 &= (1<<3) - 1; 01986 op0 <<= 11; 01987 Value |= op0; 01988 // op1: rs2 01989 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 01990 op1 &= (1<<5) - 1; 01991 Value |= op1; 01992 // op2: rd 01993 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 01994 op2 &= (1<<5) - 1; 01995 op2 <<= 25; 01996 Value |= op2; 01997 break; 01998 } 01999 case V9::FMOVQCC: { 02000 DEBUG(std::cerr << "Emitting FMOVQCC\n"); 02001 Value = 2175484000U; 02002 02003 // op0: cc 02004 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02005 op0 &= (1<<3) - 1; 02006 op0 <<= 11; 02007 Value |= op0; 02008 // op1: rs2 02009 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02010 op1 &= (1<<5) - 1; 02011 Value |= op1; 02012 // op2: rd 02013 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02014 op2 &= (1<<5) - 1; 02015 op2 <<= 25; 02016 Value |= op2; 02017 break; 02018 } 02019 case V9::FMOVQCS: { 02020 DEBUG(std::cerr << "Emitting FMOVQCS\n"); 02021 Value = 2175352928U; 02022 02023 // op0: cc 02024 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02025 op0 &= (1<<3) - 1; 02026 op0 <<= 11; 02027 Value |= op0; 02028 // op1: rs2 02029 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02030 op1 &= (1<<5) - 1; 02031 Value |= op1; 02032 // op2: rd 02033 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02034 op2 &= (1<<5) - 1; 02035 op2 <<= 25; 02036 Value |= op2; 02037 break; 02038 } 02039 case V9::FMOVQE: { 02040 DEBUG(std::cerr << "Emitting FMOVQE\n"); 02041 Value = 2175271008U; 02042 02043 // op0: cc 02044 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02045 op0 &= (1<<3) - 1; 02046 op0 <<= 11; 02047 Value |= op0; 02048 // op1: rs2 02049 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02050 op1 &= (1<<5) - 1; 02051 Value |= op1; 02052 // op2: rd 02053 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02054 op2 &= (1<<5) - 1; 02055 op2 <<= 25; 02056 Value |= op2; 02057 break; 02058 } 02059 case V9::FMOVQFA: { 02060 DEBUG(std::cerr << "Emitting FMOVQFA\n"); 02061 Value = 2175336544U; 02062 02063 // op0: cc 02064 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02065 op0 &= (1<<3) - 1; 02066 op0 <<= 11; 02067 Value |= op0; 02068 // op1: rs2 02069 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02070 op1 &= (1<<5) - 1; 02071 Value |= op1; 02072 // op2: rd 02073 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02074 op2 &= (1<<5) - 1; 02075 op2 <<= 25; 02076 Value |= op2; 02077 break; 02078 } 02079 case V9::FMOVQFE: { 02080 DEBUG(std::cerr << "Emitting FMOVQFE\n"); 02081 Value = 2175418464U; 02082 02083 // op0: cc 02084 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02085 op0 &= (1<<3) - 1; 02086 op0 <<= 11; 02087 Value |= op0; 02088 // op1: rs2 02089 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02090 op1 &= (1<<5) - 1; 02091 Value |= op1; 02092 // op2: rd 02093 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02094 op2 &= (1<<5) - 1; 02095 op2 <<= 25; 02096 Value |= op2; 02097 break; 02098 } 02099 case V9::FMOVQFG: { 02100 DEBUG(std::cerr << "Emitting FMOVQFG\n"); 02101 Value = 2175369312U; 02102 02103 // op0: cc 02104 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02105 op0 &= (1<<3) - 1; 02106 op0 <<= 11; 02107 Value |= op0; 02108 // op1: rs2 02109 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02110 op1 &= (1<<5) - 1; 02111 Value |= op1; 02112 // op2: rd 02113 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02114 op2 &= (1<<5) - 1; 02115 op2 <<= 25; 02116 Value |= op2; 02117 break; 02118 } 02119 case V9::FMOVQFGE: { 02120 DEBUG(std::cerr << "Emitting FMOVQFGE\n"); 02121 Value = 2175451232U; 02122 02123 // op0: cc 02124 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02125 op0 &= (1<<3) - 1; 02126 op0 <<= 11; 02127 Value |= op0; 02128 // op1: rs2 02129 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02130 op1 &= (1<<5) - 1; 02131 Value |= op1; 02132 // op2: rd 02133 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02134 op2 &= (1<<5) - 1; 02135 op2 <<= 25; 02136 Value |= op2; 02137 break; 02138 } 02139 case V9::FMOVQFL: { 02140 DEBUG(std::cerr << "Emitting FMOVQFL\n"); 02141 Value = 2175336544U; 02142 02143 // op0: cc 02144 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02145 op0 &= (1<<3) - 1; 02146 op0 <<= 11; 02147 Value |= op0; 02148 // op1: rs2 02149 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02150 op1 &= (1<<5) - 1; 02151 Value |= op1; 02152 // op2: rd 02153 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02154 op2 &= (1<<5) - 1; 02155 op2 <<= 25; 02156 Value |= op2; 02157 break; 02158 } 02159 case V9::FMOVQFLE: { 02160 DEBUG(std::cerr << "Emitting FMOVQFLE\n"); 02161 Value = 2175484000U; 02162 02163 // op0: cc 02164 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02165 op0 &= (1<<3) - 1; 02166 op0 <<= 11; 02167 Value |= op0; 02168 // op1: rs2 02169 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02170 op1 &= (1<<5) - 1; 02171 Value |= op1; 02172 // op2: rd 02173 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02174 op2 &= (1<<5) - 1; 02175 op2 <<= 25; 02176 Value |= op2; 02177 break; 02178 } 02179 case V9::FMOVQFLG: { 02180 DEBUG(std::cerr << "Emitting FMOVQFLG\n"); 02181 Value = 2175303776U; 02182 02183 // op0: cc 02184 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02185 op0 &= (1<<3) - 1; 02186 op0 <<= 11; 02187 Value |= op0; 02188 // op1: rs2 02189 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02190 op1 &= (1<<5) - 1; 02191 Value |= op1; 02192 // op2: rd 02193 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02194 op2 &= (1<<5) - 1; 02195 op2 <<= 25; 02196 Value |= op2; 02197 break; 02198 } 02199 case V9::FMOVQFN: { 02200 DEBUG(std::cerr << "Emitting FMOVQFN\n"); 02201 Value = 2175271008U; 02202 02203 // op0: cc 02204 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02205 op0 &= (1<<3) - 1; 02206 op0 <<= 11; 02207 Value |= op0; 02208 // op1: rs2 02209 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02210 op1 &= (1<<5) - 1; 02211 Value |= op1; 02212 // op2: rd 02213 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02214 op2 &= (1<<5) - 1; 02215 op2 <<= 25; 02216 Value |= op2; 02217 break; 02218 } 02219 case V9::FMOVQFNE: { 02220 DEBUG(std::cerr << "Emitting FMOVQFNE\n"); 02221 Value = 2175287392U; 02222 02223 // op0: cc 02224 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02225 op0 &= (1<<3) - 1; 02226 op0 <<= 11; 02227 Value |= op0; 02228 // op1: rs2 02229 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02230 op1 &= (1<<5) - 1; 02231 Value |= op1; 02232 // op2: rd 02233 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02234 op2 &= (1<<5) - 1; 02235 op2 <<= 25; 02236 Value |= op2; 02237 break; 02238 } 02239 case V9::FMOVQFO: { 02240 DEBUG(std::cerr << "Emitting FMOVQFO\n"); 02241 Value = 2175516768U; 02242 02243 // op0: cc 02244 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02245 op0 &= (1<<3) - 1; 02246 op0 <<= 11; 02247 Value |= op0; 02248 // op1: rs2 02249 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02250 op1 &= (1<<5) - 1; 02251 Value |= op1; 02252 // op2: rd 02253 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02254 op2 &= (1<<5) - 1; 02255 op2 <<= 25; 02256 Value |= op2; 02257 break; 02258 } 02259 case V9::FMOVQFU: { 02260 DEBUG(std::cerr << "Emitting FMOVQFU\n"); 02261 Value = 2175385696U; 02262 02263 // op0: cc 02264 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02265 op0 &= (1<<3) - 1; 02266 op0 <<= 11; 02267 Value |= op0; 02268 // op1: rs2 02269 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02270 op1 &= (1<<5) - 1; 02271 Value |= op1; 02272 // op2: rd 02273 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02274 op2 &= (1<<5) - 1; 02275 op2 <<= 25; 02276 Value |= op2; 02277 break; 02278 } 02279 case V9::FMOVQFUE: { 02280 DEBUG(std::cerr << "Emitting FMOVQFUE\n"); 02281 Value = 2175434848U; 02282 02283 // op0: cc 02284 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02285 op0 &= (1<<3) - 1; 02286 op0 <<= 11; 02287 Value |= op0; 02288 // op1: rs2 02289 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02290 op1 &= (1<<5) - 1; 02291 Value |= op1; 02292 // op2: rd 02293 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02294 op2 &= (1<<5) - 1; 02295 op2 <<= 25; 02296 Value |= op2; 02297 break; 02298 } 02299 case V9::FMOVQFUG: { 02300 DEBUG(std::cerr << "Emitting FMOVQFUG\n"); 02301 Value = 2175352928U; 02302 02303 // op0: cc 02304 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02305 op0 &= (1<<3) - 1; 02306 op0 <<= 11; 02307 Value |= op0; 02308 // op1: rs2 02309 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02310 op1 &= (1<<5) - 1; 02311 Value |= op1; 02312 // op2: rd 02313 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02314 op2 &= (1<<5) - 1; 02315 op2 <<= 25; 02316 Value |= op2; 02317 break; 02318 } 02319 case V9::FMOVQFUGE: { 02320 DEBUG(std::cerr << "Emitting FMOVQFUGE\n"); 02321 Value = 2175467616U; 02322 02323 // op0: cc 02324 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02325 op0 &= (1<<3) - 1; 02326 op0 <<= 11; 02327 Value |= op0; 02328 // op1: rs2 02329 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02330 op1 &= (1<<5) - 1; 02331 Value |= op1; 02332 // op2: rd 02333 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02334 op2 &= (1<<5) - 1; 02335 op2 <<= 25; 02336 Value |= op2; 02337 break; 02338 } 02339 case V9::FMOVQFUL: { 02340 DEBUG(std::cerr << "Emitting FMOVQFUL\n"); 02341 Value = 2175320160U; 02342 02343 // op0: cc 02344 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02345 op0 &= (1<<3) - 1; 02346 op0 <<= 11; 02347 Value |= op0; 02348 // op1: rs2 02349 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02350 op1 &= (1<<5) - 1; 02351 Value |= op1; 02352 // op2: rd 02353 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02354 op2 &= (1<<5) - 1; 02355 op2 <<= 25; 02356 Value |= op2; 02357 break; 02358 } 02359 case V9::FMOVQFULE: { 02360 DEBUG(std::cerr << "Emitting FMOVQFULE\n"); 02361 Value = 2175500384U; 02362 02363 // op0: cc 02364 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02365 op0 &= (1<<3) - 1; 02366 op0 <<= 11; 02367 Value |= op0; 02368 // op1: rs2 02369 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02370 op1 &= (1<<5) - 1; 02371 Value |= op1; 02372 // op2: rd 02373 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02374 op2 &= (1<<5) - 1; 02375 op2 <<= 25; 02376 Value |= op2; 02377 break; 02378 } 02379 case V9::FMOVQG: { 02380 DEBUG(std::cerr << "Emitting FMOVQG\n"); 02381 Value = 2175434848U; 02382 02383 // op0: cc 02384 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02385 op0 &= (1<<3) - 1; 02386 op0 <<= 11; 02387 Value |= op0; 02388 // op1: rs2 02389 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02390 op1 &= (1<<5) - 1; 02391 Value |= op1; 02392 // op2: rd 02393 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02394 op2 &= (1<<5) - 1; 02395 op2 <<= 25; 02396 Value |= op2; 02397 break; 02398 } 02399 case V9::FMOVQGE: { 02400 DEBUG(std::cerr << "Emitting FMOVQGE\n"); 02401 Value = 2175451232U; 02402 02403 // op0: cc 02404 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02405 op0 &= (1<<3) - 1; 02406 op0 <<= 11; 02407 Value |= op0; 02408 // op1: rs2 02409 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02410 op1 &= (1<<5) - 1; 02411 Value |= op1; 02412 // op2: rd 02413 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02414 op2 &= (1<<5) - 1; 02415 op2 <<= 25; 02416 Value |= op2; 02417 break; 02418 } 02419 case V9::FMOVQGU: { 02420 DEBUG(std::cerr << "Emitting FMOVQGU\n"); 02421 Value = 2175467616U; 02422 02423 // op0: cc 02424 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02425 op0 &= (1<<3) - 1; 02426 op0 <<= 11; 02427 Value |= op0; 02428 // op1: rs2 02429 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02430 op1 &= (1<<5) - 1; 02431 Value |= op1; 02432 // op2: rd 02433 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02434 op2 &= (1<<5) - 1; 02435 op2 <<= 25; 02436 Value |= op2; 02437 break; 02438 } 02439 case V9::FMOVQL: { 02440 DEBUG(std::cerr << "Emitting FMOVQL\n"); 02441 Value = 2175320160U; 02442 02443 // op0: cc 02444 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02445 op0 &= (1<<3) - 1; 02446 op0 <<= 11; 02447 Value |= op0; 02448 // op1: rs2 02449 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02450 op1 &= (1<<5) - 1; 02451 Value |= op1; 02452 // op2: rd 02453 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02454 op2 &= (1<<5) - 1; 02455 op2 <<= 25; 02456 Value |= op2; 02457 break; 02458 } 02459 case V9::FMOVQLE: { 02460 DEBUG(std::cerr << "Emitting FMOVQLE\n"); 02461 Value = 2175271008U; 02462 02463 // op0: cc 02464 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02465 op0 &= (1<<3) - 1; 02466 op0 <<= 11; 02467 Value |= op0; 02468 // op1: rs2 02469 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02470 op1 &= (1<<5) - 1; 02471 Value |= op1; 02472 // op2: rd 02473 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02474 op2 &= (1<<5) - 1; 02475 op2 <<= 25; 02476 Value |= op2; 02477 break; 02478 } 02479 case V9::FMOVQLEU: { 02480 DEBUG(std::cerr << "Emitting FMOVQLEU\n"); 02481 Value = 2175336544U; 02482 02483 // op0: cc 02484 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02485 op0 &= (1<<3) - 1; 02486 op0 <<= 11; 02487 Value |= op0; 02488 // op1: rs2 02489 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02490 op1 &= (1<<5) - 1; 02491 Value |= op1; 02492 // op2: rd 02493 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02494 op2 &= (1<<5) - 1; 02495 op2 <<= 25; 02496 Value |= op2; 02497 break; 02498 } 02499 case V9::FMOVQN: { 02500 DEBUG(std::cerr << "Emitting FMOVQN\n"); 02501 Value = 2175271008U; 02502 02503 // op0: cc 02504 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02505 op0 &= (1<<3) - 1; 02506 op0 <<= 11; 02507 Value |= op0; 02508 // op1: rs2 02509 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02510 op1 &= (1<<5) - 1; 02511 Value |= op1; 02512 // op2: rd 02513 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02514 op2 &= (1<<5) - 1; 02515 op2 <<= 25; 02516 Value |= op2; 02517 break; 02518 } 02519 case V9::FMOVQNE: { 02520 DEBUG(std::cerr << "Emitting FMOVQNE\n"); 02521 Value = 2175418464U; 02522 02523 // op0: cc 02524 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02525 op0 &= (1<<3) - 1; 02526 op0 <<= 11; 02527 Value |= op0; 02528 // op1: rs2 02529 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02530 op1 &= (1<<5) - 1; 02531 Value |= op1; 02532 // op2: rd 02533 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02534 op2 &= (1<<5) - 1; 02535 op2 <<= 25; 02536 Value |= op2; 02537 break; 02538 } 02539 case V9::FMOVQNEG: { 02540 DEBUG(std::cerr << "Emitting FMOVQNEG\n"); 02541 Value = 2175369312U; 02542 02543 // op0: cc 02544 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02545 op0 &= (1<<3) - 1; 02546 op0 <<= 11; 02547 Value |= op0; 02548 // op1: rs2 02549 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02550 op1 &= (1<<5) - 1; 02551 Value |= op1; 02552 // op2: rd 02553 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02554 op2 &= (1<<5) - 1; 02555 op2 <<= 25; 02556 Value |= op2; 02557 break; 02558 } 02559 case V9::FMOVQPOS: { 02560 DEBUG(std::cerr << "Emitting FMOVQPOS\n"); 02561 Value = 2175500384U; 02562 02563 // op0: cc 02564 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02565 op0 &= (1<<3) - 1; 02566 op0 <<= 11; 02567 Value |= op0; 02568 // op1: rs2 02569 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02570 op1 &= (1<<5) - 1; 02571 Value |= op1; 02572 // op2: rd 02573 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02574 op2 &= (1<<5) - 1; 02575 op2 <<= 25; 02576 Value |= op2; 02577 break; 02578 } 02579 case V9::FMOVQVC: { 02580 DEBUG(std::cerr << "Emitting FMOVQVC\n"); 02581 Value = 2175516768U; 02582 02583 // op0: cc 02584 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02585 op0 &= (1<<3) - 1; 02586 op0 <<= 11; 02587 Value |= op0; 02588 // op1: rs2 02589 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02590 op1 &= (1<<5) - 1; 02591 Value |= op1; 02592 // op2: rd 02593 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02594 op2 &= (1<<5) - 1; 02595 op2 <<= 25; 02596 Value |= op2; 02597 break; 02598 } 02599 case V9::FMOVQVS: { 02600 DEBUG(std::cerr << "Emitting FMOVQVS\n"); 02601 Value = 2175385696U; 02602 02603 // op0: cc 02604 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02605 op0 &= (1<<3) - 1; 02606 op0 <<= 11; 02607 Value |= op0; 02608 // op1: rs2 02609 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02610 op1 &= (1<<5) - 1; 02611 Value |= op1; 02612 // op2: rd 02613 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02614 op2 &= (1<<5) - 1; 02615 op2 <<= 25; 02616 Value |= op2; 02617 break; 02618 } 02619 case V9::FMOVRDGEZ: { 02620 DEBUG(std::cerr << "Emitting FMOVRDGEZ\n"); 02621 Value = 2175278272U; 02622 02623 // op0: rs1 02624 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02625 op0 &= (1<<5) - 1; 02626 op0 <<= 14; 02627 Value |= op0; 02628 // op1: rs2 02629 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02630 op1 &= (1<<5) - 1; 02631 Value |= op1; 02632 // op2: rd 02633 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02634 op2 &= (1<<5) - 1; 02635 op2 <<= 25; 02636 Value |= op2; 02637 break; 02638 } 02639 case V9::FMOVRDGZ: { 02640 DEBUG(std::cerr << "Emitting FMOVRDGZ\n"); 02641 Value = 2175277248U; 02642 02643 // op0: rs1 02644 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02645 op0 &= (1<<5) - 1; 02646 op0 <<= 14; 02647 Value |= op0; 02648 // op1: rs2 02649 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02650 op1 &= (1<<5) - 1; 02651 Value |= op1; 02652 // op2: rd 02653 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02654 op2 &= (1<<5) - 1; 02655 op2 <<= 25; 02656 Value |= op2; 02657 break; 02658 } 02659 case V9::FMOVRDLEZ: { 02660 DEBUG(std::cerr << "Emitting FMOVRDLEZ\n"); 02661 Value = 2175273152U; 02662 02663 // op0: rs1 02664 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02665 op0 &= (1<<5) - 1; 02666 op0 <<= 14; 02667 Value |= op0; 02668 // op1: rs2 02669 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02670 op1 &= (1<<5) - 1; 02671 Value |= op1; 02672 // op2: rd 02673 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02674 op2 &= (1<<5) - 1; 02675 op2 <<= 25; 02676 Value |= op2; 02677 break; 02678 } 02679 case V9::FMOVRDLZ: { 02680 DEBUG(std::cerr << "Emitting FMOVRDLZ\n"); 02681 Value = 2175274176U; 02682 02683 // op0: rs1 02684 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02685 op0 &= (1<<5) - 1; 02686 op0 <<= 14; 02687 Value |= op0; 02688 // op1: rs2 02689 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02690 op1 &= (1<<5) - 1; 02691 Value |= op1; 02692 // op2: rd 02693 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02694 op2 &= (1<<5) - 1; 02695 op2 <<= 25; 02696 Value |= op2; 02697 break; 02698 } 02699 case V9::FMOVRDNZ: { 02700 DEBUG(std::cerr << "Emitting FMOVRDNZ\n"); 02701 Value = 2175276224U; 02702 02703 // op0: rs1 02704 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02705 op0 &= (1<<5) - 1; 02706 op0 <<= 14; 02707 Value |= op0; 02708 // op1: rs2 02709 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02710 op1 &= (1<<5) - 1; 02711 Value |= op1; 02712 // op2: rd 02713 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02714 op2 &= (1<<5) - 1; 02715 op2 <<= 25; 02716 Value |= op2; 02717 break; 02718 } 02719 case V9::FMOVRDZ: { 02720 DEBUG(std::cerr << "Emitting FMOVRDZ\n"); 02721 Value = 2175272128U; 02722 02723 // op0: rs1 02724 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02725 op0 &= (1<<5) - 1; 02726 op0 <<= 14; 02727 Value |= op0; 02728 // op1: rs2 02729 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02730 op1 &= (1<<5) - 1; 02731 Value |= op1; 02732 // op2: rd 02733 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02734 op2 &= (1<<5) - 1; 02735 op2 <<= 25; 02736 Value |= op2; 02737 break; 02738 } 02739 case V9::FMOVRQGEZ: { 02740 DEBUG(std::cerr << "Emitting FMOVRQGEZ\n"); 02741 Value = 2175278304U; 02742 02743 // op0: rs1 02744 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02745 op0 &= (1<<5) - 1; 02746 op0 <<= 14; 02747 Value |= op0; 02748 // op1: rs2 02749 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02750 op1 &= (1<<5) - 1; 02751 Value |= op1; 02752 // op2: rd 02753 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02754 op2 &= (1<<5) - 1; 02755 op2 <<= 25; 02756 Value |= op2; 02757 break; 02758 } 02759 case V9::FMOVRQGZ: { 02760 DEBUG(std::cerr << "Emitting FMOVRQGZ\n"); 02761 Value = 2175277280U; 02762 02763 // op0: rs1 02764 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02765 op0 &= (1<<5) - 1; 02766 op0 <<= 14; 02767 Value |= op0; 02768 // op1: rs2 02769 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02770 op1 &= (1<<5) - 1; 02771 Value |= op1; 02772 // op2: rd 02773 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02774 op2 &= (1<<5) - 1; 02775 op2 <<= 25; 02776 Value |= op2; 02777 break; 02778 } 02779 case V9::FMOVRQLEZ: { 02780 DEBUG(std::cerr << "Emitting FMOVRQLEZ\n"); 02781 Value = 2175273184U; 02782 02783 // op0: rs1 02784 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02785 op0 &= (1<<5) - 1; 02786 op0 <<= 14; 02787 Value |= op0; 02788 // op1: rs2 02789 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02790 op1 &= (1<<5) - 1; 02791 Value |= op1; 02792 // op2: rd 02793 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02794 op2 &= (1<<5) - 1; 02795 op2 <<= 25; 02796 Value |= op2; 02797 break; 02798 } 02799 case V9::FMOVRQLZ: { 02800 DEBUG(std::cerr << "Emitting FMOVRQLZ\n"); 02801 Value = 2175274208U; 02802 02803 // op0: rs1 02804 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02805 op0 &= (1<<5) - 1; 02806 op0 <<= 14; 02807 Value |= op0; 02808 // op1: rs2 02809 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02810 op1 &= (1<<5) - 1; 02811 Value |= op1; 02812 // op2: rd 02813 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02814 op2 &= (1<<5) - 1; 02815 op2 <<= 25; 02816 Value |= op2; 02817 break; 02818 } 02819 case V9::FMOVRQNZ: { 02820 DEBUG(std::cerr << "Emitting FMOVRQNZ\n"); 02821 Value = 2175276256U; 02822 02823 // op0: rs1 02824 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02825 op0 &= (1<<5) - 1; 02826 op0 <<= 14; 02827 Value |= op0; 02828 // op1: rs2 02829 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02830 op1 &= (1<<5) - 1; 02831 Value |= op1; 02832 // op2: rd 02833 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02834 op2 &= (1<<5) - 1; 02835 op2 <<= 25; 02836 Value |= op2; 02837 break; 02838 } 02839 case V9::FMOVRQZ: { 02840 DEBUG(std::cerr << "Emitting FMOVRQZ\n"); 02841 Value = 2175272160U; 02842 02843 // op0: rs1 02844 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02845 op0 &= (1<<5) - 1; 02846 op0 <<= 14; 02847 Value |= op0; 02848 // op1: rs2 02849 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02850 op1 &= (1<<5) - 1; 02851 Value |= op1; 02852 // op2: rd 02853 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02854 op2 &= (1<<5) - 1; 02855 op2 <<= 25; 02856 Value |= op2; 02857 break; 02858 } 02859 case V9::FMOVRSGEZ: { 02860 DEBUG(std::cerr << "Emitting FMOVRSGEZ\n"); 02861 Value = 2175278240U; 02862 02863 // op0: rs1 02864 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02865 op0 &= (1<<5) - 1; 02866 op0 <<= 14; 02867 Value |= op0; 02868 // op1: rs2 02869 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02870 op1 &= (1<<5) - 1; 02871 Value |= op1; 02872 // op2: rd 02873 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02874 op2 &= (1<<5) - 1; 02875 op2 <<= 25; 02876 Value |= op2; 02877 break; 02878 } 02879 case V9::FMOVRSGZ: { 02880 DEBUG(std::cerr << "Emitting FMOVRSGZ\n"); 02881 Value = 2175277216U; 02882 02883 // op0: rs1 02884 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02885 op0 &= (1<<5) - 1; 02886 op0 <<= 14; 02887 Value |= op0; 02888 // op1: rs2 02889 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02890 op1 &= (1<<5) - 1; 02891 Value |= op1; 02892 // op2: rd 02893 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02894 op2 &= (1<<5) - 1; 02895 op2 <<= 25; 02896 Value |= op2; 02897 break; 02898 } 02899 case V9::FMOVRSLEZ: { 02900 DEBUG(std::cerr << "Emitting FMOVRSLEZ\n"); 02901 Value = 2175273120U; 02902 02903 // op0: rs1 02904 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02905 op0 &= (1<<5) - 1; 02906 op0 <<= 14; 02907 Value |= op0; 02908 // op1: rs2 02909 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02910 op1 &= (1<<5) - 1; 02911 Value |= op1; 02912 // op2: rd 02913 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02914 op2 &= (1<<5) - 1; 02915 op2 <<= 25; 02916 Value |= op2; 02917 break; 02918 } 02919 case V9::FMOVRSLZ: { 02920 DEBUG(std::cerr << "Emitting FMOVRSLZ\n"); 02921 Value = 2175274144U; 02922 02923 // op0: rs1 02924 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02925 op0 &= (1<<5) - 1; 02926 op0 <<= 14; 02927 Value |= op0; 02928 // op1: rs2 02929 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02930 op1 &= (1<<5) - 1; 02931 Value |= op1; 02932 // op2: rd 02933 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02934 op2 &= (1<<5) - 1; 02935 op2 <<= 25; 02936 Value |= op2; 02937 break; 02938 } 02939 case V9::FMOVRSNZ: { 02940 DEBUG(std::cerr << "Emitting FMOVRSNZ\n"); 02941 Value = 2175276192U; 02942 02943 // op0: rs1 02944 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02945 op0 &= (1<<5) - 1; 02946 op0 <<= 14; 02947 Value |= op0; 02948 // op1: rs2 02949 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02950 op1 &= (1<<5) - 1; 02951 Value |= op1; 02952 // op2: rd 02953 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02954 op2 &= (1<<5) - 1; 02955 op2 <<= 25; 02956 Value |= op2; 02957 break; 02958 } 02959 case V9::FMOVRSZ: { 02960 DEBUG(std::cerr << "Emitting FMOVRSZ\n"); 02961 Value = 2175272096U; 02962 02963 // op0: rs1 02964 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02965 op0 &= (1<<5) - 1; 02966 op0 <<= 14; 02967 Value |= op0; 02968 // op1: rs2 02969 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02970 op1 &= (1<<5) - 1; 02971 Value |= op1; 02972 // op2: rd 02973 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 02974 op2 &= (1<<5) - 1; 02975 op2 <<= 25; 02976 Value |= op2; 02977 break; 02978 } 02979 case V9::FMOVS: { 02980 DEBUG(std::cerr << "Emitting FMOVS\n"); 02981 Value = 2174746656U; 02982 02983 // op0: rs2 02984 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 02985 op0 &= (1<<5) - 1; 02986 Value |= op0; 02987 // op1: rd 02988 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 02989 op1 &= (1<<5) - 1; 02990 op1 <<= 25; 02991 Value |= op1; 02992 break; 02993 } 02994 case V9::FMOVSA: { 02995 DEBUG(std::cerr << "Emitting FMOVSA\n"); 02996 Value = 2175402016U; 02997 02998 // op0: cc 02999 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03000 op0 &= (1<<3) - 1; 03001 op0 <<= 11; 03002 Value |= op0; 03003 // op1: rs2 03004 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03005 op1 &= (1<<5) - 1; 03006 Value |= op1; 03007 // op2: rd 03008 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03009 op2 &= (1<<5) - 1; 03010 op2 <<= 25; 03011 Value |= op2; 03012 break; 03013 } 03014 case V9::FMOVSCC: { 03015 DEBUG(std::cerr << "Emitting FMOVSCC\n"); 03016 Value = 2175483936U; 03017 03018 // op0: cc 03019 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03020 op0 &= (1<<3) - 1; 03021 op0 <<= 11; 03022 Value |= op0; 03023 // op1: rs2 03024 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03025 op1 &= (1<<5) - 1; 03026 Value |= op1; 03027 // op2: rd 03028 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03029 op2 &= (1<<5) - 1; 03030 op2 <<= 25; 03031 Value |= op2; 03032 break; 03033 } 03034 case V9::FMOVSCS: { 03035 DEBUG(std::cerr << "Emitting FMOVSCS\n"); 03036 Value = 2175352864U; 03037 03038 // op0: cc 03039 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03040 op0 &= (1<<3) - 1; 03041 op0 <<= 11; 03042 Value |= op0; 03043 // op1: rs2 03044 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03045 op1 &= (1<<5) - 1; 03046 Value |= op1; 03047 // op2: rd 03048 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03049 op2 &= (1<<5) - 1; 03050 op2 <<= 25; 03051 Value |= op2; 03052 break; 03053 } 03054 case V9::FMOVSE: { 03055 DEBUG(std::cerr << "Emitting FMOVSE\n"); 03056 Value = 2175270944U; 03057 03058 // op0: cc 03059 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03060 op0 &= (1<<3) - 1; 03061 op0 <<= 11; 03062 Value |= op0; 03063 // op1: rs2 03064 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03065 op1 &= (1<<5) - 1; 03066 Value |= op1; 03067 // op2: rd 03068 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03069 op2 &= (1<<5) - 1; 03070 op2 <<= 25; 03071 Value |= op2; 03072 break; 03073 } 03074 case V9::FMOVSFA: { 03075 DEBUG(std::cerr << "Emitting FMOVSFA\n"); 03076 Value = 2175336480U; 03077 03078 // op0: cc 03079 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03080 op0 &= (1<<3) - 1; 03081 op0 <<= 11; 03082 Value |= op0; 03083 // op1: rs2 03084 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03085 op1 &= (1<<5) - 1; 03086 Value |= op1; 03087 // op2: rd 03088 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03089 op2 &= (1<<5) - 1; 03090 op2 <<= 25; 03091 Value |= op2; 03092 break; 03093 } 03094 case V9::FMOVSFE: { 03095 DEBUG(std::cerr << "Emitting FMOVSFE\n"); 03096 Value = 2175418400U; 03097 03098 // op0: cc 03099 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03100 op0 &= (1<<3) - 1; 03101 op0 <<= 11; 03102 Value |= op0; 03103 // op1: rs2 03104 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03105 op1 &= (1<<5) - 1; 03106 Value |= op1; 03107 // op2: rd 03108 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03109 op2 &= (1<<5) - 1; 03110 op2 <<= 25; 03111 Value |= op2; 03112 break; 03113 } 03114 case V9::FMOVSFG: { 03115 DEBUG(std::cerr << "Emitting FMOVSFG\n"); 03116 Value = 2175369248U; 03117 03118 // op0: cc 03119 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03120 op0 &= (1<<3) - 1; 03121 op0 <<= 11; 03122 Value |= op0; 03123 // op1: rs2 03124 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03125 op1 &= (1<<5) - 1; 03126 Value |= op1; 03127 // op2: rd 03128 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03129 op2 &= (1<<5) - 1; 03130 op2 <<= 25; 03131 Value |= op2; 03132 break; 03133 } 03134 case V9::FMOVSFGE: { 03135 DEBUG(std::cerr << "Emitting FMOVSFGE\n"); 03136 Value = 2175451168U; 03137 03138 // op0: cc 03139 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03140 op0 &= (1<<3) - 1; 03141 op0 <<= 11; 03142 Value |= op0; 03143 // op1: rs2 03144 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03145 op1 &= (1<<5) - 1; 03146 Value |= op1; 03147 // op2: rd 03148 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03149 op2 &= (1<<5) - 1; 03150 op2 <<= 25; 03151 Value |= op2; 03152 break; 03153 } 03154 case V9::FMOVSFL: { 03155 DEBUG(std::cerr << "Emitting FMOVSFL\n"); 03156 Value = 2175336480U; 03157 03158 // op0: cc 03159 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03160 op0 &= (1<<3) - 1; 03161 op0 <<= 11; 03162 Value |= op0; 03163 // op1: rs2 03164 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03165 op1 &= (1<<5) - 1; 03166 Value |= op1; 03167 // op2: rd 03168 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03169 op2 &= (1<<5) - 1; 03170 op2 <<= 25; 03171 Value |= op2; 03172 break; 03173 } 03174 case V9::FMOVSFLE: { 03175 DEBUG(std::cerr << "Emitting FMOVSFLE\n"); 03176 Value = 2175483936U; 03177 03178 // op0: cc 03179 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03180 op0 &= (1<<3) - 1; 03181 op0 <<= 11; 03182 Value |= op0; 03183 // op1: rs2 03184 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03185 op1 &= (1<<5) - 1; 03186 Value |= op1; 03187 // op2: rd 03188 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03189 op2 &= (1<<5) - 1; 03190 op2 <<= 25; 03191 Value |= op2; 03192 break; 03193 } 03194 case V9::FMOVSFLG: { 03195 DEBUG(std::cerr << "Emitting FMOVSFLG\n"); 03196 Value = 2175303712U; 03197 03198 // op0: cc 03199 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03200 op0 &= (1<<3) - 1; 03201 op0 <<= 11; 03202 Value |= op0; 03203 // op1: rs2 03204 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03205 op1 &= (1<<5) - 1; 03206 Value |= op1; 03207 // op2: rd 03208 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03209 op2 &= (1<<5) - 1; 03210 op2 <<= 25; 03211 Value |= op2; 03212 break; 03213 } 03214 case V9::FMOVSFN: { 03215 DEBUG(std::cerr << "Emitting FMOVSFN\n"); 03216 Value = 2175270944U; 03217 03218 // op0: cc 03219 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03220 op0 &= (1<<3) - 1; 03221 op0 <<= 11; 03222 Value |= op0; 03223 // op1: rs2 03224 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03225 op1 &= (1<<5) - 1; 03226 Value |= op1; 03227 // op2: rd 03228 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03229 op2 &= (1<<5) - 1; 03230 op2 <<= 25; 03231 Value |= op2; 03232 break; 03233 } 03234 case V9::FMOVSFNE: { 03235 DEBUG(std::cerr << "Emitting FMOVSFNE\n"); 03236 Value = 2175287328U; 03237 03238 // op0: cc 03239 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03240 op0 &= (1<<3) - 1; 03241 op0 <<= 11; 03242 Value |= op0; 03243 // op1: rs2 03244 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03245 op1 &= (1<<5) - 1; 03246 Value |= op1; 03247 // op2: rd 03248 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03249 op2 &= (1<<5) - 1; 03250 op2 <<= 25; 03251 Value |= op2; 03252 break; 03253 } 03254 case V9::FMOVSFO: { 03255 DEBUG(std::cerr << "Emitting FMOVSFO\n"); 03256 Value = 2175516704U; 03257 03258 // op0: cc 03259 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03260 op0 &= (1<<3) - 1; 03261 op0 <<= 11; 03262 Value |= op0; 03263 // op1: rs2 03264 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03265 op1 &= (1<<5) - 1; 03266 Value |= op1; 03267 // op2: rd 03268 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03269 op2 &= (1<<5) - 1; 03270 op2 <<= 25; 03271 Value |= op2; 03272 break; 03273 } 03274 case V9::FMOVSFU: { 03275 DEBUG(std::cerr << "Emitting FMOVSFU\n"); 03276 Value = 2175385632U; 03277 03278 // op0: cc 03279 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03280 op0 &= (1<<3) - 1; 03281 op0 <<= 11; 03282 Value |= op0; 03283 // op1: rs2 03284 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03285 op1 &= (1<<5) - 1; 03286 Value |= op1; 03287 // op2: rd 03288 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03289 op2 &= (1<<5) - 1; 03290 op2 <<= 25; 03291 Value |= op2; 03292 break; 03293 } 03294 case V9::FMOVSFUE: { 03295 DEBUG(std::cerr << "Emitting FMOVSFUE\n"); 03296 Value = 2175434784U; 03297 03298 // op0: cc 03299 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03300 op0 &= (1<<3) - 1; 03301 op0 <<= 11; 03302 Value |= op0; 03303 // op1: rs2 03304 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03305 op1 &= (1<<5) - 1; 03306 Value |= op1; 03307 // op2: rd 03308 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03309 op2 &= (1<<5) - 1; 03310 op2 <<= 25; 03311 Value |= op2; 03312 break; 03313 } 03314 case V9::FMOVSFUG: { 03315 DEBUG(std::cerr << "Emitting FMOVSFUG\n"); 03316 Value = 2175352864U; 03317 03318 // op0: cc 03319 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03320 op0 &= (1<<3) - 1; 03321 op0 <<= 11; 03322 Value |= op0; 03323 // op1: rs2 03324 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03325 op1 &= (1<<5) - 1; 03326 Value |= op1; 03327 // op2: rd 03328 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03329 op2 &= (1<<5) - 1; 03330 op2 <<= 25; 03331 Value |= op2; 03332 break; 03333 } 03334 case V9::FMOVSFUGE: { 03335 DEBUG(std::cerr << "Emitting FMOVSFUGE\n"); 03336 Value = 2175467552U; 03337 03338 // op0: cc 03339 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03340 op0 &= (1<<3) - 1; 03341 op0 <<= 11; 03342 Value |= op0; 03343 // op1: rs2 03344 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03345 op1 &= (1<<5) - 1; 03346 Value |= op1; 03347 // op2: rd 03348 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03349 op2 &= (1<<5) - 1; 03350 op2 <<= 25; 03351 Value |= op2; 03352 break; 03353 } 03354 case V9::FMOVSFUL: { 03355 DEBUG(std::cerr << "Emitting FMOVSFUL\n"); 03356 Value = 2175320096U; 03357 03358 // op0: cc 03359 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03360 op0 &= (1<<3) - 1; 03361 op0 <<= 11; 03362 Value |= op0; 03363 // op1: rs2 03364 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03365 op1 &= (1<<5) - 1; 03366 Value |= op1; 03367 // op2: rd 03368 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03369 op2 &= (1<<5) - 1; 03370 op2 <<= 25; 03371 Value |= op2; 03372 break; 03373 } 03374 case V9::FMOVSFULE: { 03375 DEBUG(std::cerr << "Emitting FMOVSFULE\n"); 03376 Value = 2175500320U; 03377 03378 // op0: cc 03379 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03380 op0 &= (1<<3) - 1; 03381 op0 <<= 11; 03382 Value |= op0; 03383 // op1: rs2 03384 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03385 op1 &= (1<<5) - 1; 03386 Value |= op1; 03387 // op2: rd 03388 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03389 op2 &= (1<<5) - 1; 03390 op2 <<= 25; 03391 Value |= op2; 03392 break; 03393 } 03394 case V9::FMOVSG: { 03395 DEBUG(std::cerr << "Emitting FMOVSG\n"); 03396 Value = 2175434784U; 03397 03398 // op0: cc 03399 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03400 op0 &= (1<<3) - 1; 03401 op0 <<= 11; 03402 Value |= op0; 03403 // op1: rs2 03404 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03405 op1 &= (1<<5) - 1; 03406 Value |= op1; 03407 // op2: rd 03408 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03409 op2 &= (1<<5) - 1; 03410 op2 <<= 25; 03411 Value |= op2; 03412 break; 03413 } 03414 case V9::FMOVSGE: { 03415 DEBUG(std::cerr << "Emitting FMOVSGE\n"); 03416 Value = 2175451168U; 03417 03418 // op0: cc 03419 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03420 op0 &= (1<<3) - 1; 03421 op0 <<= 11; 03422 Value |= op0; 03423 // op1: rs2 03424 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03425 op1 &= (1<<5) - 1; 03426 Value |= op1; 03427 // op2: rd 03428 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03429 op2 &= (1<<5) - 1; 03430 op2 <<= 25; 03431 Value |= op2; 03432 break; 03433 } 03434 case V9::FMOVSGU: { 03435 DEBUG(std::cerr << "Emitting FMOVSGU\n"); 03436 Value = 2175467552U; 03437 03438 // op0: cc 03439 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03440 op0 &= (1<<3) - 1; 03441 op0 <<= 11; 03442 Value |= op0; 03443 // op1: rs2 03444 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03445 op1 &= (1<<5) - 1; 03446 Value |= op1; 03447 // op2: rd 03448 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03449 op2 &= (1<<5) - 1; 03450 op2 <<= 25; 03451 Value |= op2; 03452 break; 03453 } 03454 case V9::FMOVSL: { 03455 DEBUG(std::cerr << "Emitting FMOVSL\n"); 03456 Value = 2175320096U; 03457 03458 // op0: cc 03459 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03460 op0 &= (1<<3) - 1; 03461 op0 <<= 11; 03462 Value |= op0; 03463 // op1: rs2 03464 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03465 op1 &= (1<<5) - 1; 03466 Value |= op1; 03467 // op2: rd 03468 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03469 op2 &= (1<<5) - 1; 03470 op2 <<= 25; 03471 Value |= op2; 03472 break; 03473 } 03474 case V9::FMOVSLE: { 03475 DEBUG(std::cerr << "Emitting FMOVSLE\n"); 03476 Value = 2175270944U; 03477 03478 // op0: cc 03479 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03480 op0 &= (1<<3) - 1; 03481 op0 <<= 11; 03482 Value |= op0; 03483 // op1: rs2 03484 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03485 op1 &= (1<<5) - 1; 03486 Value |= op1; 03487 // op2: rd 03488 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03489 op2 &= (1<<5) - 1; 03490 op2 <<= 25; 03491 Value |= op2; 03492 break; 03493 } 03494 case V9::FMOVSLEU: { 03495 DEBUG(std::cerr << "Emitting FMOVSLEU\n"); 03496 Value = 2175336480U; 03497 03498 // op0: cc 03499 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03500 op0 &= (1<<3) - 1; 03501 op0 <<= 11; 03502 Value |= op0; 03503 // op1: rs2 03504 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03505 op1 &= (1<<5) - 1; 03506 Value |= op1; 03507 // op2: rd 03508 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03509 op2 &= (1<<5) - 1; 03510 op2 <<= 25; 03511 Value |= op2; 03512 break; 03513 } 03514 case V9::FMOVSN: { 03515 DEBUG(std::cerr << "Emitting FMOVSN\n"); 03516 Value = 2175270944U; 03517 03518 // op0: cc 03519 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03520 op0 &= (1<<3) - 1; 03521 op0 <<= 11; 03522 Value |= op0; 03523 // op1: rs2 03524 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03525 op1 &= (1<<5) - 1; 03526 Value |= op1; 03527 // op2: rd 03528 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03529 op2 &= (1<<5) - 1; 03530 op2 <<= 25; 03531 Value |= op2; 03532 break; 03533 } 03534 case V9::FMOVSNE: { 03535 DEBUG(std::cerr << "Emitting FMOVSNE\n"); 03536 Value = 2175418400U; 03537 03538 // op0: cc 03539 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03540 op0 &= (1<<3) - 1; 03541 op0 <<= 11; 03542 Value |= op0; 03543 // op1: rs2 03544 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03545 op1 &= (1<<5) - 1; 03546 Value |= op1; 03547 // op2: rd 03548 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03549 op2 &= (1<<5) - 1; 03550 op2 <<= 25; 03551 Value |= op2; 03552 break; 03553 } 03554 case V9::FMOVSNEG: { 03555 DEBUG(std::cerr << "Emitting FMOVSNEG\n"); 03556 Value = 2175369248U; 03557 03558 // op0: cc 03559 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03560 op0 &= (1<<3) - 1; 03561 op0 <<= 11; 03562 Value |= op0; 03563 // op1: rs2 03564 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03565 op1 &= (1<<5) - 1; 03566 Value |= op1; 03567 // op2: rd 03568 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03569 op2 &= (1<<5) - 1; 03570 op2 <<= 25; 03571 Value |= op2; 03572 break; 03573 } 03574 case V9::FMOVSPOS: { 03575 DEBUG(std::cerr << "Emitting FMOVSPOS\n"); 03576 Value = 2175500320U; 03577 03578 // op0: cc 03579 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03580 op0 &= (1<<3) - 1; 03581 op0 <<= 11; 03582 Value |= op0; 03583 // op1: rs2 03584 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03585 op1 &= (1<<5) - 1; 03586 Value |= op1; 03587 // op2: rd 03588 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03589 op2 &= (1<<5) - 1; 03590 op2 <<= 25; 03591 Value |= op2; 03592 break; 03593 } 03594 case V9::FMOVSVC: { 03595 DEBUG(std::cerr << "Emitting FMOVSVC\n"); 03596 Value = 2175516704U; 03597 03598 // op0: cc 03599 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03600 op0 &= (1<<3) - 1; 03601 op0 <<= 11; 03602 Value |= op0; 03603 // op1: rs2 03604 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03605 op1 &= (1<<5) - 1; 03606 Value |= op1; 03607 // op2: rd 03608 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03609 op2 &= (1<<5) - 1; 03610 op2 <<= 25; 03611 Value |= op2; 03612 break; 03613 } 03614 case V9::FMOVSVS: { 03615 DEBUG(std::cerr << "Emitting FMOVSVS\n"); 03616 Value = 2175385632U; 03617 03618 // op0: cc 03619 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03620 op0 &= (1<<3) - 1; 03621 op0 <<= 11; 03622 Value |= op0; 03623 // op1: rs2 03624 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03625 op1 &= (1<<5) - 1; 03626 Value |= op1; 03627 // op2: rd 03628 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03629 op2 &= (1<<5) - 1; 03630 op2 <<= 25; 03631 Value |= op2; 03632 break; 03633 } 03634 case V9::FMULD: { 03635 DEBUG(std::cerr << "Emitting FMULD\n"); 03636 Value = 2174748992U; 03637 03638 // op0: rs1 03639 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03640 op0 &= (1<<5) - 1; 03641 op0 <<= 14; 03642 Value |= op0; 03643 // op1: rs2 03644 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03645 op1 &= (1<<5) - 1; 03646 Value |= op1; 03647 // op2: rd 03648 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03649 op2 &= (1<<5) - 1; 03650 op2 <<= 25; 03651 Value |= op2; 03652 break; 03653 } 03654 case V9::FMULQ: { 03655 DEBUG(std::cerr << "Emitting FMULQ\n"); 03656 Value = 2174749024U; 03657 03658 // op0: rs1 03659 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03660 op0 &= (1<<5) - 1; 03661 op0 <<= 14; 03662 Value |= op0; 03663 // op1: rs2 03664 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03665 op1 &= (1<<5) - 1; 03666 Value |= op1; 03667 // op2: rd 03668 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03669 op2 &= (1<<5) - 1; 03670 op2 <<= 25; 03671 Value |= op2; 03672 break; 03673 } 03674 case V9::FMULS: { 03675 DEBUG(std::cerr << "Emitting FMULS\n"); 03676 Value = 2174748960U; 03677 03678 // op0: rs1 03679 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03680 op0 &= (1<<5) - 1; 03681 op0 <<= 14; 03682 Value |= op0; 03683 // op1: rs2 03684 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03685 op1 &= (1<<5) - 1; 03686 Value |= op1; 03687 // op2: rd 03688 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03689 op2 &= (1<<5) - 1; 03690 op2 <<= 25; 03691 Value |= op2; 03692 break; 03693 } 03694 case V9::FNEGD: { 03695 DEBUG(std::cerr << "Emitting FNEGD\n"); 03696 Value = 2174746816U; 03697 03698 // op0: rs2 03699 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03700 op0 &= (1<<5) - 1; 03701 Value |= op0; 03702 // op1: rd 03703 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03704 op1 &= (1<<5) - 1; 03705 op1 <<= 25; 03706 Value |= op1; 03707 break; 03708 } 03709 case V9::FNEGS: { 03710 DEBUG(std::cerr << "Emitting FNEGS\n"); 03711 Value = 2174746784U; 03712 03713 // op0: rs2 03714 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03715 op0 &= (1<<5) - 1; 03716 Value |= op0; 03717 // op1: rd 03718 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03719 op1 &= (1<<5) - 1; 03720 op1 <<= 25; 03721 Value |= op1; 03722 break; 03723 } 03724 case V9::FQTOD: { 03725 DEBUG(std::cerr << "Emitting FQTOD\n"); 03726 Value = 2174753120U; 03727 03728 // op0: rs2 03729 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03730 op0 &= (1<<5) - 1; 03731 Value |= op0; 03732 // op1: rd 03733 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03734 op1 &= (1<<5) - 1; 03735 op1 <<= 25; 03736 Value |= op1; 03737 break; 03738 } 03739 case V9::FQTOI: { 03740 DEBUG(std::cerr << "Emitting FQTOI\n"); 03741 Value = 2174753376U; 03742 03743 // op0: rs2 03744 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03745 op0 &= (1<<5) - 1; 03746 Value |= op0; 03747 // op1: rd 03748 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03749 op1 &= (1<<5) - 1; 03750 op1 <<= 25; 03751 Value |= op1; 03752 break; 03753 } 03754 case V9::FQTOS: { 03755 DEBUG(std::cerr << "Emitting FQTOS\n"); 03756 Value = 2174752992U; 03757 03758 // op0: rs2 03759 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03760 op0 &= (1<<5) - 1; 03761 Value |= op0; 03762 // op1: rd 03763 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03764 op1 &= (1<<5) - 1; 03765 op1 <<= 25; 03766 Value |= op1; 03767 break; 03768 } 03769 case V9::FQTOX: { 03770 DEBUG(std::cerr << "Emitting FQTOX\n"); 03771 Value = 2174750816U; 03772 03773 // op0: rs2 03774 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03775 op0 &= (1<<5) - 1; 03776 Value |= op0; 03777 // op1: rd 03778 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03779 op1 &= (1<<5) - 1; 03780 op1 <<= 25; 03781 Value |= op1; 03782 break; 03783 } 03784 case V9::FSMULD: { 03785 DEBUG(std::cerr << "Emitting FSMULD\n"); 03786 Value = 2174749984U; 03787 03788 // op0: rs1 03789 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03790 op0 &= (1<<5) - 1; 03791 op0 <<= 14; 03792 Value |= op0; 03793 // op1: rs2 03794 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03795 op1 &= (1<<5) - 1; 03796 Value |= op1; 03797 // op2: rd 03798 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03799 op2 &= (1<<5) - 1; 03800 op2 <<= 25; 03801 Value |= op2; 03802 break; 03803 } 03804 case V9::FSQRTD: { 03805 DEBUG(std::cerr << "Emitting FSQRTD\n"); 03806 Value = 2174747968U; 03807 03808 // op0: rs2 03809 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03810 op0 &= (1<<5) - 1; 03811 Value |= op0; 03812 // op1: rd 03813 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03814 op1 &= (1<<5) - 1; 03815 op1 <<= 25; 03816 Value |= op1; 03817 break; 03818 } 03819 case V9::FSQRTQ: { 03820 DEBUG(std::cerr << "Emitting FSQRTQ\n"); 03821 Value = 2174748000U; 03822 03823 // op0: rs2 03824 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03825 op0 &= (1<<5) - 1; 03826 Value |= op0; 03827 // op1: rd 03828 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03829 op1 &= (1<<5) - 1; 03830 op1 <<= 25; 03831 Value |= op1; 03832 break; 03833 } 03834 case V9::FSQRTS: { 03835 DEBUG(std::cerr << "Emitting FSQRTS\n"); 03836 Value = 2174747936U; 03837 03838 // op0: rs2 03839 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03840 op0 &= (1<<5) - 1; 03841 Value |= op0; 03842 // op1: rd 03843 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03844 op1 &= (1<<5) - 1; 03845 op1 <<= 25; 03846 Value |= op1; 03847 break; 03848 } 03849 case V9::FSTOD: { 03850 DEBUG(std::cerr << "Emitting FSTOD\n"); 03851 Value = 2174753056U; 03852 03853 // op0: rs2 03854 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03855 op0 &= (1<<5) - 1; 03856 Value |= op0; 03857 // op1: rd 03858 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03859 op1 &= (1<<5) - 1; 03860 op1 <<= 25; 03861 Value |= op1; 03862 break; 03863 } 03864 case V9::FSTOI: { 03865 DEBUG(std::cerr << "Emitting FSTOI\n"); 03866 Value = 2174753312U; 03867 03868 // op0: rs2 03869 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03870 op0 &= (1<<5) - 1; 03871 Value |= op0; 03872 // op1: rd 03873 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03874 op1 &= (1<<5) - 1; 03875 op1 <<= 25; 03876 Value |= op1; 03877 break; 03878 } 03879 case V9::FSTOQ: { 03880 DEBUG(std::cerr << "Emitting FSTOQ\n"); 03881 Value = 2174753184U; 03882 03883 // op0: rs2 03884 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03885 op0 &= (1<<5) - 1; 03886 Value |= op0; 03887 // op1: rd 03888 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03889 op1 &= (1<<5) - 1; 03890 op1 <<= 25; 03891 Value |= op1; 03892 break; 03893 } 03894 case V9::FSTOX: { 03895 DEBUG(std::cerr << "Emitting FSTOX\n"); 03896 Value = 2174750752U; 03897 03898 // op0: rs2 03899 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03900 op0 &= (1<<5) - 1; 03901 Value |= op0; 03902 // op1: rd 03903 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03904 op1 &= (1<<5) - 1; 03905 op1 <<= 25; 03906 Value |= op1; 03907 break; 03908 } 03909 case V9::FSUBD: { 03910 DEBUG(std::cerr << "Emitting FSUBD\n"); 03911 Value = 2174748864U; 03912 03913 // op0: rs1 03914 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03915 op0 &= (1<<5) - 1; 03916 op0 <<= 14; 03917 Value |= op0; 03918 // op1: rs2 03919 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03920 op1 &= (1<<5) - 1; 03921 Value |= op1; 03922 // op2: rd 03923 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03924 op2 &= (1<<5) - 1; 03925 op2 <<= 25; 03926 Value |= op2; 03927 break; 03928 } 03929 case V9::FSUBQ: { 03930 DEBUG(std::cerr << "Emitting FSUBQ\n"); 03931 Value = 2174748896U; 03932 03933 // op0: rs1 03934 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03935 op0 &= (1<<5) - 1; 03936 op0 <<= 14; 03937 Value |= op0; 03938 // op1: rs2 03939 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03940 op1 &= (1<<5) - 1; 03941 Value |= op1; 03942 // op2: rd 03943 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03944 op2 &= (1<<5) - 1; 03945 op2 <<= 25; 03946 Value |= op2; 03947 break; 03948 } 03949 case V9::FSUBS: { 03950 DEBUG(std::cerr << "Emitting FSUBS\n"); 03951 Value = 2174748832U; 03952 03953 // op0: rs1 03954 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03955 op0 &= (1<<5) - 1; 03956 op0 <<= 14; 03957 Value |= op0; 03958 // op1: rs2 03959 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03960 op1 &= (1<<5) - 1; 03961 Value |= op1; 03962 // op2: rd 03963 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 03964 op2 &= (1<<5) - 1; 03965 op2 <<= 25; 03966 Value |= op2; 03967 break; 03968 } 03969 case V9::FXTOD: { 03970 DEBUG(std::cerr << "Emitting FXTOD\n"); 03971 Value = 2174750976U; 03972 03973 // op0: rs2 03974 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03975 op0 &= (1<<5) - 1; 03976 Value |= op0; 03977 // op1: rd 03978 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03979 op1 &= (1<<5) - 1; 03980 op1 <<= 25; 03981 Value |= op1; 03982 break; 03983 } 03984 case V9::FXTOQ: { 03985 DEBUG(std::cerr << "Emitting FXTOQ\n"); 03986 Value = 2174751104U; 03987 03988 // op0: rs2 03989 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 03990 op0 &= (1<<5) - 1; 03991 Value |= op0; 03992 // op1: rd 03993 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 03994 op1 &= (1<<5) - 1; 03995 op1 <<= 25; 03996 Value |= op1; 03997 break; 03998 } 03999 case V9::FXTOS: { 04000 DEBUG(std::cerr << "Emitting FXTOS\n"); 04001 Value = 2174750848U; 04002 04003 // op0: rs2 04004 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04005 op0 &= (1<<5) - 1; 04006 Value |= op0; 04007 // op1: rd 04008 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04009 op1 &= (1<<5) - 1; 04010 op1 <<= 25; 04011 Value |= op1; 04012 break; 04013 } 04014 case V9::JMPLCALLi: { 04015 DEBUG(std::cerr << "Emitting JMPLCALLi\n"); 04016 Value = 2176851968U; 04017 04018 // op0: rs1 04019 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04020 op0 &= (1<<5) - 1; 04021 op0 <<= 14; 04022 Value |= op0; 04023 // op1: simm13 04024 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04025 op1 &= (1<<13) - 1; 04026 Value |= op1; 04027 // op2: rd 04028 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04029 op2 &= (1<<5) - 1; 04030 op2 <<= 25; 04031 Value |= op2; 04032 break; 04033 } 04034 case V9::JMPLCALLr: { 04035 DEBUG(std::cerr << "Emitting JMPLCALLr\n"); 04036 Value = 2176843776U; 04037 04038 // op0: rs1 04039 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04040 op0 &= (1<<5) - 1; 04041 op0 <<= 14; 04042 Value |= op0; 04043 // op1: rs2 04044 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04045 op1 &= (1<<5) - 1; 04046 Value |= op1; 04047 // op2: rd 04048 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04049 op2 &= (1<<5) - 1; 04050 op2 <<= 25; 04051 Value |= op2; 04052 break; 04053 } 04054 case V9::JMPLRETi: { 04055 DEBUG(std::cerr << "Emitting JMPLRETi\n"); 04056 Value = 2176851968U; 04057 04058 // op0: rs1 04059 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04060 op0 &= (1<<5) - 1; 04061 op0 <<= 14; 04062 Value |= op0; 04063 // op1: simm13 04064 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04065 op1 &= (1<<13) - 1; 04066 Value |= op1; 04067 // op2: rd 04068 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04069 op2 &= (1<<5) - 1; 04070 op2 <<= 25; 04071 Value |= op2; 04072 break; 04073 } 04074 case V9::JMPLRETr: { 04075 DEBUG(std::cerr << "Emitting JMPLRETr\n"); 04076 Value = 2176843776U; 04077 04078 // op0: rs1 04079 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04080 op0 &= (1<<5) - 1; 04081 op0 <<= 14; 04082 Value |= op0; 04083 // op1: rs2 04084 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04085 op1 &= (1<<5) - 1; 04086 Value |= op1; 04087 // op2: rd 04088 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04089 op2 &= (1<<5) - 1; 04090 op2 <<= 25; 04091 Value |= op2; 04092 break; 04093 } 04094 case V9::LDDFi: { 04095 DEBUG(std::cerr << "Emitting LDDFi\n"); 04096 Value = 3239583744U; 04097 04098 // op0: rs1 04099 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04100 op0 &= (1<<5) - 1; 04101 op0 <<= 14; 04102 Value |= op0; 04103 // op1: simm13 04104 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04105 op1 &= (1<<13) - 1; 04106 Value |= op1; 04107 // op2: rd 04108 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04109 op2 &= (1<<5) - 1; 04110 op2 <<= 25; 04111 Value |= op2; 04112 break; 04113 } 04114 case V9::LDDFr: { 04115 DEBUG(std::cerr << "Emitting LDDFr\n"); 04116 Value = 3239575552U; 04117 04118 // op0: rs1 04119 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04120 op0 &= (1<<5) - 1; 04121 op0 <<= 14; 04122 Value |= op0; 04123 // op1: rs2 04124 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04125 op1 &= (1<<5) - 1; 04126 Value |= op1; 04127 // op2: rd 04128 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04129 op2 &= (1<<5) - 1; 04130 op2 <<= 25; 04131 Value |= op2; 04132 break; 04133 } 04134 case V9::LDFSRi: { 04135 DEBUG(std::cerr << "Emitting LDFSRi\n"); 04136 Value = 3238535168U; 04137 04138 // op0: rs1 04139 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04140 op0 &= (1<<5) - 1; 04141 op0 <<= 14; 04142 Value |= op0; 04143 // op1: simm13 04144 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04145 op1 &= (1<<13) - 1; 04146 Value |= op1; 04147 break; 04148 } 04149 case V9::LDFSRr: { 04150 DEBUG(std::cerr << "Emitting LDFSRr\n"); 04151 Value = 3238526976U; 04152 04153 // op0: rs1 04154 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04155 op0 &= (1<<5) - 1; 04156 op0 <<= 14; 04157 Value |= op0; 04158 // op1: rs2 04159 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04160 op1 &= (1<<5) - 1; 04161 Value |= op1; 04162 break; 04163 } 04164 case V9::LDFi: { 04165 DEBUG(std::cerr << "Emitting LDFi\n"); 04166 Value = 3238010880U; 04167 04168 // op0: rs1 04169 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04170 op0 &= (1<<5) - 1; 04171 op0 <<= 14; 04172 Value |= op0; 04173 // op1: simm13 04174 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04175 op1 &= (1<<13) - 1; 04176 Value |= op1; 04177 // op2: rd 04178 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04179 op2 &= (1<<5) - 1; 04180 op2 <<= 25; 04181 Value |= op2; 04182 break; 04183 } 04184 case V9::LDFr: { 04185 DEBUG(std::cerr << "Emitting LDFr\n"); 04186 Value = 3238002688U; 04187 04188 // op0: rs1 04189 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04190 op0 &= (1<<5) - 1; 04191 op0 <<= 14; 04192 Value |= op0; 04193 // op1: rs2 04194 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04195 op1 &= (1<<5) - 1; 04196 Value |= op1; 04197 // op2: rd 04198 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04199 op2 &= (1<<5) - 1; 04200 op2 <<= 25; 04201 Value |= op2; 04202 break; 04203 } 04204 case V9::LDQFi: { 04205 DEBUG(std::cerr << "Emitting LDQFi\n"); 04206 Value = 3239059456U; 04207 04208 // op0: rs1 04209 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04210 op0 &= (1<<5) - 1; 04211 op0 <<= 14; 04212 Value |= op0; 04213 // op1: simm13 04214 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04215 op1 &= (1<<13) - 1; 04216 Value |= op1; 04217 // op2: rd 04218 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04219 op2 &= (1<<5) - 1; 04220 op2 <<= 25; 04221 Value |= op2; 04222 break; 04223 } 04224 case V9::LDQFr: { 04225 DEBUG(std::cerr << "Emitting LDQFr\n"); 04226 Value = 3239051264U; 04227 04228 // op0: rs1 04229 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04230 op0 &= (1<<5) - 1; 04231 op0 <<= 14; 04232 Value |= op0; 04233 // op1: rs2 04234 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04235 op1 &= (1<<5) - 1; 04236 Value |= op1; 04237 // op2: rd 04238 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04239 op2 &= (1<<5) - 1; 04240 op2 <<= 25; 04241 Value |= op2; 04242 break; 04243 } 04244 case V9::LDSBi: { 04245 DEBUG(std::cerr << "Emitting LDSBi\n"); 04246 Value = 3225952256U; 04247 04248 // op0: rs1 04249 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04250 op0 &= (1<<5) - 1; 04251 op0 <<= 14; 04252 Value |= op0; 04253 // op1: simm13 04254 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04255 op1 &= (1<<13) - 1; 04256 Value |= op1; 04257 // op2: rd 04258 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04259 op2 &= (1<<5) - 1; 04260 op2 <<= 25; 04261 Value |= op2; 04262 break; 04263 } 04264 case V9::LDSBr: { 04265 DEBUG(std::cerr << "Emitting LDSBr\n"); 04266 Value = 3225944064U; 04267 04268 // op0: rs1 04269 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04270 op0 &= (1<<5) - 1; 04271 op0 <<= 14; 04272 Value |= op0; 04273 // op1: rs2 04274 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04275 op1 &= (1<<5) - 1; 04276 Value |= op1; 04277 // op2: rd 04278 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04279 op2 &= (1<<5) - 1; 04280 op2 <<= 25; 04281 Value |= op2; 04282 break; 04283 } 04284 case V9::LDSHi: { 04285 DEBUG(std::cerr << "Emitting LDSHi\n"); 04286 Value = 3226476544U; 04287 04288 // op0: rs1 04289 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04290 op0 &= (1<<5) - 1; 04291 op0 <<= 14; 04292 Value |= op0; 04293 // op1: simm13 04294 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04295 op1 &= (1<<13) - 1; 04296 Value |= op1; 04297 // op2: rd 04298 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04299 op2 &= (1<<5) - 1; 04300 op2 <<= 25; 04301 Value |= op2; 04302 break; 04303 } 04304 case V9::LDSHr: { 04305 DEBUG(std::cerr << "Emitting LDSHr\n"); 04306 Value = 3226468352U; 04307 04308 // op0: rs1 04309 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04310 op0 &= (1<<5) - 1; 04311 op0 <<= 14; 04312 Value |= op0; 04313 // op1: rs2 04314 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04315 op1 &= (1<<5) - 1; 04316 Value |= op1; 04317 // op2: rd 04318 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04319 op2 &= (1<<5) - 1; 04320 op2 <<= 25; 04321 Value |= op2; 04322 break; 04323 } 04324 case V9::LDSWi: { 04325 DEBUG(std::cerr << "Emitting LDSWi\n"); 04326 Value = 3225427968U; 04327 04328 // op0: rs1 04329 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04330 op0 &= (1<<5) - 1; 04331 op0 <<= 14; 04332 Value |= op0; 04333 // op1: simm13 04334 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04335 op1 &= (1<<13) - 1; 04336 Value |= op1; 04337 // op2: rd 04338 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04339 op2 &= (1<<5) - 1; 04340 op2 <<= 25; 04341 Value |= op2; 04342 break; 04343 } 04344 case V9::LDSWr: { 04345 DEBUG(std::cerr << "Emitting LDSWr\n"); 04346 Value = 3225419776U; 04347 04348 // op0: rs1 04349 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04350 op0 &= (1<<5) - 1; 04351 op0 <<= 14; 04352 Value |= op0; 04353 // op1: rs2 04354 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04355 op1 &= (1<<5) - 1; 04356 Value |= op1; 04357 // op2: rd 04358 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04359 op2 &= (1<<5) - 1; 04360 op2 <<= 25; 04361 Value |= op2; 04362 break; 04363 } 04364 case V9::LDUBi: { 04365 DEBUG(std::cerr << "Emitting LDUBi\n"); 04366 Value = 3221757952U; 04367 04368 // op0: rs1 04369 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04370 op0 &= (1<<5) - 1; 04371 op0 <<= 14; 04372 Value |= op0; 04373 // op1: simm13 04374 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04375 op1 &= (1<<13) - 1; 04376 Value |= op1; 04377 // op2: rd 04378 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04379 op2 &= (1<<5) - 1; 04380 op2 <<= 25; 04381 Value |= op2; 04382 break; 04383 } 04384 case V9::LDUBr: { 04385 DEBUG(std::cerr << "Emitting LDUBr\n"); 04386 Value = 3221749760U; 04387 04388 // op0: rs1 04389 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04390 op0 &= (1<<5) - 1; 04391 op0 <<= 14; 04392 Value |= op0; 04393 // op1: rs2 04394 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04395 op1 &= (1<<5) - 1; 04396 Value |= op1; 04397 // op2: rd 04398 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04399 op2 &= (1<<5) - 1; 04400 op2 <<= 25; 04401 Value |= op2; 04402 break; 04403 } 04404 case V9::LDUHi: { 04405 DEBUG(std::cerr << "Emitting LDUHi\n"); 04406 Value = 3222282240U; 04407 04408 // op0: rs1 04409 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04410 op0 &= (1<<5) - 1; 04411 op0 <<= 14; 04412 Value |= op0; 04413 // op1: simm13 04414 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04415 op1 &= (1<<13) - 1; 04416 Value |= op1; 04417 // op2: rd 04418 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04419 op2 &= (1<<5) - 1; 04420 op2 <<= 25; 04421 Value |= op2; 04422 break; 04423 } 04424 case V9::LDUHr: { 04425 DEBUG(std::cerr << "Emitting LDUHr\n"); 04426 Value = 3222274048U; 04427 04428 // op0: rs1 04429 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04430 op0 &= (1<<5) - 1; 04431 op0 <<= 14; 04432 Value |= op0; 04433 // op1: rs2 04434 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04435 op1 &= (1<<5) - 1; 04436 Value |= op1; 04437 // op2: rd 04438 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04439 op2 &= (1<<5) - 1; 04440 op2 <<= 25; 04441 Value |= op2; 04442 break; 04443 } 04444 case V9::LDUWi: { 04445 DEBUG(std::cerr << "Emitting LDUWi\n"); 04446 Value = 3221233664U; 04447 04448 // op0: rs1 04449 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04450 op0 &= (1<<5) - 1; 04451 op0 <<= 14; 04452 Value |= op0; 04453 // op1: simm13 04454 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04455 op1 &= (1<<13) - 1; 04456 Value |= op1; 04457 // op2: rd 04458 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04459 op2 &= (1<<5) - 1; 04460 op2 <<= 25; 04461 Value |= op2; 04462 break; 04463 } 04464 case V9::LDUWr: { 04465 DEBUG(std::cerr << "Emitting LDUWr\n"); 04466 Value = 3221225472U; 04467 04468 // op0: rs1 04469 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04470 op0 &= (1<<5) - 1; 04471 op0 <<= 14; 04472 Value |= op0; 04473 // op1: rs2 04474 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04475 op1 &= (1<<5) - 1; 04476 Value |= op1; 04477 // op2: rd 04478 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04479 op2 &= (1<<5) - 1; 04480 op2 <<= 25; 04481 Value |= op2; 04482 break; 04483 } 04484 case V9::LDXFSRi: { 04485 DEBUG(std::cerr << "Emitting LDXFSRi\n"); 04486 Value = 3272089600U; 04487 04488 // op0: rs1 04489 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04490 op0 &= (1<<5) - 1; 04491 op0 <<= 14; 04492 Value |= op0; 04493 // op1: simm13 04494 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04495 op1 &= (1<<13) - 1; 04496 Value |= op1; 04497 break; 04498 } 04499 case V9::LDXFSRr: { 04500 DEBUG(std::cerr << "Emitting LDXFSRr\n"); 04501 Value = 3272081408U; 04502 04503 // op0: rs1 04504 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04505 op0 &= (1<<5) - 1; 04506 op0 <<= 14; 04507 Value |= op0; 04508 // op1: rs2 04509 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04510 op1 &= (1<<5) - 1; 04511 Value |= op1; 04512 break; 04513 } 04514 case V9::LDXi: { 04515 DEBUG(std::cerr << "Emitting LDXi\n"); 04516 Value = 3227000832U; 04517 04518 // op0: rs1 04519 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04520 op0 &= (1<<5) - 1; 04521 op0 <<= 14; 04522 Value |= op0; 04523 // op1: simm13 04524 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04525 op1 &= (1<<13) - 1; 04526 Value |= op1; 04527 // op2: rd 04528 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04529 op2 &= (1<<5) - 1; 04530 op2 <<= 25; 04531 Value |= op2; 04532 break; 04533 } 04534 case V9::LDXr: { 04535 DEBUG(std::cerr << "Emitting LDXr\n"); 04536 Value = 3226992640U; 04537 04538 // op0: rs1 04539 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04540 op0 &= (1<<5) - 1; 04541 op0 <<= 14; 04542 Value |= op0; 04543 // op1: rs2 04544 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04545 op1 &= (1<<5) - 1; 04546 Value |= op1; 04547 // op2: rd 04548 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04549 op2 &= (1<<5) - 1; 04550 op2 <<= 25; 04551 Value |= op2; 04552 break; 04553 } 04554 case V9::MOVAi: { 04555 DEBUG(std::cerr << "Emitting MOVAi\n"); 04556 Value = 2170691584U; 04557 04558 // op0: cc 04559 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04560 // op1: simm11 04561 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04562 op1 &= (1<<11) - 1; 04563 Value |= op1; 04564 // op2: rd 04565 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04566 op2 &= (1<<5) - 1; 04567 op2 <<= 25; 04568 Value |= op2; 04569 Value |= getValueBit(op0, 2) << 18; 04570 Value |= getValueBit(op0, 1) << 12; 04571 Value |= getValueBit(op0, 0) << 11; 04572 break; 04573 } 04574 case V9::MOVAr: { 04575 DEBUG(std::cerr << "Emitting MOVAr\n"); 04576 Value = 2170683392U; 04577 04578 // op0: cc 04579 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04580 // op1: rs2 04581 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04582 op1 &= (1<<5) - 1; 04583 Value |= op1; 04584 // op2: rd 04585 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04586 op2 &= (1<<5) - 1; 04587 op2 <<= 25; 04588 Value |= op2; 04589 Value |= getValueBit(op0, 2) << 18; 04590 Value |= getValueBit(op0, 1) << 12; 04591 Value |= getValueBit(op0, 0) << 11; 04592 break; 04593 } 04594 case V9::MOVCCi: { 04595 DEBUG(std::cerr << "Emitting MOVCCi\n"); 04596 Value = 2170773504U; 04597 04598 // op0: cc 04599 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04600 // op1: simm11 04601 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04602 op1 &= (1<<11) - 1; 04603 Value |= op1; 04604 // op2: rd 04605 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04606 op2 &= (1<<5) - 1; 04607 op2 <<= 25; 04608 Value |= op2; 04609 Value |= getValueBit(op0, 2) << 18; 04610 Value |= getValueBit(op0, 1) << 12; 04611 Value |= getValueBit(op0, 0) << 11; 04612 break; 04613 } 04614 case V9::MOVCCr: { 04615 DEBUG(std::cerr << "Emitting MOVCCr\n"); 04616 Value = 2170765312U; 04617 04618 // op0: cc 04619 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04620 // op1: rs2 04621 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04622 op1 &= (1<<5) - 1; 04623 Value |= op1; 04624 // op2: rd 04625 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04626 op2 &= (1<<5) - 1; 04627 op2 <<= 25; 04628 Value |= op2; 04629 Value |= getValueBit(op0, 2) << 18; 04630 Value |= getValueBit(op0, 1) << 12; 04631 Value |= getValueBit(op0, 0) << 11; 04632 break; 04633 } 04634 case V9::MOVCSi: { 04635 DEBUG(std::cerr << "Emitting MOVCSi\n"); 04636 Value = 2170642432U; 04637 04638 // op0: cc 04639 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04640 // op1: simm11 04641 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04642 op1 &= (1<<11) - 1; 04643 Value |= op1; 04644 // op2: rd 04645 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04646 op2 &= (1<<5) - 1; 04647 op2 <<= 25; 04648 Value |= op2; 04649 Value |= getValueBit(op0, 2) << 18; 04650 Value |= getValueBit(op0, 1) << 12; 04651 Value |= getValueBit(op0, 0) << 11; 04652 break; 04653 } 04654 case V9::MOVCSr: { 04655 DEBUG(std::cerr << "Emitting MOVCSr\n"); 04656 Value = 2170634240U; 04657 04658 // op0: cc 04659 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04660 // op1: rs2 04661 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04662 op1 &= (1<<5) - 1; 04663 Value |= op1; 04664 // op2: rd 04665 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04666 op2 &= (1<<5) - 1; 04667 op2 <<= 25; 04668 Value |= op2; 04669 Value |= getValueBit(op0, 2) << 18; 04670 Value |= getValueBit(op0, 1) << 12; 04671 Value |= getValueBit(op0, 0) << 11; 04672 break; 04673 } 04674 case V9::MOVEi: { 04675 DEBUG(std::cerr << "Emitting MOVEi\n"); 04676 Value = 2170576896U; 04677 04678 // op0: cc 04679 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04680 // op1: simm11 04681 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04682 op1 &= (1<<11) - 1; 04683 Value |= op1; 04684 // op2: rd 04685 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04686 op2 &= (1<<5) - 1; 04687 op2 <<= 25; 04688 Value |= op2; 04689 Value |= getValueBit(op0, 2) << 18; 04690 Value |= getValueBit(op0, 1) << 12; 04691 Value |= getValueBit(op0, 0) << 11; 04692 break; 04693 } 04694 case V9::MOVEr: { 04695 DEBUG(std::cerr << "Emitting MOVEr\n"); 04696 Value = 2170568704U; 04697 04698 // op0: cc 04699 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04700 // op1: rs2 04701 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04702 op1 &= (1<<5) - 1; 04703 Value |= op1; 04704 // op2: rd 04705 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04706 op2 &= (1<<5) - 1; 04707 op2 <<= 25; 04708 Value |= op2; 04709 Value |= getValueBit(op0, 2) << 18; 04710 Value |= getValueBit(op0, 1) << 12; 04711 Value |= getValueBit(op0, 0) << 11; 04712 break; 04713 } 04714 case V9::MOVFAi: { 04715 DEBUG(std::cerr << "Emitting MOVFAi\n"); 04716 Value = 2170691584U; 04717 04718 // op0: cc 04719 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04720 // op1: simm11 04721 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04722 op1 &= (1<<11) - 1; 04723 Value |= op1; 04724 // op2: rd 04725 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04726 op2 &= (1<<5) - 1; 04727 op2 <<= 25; 04728 Value |= op2; 04729 Value |= getValueBit(op0, 2) << 18; 04730 Value |= getValueBit(op0, 1) << 12; 04731 Value |= getValueBit(op0, 0) << 11; 04732 break; 04733 } 04734 case V9::MOVFAr: { 04735 DEBUG(std::cerr << "Emitting MOVFAr\n"); 04736 Value = 2170683392U; 04737 04738 // op0: cc 04739 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04740 // op1: rs2 04741 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04742 op1 &= (1<<5) - 1; 04743 Value |= op1; 04744 // op2: rd 04745 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04746 op2 &= (1<<5) - 1; 04747 op2 <<= 25; 04748 Value |= op2; 04749 Value |= getValueBit(op0, 2) << 18; 04750 Value |= getValueBit(op0, 1) << 12; 04751 Value |= getValueBit(op0, 0) << 11; 04752 break; 04753 } 04754 case V9::MOVFEi: { 04755 DEBUG(std::cerr << "Emitting MOVFEi\n"); 04756 Value = 2170707968U; 04757 04758 // op0: cc 04759 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04760 // op1: simm11 04761 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04762 op1 &= (1<<11) - 1; 04763 Value |= op1; 04764 // op2: rd 04765 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04766 op2 &= (1<<5) - 1; 04767 op2 <<= 25; 04768 Value |= op2; 04769 Value |= getValueBit(op0, 2) << 18; 04770 Value |= getValueBit(op0, 1) << 12; 04771 Value |= getValueBit(op0, 0) << 11; 04772 break; 04773 } 04774 case V9::MOVFEr: { 04775 DEBUG(std::cerr << "Emitting MOVFEr\n"); 04776 Value = 2170699776U; 04777 04778 // op0: cc 04779 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04780 // op1: rs2 04781 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04782 op1 &= (1<<5) - 1; 04783 Value |= op1; 04784 // op2: rd 04785 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04786 op2 &= (1<<5) - 1; 04787 op2 <<= 25; 04788 Value |= op2; 04789 Value |= getValueBit(op0, 2) << 18; 04790 Value |= getValueBit(op0, 1) << 12; 04791 Value |= getValueBit(op0, 0) << 11; 04792 break; 04793 } 04794 case V9::MOVFGEi: { 04795 DEBUG(std::cerr << "Emitting MOVFGEi\n"); 04796 Value = 2170740736U; 04797 04798 // op0: cc 04799 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04800 // op1: simm11 04801 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04802 op1 &= (1<<11) - 1; 04803 Value |= op1; 04804 // op2: rd 04805 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04806 op2 &= (1<<5) - 1; 04807 op2 <<= 25; 04808 Value |= op2; 04809 Value |= getValueBit(op0, 2) << 18; 04810 Value |= getValueBit(op0, 1) << 12; 04811 Value |= getValueBit(op0, 0) << 11; 04812 break; 04813 } 04814 case V9::MOVFGEr: { 04815 DEBUG(std::cerr << "Emitting MOVFGEr\n"); 04816 Value = 2170732544U; 04817 04818 // op0: cc 04819 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04820 // op1: rs2 04821 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04822 op1 &= (1<<5) - 1; 04823 Value |= op1; 04824 // op2: rd 04825 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04826 op2 &= (1<<5) - 1; 04827 op2 <<= 25; 04828 Value |= op2; 04829 Value |= getValueBit(op0, 2) << 18; 04830 Value |= getValueBit(op0, 1) << 12; 04831 Value |= getValueBit(op0, 0) << 11; 04832 break; 04833 } 04834 case V9::MOVFGi: { 04835 DEBUG(std::cerr << "Emitting MOVFGi\n"); 04836 Value = 2170658816U; 04837 04838 // op0: cc 04839 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04840 // op1: simm11 04841 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04842 op1 &= (1<<11) - 1; 04843 Value |= op1; 04844 // op2: rd 04845 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04846 op2 &= (1<<5) - 1; 04847 op2 <<= 25; 04848 Value |= op2; 04849 Value |= getValueBit(op0, 2) << 18; 04850 Value |= getValueBit(op0, 1) << 12; 04851 Value |= getValueBit(op0, 0) << 11; 04852 break; 04853 } 04854 case V9::MOVFGr: { 04855 DEBUG(std::cerr << "Emitting MOVFGr\n"); 04856 Value = 2170650624U; 04857 04858 // op0: cc 04859 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04860 // op1: rs2 04861 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04862 op1 &= (1<<5) - 1; 04863 Value |= op1; 04864 // op2: rd 04865 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04866 op2 &= (1<<5) - 1; 04867 op2 <<= 25; 04868 Value |= op2; 04869 Value |= getValueBit(op0, 2) << 18; 04870 Value |= getValueBit(op0, 1) << 12; 04871 Value |= getValueBit(op0, 0) << 11; 04872 break; 04873 } 04874 case V9::MOVFLEi: { 04875 DEBUG(std::cerr << "Emitting MOVFLEi\n"); 04876 Value = 2170773504U; 04877 04878 // op0: cc 04879 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04880 // op1: simm11 04881 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04882 op1 &= (1<<11) - 1; 04883 Value |= op1; 04884 // op2: rd 04885 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04886 op2 &= (1<<5) - 1; 04887 op2 <<= 25; 04888 Value |= op2; 04889 Value |= getValueBit(op0, 2) << 18; 04890 Value |= getValueBit(op0, 1) << 12; 04891 Value |= getValueBit(op0, 0) << 11; 04892 break; 04893 } 04894 case V9::MOVFLEr: { 04895 DEBUG(std::cerr << "Emitting MOVFLEr\n"); 04896 Value = 2170765312U; 04897 04898 // op0: cc 04899 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04900 // op1: rs2 04901 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04902 op1 &= (1<<5) - 1; 04903 Value |= op1; 04904 // op2: rd 04905 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04906 op2 &= (1<<5) - 1; 04907 op2 <<= 25; 04908 Value |= op2; 04909 Value |= getValueBit(op0, 2) << 18; 04910 Value |= getValueBit(op0, 1) << 12; 04911 Value |= getValueBit(op0, 0) << 11; 04912 break; 04913 } 04914 case V9::MOVFLGi: { 04915 DEBUG(std::cerr << "Emitting MOVFLGi\n"); 04916 Value = 2170593280U; 04917 04918 // op0: cc 04919 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04920 // op1: simm11 04921 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04922 op1 &= (1<<11) - 1; 04923 Value |= op1; 04924 // op2: rd 04925 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04926 op2 &= (1<<5) - 1; 04927 op2 <<= 25; 04928 Value |= op2; 04929 Value |= getValueBit(op0, 2) << 18; 04930 Value |= getValueBit(op0, 1) << 12; 04931 Value |= getValueBit(op0, 0) << 11; 04932 break; 04933 } 04934 case V9::MOVFLGr: { 04935 DEBUG(std::cerr << "Emitting MOVFLGr\n"); 04936 Value = 2170585088U; 04937 04938 // op0: cc 04939 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04940 // op1: rs2 04941 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04942 op1 &= (1<<5) - 1; 04943 Value |= op1; 04944 // op2: rd 04945 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04946 op2 &= (1<<5) - 1; 04947 op2 <<= 25; 04948 Value |= op2; 04949 Value |= getValueBit(op0, 2) << 18; 04950 Value |= getValueBit(op0, 1) << 12; 04951 Value |= getValueBit(op0, 0) << 11; 04952 break; 04953 } 04954 case V9::MOVFLi: { 04955 DEBUG(std::cerr << "Emitting MOVFLi\n"); 04956 Value = 2170626048U; 04957 04958 // op0: cc 04959 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04960 // op1: simm11 04961 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04962 op1 &= (1<<11) - 1; 04963 Value |= op1; 04964 // op2: rd 04965 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04966 op2 &= (1<<5) - 1; 04967 op2 <<= 25; 04968 Value |= op2; 04969 Value |= getValueBit(op0, 2) << 18; 04970 Value |= getValueBit(op0, 1) << 12; 04971 Value |= getValueBit(op0, 0) << 11; 04972 break; 04973 } 04974 case V9::MOVFLr: { 04975 DEBUG(std::cerr << "Emitting MOVFLr\n"); 04976 Value = 2170617856U; 04977 04978 // op0: cc 04979 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 04980 // op1: rs2 04981 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 04982 op1 &= (1<<5) - 1; 04983 Value |= op1; 04984 // op2: rd 04985 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 04986 op2 &= (1<<5) - 1; 04987 op2 <<= 25; 04988 Value |= op2; 04989 Value |= getValueBit(op0, 2) << 18; 04990 Value |= getValueBit(op0, 1) << 12; 04991 Value |= getValueBit(op0, 0) << 11; 04992 break; 04993 } 04994 case V9::MOVFNEi: { 04995 DEBUG(std::cerr << "Emitting MOVFNEi\n"); 04996 Value = 2170576896U; 04997 04998 // op0: cc 04999 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05000 // op1: simm11 05001 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05002 op1 &= (1<<11) - 1; 05003 Value |= op1; 05004 // op2: rd 05005 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05006 op2 &= (1<<5) - 1; 05007 op2 <<= 25; 05008 Value |= op2; 05009 Value |= getValueBit(op0, 2) << 18; 05010 Value |= getValueBit(op0, 1) << 12; 05011 Value |= getValueBit(op0, 0) << 11; 05012 break; 05013 } 05014 case V9::MOVFNEr: { 05015 DEBUG(std::cerr << "Emitting MOVFNEr\n"); 05016 Value = 2170568704U; 05017 05018 // op0: cc 05019 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05020 // op1: rs2 05021 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05022 op1 &= (1<<5) - 1; 05023 Value |= op1; 05024 // op2: rd 05025 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05026 op2 &= (1<<5) - 1; 05027 op2 <<= 25; 05028 Value |= op2; 05029 Value |= getValueBit(op0, 2) << 18; 05030 Value |= getValueBit(op0, 1) << 12; 05031 Value |= getValueBit(op0, 0) << 11; 05032 break; 05033 } 05034 case V9::MOVFNi: { 05035 DEBUG(std::cerr << "Emitting MOVFNi\n"); 05036 Value = 2170560512U; 05037 05038 // op0: cc 05039 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05040 // op1: simm11 05041 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05042 op1 &= (1<<11) - 1; 05043 Value |= op1; 05044 // op2: rd 05045 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05046 op2 &= (1<<5) - 1; 05047 op2 <<= 25; 05048 Value |= op2; 05049 Value |= getValueBit(op0, 2) << 18; 05050 Value |= getValueBit(op0, 1) << 12; 05051 Value |= getValueBit(op0, 0) << 11; 05052 break; 05053 } 05054 case V9::MOVFNr: { 05055 DEBUG(std::cerr << "Emitting MOVFNr\n"); 05056 Value = 2170552320U; 05057 05058 // op0: cc 05059 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05060 // op1: rs2 05061 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05062 op1 &= (1<<5) - 1; 05063 Value |= op1; 05064 // op2: rd 05065 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05066 op2 &= (1<<5) - 1; 05067 op2 <<= 25; 05068 Value |= op2; 05069 Value |= getValueBit(op0, 2) << 18; 05070 Value |= getValueBit(op0, 1) << 12; 05071 Value |= getValueBit(op0, 0) << 11; 05072 break; 05073 } 05074 case V9::MOVFOi: { 05075 DEBUG(std::cerr << "Emitting MOVFOi\n"); 05076 Value = 2170806272U; 05077 05078 // op0: cc 05079 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05080 // op1: simm11 05081 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05082 op1 &= (1<<11) - 1; 05083 Value |= op1; 05084 // op2: rd 05085 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05086 op2 &= (1<<5) - 1; 05087 op2 <<= 25; 05088 Value |= op2; 05089 Value |= getValueBit(op0, 2) << 18; 05090 Value |= getValueBit(op0, 1) << 12; 05091 Value |= getValueBit(op0, 0) << 11; 05092 break; 05093 } 05094 case V9::MOVFOr: { 05095 DEBUG(std::cerr << "Emitting MOVFOr\n"); 05096 Value = 2170798080U; 05097 05098 // op0: cc 05099 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05100 // op1: rs2 05101 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05102 op1 &= (1<<5) - 1; 05103 Value |= op1; 05104 // op2: rd 05105 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05106 op2 &= (1<<5) - 1; 05107 op2 <<= 25; 05108 Value |= op2; 05109 Value |= getValueBit(op0, 2) << 18; 05110 Value |= getValueBit(op0, 1) << 12; 05111 Value |= getValueBit(op0, 0) << 11; 05112 break; 05113 } 05114 case V9::MOVFUEi: { 05115 DEBUG(std::cerr << "Emitting MOVFUEi\n"); 05116 Value = 2170724352U; 05117 05118 // op0: cc 05119 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05120 // op1: simm11 05121 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05122 op1 &= (1<<11) - 1; 05123 Value |= op1; 05124 // op2: rd 05125 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05126 op2 &= (1<<5) - 1; 05127 op2 <<= 25; 05128 Value |= op2; 05129 Value |= getValueBit(op0, 2) << 18; 05130 Value |= getValueBit(op0, 1) << 12; 05131 Value |= getValueBit(op0, 0) << 11; 05132 break; 05133 } 05134 case V9::MOVFUEr: { 05135 DEBUG(std::cerr << "Emitting MOVFUEr\n"); 05136 Value = 2170716160U; 05137 05138 // op0: cc 05139 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05140 // op1: rs2 05141 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05142 op1 &= (1<<5) - 1; 05143 Value |= op1; 05144 // op2: rd 05145 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05146 op2 &= (1<<5) - 1; 05147 op2 <<= 25; 05148 Value |= op2; 05149 Value |= getValueBit(op0, 2) << 18; 05150 Value |= getValueBit(op0, 1) << 12; 05151 Value |= getValueBit(op0, 0) << 11; 05152 break; 05153 } 05154 case V9::MOVFUGEi: { 05155 DEBUG(std::cerr << "Emitting MOVFUGEi\n"); 05156 Value = 2170757120U; 05157 05158 // op0: cc 05159 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05160 // op1: simm11 05161 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05162 op1 &= (1<<11) - 1; 05163 Value |= op1; 05164 // op2: rd 05165 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05166 op2 &= (1<<5) - 1; 05167 op2 <<= 25; 05168 Value |= op2; 05169 Value |= getValueBit(op0, 2) << 18; 05170 Value |= getValueBit(op0, 1) << 12; 05171 Value |= getValueBit(op0, 0) << 11; 05172 break; 05173 } 05174 case V9::MOVFUGEr: { 05175 DEBUG(std::cerr << "Emitting MOVFUGEr\n"); 05176 Value = 2170748928U; 05177 05178 // op0: cc 05179 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05180 // op1: rs2 05181 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05182 op1 &= (1<<5) - 1; 05183 Value |= op1; 05184 // op2: rd 05185 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05186 op2 &= (1<<5) - 1; 05187 op2 <<= 25; 05188 Value |= op2; 05189 Value |= getValueBit(op0, 2) << 18; 05190 Value |= getValueBit(op0, 1) << 12; 05191 Value |= getValueBit(op0, 0) << 11; 05192 break; 05193 } 05194 case V9::MOVFUGi: { 05195 DEBUG(std::cerr << "Emitting MOVFUGi\n"); 05196 Value = 2170642432U; 05197 05198 // op0: cc 05199 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05200 // op1: simm11 05201 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05202 op1 &= (1<<11) - 1; 05203 Value |= op1; 05204 // op2: rd 05205 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05206 op2 &= (1<<5) - 1; 05207 op2 <<= 25; 05208 Value |= op2; 05209 Value |= getValueBit(op0, 2) << 18; 05210 Value |= getValueBit(op0, 1) << 12; 05211 Value |= getValueBit(op0, 0) << 11; 05212 break; 05213 } 05214 case V9::MOVFUGr: { 05215 DEBUG(std::cerr << "Emitting MOVFUGr\n"); 05216 Value = 2170634240U; 05217 05218 // op0: cc 05219 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05220 // op1: rs2 05221 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05222 op1 &= (1<<5) - 1; 05223 Value |= op1; 05224 // op2: rd 05225 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05226 op2 &= (1<<5) - 1; 05227 op2 <<= 25; 05228 Value |= op2; 05229 Value |= getValueBit(op0, 2) << 18; 05230 Value |= getValueBit(op0, 1) << 12; 05231 Value |= getValueBit(op0, 0) << 11; 05232 break; 05233 } 05234 case V9::MOVFULEi: { 05235 DEBUG(std::cerr << "Emitting MOVFULEi\n"); 05236 Value = 2170789888U; 05237 05238 // op0: cc 05239 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05240 // op1: simm11 05241 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05242 op1 &= (1<<11) - 1; 05243 Value |= op1; 05244 // op2: rd 05245 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05246 op2 &= (1<<5) - 1; 05247 op2 <<= 25; 05248 Value |= op2; 05249 Value |= getValueBit(op0, 2) << 18; 05250 Value |= getValueBit(op0, 1) << 12; 05251 Value |= getValueBit(op0, 0) << 11; 05252 break; 05253 } 05254 case V9::MOVFULEr: { 05255 DEBUG(std::cerr << "Emitting MOVFULEr\n"); 05256 Value = 2170781696U; 05257 05258 // op0: cc 05259 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05260 // op1: rs2 05261 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05262 op1 &= (1<<5) - 1; 05263 Value |= op1; 05264 // op2: rd 05265 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05266 op2 &= (1<<5) - 1; 05267 op2 <<= 25; 05268 Value |= op2; 05269 Value |= getValueBit(op0, 2) << 18; 05270 Value |= getValueBit(op0, 1) << 12; 05271 Value |= getValueBit(op0, 0) << 11; 05272 break; 05273 } 05274 case V9::MOVFULi: { 05275 DEBUG(std::cerr << "Emitting MOVFULi\n"); 05276 Value = 2170609664U; 05277 05278 // op0: cc 05279 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05280 // op1: simm11 05281 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05282 op1 &= (1<<11) - 1; 05283 Value |= op1; 05284 // op2: rd 05285 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05286 op2 &= (1<<5) - 1; 05287 op2 <<= 25; 05288 Value |= op2; 05289 Value |= getValueBit(op0, 2) << 18; 05290 Value |= getValueBit(op0, 1) << 12; 05291 Value |= getValueBit(op0, 0) << 11; 05292 break; 05293 } 05294 case V9::MOVFULr: { 05295 DEBUG(std::cerr << "Emitting MOVFULr\n"); 05296 Value = 2170601472U; 05297 05298 // op0: cc 05299 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05300 // op1: rs2 05301 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05302 op1 &= (1<<5) - 1; 05303 Value |= op1; 05304 // op2: rd 05305 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05306 op2 &= (1<<5) - 1; 05307 op2 <<= 25; 05308 Value |= op2; 05309 Value |= getValueBit(op0, 2) << 18; 05310 Value |= getValueBit(op0, 1) << 12; 05311 Value |= getValueBit(op0, 0) << 11; 05312 break; 05313 } 05314 case V9::MOVFUi: { 05315 DEBUG(std::cerr << "Emitting MOVFUi\n"); 05316 Value = 2170675200U; 05317 05318 // op0: cc 05319 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05320 // op1: simm11 05321 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05322 op1 &= (1<<11) - 1; 05323 Value |= op1; 05324 // op2: rd 05325 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05326 op2 &= (1<<5) - 1; 05327 op2 <<= 25; 05328 Value |= op2; 05329 Value |= getValueBit(op0, 2) << 18; 05330 Value |= getValueBit(op0, 1) << 12; 05331 Value |= getValueBit(op0, 0) << 11; 05332 break; 05333 } 05334 case V9::MOVFUr: { 05335 DEBUG(std::cerr << "Emitting MOVFUr\n"); 05336 Value = 2170667008U; 05337 05338 // op0: cc 05339 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05340 // op1: rs2 05341 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05342 op1 &= (1<<5) - 1; 05343 Value |= op1; 05344 // op2: rd 05345 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05346 op2 &= (1<<5) - 1; 05347 op2 <<= 25; 05348 Value |= op2; 05349 Value |= getValueBit(op0, 2) << 18; 05350 Value |= getValueBit(op0, 1) << 12; 05351 Value |= getValueBit(op0, 0) << 11; 05352 break; 05353 } 05354 case V9::MOVGEi: { 05355 DEBUG(std::cerr << "Emitting MOVGEi\n"); 05356 Value = 2170740736U; 05357 05358 // op0: cc 05359 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05360 // op1: simm11 05361 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05362 op1 &= (1<<11) - 1; 05363 Value |= op1; 05364 // op2: rd 05365 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05366 op2 &= (1<<5) - 1; 05367 op2 <<= 25; 05368 Value |= op2; 05369 Value |= getValueBit(op0, 2) << 18; 05370 Value |= getValueBit(op0, 1) << 12; 05371 Value |= getValueBit(op0, 0) << 11; 05372 break; 05373 } 05374 case V9::MOVGEr: { 05375 DEBUG(std::cerr << "Emitting MOVGEr\n"); 05376 Value = 2170732544U; 05377 05378 // op0: cc 05379 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05380 // op1: rs2 05381 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05382 op1 &= (1<<5) - 1; 05383 Value |= op1; 05384 // op2: rd 05385 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05386 op2 &= (1<<5) - 1; 05387 op2 <<= 25; 05388 Value |= op2; 05389 Value |= getValueBit(op0, 2) << 18; 05390 Value |= getValueBit(op0, 1) << 12; 05391 Value |= getValueBit(op0, 0) << 11; 05392 break; 05393 } 05394 case V9::MOVGUi: { 05395 DEBUG(std::cerr << "Emitting MOVGUi\n"); 05396 Value = 2170757120U; 05397 05398 // op0: cc 05399 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05400 // op1: simm11 05401 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05402 op1 &= (1<<11) - 1; 05403 Value |= op1; 05404 // op2: rd 05405 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05406 op2 &= (1<<5) - 1; 05407 op2 <<= 25; 05408 Value |= op2; 05409 Value |= getValueBit(op0, 2) << 18; 05410 Value |= getValueBit(op0, 1) << 12; 05411 Value |= getValueBit(op0, 0) << 11; 05412 break; 05413 } 05414 case V9::MOVGUr: { 05415 DEBUG(std::cerr << "Emitting MOVGUr\n"); 05416 Value = 2170748928U; 05417 05418 // op0: cc 05419 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05420 // op1: rs2 05421 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05422 op1 &= (1<<5) - 1; 05423 Value |= op1; 05424 // op2: rd 05425 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05426 op2 &= (1<<5) - 1; 05427 op2 <<= 25; 05428 Value |= op2; 05429 Value |= getValueBit(op0, 2) << 18; 05430 Value |= getValueBit(op0, 1) << 12; 05431 Value |= getValueBit(op0, 0) << 11; 05432 break; 05433 } 05434 case V9::MOVGi: { 05435 DEBUG(std::cerr << "Emitting MOVGi\n"); 05436 Value = 2170724352U; 05437 05438 // op0: cc 05439 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05440 // op1: simm11 05441 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05442 op1 &= (1<<11) - 1; 05443 Value |= op1; 05444 // op2: rd 05445 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05446 op2 &= (1<<5) - 1; 05447 op2 <<= 25; 05448 Value |= op2; 05449 Value |= getValueBit(op0, 2) << 18; 05450 Value |= getValueBit(op0, 1) << 12; 05451 Value |= getValueBit(op0, 0) << 11; 05452 break; 05453 } 05454 case V9::MOVGr: { 05455 DEBUG(std::cerr << "Emitting MOVGr\n"); 05456 Value = 2170716160U; 05457 05458 // op0: cc 05459 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05460 // op1: rs2 05461 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05462 op1 &= (1<<5) - 1; 05463 Value |= op1; 05464 // op2: rd 05465 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05466 op2 &= (1<<5) - 1; 05467 op2 <<= 25; 05468 Value |= op2; 05469 Value |= getValueBit(op0, 2) << 18; 05470 Value |= getValueBit(op0, 1) << 12; 05471 Value |= getValueBit(op0, 0) << 11; 05472 break; 05473 } 05474 case V9::MOVLEUi: { 05475 DEBUG(std::cerr << "Emitting MOVLEUi\n"); 05476 Value = 2170626048U; 05477 05478 // op0: cc 05479 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05480 // op1: simm11 05481 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05482 op1 &= (1<<11) - 1; 05483 Value |= op1; 05484 // op2: rd 05485 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05486 op2 &= (1<<5) - 1; 05487 op2 <<= 25; 05488 Value |= op2; 05489 Value |= getValueBit(op0, 2) << 18; 05490 Value |= getValueBit(op0, 1) << 12; 05491 Value |= getValueBit(op0, 0) << 11; 05492 break; 05493 } 05494 case V9::MOVLEUr: { 05495 DEBUG(std::cerr << "Emitting MOVLEUr\n"); 05496 Value = 2170617856U; 05497 05498 // op0: cc 05499 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05500 // op1: rs2 05501 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05502 op1 &= (1<<5) - 1; 05503 Value |= op1; 05504 // op2: rd 05505 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05506 op2 &= (1<<5) - 1; 05507 op2 <<= 25; 05508 Value |= op2; 05509 Value |= getValueBit(op0, 2) << 18; 05510 Value |= getValueBit(op0, 1) << 12; 05511 Value |= getValueBit(op0, 0) << 11; 05512 break; 05513 } 05514 case V9::MOVLEi: { 05515 DEBUG(std::cerr << "Emitting MOVLEi\n"); 05516 Value = 2170593280U; 05517 05518 // op0: cc 05519 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05520 // op1: simm11 05521 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05522 op1 &= (1<<11) - 1; 05523 Value |= op1; 05524 // op2: rd 05525 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05526 op2 &= (1<<5) - 1; 05527 op2 <<= 25; 05528 Value |= op2; 05529 Value |= getValueBit(op0, 2) << 18; 05530 Value |= getValueBit(op0, 1) << 12; 05531 Value |= getValueBit(op0, 0) << 11; 05532 break; 05533 } 05534 case V9::MOVLEr: { 05535 DEBUG(std::cerr << "Emitting MOVLEr\n"); 05536 Value = 2170585088U; 05537 05538 // op0: cc 05539 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05540 // op1: rs2 05541 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05542 op1 &= (1<<5) - 1; 05543 Value |= op1; 05544 // op2: rd 05545 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05546 op2 &= (1<<5) - 1; 05547 op2 <<= 25; 05548 Value |= op2; 05549 Value |= getValueBit(op0, 2) << 18; 05550 Value |= getValueBit(op0, 1) << 12; 05551 Value |= getValueBit(op0, 0) << 11; 05552 break; 05553 } 05554 case V9::MOVLi: { 05555 DEBUG(std::cerr << "Emitting MOVLi\n"); 05556 Value = 2170609664U; 05557 05558 // op0: cc 05559 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05560 // op1: simm11 05561 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05562 op1 &= (1<<11) - 1; 05563 Value |= op1; 05564 // op2: rd 05565 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05566 op2 &= (1<<5) - 1; 05567 op2 <<= 25; 05568 Value |= op2; 05569 Value |= getValueBit(op0, 2) << 18; 05570 Value |= getValueBit(op0, 1) << 12; 05571 Value |= getValueBit(op0, 0) << 11; 05572 break; 05573 } 05574 case V9::MOVLr: { 05575 DEBUG(std::cerr << "Emitting MOVLr\n"); 05576 Value = 2170601472U; 05577 05578 // op0: cc 05579 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05580 // op1: rs2 05581 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05582 op1 &= (1<<5) - 1; 05583 Value |= op1; 05584 // op2: rd 05585 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05586 op2 &= (1<<5) - 1; 05587 op2 <<= 25; 05588 Value |= op2; 05589 Value |= getValueBit(op0, 2) << 18; 05590 Value |= getValueBit(op0, 1) << 12; 05591 Value |= getValueBit(op0, 0) << 11; 05592 break; 05593 } 05594 case V9::MOVNEGi: { 05595 DEBUG(std::cerr << "Emitting MOVNEGi\n"); 05596 Value = 2170658816U; 05597 05598 // op0: cc 05599 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05600 // op1: simm11 05601 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05602 op1 &= (1<<11) - 1; 05603 Value |= op1; 05604 // op2: rd 05605 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05606 op2 &= (1<<5) - 1; 05607 op2 <<= 25; 05608 Value |= op2; 05609 Value |= getValueBit(op0, 2) << 18; 05610 Value |= getValueBit(op0, 1) << 12; 05611 Value |= getValueBit(op0, 0) << 11; 05612 break; 05613 } 05614 case V9::MOVNEGr: { 05615 DEBUG(std::cerr << "Emitting MOVNEGr\n"); 05616 Value = 2170650624U; 05617 05618 // op0: cc 05619 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05620 // op1: rs2 05621 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05622 op1 &= (1<<5) - 1; 05623 Value |= op1; 05624 // op2: rd 05625 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05626 op2 &= (1<<5) - 1; 05627 op2 <<= 25; 05628 Value |= op2; 05629 Value |= getValueBit(op0, 2) << 18; 05630 Value |= getValueBit(op0, 1) << 12; 05631 Value |= getValueBit(op0, 0) << 11; 05632 break; 05633 } 05634 case V9::MOVNEi: { 05635 DEBUG(std::cerr << "Emitting MOVNEi\n"); 05636 Value = 2170707968U; 05637 05638 // op0: cc 05639 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05640 // op1: simm11 05641 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05642 op1 &= (1<<11) - 1; 05643 Value |= op1; 05644 // op2: rd 05645 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05646 op2 &= (1<<5) - 1; 05647 op2 <<= 25; 05648 Value |= op2; 05649 Value |= getValueBit(op0, 2) << 18; 05650 Value |= getValueBit(op0, 1) << 12; 05651 Value |= getValueBit(op0, 0) << 11; 05652 break; 05653 } 05654 case V9::MOVNEr: { 05655 DEBUG(std::cerr << "Emitting MOVNEr\n"); 05656 Value = 2170699776U; 05657 05658 // op0: cc 05659 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05660 // op1: rs2 05661 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05662 op1 &= (1<<5) - 1; 05663 Value |= op1; 05664 // op2: rd 05665 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05666 op2 &= (1<<5) - 1; 05667 op2 <<= 25; 05668 Value |= op2; 05669 Value |= getValueBit(op0, 2) << 18; 05670 Value |= getValueBit(op0, 1) << 12; 05671 Value |= getValueBit(op0, 0) << 11; 05672 break; 05673 } 05674 case V9::MOVNi: { 05675 DEBUG(std::cerr << "Emitting MOVNi\n"); 05676 Value = 2170560512U; 05677 05678 // op0: cc 05679 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05680 // op1: simm11 05681 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05682 op1 &= (1<<11) - 1; 05683 Value |= op1; 05684 // op2: rd 05685 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05686 op2 &= (1<<5) - 1; 05687 op2 <<= 25; 05688 Value |= op2; 05689 Value |= getValueBit(op0, 2) << 18; 05690 Value |= getValueBit(op0, 1) << 12; 05691 Value |= getValueBit(op0, 0) << 11; 05692 break; 05693 } 05694 case V9::MOVNr: { 05695 DEBUG(std::cerr << "Emitting MOVNr\n"); 05696 Value = 2170552320U; 05697 05698 // op0: cc 05699 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05700 // op1: rs2 05701 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05702 op1 &= (1<<5) - 1; 05703 Value |= op1; 05704 // op2: rd 05705 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05706 op2 &= (1<<5) - 1; 05707 op2 <<= 25; 05708 Value |= op2; 05709 Value |= getValueBit(op0, 2) << 18; 05710 Value |= getValueBit(op0, 1) << 12; 05711 Value |= getValueBit(op0, 0) << 11; 05712 break; 05713 } 05714 case V9::MOVPOSi: { 05715 DEBUG(std::cerr << "Emitting MOVPOSi\n"); 05716 Value = 2170789888U; 05717 05718 // op0: cc 05719 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05720 // op1: simm11 05721 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05722 op1 &= (1<<11) - 1; 05723 Value |= op1; 05724 // op2: rd 05725 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05726 op2 &= (1<<5) - 1; 05727 op2 <<= 25; 05728 Value |= op2; 05729 Value |= getValueBit(op0, 2) << 18; 05730 Value |= getValueBit(op0, 1) << 12; 05731 Value |= getValueBit(op0, 0) << 11; 05732 break; 05733 } 05734 case V9::MOVPOSr: { 05735 DEBUG(std::cerr << "Emitting MOVPOSr\n"); 05736 Value = 2170781696U; 05737 05738 // op0: cc 05739 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05740 // op1: rs2 05741 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05742 op1 &= (1<<5) - 1; 05743 Value |= op1; 05744 // op2: rd 05745 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05746 op2 &= (1<<5) - 1; 05747 op2 <<= 25; 05748 Value |= op2; 05749 Value |= getValueBit(op0, 2) << 18; 05750 Value |= getValueBit(op0, 1) << 12; 05751 Value |= getValueBit(op0, 0) << 11; 05752 break; 05753 } 05754 case V9::MOVRGEZi: { 05755 DEBUG(std::cerr << "Emitting MOVRGEZi\n"); 05756 Value = 2172140544U; 05757 05758 // op0: rs1 05759 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05760 op0 &= (1<<5) - 1; 05761 op0 <<= 14; 05762 Value |= op0; 05763 // op1: simm10 05764 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05765 op1 &= (1<<10) - 1; 05766 Value |= op1; 05767 // op2: rd 05768 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05769 op2 &= (1<<5) - 1; 05770 op2 <<= 25; 05771 Value |= op2; 05772 break; 05773 } 05774 case V9::MOVRGEZr: { 05775 DEBUG(std::cerr << "Emitting MOVRGEZr\n"); 05776 Value = 2172132352U; 05777 05778 // op0: rs1 05779 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05780 op0 &= (1<<5) - 1; 05781 op0 <<= 14; 05782 Value |= op0; 05783 // op1: rs2 05784 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05785 op1 &= (1<<5) - 1; 05786 Value |= op1; 05787 // op2: rd 05788 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05789 op2 &= (1<<5) - 1; 05790 op2 <<= 25; 05791 Value |= op2; 05792 break; 05793 } 05794 case V9::MOVRGZi: { 05795 DEBUG(std::cerr << "Emitting MOVRGZi\n"); 05796 Value = 2172139520U; 05797 05798 // op0: rs1 05799 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05800 op0 &= (1<<5) - 1; 05801 op0 <<= 14; 05802 Value |= op0; 05803 // op1: simm10 05804 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05805 op1 &= (1<<10) - 1; 05806 Value |= op1; 05807 // op2: rd 05808 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05809 op2 &= (1<<5) - 1; 05810 op2 <<= 25; 05811 Value |= op2; 05812 break; 05813 } 05814 case V9::MOVRGZr: { 05815 DEBUG(std::cerr << "Emitting MOVRGZr\n"); 05816 Value = 2172131328U; 05817 05818 // op0: rs1 05819 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05820 op0 &= (1<<5) - 1; 05821 op0 <<= 14; 05822 Value |= op0; 05823 // op1: rs2 05824 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05825 op1 &= (1<<5) - 1; 05826 Value |= op1; 05827 // op2: rd 05828 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05829 op2 &= (1<<5) - 1; 05830 op2 <<= 25; 05831 Value |= op2; 05832 break; 05833 } 05834 case V9::MOVRLEZi: { 05835 DEBUG(std::cerr << "Emitting MOVRLEZi\n"); 05836 Value = 2172135424U; 05837 05838 // op0: rs1 05839 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05840 op0 &= (1<<5) - 1; 05841 op0 <<= 14; 05842 Value |= op0; 05843 // op1: simm10 05844 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05845 op1 &= (1<<10) - 1; 05846 Value |= op1; 05847 // op2: rd 05848 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05849 op2 &= (1<<5) - 1; 05850 op2 <<= 25; 05851 Value |= op2; 05852 break; 05853 } 05854 case V9::MOVRLEZr: { 05855 DEBUG(std::cerr << "Emitting MOVRLEZr\n"); 05856 Value = 2172127232U; 05857 05858 // op0: rs1 05859 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05860 op0 &= (1<<5) - 1; 05861 op0 <<= 14; 05862 Value |= op0; 05863 // op1: rs2 05864 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05865 op1 &= (1<<5) - 1; 05866 Value |= op1; 05867 // op2: rd 05868 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05869 op2 &= (1<<5) - 1; 05870 op2 <<= 25; 05871 Value |= op2; 05872 break; 05873 } 05874 case V9::MOVRLZi: { 05875 DEBUG(std::cerr << "Emitting MOVRLZi\n"); 05876 Value = 2172136448U; 05877 05878 // op0: rs1 05879 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05880 op0 &= (1<<5) - 1; 05881 op0 <<= 14; 05882 Value |= op0; 05883 // op1: simm10 05884 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05885 op1 &= (1<<10) - 1; 05886 Value |= op1; 05887 // op2: rd 05888 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05889 op2 &= (1<<5) - 1; 05890 op2 <<= 25; 05891 Value |= op2; 05892 break; 05893 } 05894 case V9::MOVRLZr: { 05895 DEBUG(std::cerr << "Emitting MOVRLZr\n"); 05896 Value = 2172128256U; 05897 05898 // op0: rs1 05899 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05900 op0 &= (1<<5) - 1; 05901 op0 <<= 14; 05902 Value |= op0; 05903 // op1: rs2 05904 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05905 op1 &= (1<<5) - 1; 05906 Value |= op1; 05907 // op2: rd 05908 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05909 op2 &= (1<<5) - 1; 05910 op2 <<= 25; 05911 Value |= op2; 05912 break; 05913 } 05914 case V9::MOVRNZi: { 05915 DEBUG(std::cerr << "Emitting MOVRNZi\n"); 05916 Value = 2172138496U; 05917 05918 // op0: rs1 05919 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05920 op0 &= (1<<5) - 1; 05921 op0 <<= 14; 05922 Value |= op0; 05923 // op1: simm10 05924 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05925 op1 &= (1<<10) - 1; 05926 Value |= op1; 05927 // op2: rd 05928 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05929 op2 &= (1<<5) - 1; 05930 op2 <<= 25; 05931 Value |= op2; 05932 break; 05933 } 05934 case V9::MOVRNZr: { 05935 DEBUG(std::cerr << "Emitting MOVRNZr\n"); 05936 Value = 2172130304U; 05937 05938 // op0: rs1 05939 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05940 op0 &= (1<<5) - 1; 05941 op0 <<= 14; 05942 Value |= op0; 05943 // op1: rs2 05944 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05945 op1 &= (1<<5) - 1; 05946 Value |= op1; 05947 // op2: rd 05948 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05949 op2 &= (1<<5) - 1; 05950 op2 <<= 25; 05951 Value |= op2; 05952 break; 05953 } 05954 case V9::MOVRZi: { 05955 DEBUG(std::cerr << "Emitting MOVRZi\n"); 05956 Value = 2172134400U; 05957 05958 // op0: rs1 05959 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05960 op0 &= (1<<5) - 1; 05961 op0 <<= 14; 05962 Value |= op0; 05963 // op1: simm10 05964 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05965 op1 &= (1<<10) - 1; 05966 Value |= op1; 05967 // op2: rd 05968 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05969 op2 &= (1<<5) - 1; 05970 op2 <<= 25; 05971 Value |= op2; 05972 break; 05973 } 05974 case V9::MOVRZr: { 05975 DEBUG(std::cerr << "Emitting MOVRZr\n"); 05976 Value = 2172126208U; 05977 05978 // op0: rs1 05979 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 05980 op0 &= (1<<5) - 1; 05981 op0 <<= 14; 05982 Value |= op0; 05983 // op1: rs2 05984 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 05985 op1 &= (1<<5) - 1; 05986 Value |= op1; 05987 // op2: rd 05988 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 05989 op2 &= (1<<5) - 1; 05990 op2 <<= 25; 05991 Value |= op2; 05992 break; 05993 } 05994 case V9::MOVVCi: { 05995 DEBUG(std::cerr << "Emitting MOVVCi\n"); 05996 Value = 2170806272U; 05997 05998 // op0: cc 05999 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06000 // op1: simm11 06001 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06002 op1 &= (1<<11) - 1; 06003 Value |= op1; 06004 // op2: rd 06005 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06006 op2 &= (1<<5) - 1; 06007 op2 <<= 25; 06008 Value |= op2; 06009 Value |= getValueBit(op0, 2) << 18; 06010 Value |= getValueBit(op0, 1) << 12; 06011 Value |= getValueBit(op0, 0) << 11; 06012 break; 06013 } 06014 case V9::MOVVCr: { 06015 DEBUG(std::cerr << "Emitting MOVVCr\n"); 06016 Value = 2170798080U; 06017 06018 // op0: cc 06019 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06020 // op1: rs2 06021 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06022 op1 &= (1<<5) - 1; 06023 Value |= op1; 06024 // op2: rd 06025 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06026 op2 &= (1<<5) - 1; 06027 op2 <<= 25; 06028 Value |= op2; 06029 Value |= getValueBit(op0, 2) << 18; 06030 Value |= getValueBit(op0, 1) << 12; 06031 Value |= getValueBit(op0, 0) << 11; 06032 break; 06033 } 06034 case V9::MOVVSi: { 06035 DEBUG(std::cerr << "Emitting MOVVSi\n"); 06036 Value = 2170675200U; 06037 06038 // op0: cc 06039 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06040 // op1: simm11 06041 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06042 op1 &= (1<<11) - 1; 06043 Value |= op1; 06044 // op2: rd 06045 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06046 op2 &= (1<<5) - 1; 06047 op2 <<= 25; 06048 Value |= op2; 06049 Value |= getValueBit(op0, 2) << 18; 06050 Value |= getValueBit(op0, 1) << 12; 06051 Value |= getValueBit(op0, 0) << 11; 06052 break; 06053 } 06054 case V9::MOVVSr: { 06055 DEBUG(std::cerr << "Emitting MOVVSr\n"); 06056 Value = 2170667008U; 06057 06058 // op0: cc 06059 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06060 // op1: rs2 06061 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06062 op1 &= (1<<5) - 1; 06063 Value |= op1; 06064 // op2: rd 06065 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06066 op2 &= (1<<5) - 1; 06067 op2 <<= 25; 06068 Value |= op2; 06069 Value |= getValueBit(op0, 2) << 18; 06070 Value |= getValueBit(op0, 1) << 12; 06071 Value |= getValueBit(op0, 0) << 11; 06072 break; 06073 } 06074 case V9::MULXi: { 06075 DEBUG(std::cerr << "Emitting MULXi\n"); 06076 Value = 2152210432U; 06077 06078 // op0: rs1 06079 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06080 op0 &= (1<<5) - 1; 06081 op0 <<= 14; 06082 Value |= op0; 06083 // op1: simm13 06084 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06085 op1 &= (1<<13) - 1; 06086 Value |= op1; 06087 // op2: rd 06088 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06089 op2 &= (1<<5) - 1; 06090 op2 <<= 25; 06091 Value |= op2; 06092 break; 06093 } 06094 case V9::MULXr: { 06095 DEBUG(std::cerr << "Emitting MULXr\n"); 06096 Value = 2152202240U; 06097 06098 // op0: rs1 06099 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06100 op0 &= (1<<5) - 1; 06101 op0 <<= 14; 06102 Value |= op0; 06103 // op1: rs2 06104 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06105 op1 &= (1<<5) - 1; 06106 Value |= op1; 06107 // op2: rd 06108 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06109 op2 &= (1<<5) - 1; 06110 op2 <<= 25; 06111 Value |= op2; 06112 break; 06113 } 06114 case V9::NOP: { 06115 DEBUG(std::cerr << "Emitting NOP\n"); 06116 Value = 16777216U; 06117 06118 break; 06119 } 06120 case V9::ORNcci: { 06121 DEBUG(std::cerr << "Emitting ORNcci\n"); 06122 Value = 2159026176U; 06123 06124 // op0: rs1 06125 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06126 op0 &= (1<<5) - 1; 06127 op0 <<= 14; 06128 Value |= op0; 06129 // op1: simm13 06130 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06131 op1 &= (1<<13) - 1; 06132 Value |= op1; 06133 // op2: rd 06134 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06135 op2 &= (1<<5) - 1; 06136 op2 <<= 25; 06137 Value |= op2; 06138 break; 06139 } 06140 case V9::ORNccr: { 06141 DEBUG(std::cerr << "Emitting ORNccr\n"); 06142 Value = 2159017984U; 06143 06144 // op0: rs1 06145 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06146 op0 &= (1<<5) - 1; 06147 op0 <<= 14; 06148 Value |= op0; 06149 // op1: rs2 06150 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06151 op1 &= (1<<5) - 1; 06152 Value |= op1; 06153 // op2: rd 06154 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06155 op2 &= (1<<5) - 1; 06156 op2 <<= 25; 06157 Value |= op2; 06158 break; 06159 } 06160 case V9::ORNi: { 06161 DEBUG(std::cerr << "Emitting ORNi\n"); 06162 Value = 2150637568U; 06163 06164 // op0: rs1 06165 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06166 op0 &= (1<<5) - 1; 06167 op0 <<= 14; 06168 Value |= op0; 06169 // op1: simm13 06170 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06171 op1 &= (1<<13) - 1; 06172 Value |= op1; 06173 // op2: rd 06174 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06175 op2 &= (1<<5) - 1; 06176 op2 <<= 25; 06177 Value |= op2; 06178 break; 06179 } 06180 case V9::ORNr: { 06181 DEBUG(std::cerr << "Emitting ORNr\n"); 06182 Value = 2150629376U; 06183 06184 // op0: rs1 06185 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06186 op0 &= (1<<5) - 1; 06187 op0 <<= 14; 06188 Value |= op0; 06189 // op1: rs2 06190 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06191 op1 &= (1<<5) - 1; 06192 Value |= op1; 06193 // op2: rd 06194 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06195 op2 &= (1<<5) - 1; 06196 op2 <<= 25; 06197 Value |= op2; 06198 break; 06199 } 06200 case V9::ORcci: { 06201 DEBUG(std::cerr << "Emitting ORcci\n"); 06202 Value = 2156929024U; 06203 06204 // op0: rs1 06205 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06206 op0 &= (1<<5) - 1; 06207 op0 <<= 14; 06208 Value |= op0; 06209 // op1: simm13 06210 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06211 op1 &= (1<<13) - 1; 06212 Value |= op1; 06213 // op2: rd 06214 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06215 op2 &= (1<<5) - 1; 06216 op2 <<= 25; 06217 Value |= op2; 06218 break; 06219 } 06220 case V9::ORccr: { 06221 DEBUG(std::cerr << "Emitting ORccr\n"); 06222 Value = 2156920832U; 06223 06224 // op0: rs1 06225 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06226 op0 &= (1<<5) - 1; 06227 op0 <<= 14; 06228 Value |= op0; 06229 // op1: rs2 06230 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06231 op1 &= (1<<5) - 1; 06232 Value |= op1; 06233 // op2: rd 06234 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06235 op2 &= (1<<5) - 1; 06236 op2 <<= 25; 06237 Value |= op2; 06238 break; 06239 } 06240 case V9::ORi: { 06241 DEBUG(std::cerr << "Emitting ORi\n"); 06242 Value = 2148540416U; 06243 06244 // op0: rs1 06245 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06246 op0 &= (1<<5) - 1; 06247 op0 <<= 14; 06248 Value |= op0; 06249 // op1: simm13 06250 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06251 op1 &= (1<<13) - 1; 06252 Value |= op1; 06253 // op2: rd 06254 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06255 op2 &= (1<<5) - 1; 06256 op2 <<= 25; 06257 Value |= op2; 06258 break; 06259 } 06260 case V9::ORr: { 06261 DEBUG(std::cerr << "Emitting ORr\n"); 06262 Value = 2148532224U; 06263 06264 // op0: rs1 06265 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06266 op0 &= (1<<5) - 1; 06267 op0 <<= 14; 06268 Value |= op0; 06269 // op1: rs2 06270 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06271 op1 &= (1<<5) - 1; 06272 Value |= op1; 06273 // op2: rd 06274 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06275 op2 &= (1<<5) - 1; 06276 op2 <<= 25; 06277 Value |= op2; 06278 break; 06279 } 06280 case V9::PHI: { 06281 DEBUG(std::cerr << "Emitting PHI\n"); 06282 Value = 0U; 06283 06284 break; 06285 } 06286 case V9::RDCCR: { 06287 DEBUG(std::cerr << "Emitting RDCCR\n"); 06288 Value = 2168487936U; 06289 06290 // op0: rd 06291 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06292 op0 &= (1<<5) - 1; 06293 op0 <<= 25; 06294 Value |= op0; 06295 break; 06296 } 06297 case V9::RESTOREi: { 06298 DEBUG(std::cerr << "Emitting RESTOREi\n"); 06299 Value = 2179473408U; 06300 06301 // op0: rs1 06302 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06303 op0 &= (1<<5) - 1; 06304 op0 <<= 14; 06305 Value |= op0; 06306 // op1: simm13 06307 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06308 op1 &= (1<<13) - 1; 06309 Value |= op1; 06310 // op2: rd 06311 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06312 op2 &= (1<<5) - 1; 06313 op2 <<= 25; 06314 Value |= op2; 06315 break; 06316 } 06317 case V9::RESTOREr: { 06318 DEBUG(std::cerr << "Emitting RESTOREr\n"); 06319 Value = 2179465216U; 06320 06321 // op0: rs1 06322 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06323 op0 &= (1<<5) - 1; 06324 op0 <<= 14; 06325 Value |= op0; 06326 // op1: rs2 06327 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06328 op1 &= (1<<5) - 1; 06329 Value |= op1; 06330 // op2: rd 06331 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06332 op2 &= (1<<5) - 1; 06333 op2 <<= 25; 06334 Value |= op2; 06335 break; 06336 } 06337 case V9::SAVEi: { 06338 DEBUG(std::cerr << "Emitting SAVEi\n"); 06339 Value = 2178949120U; 06340 06341 // op0: rs1 06342 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06343 op0 &= (1<<5) - 1; 06344 op0 <<= 14; 06345 Value |= op0; 06346 // op1: simm13 06347 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06348 op1 &= (1<<13) - 1; 06349 Value |= op1; 06350 // op2: rd 06351 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06352 op2 &= (1<<5) - 1; 06353 op2 <<= 25; 06354 Value |= op2; 06355 break; 06356 } 06357 case V9::SAVEr: { 06358 DEBUG(std::cerr << "Emitting SAVEr\n"); 06359 Value = 2178940928U; 06360 06361 // op0: rs1 06362 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06363 op0 &= (1<<5) - 1; 06364 op0 <<= 14; 06365 Value |= op0; 06366 // op1: rs2 06367 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06368 op1 &= (1<<5) - 1; 06369 Value |= op1; 06370 // op2: rd 06371 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06372 op2 &= (1<<5) - 1; 06373 op2 <<= 25; 06374 Value |= op2; 06375 break; 06376 } 06377 case V9::SDIVXi: { 06378 DEBUG(std::cerr << "Emitting SDIVXi\n"); 06379 Value = 2171084800U; 06380 06381 // op0: rs1 06382 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06383 op0 &= (1<<5) - 1; 06384 op0 <<= 14; 06385 Value |= op0; 06386 // op1: simm13 06387 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06388 op1 &= (1<<13) - 1; 06389 Value |= op1; 06390 // op2: rd 06391 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06392 op2 &= (1<<5) - 1; 06393 op2 <<= 25; 06394 Value |= op2; 06395 break; 06396 } 06397 case V9::SDIVXr: { 06398 DEBUG(std::cerr << "Emitting SDIVXr\n"); 06399 Value = 2171076608U; 06400 06401 // op0: rs1 06402 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06403 op0 &= (1<<5) - 1; 06404 op0 <<= 14; 06405 Value |= op0; 06406 // op1: rs2 06407 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06408 op1 &= (1<<5) - 1; 06409 Value |= op1; 06410 // op2: rd 06411 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06412 op2 &= (1<<5) - 1; 06413 op2 <<= 25; 06414 Value |= op2; 06415 break; 06416 } 06417 case V9::SETHI: { 06418 DEBUG(std::cerr << "Emitting SETHI\n"); 06419 Value = 16777216U; 06420 06421 // op0: imm 06422 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06423 op0 &= (1<<22) - 1; 06424 Value |= op0; 06425 // op1: rd 06426 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06427 op1 &= (1<<5) - 1; 06428 op1 <<= 25; 06429 Value |= op1; 06430 break; 06431 } 06432 case V9::SLLXi6: { 06433 DEBUG(std::cerr << "Emitting SLLXi6\n"); 06434 Value = 2166894592U; 06435 06436 // op0: rs1 06437 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06438 op0 &= (1<<5) - 1; 06439 op0 <<= 14; 06440 Value |= op0; 06441 // op1: shcnt 06442 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06443 op1 &= (1<<6) - 1; 06444 Value |= op1; 06445 // op2: rd 06446 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06447 op2 &= (1<<5) - 1; 06448 op2 <<= 25; 06449 Value |= op2; 06450 break; 06451 } 06452 case V9::SLLXr6: { 06453 DEBUG(std::cerr << "Emitting SLLXr6\n"); 06454 Value = 2166886400U; 06455 06456 // op0: rs1 06457 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06458 op0 &= (1<<5) - 1; 06459 op0 <<= 14; 06460 Value |= op0; 06461 // op1: rs2 06462 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06463 op1 &= (1<<5) - 1; 06464 Value |= op1; 06465 // op2: rd 06466 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06467 op2 &= (1<<5) - 1; 06468 op2 <<= 25; 06469 Value |= op2; 06470 break; 06471 } 06472 case V9::SLLi5: { 06473 DEBUG(std::cerr << "Emitting SLLi5\n"); 06474 Value = 2166890496U; 06475 06476 // op0: rs1 06477 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06478 op0 &= (1<<5) - 1; 06479 op0 <<= 14; 06480 Value |= op0; 06481 // op1: shcnt 06482 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06483 op1 &= (1<<5) - 1; 06484 Value |= op1; 06485 // op2: rd 06486 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06487 op2 &= (1<<5) - 1; 06488 op2 <<= 25; 06489 Value |= op2; 06490 break; 06491 } 06492 case V9::SLLr5: { 06493 DEBUG(std::cerr << "Emitting SLLr5\n"); 06494 Value = 2166882304U; 06495 06496 // op0: rs1 06497 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06498 op0 &= (1<<5) - 1; 06499 op0 <<= 14; 06500 Value |= op0; 06501 // op1: rs2 06502 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06503 op1 &= (1<<5) - 1; 06504 Value |= op1; 06505 // op2: rd 06506 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06507 op2 &= (1<<5) - 1; 06508 op2 <<= 25; 06509 Value |= op2; 06510 break; 06511 } 06512 case V9::SRAXi6: { 06513 DEBUG(std::cerr << "Emitting SRAXi6\n"); 06514 Value = 2167943168U; 06515 06516 // op0: rs1 06517 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06518 op0 &= (1<<5) - 1; 06519 op0 <<= 14; 06520 Value |= op0; 06521 // op1: shcnt 06522 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06523 op1 &= (1<<6) - 1; 06524 Value |= op1; 06525 // op2: rd 06526 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06527 op2 &= (1<<5) - 1; 06528 op2 <<= 25; 06529 Value |= op2; 06530 break; 06531 } 06532 case V9::SRAXr6: { 06533 DEBUG(std::cerr << "Emitting SRAXr6\n"); 06534 Value = 2167934976U; 06535 06536 // op0: rs1 06537 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06538 op0 &= (1<<5) - 1; 06539 op0 <<= 14; 06540 Value |= op0; 06541 // op1: rs2 06542 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06543 op1 &= (1<<5) - 1; 06544 Value |= op1; 06545 // op2: rd 06546 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06547 op2 &= (1<<5) - 1; 06548 op2 <<= 25; 06549 Value |= op2; 06550 break; 06551 } 06552 case V9::SRAi5: { 06553 DEBUG(std::cerr << "Emitting SRAi5\n"); 06554 Value = 2167939072U; 06555 06556 // op0: rs1 06557 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06558 op0 &= (1<<5) - 1; 06559 op0 <<= 14; 06560 Value |= op0; 06561 // op1: shcnt 06562 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06563 op1 &= (1<<5) - 1; 06564 Value |= op1; 06565 // op2: rd 06566 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06567 op2 &= (1<<5) - 1; 06568 op2 <<= 25; 06569 Value |= op2; 06570 break; 06571 } 06572 case V9::SRAr5: { 06573 DEBUG(std::cerr << "Emitting SRAr5\n"); 06574 Value = 2167930880U; 06575 06576 // op0: rs1 06577 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06578 op0 &= (1<<5) - 1; 06579 op0 <<= 14; 06580 Value |= op0; 06581 // op1: rs2 06582 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06583 op1 &= (1<<5) - 1; 06584 Value |= op1; 06585 // op2: rd 06586 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06587 op2 &= (1<<5) - 1; 06588 op2 <<= 25; 06589 Value |= op2; 06590 break; 06591 } 06592 case V9::SRLXi6: { 06593 DEBUG(std::cerr << "Emitting SRLXi6\n"); 06594 Value = 2167418880U; 06595 06596 // op0: rs1 06597 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06598 op0 &= (1<<5) - 1; 06599 op0 <<= 14; 06600 Value |= op0; 06601 // op1: shcnt 06602 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06603 op1 &= (1<<6) - 1; 06604 Value |= op1; 06605 // op2: rd 06606 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06607 op2 &= (1<<5) - 1; 06608 op2 <<= 25; 06609 Value |= op2; 06610 break; 06611 } 06612 case V9::SRLXr6: { 06613 DEBUG(std::cerr << "Emitting SRLXr6\n"); 06614 Value = 2167410688U; 06615 06616 // op0: rs1 06617 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06618 op0 &= (1<<5) - 1; 06619 op0 <<= 14; 06620 Value |= op0; 06621 // op1: rs2 06622 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06623 op1 &= (1<<5) - 1; 06624 Value |= op1; 06625 // op2: rd 06626 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06627 op2 &= (1<<5) - 1; 06628 op2 <<= 25; 06629 Value |= op2; 06630 break; 06631 } 06632 case V9::SRLi5: { 06633 DEBUG(std::cerr << "Emitting SRLi5\n"); 06634 Value = 2167414784U; 06635 06636 // op0: rs1 06637 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06638 op0 &= (1<<5) - 1; 06639 op0 <<= 14; 06640 Value |= op0; 06641 // op1: shcnt 06642 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06643 op1 &= (1<<5) - 1; 06644 Value |= op1; 06645 // op2: rd 06646 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06647 op2 &= (1<<5) - 1; 06648 op2 <<= 25; 06649 Value |= op2; 06650 break; 06651 } 06652 case V9::SRLr5: { 06653 DEBUG(std::cerr << "Emitting SRLr5\n"); 06654 Value = 2167406592U; 06655 06656 // op0: rs1 06657 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06658 op0 &= (1<<5) - 1; 06659 op0 <<= 14; 06660 Value |= op0; 06661 // op1: rs2 06662 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06663 op1 &= (1<<5) - 1; 06664 Value |= op1; 06665 // op2: rd 06666 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06667 op2 &= (1<<5) - 1; 06668 op2 <<= 25; 06669 Value |= op2; 06670 break; 06671 } 06672 case V9::STBi: { 06673 DEBUG(std::cerr << "Emitting STBi\n"); 06674 Value = 3223855104U; 06675 06676 // op0: rd 06677 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06678 op0 &= (1<<5) - 1; 06679 op0 <<= 25; 06680 Value |= op0; 06681 // op1: rs1 06682 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06683 op1 &= (1<<5) - 1; 06684 op1 <<= 14; 06685 Value |= op1; 06686 // op2: simm13 06687 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06688 op2 &= (1<<13) - 1; 06689 Value |= op2; 06690 break; 06691 } 06692 case V9::STBr: { 06693 DEBUG(std::cerr << "Emitting STBr\n"); 06694 Value = 3223846912U; 06695 06696 // op0: rd 06697 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06698 op0 &= (1<<5) - 1; 06699 op0 <<= 25; 06700 Value |= op0; 06701 // op1: rs1 06702 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06703 op1 &= (1<<5) - 1; 06704 op1 <<= 14; 06705 Value |= op1; 06706 // op2: rs2 06707 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06708 op2 &= (1<<5) - 1; 06709 Value |= op2; 06710 break; 06711 } 06712 case V9::STDFi: { 06713 DEBUG(std::cerr << "Emitting STDFi\n"); 06714 Value = 3241680896U; 06715 06716 // op0: rd 06717 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06718 op0 &= (1<<5) - 1; 06719 op0 <<= 25; 06720 Value |= op0; 06721 // op1: rs1 06722 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06723 op1 &= (1<<5) - 1; 06724 op1 <<= 14; 06725 Value |= op1; 06726 // op2: simm13 06727 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06728 op2 &= (1<<13) - 1; 06729 Value |= op2; 06730 break; 06731 } 06732 case V9::STDFr: { 06733 DEBUG(std::cerr << "Emitting STDFr\n"); 06734 Value = 3241672704U; 06735 06736 // op0: rd 06737 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06738 op0 &= (1<<5) - 1; 06739 op0 <<= 25; 06740 Value |= op0; 06741 // op1: rs1 06742 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06743 op1 &= (1<<5) - 1; 06744 op1 <<= 14; 06745 Value |= op1; 06746 // op2: rs2 06747 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06748 op2 &= (1<<5) - 1; 06749 Value |= op2; 06750 break; 06751 } 06752 case V9::STFi: { 06753 DEBUG(std::cerr << "Emitting STFi\n"); 06754 Value = 3240108032U; 06755 06756 // op0: rd 06757 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06758 op0 &= (1<<5) - 1; 06759 op0 <<= 25; 06760 Value |= op0; 06761 // op1: rs1 06762 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06763 op1 &= (1<<5) - 1; 06764 op1 <<= 14; 06765 Value |= op1; 06766 // op2: simm13 06767 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06768 op2 &= (1<<13) - 1; 06769 Value |= op2; 06770 break; 06771 } 06772 case V9::STFr: { 06773 DEBUG(std::cerr << "Emitting STFr\n"); 06774 Value = 3240099840U; 06775 06776 // op0: rd 06777 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06778 op0 &= (1<<5) - 1; 06779 op0 <<= 25; 06780 Value |= op0; 06781 // op1: rs1 06782 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06783 op1 &= (1<<5) - 1; 06784 op1 <<= 14; 06785 Value |= op1; 06786 // op2: rs2 06787 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06788 op2 &= (1<<5) - 1; 06789 Value |= op2; 06790 break; 06791 } 06792 case V9::STHi: { 06793 DEBUG(std::cerr << "Emitting STHi\n"); 06794 Value = 3224379392U; 06795 06796 // op0: rd 06797 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06798 op0 &= (1<<5) - 1; 06799 op0 <<= 25; 06800 Value |= op0; 06801 // op1: rs1 06802 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06803 op1 &= (1<<5) - 1; 06804 op1 <<= 14; 06805 Value |= op1; 06806 // op2: simm13 06807 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06808 op2 &= (1<<13) - 1; 06809 Value |= op2; 06810 break; 06811 } 06812 case V9::STHr: { 06813 DEBUG(std::cerr << "Emitting STHr\n"); 06814 Value = 3224371200U; 06815 06816 // op0: rd 06817 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06818 op0 &= (1<<5) - 1; 06819 op0 <<= 25; 06820 Value |= op0; 06821 // op1: rs1 06822 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06823 op1 &= (1<<5) - 1; 06824 op1 <<= 14; 06825 Value |= op1; 06826 // op2: rs2 06827 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06828 op2 &= (1<<5) - 1; 06829 Value |= op2; 06830 break; 06831 } 06832 case V9::STWi: { 06833 DEBUG(std::cerr << "Emitting STWi\n"); 06834 Value = 3223330816U; 06835 06836 // op0: rd 06837 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06838 op0 &= (1<<5) - 1; 06839 op0 <<= 25; 06840 Value |= op0; 06841 // op1: rs1 06842 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06843 op1 &= (1<<5) - 1; 06844 op1 <<= 14; 06845 Value |= op1; 06846 // op2: simm13 06847 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06848 op2 &= (1<<13) - 1; 06849 Value |= op2; 06850 break; 06851 } 06852 case V9::STWr: { 06853 DEBUG(std::cerr << "Emitting STWr\n"); 06854 Value = 3223322624U; 06855 06856 // op0: rd 06857 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06858 op0 &= (1<<5) - 1; 06859 op0 <<= 25; 06860 Value |= op0; 06861 // op1: rs1 06862 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06863 op1 &= (1<<5) - 1; 06864 op1 <<= 14; 06865 Value |= op1; 06866 // op2: rs2 06867 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06868 op2 &= (1<<5) - 1; 06869 Value |= op2; 06870 break; 06871 } 06872 case V9::STXFSRi: { 06873 DEBUG(std::cerr << "Emitting STXFSRi\n"); 06874 Value = 3240632320U; 06875 06876 // op0: rd 06877 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06878 op0 &= (1<<5) - 1; 06879 op0 <<= 25; 06880 Value |= op0; 06881 // op1: rs1 06882 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06883 op1 &= (1<<5) - 1; 06884 op1 <<= 14; 06885 Value |= op1; 06886 // op2: simm13 06887 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06888 op2 &= (1<<13) - 1; 06889 Value |= op2; 06890 break; 06891 } 06892 case V9::STXFSRr: { 06893 DEBUG(std::cerr << "Emitting STXFSRr\n"); 06894 Value = 3240624128U; 06895 06896 // op0: rd 06897 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06898 op0 &= (1<<5) - 1; 06899 op0 <<= 25; 06900 Value |= op0; 06901 // op1: rs1 06902 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06903 op1 &= (1<<5) - 1; 06904 op1 <<= 14; 06905 Value |= op1; 06906 // op2: rs2 06907 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06908 op2 &= (1<<5) - 1; 06909 Value |= op2; 06910 break; 06911 } 06912 case V9::STXi: { 06913 DEBUG(std::cerr << "Emitting STXi\n"); 06914 Value = 3228573696U; 06915 06916 // op0: rd 06917 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06918 op0 &= (1<<5) - 1; 06919 op0 <<= 25; 06920 Value |= op0; 06921 // op1: rs1 06922 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06923 op1 &= (1<<5) - 1; 06924 op1 <<= 14; 06925 Value |= op1; 06926 // op2: simm13 06927 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06928 op2 &= (1<<13) - 1; 06929 Value |= op2; 06930 break; 06931 } 06932 case V9::STXr: { 06933 DEBUG(std::cerr << "Emitting STXr\n"); 06934 Value = 3228565504U; 06935 06936 // op0: rd 06937 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06938 op0 &= (1<<5) - 1; 06939 op0 <<= 25; 06940 Value |= op0; 06941 // op1: rs1 06942 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06943 op1 &= (1<<5) - 1; 06944 op1 <<= 14; 06945 Value |= op1; 06946 // op2: rs2 06947 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06948 op2 &= (1<<5) - 1; 06949 Value |= op2; 06950 break; 06951 } 06952 case V9::SUBCcci: { 06953 DEBUG(std::cerr << "Emitting SUBCcci\n"); 06954 Value = 2162171904U; 06955 06956 // op0: rs1 06957 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06958 op0 &= (1<<5) - 1; 06959 op0 <<= 14; 06960 Value |= op0; 06961 // op1: simm13 06962 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06963 op1 &= (1<<13) - 1; 06964 Value |= op1; 06965 // op2: rd 06966 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06967 op2 &= (1<<5) - 1; 06968 op2 <<= 25; 06969 Value |= op2; 06970 break; 06971 } 06972 case V9::SUBCccr: { 06973 DEBUG(std::cerr << "Emitting SUBCccr\n"); 06974 Value = 2162163712U; 06975 06976 // op0: rs1 06977 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06978 op0 &= (1<<5) - 1; 06979 op0 <<= 14; 06980 Value |= op0; 06981 // op1: rs2 06982 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 06983 op1 &= (1<<5) - 1; 06984 Value |= op1; 06985 // op2: rd 06986 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 06987 op2 &= (1<<5) - 1; 06988 op2 <<= 25; 06989 Value |= op2; 06990 break; 06991 } 06992 case V9::SUBCi: { 06993 DEBUG(std::cerr << "Emitting SUBCi\n"); 06994 Value = 2153783296U; 06995 06996 // op0: rs1 06997 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 06998 op0 &= (1<<5) - 1; 06999 op0 <<= 14; 07000 Value |= op0; 07001 // op1: simm13 07002 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07003 op1 &= (1<<13) - 1; 07004 Value |= op1; 07005 // op2: rd 07006 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07007 op2 &= (1<<5) - 1; 07008 op2 <<= 25; 07009 Value |= op2; 07010 break; 07011 } 07012 case V9::SUBCr: { 07013 DEBUG(std::cerr << "Emitting SUBCr\n"); 07014 Value = 2153775104U; 07015 07016 // op0: rs1 07017 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07018 op0 &= (1<<5) - 1; 07019 op0 <<= 14; 07020 Value |= op0; 07021 // op1: rs2 07022 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07023 op1 &= (1<<5) - 1; 07024 Value |= op1; 07025 // op2: rd 07026 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07027 op2 &= (1<<5) - 1; 07028 op2 <<= 25; 07029 Value |= op2; 07030 break; 07031 } 07032 case V9::SUBcci: { 07033 DEBUG(std::cerr << "Emitting SUBcci\n"); 07034 Value = 2157977600U; 07035 07036 // op0: rs1 07037 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07038 op0 &= (1<<5) - 1; 07039 op0 <<= 14; 07040 Value |= op0; 07041 // op1: simm13 07042 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07043 op1 &= (1<<13) - 1; 07044 Value |= op1; 07045 // op2: rd 07046 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07047 op2 &= (1<<5) - 1; 07048 op2 <<= 25; 07049 Value |= op2; 07050 break; 07051 } 07052 case V9::SUBccr: { 07053 DEBUG(std::cerr << "Emitting SUBccr\n"); 07054 Value = 2157969408U; 07055 07056 // op0: rs1 07057 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07058 op0 &= (1<<5) - 1; 07059 op0 <<= 14; 07060 Value |= op0; 07061 // op1: rs2 07062 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07063 op1 &= (1<<5) - 1; 07064 Value |= op1; 07065 // op2: rd 07066 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07067 op2 &= (1<<5) - 1; 07068 op2 <<= 25; 07069 Value |= op2; 07070 break; 07071 } 07072 case V9::SUBi: { 07073 DEBUG(std::cerr << "Emitting SUBi\n"); 07074 Value = 2149588992U; 07075 07076 // op0: rs1 07077 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07078 op0 &= (1<<5) - 1; 07079 op0 <<= 14; 07080 Value |= op0; 07081 // op1: simm13 07082 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07083 op1 &= (1<<13) - 1; 07084 Value |= op1; 07085 // op2: rd 07086 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07087 op2 &= (1<<5) - 1; 07088 op2 <<= 25; 07089 Value |= op2; 07090 break; 07091 } 07092 case V9::SUBr: { 07093 DEBUG(std::cerr << "Emitting SUBr\n"); 07094 Value = 2149580800U; 07095 07096 // op0: rs1 07097 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07098 op0 &= (1<<5) - 1; 07099 op0 <<= 14; 07100 Value |= op0; 07101 // op1: rs2 07102 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07103 op1 &= (1<<5) - 1; 07104 Value |= op1; 07105 // op2: rd 07106 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07107 op2 &= (1<<5) - 1; 07108 op2 <<= 25; 07109 Value |= op2; 07110 break; 07111 } 07112 case V9::UDIVXi: { 07113 DEBUG(std::cerr << "Emitting UDIVXi\n"); 07114 Value = 2154307584U; 07115 07116 // op0: rs1 07117 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07118 op0 &= (1<<5) - 1; 07119 op0 <<= 14; 07120 Value |= op0; 07121 // op1: simm13 07122 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07123 op1 &= (1<<13) - 1; 07124 Value |= op1; 07125 // op2: rd 07126 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07127 op2 &= (1<<5) - 1; 07128 op2 <<= 25; 07129 Value |= op2; 07130 break; 07131 } 07132 case V9::UDIVXr: { 07133 DEBUG(std::cerr << "Emitting UDIVXr\n"); 07134 Value = 2154299392U; 07135 07136 // op0: rs1 07137 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07138 op0 &= (1<<5) - 1; 07139 op0 <<= 14; 07140 Value |= op0; 07141 // op1: rs2 07142 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07143 op1 &= (1<<5) - 1; 07144 Value |= op1; 07145 // op2: rd 07146 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07147 op2 &= (1<<5) - 1; 07148 op2 <<= 25; 07149 Value |= op2; 07150 break; 07151 } 07152 case V9::WRCCRi: { 07153 DEBUG(std::cerr << "Emitting WRCCRi\n"); 07154 Value = 2239766528U; 07155 07156 // op0: rs1 07157 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07158 op0 &= (1<<5) - 1; 07159 op0 <<= 14; 07160 Value |= op0; 07161 // op1: simm13 07162 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07163 op1 &= (1<<13) - 1; 07164 Value |= op1; 07165 break; 07166 } 07167 case V9::WRCCRr: { 07168 DEBUG(std::cerr << "Emitting WRCCRr\n"); 07169 Value = 2239758336U; 07170 07171 // op0: rs1 07172 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07173 op0 &= (1<<5) - 1; 07174 op0 <<= 14; 07175 Value |= op0; 07176 // op1: rs2 07177 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07178 op1 &= (1<<5) - 1; 07179 Value |= op1; 07180 break; 07181 } 07182 case V9::XNORcci: { 07183 DEBUG(std::cerr << "Emitting XNORcci\n"); 07184 Value = 2159550464U; 07185 07186 // op0: rs1 07187 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07188 op0 &= (1<<5) - 1; 07189 op0 <<= 14; 07190 Value |= op0; 07191 // op1: simm13 07192 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07193 op1 &= (1<<13) - 1; 07194 Value |= op1; 07195 // op2: rd 07196 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07197 op2 &= (1<<5) - 1; 07198 op2 <<= 25; 07199 Value |= op2; 07200 break; 07201 } 07202 case V9::XNORccr: { 07203 DEBUG(std::cerr << "Emitting XNORccr\n"); 07204 Value = 2159542272U; 07205 07206 // op0: rs1 07207 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07208 op0 &= (1<<5) - 1; 07209 op0 <<= 14; 07210 Value |= op0; 07211 // op1: rs2 07212 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07213 op1 &= (1<<5) - 1; 07214 Value |= op1; 07215 // op2: rd 07216 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07217 op2 &= (1<<5) - 1; 07218 op2 <<= 25; 07219 Value |= op2; 07220 break; 07221 } 07222 case V9::XNORi: { 07223 DEBUG(std::cerr << "Emitting XNORi\n"); 07224 Value = 2151161856U; 07225 07226 // op0: rs1 07227 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07228 op0 &= (1<<5) - 1; 07229 op0 <<= 14; 07230 Value |= op0; 07231 // op1: simm13 07232 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07233 op1 &= (1<<13) - 1; 07234 Value |= op1; 07235 // op2: rd 07236 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07237 op2 &= (1<<5) - 1; 07238 op2 <<= 25; 07239 Value |= op2; 07240 break; 07241 } 07242 case V9::XNORr: { 07243 DEBUG(std::cerr << "Emitting XNORr\n"); 07244 Value = 2151153664U; 07245 07246 // op0: rs1 07247 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07248 op0 &= (1<<5) - 1; 07249 op0 <<= 14; 07250 Value |= op0; 07251 // op1: rs2 07252 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07253 op1 &= (1<<5) - 1; 07254 Value |= op1; 07255 // op2: rd 07256 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07257 op2 &= (1<<5) - 1; 07258 op2 <<= 25; 07259 Value |= op2; 07260 break; 07261 } 07262 case V9::XORcci: { 07263 DEBUG(std::cerr << "Emitting XORcci\n"); 07264 Value = 2157453312U; 07265 07266 // op0: rs1 07267 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07268 op0 &= (1<<5) - 1; 07269 op0 <<= 14; 07270 Value |= op0; 07271 // op1: simm13 07272 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07273 op1 &= (1<<13) - 1; 07274 Value |= op1; 07275 // op2: rd 07276 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07277 op2 &= (1<<5) - 1; 07278 op2 <<= 25; 07279 Value |= op2; 07280 break; 07281 } 07282 case V9::XORccr: { 07283 DEBUG(std::cerr << "Emitting XORccr\n"); 07284 Value = 2157445120U; 07285 07286 // op0: rs1 07287 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07288 op0 &= (1<<5) - 1; 07289 op0 <<= 14; 07290 Value |= op0; 07291 // op1: rs2 07292 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07293 op1 &= (1<<5) - 1; 07294 Value |= op1; 07295 // op2: rd 07296 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07297 op2 &= (1<<5) - 1; 07298 op2 <<= 25; 07299 Value |= op2; 07300 break; 07301 } 07302 case V9::XORi: { 07303 DEBUG(std::cerr << "Emitting XORi\n"); 07304 Value = 2149064704U; 07305 07306 // op0: rs1 07307 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07308 op0 &= (1<<5) - 1; 07309 op0 <<= 14; 07310 Value |= op0; 07311 // op1: simm13 07312 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07313 op1 &= (1<<13) - 1; 07314 Value |= op1; 07315 // op2: rd 07316 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07317 op2 &= (1<<5) - 1; 07318 op2 <<= 25; 07319 Value |= op2; 07320 break; 07321 } 07322 case V9::XORr: { 07323 DEBUG(std::cerr << "Emitting XORr\n"); 07324 Value = 2149056512U; 07325 07326 // op0: rs1 07327 int64_t op0 = getMachineOpValue(MI, MI.getOperand(0)); 07328 op0 &= (1<<5) - 1; 07329 op0 <<= 14; 07330 Value |= op0; 07331 // op1: rs2 07332 int64_t op1 = getMachineOpValue(MI, MI.getOperand(1)); 07333 op1 &= (1<<5) - 1; 07334 Value |= op1; 07335 // op2: rd 07336 int64_t op2 = getMachineOpValue(MI, MI.getOperand(2)); 07337 op2 &= (1<<5) - 1; 07338 op2 <<= 25; 07339 Value |= op2; 07340 break; 07341 } 07342 default: 07343 std::cerr << "Not supported instr: " << MI << "\n"; 07344 abort(); 07345 } 07346 return Value; 07347 } 07348 07349 } // End llvm namespace