LLVM API Documentation
00001 //===-- MachineInstr.cpp --------------------------------------------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // Methods common to all machine instructions. 00011 // 00012 // FIXME: Now that MachineInstrs have parent pointers, they should always 00013 // print themselves using their MachineFunction's TargetMachine. 00014 // 00015 //===----------------------------------------------------------------------===// 00016 00017 #include "llvm/CodeGen/MachineInstr.h" 00018 #include "llvm/CodeGen/MachineFunction.h" 00019 #include "llvm/Value.h" 00020 #include "llvm/Target/TargetMachine.h" 00021 #include "llvm/Target/TargetInstrInfo.h" 00022 #include "llvm/Target/MRegisterInfo.h" 00023 #include "llvm/Support/LeakDetector.h" 00024 #include <iostream> 00025 00026 using namespace llvm; 00027 00028 // Global variable holding an array of descriptors for machine instructions. 00029 // The actual object needs to be created separately for each target machine. 00030 // This variable is initialized and reset by class TargetInstrInfo. 00031 // 00032 // FIXME: This should be a property of the target so that more than one target 00033 // at a time can be active... 00034 // 00035 namespace llvm { 00036 extern const TargetInstrDescriptor *TargetInstrDescriptors; 00037 } 00038 00039 // Constructor for instructions with variable #operands 00040 MachineInstr::MachineInstr(short opcode, unsigned numOperands) 00041 : Opcode(opcode), 00042 numImplicitRefs(0), 00043 operands(numOperands, MachineOperand()), 00044 parent(0) { 00045 // Make sure that we get added to a machine basicblock 00046 LeakDetector::addGarbageObject(this); 00047 } 00048 00049 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 00050 /// not a resize for them. It is expected that if you use this that you call 00051 /// add* methods below to fill up the operands, instead of the Set methods. 00052 /// Eventually, the "resizing" ctors will be phased out. 00053 /// 00054 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) 00055 : Opcode(opcode), numImplicitRefs(0), parent(0) { 00056 operands.reserve(numOperands); 00057 // Make sure that we get added to a machine basicblock 00058 LeakDetector::addGarbageObject(this); 00059 } 00060 00061 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 00062 /// MachineInstr is created and added to the end of the specified basic block. 00063 /// 00064 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, 00065 unsigned numOperands) 00066 : Opcode(opcode), numImplicitRefs(0), parent(0) { 00067 assert(MBB && "Cannot use inserting ctor with null basic block!"); 00068 operands.reserve(numOperands); 00069 // Make sure that we get added to a machine basicblock 00070 LeakDetector::addGarbageObject(this); 00071 MBB->push_back(this); // Add instruction to end of basic block! 00072 } 00073 00074 /// MachineInstr ctor - Copies MachineInstr arg exactly 00075 /// 00076 MachineInstr::MachineInstr(const MachineInstr &MI) { 00077 Opcode = MI.getOpcode(); 00078 numImplicitRefs = MI.getNumImplicitRefs(); 00079 operands.reserve(MI.getNumOperands()); 00080 00081 // Add operands 00082 for (unsigned i = 0; i < MI.getNumOperands(); ++i) 00083 operands.push_back(MachineOperand(MI.getOperand(i))); 00084 00085 // Set parent, next, and prev to null 00086 parent = 0; 00087 prev = 0; 00088 next = 0; 00089 } 00090 00091 00092 MachineInstr::~MachineInstr() { 00093 LeakDetector::removeGarbageObject(this); 00094 } 00095 00096 /// clone - Create a copy of 'this' instruction that is identical in all ways 00097 /// except the following: the new instruction has no parent and it has no name 00098 /// 00099 MachineInstr* MachineInstr::clone() const { 00100 return new MachineInstr(*this); 00101 } 00102 00103 /// OperandComplete - Return true if it's illegal to add a new operand 00104 /// 00105 bool MachineInstr::OperandsComplete() const { 00106 int NumOperands = TargetInstrDescriptors[Opcode].numOperands; 00107 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 00108 return true; // Broken: we have all the operands of this instruction! 00109 return false; 00110 } 00111 00112 /// replace - Support for replacing opcode and operands of a MachineInstr in 00113 /// place. This only resets the size of the operand vector and initializes it. 00114 /// The new operands must be set explicitly later. 00115 /// 00116 void MachineInstr::replace(short opcode, unsigned numOperands) { 00117 assert(getNumImplicitRefs() == 0 && 00118 "This is probably broken because implicit refs are going to be lost."); 00119 Opcode = opcode; 00120 operands.clear(); 00121 operands.resize(numOperands, MachineOperand()); 00122 } 00123 00124 void MachineInstr::SetMachineOperandVal(unsigned i, 00125 MachineOperand::MachineOperandType opTy, 00126 Value* V) { 00127 assert(i < operands.size()); // may be explicit or implicit op 00128 operands[i].opType = opTy; 00129 operands[i].contents.value = V; 00130 operands[i].extra.regNum = -1; 00131 } 00132 00133 void 00134 MachineInstr::SetMachineOperandConst(unsigned i, 00135 MachineOperand::MachineOperandType opTy, 00136 int intValue) { 00137 assert(i < getNumOperands()); // must be explicit op 00138 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i && 00139 "immed. constant cannot be defined"); 00140 00141 operands[i].opType = opTy; 00142 operands[i].contents.value = NULL; 00143 operands[i].contents.immedVal = intValue; 00144 operands[i].extra.regNum = -1; 00145 operands[i].flags = 0; 00146 } 00147 00148 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { 00149 assert(i < getNumOperands()); // must be explicit op 00150 00151 operands[i].opType = MachineOperand::MO_MachineRegister; 00152 operands[i].contents.value = NULL; 00153 operands[i].extra.regNum = regNum; 00154 } 00155 00156 // Used only by the SPARC back-end. 00157 void MachineInstr::SetRegForOperand(unsigned i, int regNum) { 00158 assert(i < getNumOperands()); // must be explicit op 00159 operands[i].setRegForValue(regNum); 00160 } 00161 00162 // Used only by the SPARC back-end. 00163 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) { 00164 getImplicitOp(i).setRegForValue(regNum); 00165 } 00166 00167 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal 00168 /// in all operands and all implicit refs. If defsOnly == true, substitute defs 00169 /// only. 00170 /// 00171 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865, 00172 /// or make it a static function in that file. 00173 /// 00174 unsigned 00175 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 00176 bool defsOnly, bool notDefsAndUses, 00177 bool& someArgsWereIgnored) 00178 { 00179 assert((!defsOnly || !notDefsAndUses) && 00180 "notDefsAndUses is irrelevant if defsOnly == true."); 00181 00182 unsigned numSubst = 0; 00183 00184 // Substitute operands 00185 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 00186 if (*O == oldVal) 00187 if (!defsOnly || 00188 notDefsAndUses && (O.isDef() && !O.isUse()) || 00189 !notDefsAndUses && O.isDef()) 00190 { 00191 O.getMachineOperand().contents.value = newVal; 00192 ++numSubst; 00193 } else 00194 someArgsWereIgnored = true; 00195 00196 // Substitute implicit refs 00197 for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i) 00198 if (getImplicitRef(i) == oldVal) { 00199 MachineOperand Op = getImplicitOp(i); 00200 if (!defsOnly || 00201 notDefsAndUses && (Op.isDef() && !Op.isUse()) || 00202 !notDefsAndUses && Op.isDef()) 00203 { 00204 Op.contents.value = newVal; 00205 ++numSubst; 00206 } else 00207 someArgsWereIgnored = true; 00208 } 00209 return numSubst; 00210 } 00211 00212 void MachineInstr::dump() const { 00213 std::cerr << " " << *this; 00214 } 00215 00216 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { 00217 os << "(val "; 00218 os << (void*) val; // print address always 00219 if (val && val->hasName()) 00220 os << " " << val->getName(); // print name also, if available 00221 os << ")"; 00222 return os; 00223 } 00224 00225 static inline void OutputReg(std::ostream &os, unsigned RegNo, 00226 const MRegisterInfo *MRI = 0) { 00227 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { 00228 if (MRI) 00229 os << "%" << MRI->get(RegNo).Name; 00230 else 00231 os << "%mreg(" << RegNo << ")"; 00232 } else 00233 os << "%reg" << RegNo; 00234 } 00235 00236 static void print(const MachineOperand &MO, std::ostream &OS, 00237 const TargetMachine *TM) { 00238 const MRegisterInfo *MRI = 0; 00239 00240 if (TM) MRI = TM->getRegisterInfo(); 00241 00242 bool CloseParen = true; 00243 if (MO.isHiBits32()) 00244 OS << "%lm("; 00245 else if (MO.isLoBits32()) 00246 OS << "%lo("; 00247 else if (MO.isHiBits64()) 00248 OS << "%hh("; 00249 else if (MO.isLoBits64()) 00250 OS << "%hm("; 00251 else 00252 CloseParen = false; 00253 00254 switch (MO.getType()) { 00255 case MachineOperand::MO_VirtualRegister: 00256 if (MO.getVRegValue()) { 00257 OS << "%reg"; 00258 OutputValue(OS, MO.getVRegValue()); 00259 if (MO.hasAllocatedReg()) 00260 OS << "=="; 00261 } 00262 if (MO.hasAllocatedReg()) 00263 OutputReg(OS, MO.getReg(), MRI); 00264 break; 00265 case MachineOperand::MO_CCRegister: 00266 OS << "%ccreg"; 00267 OutputValue(OS, MO.getVRegValue()); 00268 if (MO.hasAllocatedReg()) { 00269 OS << "=="; 00270 OutputReg(OS, MO.getReg(), MRI); 00271 } 00272 break; 00273 case MachineOperand::MO_MachineRegister: 00274 OutputReg(OS, MO.getMachineRegNum(), MRI); 00275 break; 00276 case MachineOperand::MO_SignExtendedImmed: 00277 OS << (long)MO.getImmedValue(); 00278 break; 00279 case MachineOperand::MO_UnextendedImmed: 00280 OS << (long)MO.getImmedValue(); 00281 break; 00282 case MachineOperand::MO_PCRelativeDisp: { 00283 const Value* opVal = MO.getVRegValue(); 00284 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 00285 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 00286 if (opVal->hasName()) 00287 OS << opVal->getName(); 00288 else 00289 OS << (const void*) opVal; 00290 OS << ")"; 00291 break; 00292 } 00293 case MachineOperand::MO_MachineBasicBlock: 00294 OS << "mbb<" 00295 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 00296 << "," << (void*)MO.getMachineBasicBlock() << ">"; 00297 break; 00298 case MachineOperand::MO_FrameIndex: 00299 OS << "<fi#" << MO.getFrameIndex() << ">"; 00300 break; 00301 case MachineOperand::MO_ConstantPoolIndex: 00302 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 00303 break; 00304 case MachineOperand::MO_GlobalAddress: 00305 OS << "<ga:" << ((Value*)MO.getGlobal())->getName(); 00306 if (MO.getOffset()) OS << "+" << MO.getOffset(); 00307 OS << ">"; 00308 break; 00309 case MachineOperand::MO_ExternalSymbol: 00310 OS << "<es:" << MO.getSymbolName(); 00311 if (MO.getOffset()) OS << "+" << MO.getOffset(); 00312 OS << ">"; 00313 break; 00314 default: 00315 assert(0 && "Unrecognized operand type"); 00316 } 00317 00318 if (CloseParen) 00319 OS << ")"; 00320 } 00321 00322 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 00323 unsigned StartOp = 0; 00324 00325 // Specialize printing if op#0 is definition 00326 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { 00327 ::print(getOperand(0), OS, TM); 00328 OS << " = "; 00329 ++StartOp; // Don't print this operand again! 00330 } 00331 00332 // Must check if Target machine is not null because machine BB could not 00333 // be attached to a Machine function yet 00334 if (TM) 00335 OS << TM->getInstrInfo()->getName(getOpcode()); 00336 00337 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 00338 const MachineOperand& mop = getOperand(i); 00339 if (i != StartOp) 00340 OS << ","; 00341 OS << " "; 00342 ::print(mop, OS, TM); 00343 00344 if (mop.isDef()) 00345 if (mop.isUse()) 00346 OS << "<def&use>"; 00347 else 00348 OS << "<def>"; 00349 } 00350 00351 // code for printing implicit references 00352 if (getNumImplicitRefs()) { 00353 OS << "\tImplicitRefs: "; 00354 for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 00355 OS << "\t"; 00356 OutputValue(OS, getImplicitRef(i)); 00357 if (getImplicitOp(i).isDef()) 00358 if (getImplicitOp(i).isUse()) 00359 OS << "<def&use>"; 00360 else 00361 OS << "<def>"; 00362 } 00363 } 00364 00365 OS << "\n"; 00366 } 00367 00368 namespace llvm { 00369 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { 00370 // If the instruction is embedded into a basic block, we can find the target 00371 // info for the instruction. 00372 if (const MachineBasicBlock *MBB = MI.getParent()) { 00373 const MachineFunction *MF = MBB->getParent(); 00374 if (MF) 00375 MI.print(os, &MF->getTarget()); 00376 else 00377 MI.print(os, 0); 00378 return os; 00379 } 00380 00381 // Otherwise, print it out in the "raw" format without symbolic register names 00382 // and such. 00383 os << TargetInstrDescriptors[MI.getOpcode()].Name; 00384 00385 for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) { 00386 os << "\t" << MI.getOperand(i); 00387 if (MI.getOperand(i).isDef()) 00388 if (MI.getOperand(i).isUse()) 00389 os << "<d&u>"; 00390 else 00391 os << "<d>"; 00392 } 00393 00394 // code for printing implicit references 00395 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 00396 if (NumOfImpRefs > 0) { 00397 os << "\tImplicit: "; 00398 for (unsigned z = 0; z < NumOfImpRefs; z++) { 00399 OutputValue(os, MI.getImplicitRef(z)); 00400 if (MI.getImplicitOp(z).isDef()) 00401 if (MI.getImplicitOp(z).isUse()) 00402 os << "<d&u>"; 00403 else 00404 os << "<d>"; 00405 os << "\t"; 00406 } 00407 } 00408 00409 return os << "\n"; 00410 } 00411 00412 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { 00413 if (MO.isHiBits32()) 00414 OS << "%lm("; 00415 else if (MO.isLoBits32()) 00416 OS << "%lo("; 00417 else if (MO.isHiBits64()) 00418 OS << "%hh("; 00419 else if (MO.isLoBits64()) 00420 OS << "%hm("; 00421 00422 switch (MO.getType()) { 00423 case MachineOperand::MO_VirtualRegister: 00424 if (MO.hasAllocatedReg()) 00425 OutputReg(OS, MO.getReg()); 00426 00427 if (MO.getVRegValue()) { 00428 if (MO.hasAllocatedReg()) OS << "=="; 00429 OS << "%vreg"; 00430 OutputValue(OS, MO.getVRegValue()); 00431 } 00432 break; 00433 case MachineOperand::MO_CCRegister: 00434 OS << "%ccreg"; 00435 OutputValue(OS, MO.getVRegValue()); 00436 if (MO.hasAllocatedReg()) { 00437 OS << "=="; 00438 OutputReg(OS, MO.getReg()); 00439 } 00440 break; 00441 case MachineOperand::MO_MachineRegister: 00442 OutputReg(OS, MO.getMachineRegNum()); 00443 break; 00444 case MachineOperand::MO_SignExtendedImmed: 00445 OS << (long)MO.getImmedValue(); 00446 break; 00447 case MachineOperand::MO_UnextendedImmed: 00448 OS << (long)MO.getImmedValue(); 00449 break; 00450 case MachineOperand::MO_PCRelativeDisp: { 00451 const Value* opVal = MO.getVRegValue(); 00452 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 00453 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 00454 if (opVal->hasName()) 00455 OS << opVal->getName(); 00456 else 00457 OS << (const void*) opVal; 00458 OS << ")"; 00459 break; 00460 } 00461 case MachineOperand::MO_MachineBasicBlock: 00462 OS << "<mbb:" 00463 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 00464 << "@" << (void*)MO.getMachineBasicBlock() << ">"; 00465 break; 00466 case MachineOperand::MO_FrameIndex: 00467 OS << "<fi#" << MO.getFrameIndex() << ">"; 00468 break; 00469 case MachineOperand::MO_ConstantPoolIndex: 00470 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 00471 break; 00472 case MachineOperand::MO_GlobalAddress: 00473 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 00474 break; 00475 case MachineOperand::MO_ExternalSymbol: 00476 OS << "<es:" << MO.getSymbolName() << ">"; 00477 break; 00478 default: 00479 assert(0 && "Unrecognized operand type"); 00480 break; 00481 } 00482 00483 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) 00484 OS << ")"; 00485 00486 return OS; 00487 } 00488 00489 }