LLVM API Documentation
00001 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file was developed by the LLVM research group and is distributed under 00006 // the University of Illinois Open Source License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the VirtRegMap class. 00011 // 00012 // It also contains implementations of the the Spiller interface, which, given a 00013 // virtual register map and a machine function, eliminates all virtual 00014 // references by replacing them with physical register references - adding spill 00015 // code as necessary. 00016 // 00017 //===----------------------------------------------------------------------===// 00018 00019 #define DEBUG_TYPE "spiller" 00020 #include "VirtRegMap.h" 00021 #include "llvm/Function.h" 00022 #include "llvm/CodeGen/MachineFrameInfo.h" 00023 #include "llvm/CodeGen/MachineFunction.h" 00024 #include "llvm/CodeGen/SSARegMap.h" 00025 #include "llvm/Target/TargetMachine.h" 00026 #include "llvm/Target/TargetInstrInfo.h" 00027 #include "llvm/Support/CommandLine.h" 00028 #include "llvm/Support/Debug.h" 00029 #include "llvm/ADT/Statistic.h" 00030 #include "llvm/ADT/STLExtras.h" 00031 #include <algorithm> 00032 using namespace llvm; 00033 00034 namespace { 00035 Statistic<> NumSpills("spiller", "Number of register spills"); 00036 Statistic<> NumStores("spiller", "Number of stores added"); 00037 Statistic<> NumLoads ("spiller", "Number of loads added"); 00038 Statistic<> NumReused("spiller", "Number of values reused"); 00039 Statistic<> NumDSE ("spiller", "Number of dead stores elided"); 00040 00041 enum SpillerName { simple, local }; 00042 00043 cl::opt<SpillerName> 00044 SpillerOpt("spiller", 00045 cl::desc("Spiller to use: (default: local)"), 00046 cl::Prefix, 00047 cl::values(clEnumVal(simple, " simple spiller"), 00048 clEnumVal(local, " local spiller"), 00049 clEnumValEnd), 00050 cl::init(local)); 00051 } 00052 00053 //===----------------------------------------------------------------------===// 00054 // VirtRegMap implementation 00055 //===----------------------------------------------------------------------===// 00056 00057 void VirtRegMap::grow() { 00058 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg()); 00059 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg()); 00060 } 00061 00062 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 00063 assert(MRegisterInfo::isVirtualRegister(virtReg)); 00064 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 00065 "attempt to assign stack slot to already spilled register"); 00066 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); 00067 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 00068 RC->getAlignment()); 00069 Virt2StackSlotMap[virtReg] = frameIndex; 00070 ++NumSpills; 00071 return frameIndex; 00072 } 00073 00074 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { 00075 assert(MRegisterInfo::isVirtualRegister(virtReg)); 00076 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 00077 "attempt to assign stack slot to already spilled register"); 00078 Virt2StackSlotMap[virtReg] = frameIndex; 00079 } 00080 00081 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 00082 unsigned OpNo, MachineInstr *NewMI) { 00083 // Move previous memory references folded to new instruction. 00084 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 00085 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 00086 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 00087 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 00088 MI2VirtMap.erase(I++); 00089 } 00090 00091 ModRef MRInfo; 00092 if (!OldMI->getOperand(OpNo).isDef()) { 00093 assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?"); 00094 MRInfo = isRef; 00095 } else { 00096 MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod; 00097 } 00098 00099 // add new memory reference 00100 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 00101 } 00102 00103 void VirtRegMap::print(std::ostream &OS) const { 00104 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); 00105 00106 OS << "********** REGISTER MAP **********\n"; 00107 for (unsigned i = MRegisterInfo::FirstVirtualRegister, 00108 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { 00109 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 00110 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; 00111 00112 } 00113 00114 for (unsigned i = MRegisterInfo::FirstVirtualRegister, 00115 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) 00116 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 00117 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 00118 OS << '\n'; 00119 } 00120 00121 void VirtRegMap::dump() const { print(std::cerr); } 00122 00123 00124 //===----------------------------------------------------------------------===// 00125 // Simple Spiller Implementation 00126 //===----------------------------------------------------------------------===// 00127 00128 Spiller::~Spiller() {} 00129 00130 namespace { 00131 struct SimpleSpiller : public Spiller { 00132 bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM); 00133 }; 00134 } 00135 00136 bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF, 00137 const VirtRegMap& VRM) { 00138 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n"); 00139 DEBUG(std::cerr << "********** Function: " 00140 << MF.getFunction()->getName() << '\n'); 00141 const TargetMachine& TM = MF.getTarget(); 00142 const MRegisterInfo& MRI = *TM.getRegisterInfo(); 00143 00144 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 00145 // each vreg once (in the case where a spilled vreg is used by multiple 00146 // operands). This is always smaller than the number of operands to the 00147 // current machine instr, so it should be small. 00148 std::vector<unsigned> LoadedRegs; 00149 00150 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 00151 MBBI != E; ++MBBI) { 00152 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n"); 00153 MachineBasicBlock &MBB = *MBBI; 00154 for (MachineBasicBlock::iterator MII = MBB.begin(), 00155 E = MBB.end(); MII != E; ++MII) { 00156 MachineInstr &MI = *MII; 00157 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 00158 MachineOperand &MO = MI.getOperand(i); 00159 if (MO.isRegister() && MO.getReg() && 00160 MRegisterInfo::isVirtualRegister(MO.getReg())) { 00161 unsigned VirtReg = MO.getReg(); 00162 unsigned PhysReg = VRM.getPhys(VirtReg); 00163 if (VRM.hasStackSlot(VirtReg)) { 00164 int StackSlot = VRM.getStackSlot(VirtReg); 00165 00166 if (MO.isUse() && 00167 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 00168 == LoadedRegs.end()) { 00169 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot); 00170 LoadedRegs.push_back(VirtReg); 00171 ++NumLoads; 00172 DEBUG(std::cerr << '\t' << *prior(MII)); 00173 } 00174 00175 if (MO.isDef()) { 00176 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot); 00177 ++NumStores; 00178 } 00179 } 00180 MI.SetMachineOperandReg(i, PhysReg); 00181 } 00182 } 00183 DEBUG(std::cerr << '\t' << MI); 00184 LoadedRegs.clear(); 00185 } 00186 } 00187 return true; 00188 } 00189 00190 //===----------------------------------------------------------------------===// 00191 // Local Spiller Implementation 00192 //===----------------------------------------------------------------------===// 00193 00194 namespace { 00195 /// LocalSpiller - This spiller does a simple pass over the machine basic 00196 /// block to attempt to keep spills in registers as much as possible for 00197 /// blocks that have low register pressure (the vreg may be spilled due to 00198 /// register pressure in other blocks). 00199 class LocalSpiller : public Spiller { 00200 const MRegisterInfo *MRI; 00201 const TargetInstrInfo *TII; 00202 public: 00203 bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) { 00204 MRI = MF.getTarget().getRegisterInfo(); 00205 TII = MF.getTarget().getInstrInfo(); 00206 DEBUG(std::cerr << "\n**** Local spiller rewriting function '" 00207 << MF.getFunction()->getName() << "':\n"); 00208 00209 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 00210 MBB != E; ++MBB) 00211 RewriteMBB(*MBB, VRM); 00212 return true; 00213 } 00214 private: 00215 void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM); 00216 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots, 00217 std::map<unsigned, int> &PhysRegs); 00218 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots, 00219 std::map<unsigned, int> &PhysRegs); 00220 }; 00221 } 00222 00223 void LocalSpiller::ClobberPhysRegOnly(unsigned PhysReg, 00224 std::map<int, unsigned> &SpillSlots, 00225 std::map<unsigned, int> &PhysRegs) { 00226 std::map<unsigned, int>::iterator I = PhysRegs.find(PhysReg); 00227 if (I != PhysRegs.end()) { 00228 int Slot = I->second; 00229 PhysRegs.erase(I); 00230 assert(SpillSlots[Slot] == PhysReg && "Bidirectional map mismatch!"); 00231 SpillSlots.erase(Slot); 00232 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg) 00233 << " clobbered, invalidating SS#" << Slot << "\n"); 00234 00235 } 00236 } 00237 00238 void LocalSpiller::ClobberPhysReg(unsigned PhysReg, 00239 std::map<int, unsigned> &SpillSlots, 00240 std::map<unsigned, int> &PhysRegs) { 00241 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) 00242 ClobberPhysRegOnly(*AS, SpillSlots, PhysRegs); 00243 ClobberPhysRegOnly(PhysReg, SpillSlots, PhysRegs); 00244 } 00245 00246 00247 // ReusedOp - For each reused operand, we keep track of a bit of information, in 00248 // case we need to rollback upon processing a new operand. See comments below. 00249 namespace { 00250 struct ReusedOp { 00251 // The MachineInstr operand that reused an available value. 00252 unsigned Operand; 00253 00254 // StackSlot - The spill slot of the value being reused. 00255 unsigned StackSlot; 00256 00257 // PhysRegReused - The physical register the value was available in. 00258 unsigned PhysRegReused; 00259 00260 // AssignedPhysReg - The physreg that was assigned for use by the reload. 00261 unsigned AssignedPhysReg; 00262 00263 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr) 00264 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {} 00265 }; 00266 } 00267 00268 00269 /// rewriteMBB - Keep track of which spills are available even after the 00270 /// register allocator is done with them. If possible, avoid reloading vregs. 00271 void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) { 00272 00273 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual 00274 // register values that are still available, due to being loaded to stored to, 00275 // but not invalidated yet. 00276 std::map<int, unsigned> SpillSlotsAvailable; 00277 00278 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating 00279 // which physregs are in use holding a stack slot value. 00280 std::map<unsigned, int> PhysRegsAvailable; 00281 00282 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n"); 00283 00284 std::vector<ReusedOp> ReusedOperands; 00285 00286 // DefAndUseVReg - When we see a def&use operand that is spilled, keep track 00287 // of it. ".first" is the machine operand index (should always be 0 for now), 00288 // and ".second" is the virtual register that is spilled. 00289 std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg; 00290 00291 // MaybeDeadStores - When we need to write a value back into a stack slot, 00292 // keep track of the inserted store. If the stack slot value is never read 00293 // (because the value was used from some available register, for example), and 00294 // subsequently stored to, the original store is dead. This map keeps track 00295 // of inserted stores that are not used. If we see a subsequent store to the 00296 // same stack slot, the original store is deleted. 00297 std::map<int, MachineInstr*> MaybeDeadStores; 00298 00299 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 00300 MII != E; ) { 00301 MachineInstr &MI = *MII; 00302 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 00303 00304 ReusedOperands.clear(); 00305 DefAndUseVReg.clear(); 00306 00307 // Process all of the spilled uses and all non spilled reg references. 00308 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 00309 MachineOperand &MO = MI.getOperand(i); 00310 if (MO.isRegister() && MO.getReg() && 00311 MRegisterInfo::isVirtualRegister(MO.getReg())) { 00312 unsigned VirtReg = MO.getReg(); 00313 00314 if (!VRM.hasStackSlot(VirtReg)) { 00315 // This virtual register was assigned a physreg! 00316 MI.SetMachineOperandReg(i, VRM.getPhys(VirtReg)); 00317 } else { 00318 // Is this virtual register a spilled value? 00319 if (MO.isUse()) { 00320 int StackSlot = VRM.getStackSlot(VirtReg); 00321 unsigned PhysReg; 00322 00323 // Check to see if this stack slot is available. 00324 std::map<int, unsigned>::iterator SSI = 00325 SpillSlotsAvailable.find(StackSlot); 00326 if (SSI != SpillSlotsAvailable.end()) { 00327 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg " 00328 << MRI->getName(SSI->second) << " for vreg" 00329 << VirtReg <<" instead of reloading into physreg " 00330 << MRI->getName(VRM.getPhys(VirtReg)) << "\n"); 00331 // If this stack slot value is already available, reuse it! 00332 PhysReg = SSI->second; 00333 MI.SetMachineOperandReg(i, PhysReg); 00334 00335 // The only technical detail we have is that we don't know that 00336 // PhysReg won't be clobbered by a reloaded stack slot that occurs 00337 // later in the instruction. In particular, consider 'op V1, V2'. 00338 // If V1 is available in physreg R0, we would choose to reuse it 00339 // here, instead of reloading it into the register the allocator 00340 // indicated (say R1). However, V2 might have to be reloaded 00341 // later, and it might indicate that it needs to live in R0. When 00342 // this occurs, we need to have information available that 00343 // indicates it is safe to use R1 for the reload instead of R0. 00344 // 00345 // To further complicate matters, we might conflict with an alias, 00346 // or R0 and R1 might not be compatible with each other. In this 00347 // case, we actually insert a reload for V1 in R1, ensuring that 00348 // we can get at R0 or its alias. 00349 ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg, 00350 VRM.getPhys(VirtReg))); 00351 ++NumReused; 00352 } else { 00353 // Otherwise, reload it and remember that we have it. 00354 PhysReg = VRM.getPhys(VirtReg); 00355 00356 RecheckRegister: 00357 // Note that, if we reused a register for a previous operand, the 00358 // register we want to reload into might not actually be 00359 // available. If this occurs, use the register indicated by the 00360 // reuser. 00361 if (!ReusedOperands.empty()) // This is most often empty. 00362 for (unsigned ro = 0, e = ReusedOperands.size(); ro != e; ++ro) 00363 if (ReusedOperands[ro].PhysRegReused == PhysReg) { 00364 // Yup, use the reload register that we didn't use before. 00365 PhysReg = ReusedOperands[ro].AssignedPhysReg; 00366 goto RecheckRegister; 00367 } else { 00368 ReusedOp &Op = ReusedOperands[ro]; 00369 unsigned PRRU = Op.PhysRegReused; 00370 for (const unsigned *AS = MRI->getAliasSet(PRRU); *AS; ++AS) 00371 if (*AS == PhysReg) { 00372 // Okay, we found out that an alias of a reused register 00373 // was used. This isn't good because it means we have 00374 // to undo a previous reuse. 00375 MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg, 00376 Op.StackSlot); 00377 ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable, 00378 PhysRegsAvailable); 00379 00380 // Any stores to this stack slot are not dead anymore. 00381 MaybeDeadStores.erase(Op.StackSlot); 00382 00383 MI.SetMachineOperandReg(Op.Operand, Op.AssignedPhysReg); 00384 PhysRegsAvailable[Op.AssignedPhysReg] = Op.StackSlot; 00385 SpillSlotsAvailable[Op.StackSlot] = Op.AssignedPhysReg; 00386 PhysRegsAvailable.erase(Op.PhysRegReused); 00387 DEBUG(std::cerr << "Remembering SS#" << Op.StackSlot 00388 << " in physreg " 00389 << MRI->getName(Op.AssignedPhysReg) << "\n"); 00390 ++NumLoads; 00391 DEBUG(std::cerr << '\t' << *prior(MII)); 00392 00393 DEBUG(std::cerr << "Reuse undone!\n"); 00394 ReusedOperands.erase(ReusedOperands.begin()+ro); 00395 --NumReused; 00396 goto ContinueReload; 00397 } 00398 } 00399 ContinueReload: 00400 00401 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot); 00402 // This invalidates PhysReg. 00403 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable); 00404 00405 // Any stores to this stack slot are not dead anymore. 00406 MaybeDeadStores.erase(StackSlot); 00407 00408 MI.SetMachineOperandReg(i, PhysReg); 00409 PhysRegsAvailable[PhysReg] = StackSlot; 00410 SpillSlotsAvailable[StackSlot] = PhysReg; 00411 DEBUG(std::cerr << "Remembering SS#" << StackSlot <<" in physreg " 00412 << MRI->getName(PhysReg) << "\n"); 00413 ++NumLoads; 00414 DEBUG(std::cerr << '\t' << *prior(MII)); 00415 } 00416 00417 // If this is both a def and a use, we need to emit a store to the 00418 // stack slot after the instruction. Keep track of D&U operands 00419 // because we already changed it to a physreg here. 00420 if (MO.isDef()) { 00421 // Remember that this was a def-and-use operand, and that the 00422 // stack slot is live after this instruction executes. 00423 DefAndUseVReg.push_back(std::make_pair(i, VirtReg)); 00424 } 00425 } 00426 } 00427 } 00428 } 00429 00430 // Loop over all of the implicit defs, clearing them from our available 00431 // sets. 00432 const TargetInstrDescriptor &InstrDesc = TII->get(MI.getOpcode()); 00433 for (const unsigned* ImpDef = InstrDesc.ImplicitDefs; *ImpDef; ++ImpDef) 00434 ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable); 00435 00436 DEBUG(std::cerr << '\t' << MI); 00437 00438 // If we have folded references to memory operands, make sure we clear all 00439 // physical registers that may contain the value of the spilled virtual 00440 // register 00441 VirtRegMap::MI2VirtMapTy::const_iterator I, E; 00442 for (tie(I, E) = VRM.getFoldedVirts(&MI); I != E; ++I) { 00443 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: " 00444 << I->second.second); 00445 unsigned VirtReg = I->second.first; 00446 VirtRegMap::ModRef MR = I->second.second; 00447 if (VRM.hasStackSlot(VirtReg)) { 00448 int SS = VRM.getStackSlot(VirtReg); 00449 DEBUG(std::cerr << " - StackSlot: " << SS << "\n"); 00450 00451 // If this reference is not a use, any previous store is now dead. 00452 // Otherwise, the store to this stack slot is not dead anymore. 00453 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS); 00454 if (MDSI != MaybeDeadStores.end()) { 00455 if (MR & VirtRegMap::isRef) // Previous store is not dead. 00456 MaybeDeadStores.erase(MDSI); 00457 else { 00458 // If we get here, the store is dead, nuke it now. 00459 assert(MR == VirtRegMap::isMod && "Can't be modref!"); 00460 MBB.erase(MDSI->second); 00461 MaybeDeadStores.erase(MDSI); 00462 ++NumDSE; 00463 } 00464 } 00465 00466 // If the spill slot value is available, and this is a new definition of 00467 // the value, the value is not available anymore. 00468 if (MR & VirtRegMap::isMod) { 00469 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS); 00470 if (It != SpillSlotsAvailable.end()) { 00471 PhysRegsAvailable.erase(It->second); 00472 SpillSlotsAvailable.erase(It); 00473 } 00474 } 00475 } else { 00476 DEBUG(std::cerr << ": No stack slot!\n"); 00477 } 00478 } 00479 00480 // Process all of the spilled defs. 00481 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 00482 MachineOperand &MO = MI.getOperand(i); 00483 if (MO.isRegister() && MO.getReg() && MO.isDef()) { 00484 unsigned VirtReg = MO.getReg(); 00485 00486 bool TakenCareOf = false; 00487 if (!MRegisterInfo::isVirtualRegister(VirtReg)) { 00488 // Check to see if this is a def-and-use vreg operand that we do need 00489 // to insert a store for. 00490 bool OpTakenCareOf = false; 00491 if (MO.isUse() && !DefAndUseVReg.empty()) { 00492 for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau) 00493 if (DefAndUseVReg[dau].first == i) { 00494 VirtReg = DefAndUseVReg[dau].second; 00495 OpTakenCareOf = true; 00496 break; 00497 } 00498 } 00499 00500 if (!OpTakenCareOf) { 00501 ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable); 00502 TakenCareOf = true; 00503 } 00504 } 00505 00506 if (!TakenCareOf) { 00507 // The only vregs left are stack slot definitions. 00508 int StackSlot = VRM.getStackSlot(VirtReg); 00509 unsigned PhysReg; 00510 00511 // If this is a def&use operand, and we used a different physreg for 00512 // it than the one assigned, make sure to execute the store from the 00513 // correct physical register. 00514 if (MO.getReg() == VirtReg) 00515 PhysReg = VRM.getPhys(VirtReg); 00516 else 00517 PhysReg = MO.getReg(); 00518 00519 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot); 00520 DEBUG(std::cerr << "Store:\t" << *next(MII)); 00521 MI.SetMachineOperandReg(i, PhysReg); 00522 00523 // If there is a dead store to this stack slot, nuke it now. 00524 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 00525 if (LastStore) { 00526 DEBUG(std::cerr << " Killed store:\t" << *LastStore); 00527 ++NumDSE; 00528 MBB.erase(LastStore); 00529 } 00530 LastStore = next(MII); 00531 00532 // If the stack slot value was previously available in some other 00533 // register, change it now. Otherwise, make the register available, 00534 // in PhysReg. 00535 std::map<int, unsigned>::iterator SSA = 00536 SpillSlotsAvailable.find(StackSlot); 00537 if (SSA != SpillSlotsAvailable.end()) { 00538 // Remove the record for physreg. 00539 PhysRegsAvailable.erase(SSA->second); 00540 SpillSlotsAvailable.erase(SSA); 00541 } 00542 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable); 00543 00544 PhysRegsAvailable[PhysReg] = StackSlot; 00545 SpillSlotsAvailable[StackSlot] = PhysReg; 00546 DEBUG(std::cerr << "Updating SS#" << StackSlot <<" in physreg " 00547 << MRI->getName(PhysReg) << " for virtreg #" 00548 << VirtReg << "\n"); 00549 00550 ++NumStores; 00551 VirtReg = PhysReg; 00552 } 00553 } 00554 } 00555 MII = NextMII; 00556 } 00557 } 00558 00559 00560 00561 llvm::Spiller* llvm::createSpiller() { 00562 switch (SpillerOpt) { 00563 default: assert(0 && "Unreachable!"); 00564 case local: 00565 return new LocalSpiller(); 00566 case simple: 00567 return new SimpleSpiller(); 00568 } 00569 }