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gnetlist is the gEDA netlister. It takes as input schematic files
and produces a netlist. A netlist is a textual representation of a
schematic. This textual representation has all of the connections
between devices completely resolved. This means that all the
connections associated with a net are grouped together. The netlister
also handles hierarchies of schematics.
gnetlist has a very flexible architecture. The main program,
which is written in C, reads in a schematic (using routines from
libgeda) and creates an internal representation of the schematic data.
This internal representation is then manipulated by a backend which is
responsible for writing the various netlist formats. The backend for
each netlist format is written in scheme (specifically Guile). This
architecture not only allows for an infinite number of netlist
formats, but also allows the netlister to generate other reports (like
bill of material lists).
As of 20001006 gnetlist has scheme backends to support the following
netlist formats:
- PCB & PCBboard - UNIX PCB netlist format.
- Allegro netlist format
- BAE netlist format
- BOM & BOM2 - Bill of Material generators
- DRC - Start of a design rule checker
- gEDA - the native format of gEDA, mainly used for testing
- Gossip netlist format
- PADS netlist format
- ProtelII netlist format
- Spice compatible netlist format
- Tango netlist format
- Verilog code
- VHDL code
- VIPEC netlist format
- VAMS - VHDL-AMS netlist format
This list is constantly growing. Several lacking features (as of
20001006) are: no support for buses, error detection and reporting is
fairly limited, and ... (many more).
Next: Installation
Up: gEDA gnetlist Users Guide
Previous: Introduction
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Ales Hvezda
2004-01-11