There are other generators built into Electric. These commands (in menu Tool / Generation) may be used:
1
010101
011001
100101
101010
4
00000000
10000000
01000000
11000000
f = (a and b and (not c)) or ((not b) and (not a)) |
g = (a and c) or ((not a) and (not c)) |
4 3
1 1 0
0 0 X
1 X 1
0 X 0
Unlike other fill generators, Electric's fill generator creates cells containing power and ground grids of specified layers, usually starting at Metal-2. These cells can also be arrayed into tile cells to cover larger areas. When Metal-1 is filled, the generator will cover the area with cap transistors whose functionality is to prevent voltage drops in the power grid.
The Fill dialog has two tabs: "Floorplan" and "Tiling". The Floorplan section specifies what is inside of a single fill cell. The Tiling section specifies how those cells are arrayed.
The Floorplan section offers two fill techniques: Template Fill and Fill Cell (not yet available). Template Fill generates fill cells of a given width and height. The default values reflect the minimum spacing rules given by the technology. The "Reserved Space" section lets you specify which layers of metal will be in the fill cells. These metal layers alternate running horizontally and vertically (the "Even layer orientation" controls which layer runs horizontally first).
The fill cell will have four metal wires running in each direction: the outer two are Ground and the inner two are Power. The spacing between the inner two is given in the "Vdd Space" section next to the selected metal layer. The spacing between the ground wires and the edge is half of the "Gnd Space" value. The spacing between the power and ground wires is the minimal design-rule spacing for that layer of metal. The width of the wires is then adjusted to fill the remaining space in the cell. | ![]() |
![]() | The Tiling section lets you request arrays of fill cells to be generated. Check the desired sizes and they will be generated. Each generated array cell will contain the specified-size array, and it will be internally wired. |
The gate layout generator recognizes these gates from the Purple and Red libraries:
inv | mullerC_sy | nand2HTen | nms2K |
inv2i | nand2 | nand3 | nms2_sy |
inv2iKn | nand2HLT_sy | nand3LT | nms3_sy3 |
inv2iKp | nand2LT | nand3LT_sy3 | nor2 |
invCLK | nand2LT_sy | nand3LTen | nor2kresetV |
invCTLn | nand2PH | nand3MLT | pms1 |
invHT | nand2_sy | nand3en | pms1K |
invK | nand2en | nms1 | pms2 |
invLT | nand2k | nms1K | pms2_sy |
inv_passgate | nand2LTen | nms2 |