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sleep.h
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1 /* Copyright (c) 2002, 2004 Theodore A. Roth
2  Copyright (c) 2004, 2007, 2008 Eric B. Weddington
3  Copyright (c) 2005, 2006, 2007 Joerg Wunsch
4  All rights reserved.
5 
6  Redistribution and use in source and binary forms, with or without
7  modification, are permitted provided that the following conditions are met:
8 
9  * Redistributions of source code must retain the above copyright
10  notice, this list of conditions and the following disclaimer.
11 
12  * Redistributions in binary form must reproduce the above copyright
13  notice, this list of conditions and the following disclaimer in
14  the documentation and/or other materials provided with the
15  distribution.
16 
17  * Neither the name of the copyright holders nor the names of
18  contributors may be used to endorse or promote products derived
19  from this software without specific prior written permission.
20 
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE. */
32 
33 /* $Id$ */
34 
35 #ifndef _AVR_SLEEP_H_
36 #define _AVR_SLEEP_H_ 1
37 
38 #include <avr/io.h>
39 #include <stdint.h>
40 
41 
42 /** \file */
43 
44 /** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
45 
46  \code #include <avr/sleep.h>\endcode
47 
48  Use of the \c SLEEP instruction can allow an application to reduce its
49  power comsumption considerably. AVR devices can be put into different
50  sleep modes. Refer to the datasheet for the details relating to the device
51  you are using.
52 
53  There are several macros provided in this header file to actually
54  put the device into sleep mode. The simplest way is to optionally
55  set the desired sleep mode using \c set_sleep_mode() (it usually
56  defaults to idle mode where the CPU is put on sleep but all
57  peripheral clocks are still running), and then call
58  \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
59  to sleep, and clears the sleep enable bit.
60 
61  Example:
62  \code
63  #include <avr/sleep.h>
64 
65  ...
66  set_sleep_mode(<mode>);
67  sleep_mode();
68  \endcode
69 
70  Note that unless your purpose is to completely lock the CPU (until a
71  hardware reset), interrupts need to be enabled before going to sleep.
72 
73  As the \c sleep_mode() macro might cause race conditions in some
74  situations, the individual steps of manipulating the sleep enable
75  (SE) bit, and actually issuing the \c SLEEP instruction, are provided
76  in the macros \c sleep_enable(), \c sleep_disable(), and
77  \c sleep_cpu(). This also allows for test-and-sleep scenarios that
78  take care of not missing the interrupt that will awake the device
79  from sleep.
80 
81  Example:
82  \code
83  #include <avr/interrupt.h>
84  #include <avr/sleep.h>
85 
86  ...
87  set_sleep_mode(<mode>);
88  cli();
89  if (some_condition)
90  {
91  sleep_enable();
92  sei();
93  sleep_cpu();
94  sleep_disable();
95  }
96  sei();
97  \endcode
98 
99  This sequence ensures an atomic test of \c some_condition with
100  interrupts being disabled. If the condition is met, sleep mode
101  will be prepared, and the \c SLEEP instruction will be scheduled
102  immediately after an \c SEI instruction. As the intruction right
103  after the \c SEI is guaranteed to be executed before an interrupt
104  could trigger, it is sure the device will really be put to sleep.
105 
106  Some devices have the ability to disable the Brown Out Detector (BOD) before
107  going to sleep. This will also reduce power while sleeping. If the
108  specific AVR device has this ability then an additional macro is defined:
109  \c sleep_bod_disable(). This macro generates inlined assembly code
110  that will correctly implement the timed sequence for disabling the BOD
111  before sleeping. However, there is a limited number of cycles after the
112  BOD has been disabled that the device can be put into sleep mode, otherwise
113  the BOD will not truly be disabled. Recommended practice is to disable
114  the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
115  put the device to sleep (\c sleep_cpu()), like so:
116 
117  \code
118  #include <avr/interrupt.h>
119  #include <avr/sleep.h>
120 
121  ...
122  set_sleep_mode(<mode>);
123  cli();
124  if (some_condition)
125  {
126  sleep_enable();
127  sleep_bod_disable();
128  sei();
129  sleep_cpu();
130  sleep_disable();
131  }
132  sei();
133  \endcode
134 */
135 
136 
137 /* Define an internal sleep control register and an internal sleep enable bit mask. */
138 #if defined(SLEEP_CTRL)
139 
140  /* XMEGA devices */
141  #define _SLEEP_CONTROL_REG SLEEP_CTRL
142  #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm
143 
144 #elif defined(SMCR)
145 
146  #define _SLEEP_CONTROL_REG SMCR
147  #define _SLEEP_ENABLE_MASK _BV(SE)
148 
149 #elif defined(__AVR_AT94K__)
150 
151  #define _SLEEP_CONTROL_REG MCUR
152  #define _SLEEP_ENABLE_MASK _BV(SE)
153 
154 #else
155 
156  #define _SLEEP_CONTROL_REG MCUCR
157  #define _SLEEP_ENABLE_MASK _BV(SE)
158 
159 #endif
160 
161 
162 /* Define set_sleep_mode() and sleep mode values per device. */
163 #if defined(__AVR_ATmega161__)
164 
165  #define SLEEP_MODE_IDLE 0
166  #define SLEEP_MODE_PWR_DOWN 1
167  #define SLEEP_MODE_PWR_SAVE 2
168 
169  #define set_sleep_mode(mode) \
170  do { \
171  MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
172  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
173  } while(0)
174 
175 
176 #elif defined(__AVR_ATmega162__) \
177 || defined(__AVR_ATmega8515__)
178 
179  #define SLEEP_MODE_IDLE 0
180  #define SLEEP_MODE_PWR_DOWN 1
181  #define SLEEP_MODE_PWR_SAVE 2
182  #define SLEEP_MODE_ADC 3
183  #define SLEEP_MODE_STANDBY 4
184  #define SLEEP_MODE_EXT_STANDBY 5
185 
186  #define set_sleep_mode(mode) \
187  do { \
188  MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
189  MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
190  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
191  } while(0)
192 
193 #elif defined(__AVR_AT90S2313__) \
194 || defined(__AVR_AT90S2323__) \
195 || defined(__AVR_AT90S2333__) \
196 || defined(__AVR_AT90S2343__) \
197 || defined(__AVR_AT43USB320__) \
198 || defined(__AVR_AT43USB355__) \
199 || defined(__AVR_AT90S4414__) \
200 || defined(__AVR_AT90S4433__) \
201 || defined(__AVR_AT90S8515__) \
202 || defined(__AVR_ATtiny22__)
203 
204  #define SLEEP_MODE_IDLE 0
205  #define SLEEP_MODE_PWR_DOWN _BV(SM)
206 
207  #define set_sleep_mode(mode) \
208  do { \
209  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \
210  } while(0)
211 
212 #elif defined(__AVR_ATA6616C__) \
213 || defined(__AVR_ATA6617C__) \
214 || defined(__AVR_ATA664251__) \
215 || defined(__AVR_ATtiny167__) \
216 || defined(__AVR_ATtiny87__) \
217 || defined(__AVR_ATtiny441__) \
218 || defined(__AVR_ATtiny828__) \
219 || defined(__AVR_ATtiny841__)
220 
221  #define SLEEP_MODE_IDLE 0
222  #define SLEEP_MODE_ADC _BV(SM0)
223  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
224 
225  #define set_sleep_mode(mode) \
226  do { \
227  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
228  } while(0)
229 
230 #elif defined(__AVR_AT90S4434__) \
231 || defined(__AVR_ATA5505__) \
232 || defined(__AVR_ATA5272__) \
233 || defined(__AVR_AT76C711__) \
234 || defined(__AVR_AT90S8535__) \
235 || defined(__AVR_ATmega103__) \
236 || defined(__AVR_ATmega161__) \
237 || defined(__AVR_ATmega163__) \
238 || defined(__AVR_ATmega16HVB__) \
239 || defined(__AVR_ATmega16HVBrevB__) \
240 || defined(__AVR_ATmega32HVB__) \
241 || defined(__AVR_ATmega32HVBrevB__) \
242 || defined(__AVR_ATtiny13__) \
243 || defined(__AVR_ATtiny13A__) \
244 || defined(__AVR_ATtiny15__) \
245 || defined(__AVR_ATtiny24__) \
246 || defined(__AVR_ATtiny24A__) \
247 || defined(__AVR_ATtiny44__) \
248 || defined(__AVR_ATtiny44A__) \
249 || defined(__AVR_ATtiny84__) \
250 || defined(__AVR_ATtiny84A__) \
251 || defined(__AVR_ATtiny25__) \
252 || defined(__AVR_ATtiny45__) \
253 || defined(__AVR_ATtiny48__) \
254 || defined(__AVR_ATtiny85__) \
255 || defined(__AVR_ATtiny88__)
256 
257  #define SLEEP_MODE_IDLE 0
258  #define SLEEP_MODE_ADC _BV(SM0)
259  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
260  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
261 
262  #define set_sleep_mode(mode) \
263  do { \
264  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
265  } while(0)
266 
267 #elif defined(__AVR_ATmega16HVA__) \
268 || defined(__AVR_ATmega8HVA__)
269 
270  #define SLEEP_MODE_IDLE (0)
271  #define SLEEP_MODE_ADC _BV(SM0)
272  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
273  #define SLEEP_MODE_PWR_OFF _BV(SM2)
274 
275 
276  #define set_sleep_mode(mode) \
277  do { \
278  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
279  } while(0)
280 
281 #elif defined(__AVR_ATmega406__)
282 
283  #define SLEEP_MODE_IDLE (0)
284  #define SLEEP_MODE_ADC _BV(SM0)
285  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
286  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
287  #define SLEEP_MODE_PWR_OFF _BV(SM2)
288 
289  #define set_sleep_mode(mode) \
290  do { \
291  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
292  } while(0)
293 
294 #elif defined(__AVR_ATtiny2313__) \
295 || defined(__AVR_ATtiny2313A__) \
296 || defined(__AVR_ATtiny4313__)
297 
298  #define SLEEP_MODE_IDLE 0
299  #define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
300  #define SLEEP_MODE_STANDBY _BV(SM1)
301 
302  #define set_sleep_mode(mode) \
303  do { \
304  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
305  } while(0)
306 
307 #elif defined(__AVR_AT94K__) \
308 || defined(__AVR_ATmega64HVE__) \
309 || defined(__AVR_ATmega64HVE2__)
310 
311  #define SLEEP_MODE_IDLE 0
312  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
313  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
314 
315  #define set_sleep_mode(mode) \
316  do { \
317  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
318  } while(0)
319 
320 #elif defined(__AVR_ATtiny26__) \
321 || defined(__AVR_ATtiny261__) \
322 || defined(__AVR_ATtiny261A__) \
323 || defined(__AVR_ATtiny461__) \
324 || defined(__AVR_ATtiny461A__) \
325 || defined(__AVR_ATtiny861__) \
326 || defined(__AVR_ATtiny861A__) \
327 || defined(__AVR_ATtiny43U__) \
328 || defined(__AVR_ATtiny1634__)
329 
330  #define SLEEP_MODE_IDLE 0
331  #define SLEEP_MODE_ADC _BV(SM0)
332  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
333  #define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1))
334 
335  #define set_sleep_mode(mode) \
336  do { \
337  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
338  } while(0)
339 
340 #elif defined(__AVR_AT90PWM216__) \
341 || defined(__AVR_AT90PWM316__) \
342 || defined(__AVR_AT90PWM161__) \
343 || defined(__AVR_AT90PWM81__) \
344 || defined(__AVR_AT90PWM1__) \
345 || defined(__AVR_AT90PWM2__) \
346 || defined(__AVR_AT90PWM2B__) \
347 || defined(__AVR_AT90PWM3__) \
348 || defined(__AVR_AT90PWM3B__) \
349 || defined(__AVR_ATmega32M1__) \
350 || defined(__AVR_ATmega16M1__) \
351 || defined(__AVR_ATmega64M1__)
352 
353  #define SLEEP_MODE_IDLE 0
354  #define SLEEP_MODE_ADC _BV(SM0)
355  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
356  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
357 
358  #define set_sleep_mode(mode) \
359  do { \
360  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
361  } while(0)
362 
363 #elif defined(__AVR_AT90USB1286__) \
364 || defined(__AVR_AT90USB1287__) \
365 || defined(__AVR_AT90USB646__) \
366 || defined(__AVR_AT90USB647__) \
367 || defined(__AVR_ATA6614Q__) \
368 || defined(__AVR_ATmega128__) \
369 || defined(__AVR_ATmega128A__) \
370 || defined(__AVR_ATmega1280__) \
371 || defined(__AVR_ATmega1281__) \
372 || defined(__AVR_ATmega1284__) \
373 || defined(__AVR_ATmega1284P__) \
374 || defined(__AVR_ATmega128RFA1__) \
375 || defined(__AVR_ATmega128RFR2__) \
376 || defined(__AVR_ATmega1284RFR2__) \
377 || defined(__AVR_ATmega16__) \
378 || defined(__AVR_ATmega16A__) \
379 || defined(__AVR_ATmega162__) \
380 || defined(__AVR_ATmega164A__) \
381 || defined(__AVR_ATmega164P__) \
382 || defined(__AVR_ATmega164PA__) \
383 || defined(__AVR_ATmega168A__) \
384 || defined(__AVR_ATmega168P__) \
385 || defined(__AVR_ATmega168PA__) \
386 || defined(__AVR_ATmega16HVA2__) \
387 || defined(__AVR_ATmega16U4__) \
388 || defined(__AVR_ATmega2560__) \
389 || defined(__AVR_ATmega2561__) \
390 || defined(__AVR_ATmega256RFR2__) \
391 || defined(__AVR_ATmega2564RFR2__) \
392 || defined(__AVR_ATmega32__) \
393 || defined(__AVR_ATmega32A__) \
394 || defined(__AVR_ATmega323__) \
395 || defined(__AVR_ATmega324A__) \
396 || defined(__AVR_ATmega324P__) \
397 || defined(__AVR_ATmega324PA__) \
398 || defined(__AVR_ATmega328__) \
399 || defined(__AVR_ATmega328P__) \
400 || defined(__AVR_ATmega32C1__) \
401 || defined(__AVR_ATmega32U4__) \
402 || defined(__AVR_ATmega32U6__) \
403 || defined(__AVR_ATmega48A__) \
404 || defined(__AVR_ATmega48PA__) \
405 || defined(__AVR_ATmega48P__) \
406 || defined(__AVR_ATmega64__) \
407 || defined(__AVR_ATmega64A__) \
408 || defined(__AVR_ATmega640__) \
409 || defined(__AVR_ATmega644__) \
410 || defined(__AVR_ATmega644A__) \
411 || defined(__AVR_ATmega644P__) \
412 || defined(__AVR_ATmega644PA__) \
413 || defined(__AVR_ATmega64C1__) \
414 || defined(__AVR_ATmega64RFR2__) \
415 || defined(__AVR_ATmega644RFR2__) \
416 || defined(__AVR_ATmega8515__) \
417 || defined(__AVR_ATmega8535__) \
418 || defined(__AVR_ATmega88A__) \
419 || defined(__AVR_ATmega88P__) \
420 || defined(__AVR_ATmega88PA__)
421 
422  #define SLEEP_MODE_IDLE (0)
423  #define SLEEP_MODE_ADC _BV(SM0)
424  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
425  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
426  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
427  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
428 
429 
430  #define set_sleep_mode(mode) \
431  do { \
432  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
433  } while(0)
434 
435 #elif defined(__AVR_ATmega8A__) \
436 || defined(__AVR_ATmega8__) \
437 || defined(__AVR_ATmega6450A__) \
438 || defined(__AVR_ATmega6450P__) \
439 || defined(__AVR_ATmega645A__) \
440 || defined(__AVR_ATmega645P__) \
441 || defined(__AVR_ATmega3250A__) \
442 || defined(__AVR_ATmega3250PA__) \
443 || defined(__AVR_ATmega325A__) \
444 || defined(__AVR_ATmega325PA__) \
445 || defined(__AVR_ATmega165A__) \
446 || defined(__AVR_ATmega165P__) \
447 || defined(__AVR_ATmega165PA__) \
448 || defined(__AVR_ATmega169A__) \
449 || defined(__AVR_ATmega169P__) \
450 || defined(__AVR_ATmega169PA__) \
451 || defined(__AVR_ATmega329A__) \
452 || defined(__AVR_ATmega329PA__) \
453 || defined(__AVR_ATmega3290A__) \
454 || defined(__AVR_ATmega3290PA__) \
455 || defined(__AVR_ATmega649A__) \
456 || defined(__AVR_ATmega649P__) \
457 || defined(__AVR_ATmega6490A__) \
458 || defined(__AVR_ATmega6490P__) \
459 || defined(__AVR_ATmega165__) \
460 || defined(__AVR_ATmega169__) \
461 || defined(__AVR_ATmega48__) \
462 || defined(__AVR_ATmega88__) \
463 || defined(__AVR_ATmega168__) \
464 || defined(__AVR_ATmega325P__) \
465 || defined(__AVR_ATmega3250P__) \
466 || defined(__AVR_ATmega325__) \
467 || defined(__AVR_ATmega3250__) \
468 || defined(__AVR_ATmega645__) \
469 || defined(__AVR_ATmega6450__) \
470 || defined(__AVR_ATmega329__) \
471 || defined(__AVR_ATmega329P__) \
472 || defined(__AVR_ATmega3290__) \
473 || defined(__AVR_ATmega3290P__) \
474 || defined(__AVR_ATmega649__) \
475 || defined(__AVR_ATmega6490__) \
476 || defined(__AVR_AT90CAN128__) \
477 || defined(__AVR_AT90CAN32__) \
478 || defined(__AVR_AT90CAN64__) \
479 || defined(__AVR_ATA6612C__) \
480 || defined(__AVR_ATA6613C__)
481 
482  #define SLEEP_MODE_IDLE (0)
483  #define SLEEP_MODE_ADC _BV(SM0)
484  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
485  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
486  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
487 
488 
489  #define set_sleep_mode(mode) \
490  do { \
491  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
492  } while(0)
493 
494 #elif defined(__AVR_ATxmega16A4__) \
495 || defined(__AVR_ATxmega16A4U__) \
496 || defined(__AVR_ATxmega16C4__) \
497 || defined(__AVR_ATxmega16D4__) \
498 || defined(__AVR_ATxmega32A4__) \
499 || defined(__AVR_ATxmega32A4U__) \
500 || defined(__AVR_ATxmega32C3__) \
501 || defined(__AVR_ATxmega32C4__) \
502 || defined(__AVR_ATxmega32D3__) \
503 || defined(__AVR_ATxmega32D4__) \
504 || defined(__AVR_ATxmega8E5__) \
505 || defined(__AVR_ATxmega16E5__) \
506 || defined(__AVR_ATxmega32E5__) \
507 || defined(__AVR_ATxmega64A1__) \
508 || defined(__AVR_ATxmega64A1U__) \
509 || defined(__AVR_ATxmega64A3__) \
510 || defined(__AVR_ATxmega64A3U__) \
511 || defined(__AVR_ATxmega64A4U__) \
512 || defined(__AVR_ATxmega64B1__) \
513 || defined(__AVR_ATxmega64B3__) \
514 || defined(__AVR_ATxmega64C3__) \
515 || defined(__AVR_ATxmega64D3__) \
516 || defined(__AVR_ATxmega64D4__) \
517 || defined(__AVR_ATxmega128A1__) \
518 || defined(__AVR_ATxmega128A1U__) \
519 || defined(__AVR_ATxmega128A3__) \
520 || defined(__AVR_ATxmega128A3U__) \
521 || defined(__AVR_ATxmega128A4U__) \
522 || defined(__AVR_ATxmega128B1__) \
523 || defined(__AVR_ATxmega128B3__) \
524 || defined(__AVR_ATxmega128C3__) \
525 || defined(__AVR_ATxmega128D3__) \
526 || defined(__AVR_ATxmega128D4__) \
527 || defined(__AVR_ATxmega192A3__) \
528 || defined(__AVR_ATxmega192A3U__) \
529 || defined(__AVR_ATxmega192C3__) \
530 || defined(__AVR_ATxmega192D3__) \
531 || defined(__AVR_ATxmega256A3__) \
532 || defined(__AVR_ATxmega256A3U__) \
533 || defined(__AVR_ATxmega256C3__) \
534 || defined(__AVR_ATxmega256D3__) \
535 || defined(__AVR_ATxmega256A3B__) \
536 || defined(__AVR_ATxmega256A3BU__) \
537 || defined(__AVR_ATxmega384C3__) \
538 || defined(__AVR_ATxmega384D3__)
539 
540  #define SLEEP_MODE_IDLE (0)
541  #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
542  #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
543  #define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
544  #define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
545 
546  #define set_sleep_mode(mode) \
547  do { \
548  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
549  } while(0)
550 
551 #elif defined(__AVR_AT90SCR100__) \
552 || defined(__AVR_ATmega8U2__) \
553 || defined(__AVR_ATmega16U2__) \
554 || defined(__AVR_ATmega32U2__) \
555 || defined(__AVR_AT90USB162__) \
556 || defined(__AVR_AT90USB82__)
557 
558  #define SLEEP_MODE_IDLE (0)
559  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
560  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
561  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
562  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
563 
564  #define set_sleep_mode(mode) \
565  do { \
566  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
567  } while(0)
568 
569 #elif defined(__AVR_ATA6285__) \
570 || defined(__AVR_ATA6286__) \
571 || defined(__AVR_ATA6289__)
572 
573  #define SLEEP_MODE_IDLE (0)
574  #define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
575  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
576 
577  #define set_sleep_mode(mode) \
578  do { \
579  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
580  } while(0)
581 
582 #elif defined (__AVR_ATA5790__) \
583 || defined (__AVR_ATA5790N__) \
584 || defined (__AVR_ATA5795__) \
585 || defined (__AVR_ATA5782__) \
586 || defined (__AVR_ATA5831__)
587 
588  #define SLEEP_MODE_IDLE (0)
589  #define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
590  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
591  #define SLEEP_MODE_PWR_SAVE (_BV(SM1) | _BV(SM0))
592 
593  #define set_sleep_mode(mode) \
594  do { \
595  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
596  } while(0)
597 
598 #elif defined (__AVR_ATA5702M322__)
599 
600  #define SLEEP_MODE_IDLE (0)
601  #define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
602  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
603  #define SLEEP_MODE_PWR_SAVE (_BV(SM1) | _BV(SM0))
604  #define SLEEP_MODE_EXT_PWR_DOWN (_BV(SM2))
605  #define SLEEP_MODE_PWR_OFF (_BV(SM2) | _BV(SM0))
606 
607  #define set_sleep_mode(mode) \
608  do { \
609  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
610  } while(0)
611 
612 #elif defined(__AVR_ATtiny4__) \
613 || defined(__AVR_ATtiny5__) \
614 || defined(__AVR_ATtiny9__) \
615 || defined(__AVR_ATtiny10__) \
616 || defined(__AVR_ATtiny20__) \
617 || defined(__AVR_ATtiny40__)
618 
619  #define SLEEP_MODE_IDLE 0
620  #define SLEEP_MODE_ADC _BV(SM0)
621  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
622  #define SLEEP_MODE_STANDBY _BV(SM2)
623 
624  #define set_sleep_mode(mode) \
625  do { \
626  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
627  } while(0)
628 
629 #else
630 
631  #error "No SLEEP mode defined for this device."
632 
633 #endif
634 
635 
636 
637 /** \ingroup avr_sleep
638 
639  Put the device in sleep mode. How the device is brought out of sleep mode
640  depends on the specific mode selected with the set_sleep_mode() function.
641  See the data sheet for your device for more details. */
642 
643 
644 #if defined(__DOXYGEN__)
645 
646 /** \ingroup avr_sleep
647 
648  Set the SE (sleep enable) bit.
649 */
650 extern void sleep_enable (void);
651 
652 #else
653 
654 #define sleep_enable() \
655 do { \
656  _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \
657 } while(0)
658 
659 #endif
660 
661 
662 #if defined(__DOXYGEN__)
663 
664 /** \ingroup avr_sleep
665 
666  Clear the SE (sleep enable) bit.
667 */
668 extern void sleep_disable (void);
669 
670 #else
671 
672 #define sleep_disable() \
673 do { \
674  _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \
675 } while(0)
676 
677 #endif
678 
679 
680 /** \ingroup avr_sleep
681 
682  Put the device into sleep mode. The SE bit must be set
683  beforehand, and it is recommended to clear it afterwards.
684 */
685 #if defined(__DOXYGEN__)
686 
687 extern void sleep_cpu (void);
688 
689 #else
690 
691 #define sleep_cpu() \
692 do { \
693  __asm__ __volatile__ ( "sleep" "\n\t" :: ); \
694 } while(0)
695 
696 #endif
697 
698 
699 #if defined(__DOXYGEN__)
700 
701 extern void sleep_mode (void);
702 
703 #else
704 
705 #define sleep_mode() \
706 do { \
707  sleep_enable(); \
708  sleep_cpu(); \
709  sleep_disable(); \
710 } while (0)
711 
712 #endif
713 
714 
715 #if defined(__DOXYGEN__)
716 
717 extern void sleep_bod_disable (void);
718 
719 #else
720 
721 #if defined(BODS) && defined(BODSE)
722 
723 #ifdef BODCR
724 
725 #define BOD_CONTROL_REG BODCR
726 
727 #else
728 
729 #define BOD_CONTROL_REG MCUCR
730 
731 #endif
732 
733 #define sleep_bod_disable() \
734 do { \
735  uint8_t tempreg; \
736  __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
737  "ori %[tempreg], %[bods_bodse]" "\n\t" \
738  "out %[mcucr], %[tempreg]" "\n\t" \
739  "andi %[tempreg], %[not_bodse]" "\n\t" \
740  "out %[mcucr], %[tempreg]" \
741  : [tempreg] "=&d" (tempreg) \
742  : [mcucr] "I" _SFR_IO_ADDR(BOD_CONTROL_REG), \
743  [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
744  [not_bodse] "i" (~_BV(BODSE))); \
745 } while (0)
746 
747 #endif
748 
749 #endif
750 
751 
752 /*@}*/
753 
754 #endif /* _AVR_SLEEP_H_ */
void sleep_cpu(void)
void sleep_enable(void)
void sleep_disable(void)

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