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include
avr
wdt.h
Go to the documentation of this file.
1
/* Copyright (c) 2002, 2004 Marek Michalkiewicz
2
Copyright (c) 2005, 2006, 2007 Eric B. Weddington
3
All rights reserved.
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5
Redistribution and use in source and binary forms, with or without
6
modification, are permitted provided that the following conditions are met:
7
8
* Redistributions of source code must retain the above copyright
9
notice, this list of conditions and the following disclaimer.
10
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* Redistributions in binary form must reproduce the above copyright
12
notice, this list of conditions and the following disclaimer in
13
the documentation and/or other materials provided with the
14
distribution.
15
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* Neither the name of the copyright holders nor the names of
17
contributors may be used to endorse or promote products derived
18
from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30
POSSIBILITY OF SUCH DAMAGE. */
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/* $Id$ */
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34
/*
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avr/wdt.h - macros for AVR watchdog timer
36
*/
37
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#ifndef _AVR_WDT_H_
39
#define _AVR_WDT_H_
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#include <
avr/io.h
>
42
#include <
stdint.h
>
43
44
/** \file */
45
/** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
46
\code #include <avr/wdt.h> \endcode
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This header file declares the interface to some inline macros
49
handling the watchdog timer present in many AVR devices. In order
50
to prevent the watchdog timer configuration from being
51
accidentally altered by a crashing application, a special timed
52
sequence is required in order to change it. The macros within
53
this header file handle the required sequence automatically
54
before changing any value. Interrupts will be disabled during
55
the manipulation.
56
57
\note Depending on the fuse configuration of the particular
58
device, further restrictions might apply, in particular it might
59
be disallowed to turn off the watchdog timer.
60
61
Note that for newer devices (ATmega88 and newer, effectively any
62
AVR that has the option to also generate interrupts), the watchdog
63
timer remains active even after a system reset (except a power-on
64
condition), using the fastest prescaler value (approximately 15
65
ms). It is therefore required to turn off the watchdog early
66
during program startup, the datasheet recommends a sequence like
67
the following:
68
69
\code
70
#include <stdint.h>
71
#include <avr/wdt.h>
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uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
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void get_mcusr(void) \
76
__attribute__((naked)) \
77
__attribute__((section(".init3")));
78
void get_mcusr(void)
79
{
80
mcusr_mirror = MCUSR;
81
MCUSR = 0;
82
wdt_disable();
83
}
84
\endcode
85
86
Saving the value of MCUSR in \c mcusr_mirror is only needed if the
87
application later wants to examine the reset source, but in particular,
88
clearing the watchdog reset flag before disabling the
89
watchdog is required, according to the datasheet.
90
*/
91
92
/**
93
\ingroup avr_watchdog
94
Reset the watchdog timer. When the watchdog timer is enabled,
95
a call to this instruction is required before the timer expires,
96
otherwise a watchdog-initiated device reset will occur.
97
*/
98
99
#define wdt_reset() __asm__ __volatile__ ("wdr")
100
101
102
#if defined(WDP3)
103
# define _WD_PS3_MASK _BV(WDP3)
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#else
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# define _WD_PS3_MASK 0x00
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#endif
107
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#if defined(WDTCSR)
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# define _WD_CONTROL_REG WDTCSR
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#elif defined(WDTCR)
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# define _WD_CONTROL_REG WDTCR
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#else
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# define _WD_CONTROL_REG WDT
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#endif
115
116
#if defined(WDTOE)
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#define _WD_CHANGE_BIT WDTOE
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#else
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#define _WD_CHANGE_BIT WDCE
120
#endif
121
122
123
/**
124
\ingroup avr_watchdog
125
Enable the watchdog timer, configuring it for expiry after
126
\c timeout (which is a combination of the \c WDP0 through
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\c WDP2 bits to write into the \c WDTCR register; For those devices
128
that have a \c WDTCSR register, it uses the combination of the \c WDP0
129
through \c WDP3 bits).
130
131
See also the symbolic constants \c WDTO_15MS et al.
132
*/
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134
135
#if defined(__AVR_ATxmega16A4__) \
136
|| defined(__AVR_ATxmega16A4U__) \
137
|| defined(__AVR_ATxmega16C4__) \
138
|| defined(__AVR_ATxmega16D4__) \
139
|| defined(__AVR_ATxmega32A4__) \
140
|| defined(__AVR_ATxmega32A4U__) \
141
|| defined(__AVR_ATxmega32C3__) \
142
|| defined(__AVR_ATxmega32C4__) \
143
|| defined(__AVR_ATxmega32D3__) \
144
|| defined(__AVR_ATxmega32D4__) \
145
|| defined(__AVR_ATxmega8E5__) \
146
|| defined(__AVR_ATxmega16E5__) \
147
|| defined(__AVR_ATxmega32E5__) \
148
|| defined(__AVR_ATxmega64A1__) \
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|| defined(__AVR_ATxmega64A1U__) \
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|| defined(__AVR_ATxmega64A3__) \
151
|| defined(__AVR_ATxmega64A3U__) \
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|| defined(__AVR_ATxmega64A4U__) \
153
|| defined(__AVR_ATxmega64B1__) \
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|| defined(__AVR_ATxmega64B3__) \
155
|| defined(__AVR_ATxmega64C3__) \
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|| defined(__AVR_ATxmega64D3__) \
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|| defined(__AVR_ATxmega64D4__) \
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|| defined(__AVR_ATxmega128A1__) \
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|| defined(__AVR_ATxmega128A1U__) \
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|| defined(__AVR_ATxmega128A3__) \
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|| defined(__AVR_ATxmega128A3U__) \
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|| defined(__AVR_ATxmega128A4U__) \
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|| defined(__AVR_ATxmega128B1__) \
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|| defined(__AVR_ATxmega128B3__) \
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|| defined(__AVR_ATxmega128C3__) \
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|| defined(__AVR_ATxmega128D3__) \
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|| defined(__AVR_ATxmega128D4__) \
168
|| defined(__AVR_ATxmega192A3__) \
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|| defined(__AVR_ATxmega192A3U__) \
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|| defined(__AVR_ATxmega192C3__) \
171
|| defined(__AVR_ATxmega192D3__) \
172
|| defined(__AVR_ATxmega256A3__) \
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|| defined(__AVR_ATxmega256A3U__) \
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|| defined(__AVR_ATxmega256C3__) \
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|| defined(__AVR_ATxmega256D3__) \
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|| defined(__AVR_ATxmega256A3B__) \
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|| defined(__AVR_ATxmega256A3BU__) \
178
|| defined(__AVR_ATxmega384C3__) \
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|| defined(__AVR_ATxmega384D3__)
180
181
/*
182
wdt_enable(timeout) for xmega devices
183
** write signature (CCP_IOREG_gc) that enables change of protected I/O
184
registers to the CCP register
185
** At the same time,
186
1) set WDT change enable (WDT_CEN_bm)
187
2) enable WDT (WDT_ENABLE_bm)
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3) set timeout (timeout)
189
** Synchronization starts when ENABLE bit of WDT is set. So, wait till it
190
finishes (SYNCBUSY of STATUS register is automatically cleared after the
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sync is finished).
192
*/
193
#define wdt_enable(timeout) \
194
do { \
195
uint8_t temp = 0; \
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__asm__ __volatile__ ( \
197
"in __tmp_reg__, %[rampd]" "\n\t" \
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"out %[rampd], __zero_reg__" "\n\t" \
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"out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
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"sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \
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"1:lds %[tmp], %[wdt_status_reg]" "\n\t" \
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"sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \
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"rjmp 1b" "\n\t" \
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"out %[rampd], __tmp_reg__" "\n\t" \
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: "=r" (temp) \
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: [rampd] "M" (_SFR_MEM_ADDR(RAMPD)), \
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[ccp_reg] "I" (_SFR_MEM_ADDR(CCP)), \
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[ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
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[wdt_reg] "M" (_SFR_MEM_ADDR(WDT_CTRL)), \
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[wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \
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[wdt_status_reg] "M" (_SFR_MEM_ADDR(WDT_STATUS)), \
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[wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm), \
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[tmp] "r" (temp) \
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: "r0" \
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); \
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} while(0)
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#define wdt_disable() \
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__asm__ __volatile__ ( \
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"in __tmp_reg__, %[rampd]" "\n\t" \
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"out %[rampd], __zero_reg__" "\n\t" \
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"out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \
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"sts %[wdt_reg], %[disable_mask]" "\n\t" \
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"out %[rampd], __tmp_reg__" "\n\t" \
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: \
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: [rampd] "M" (_SFR_MEM_ADDR(RAMPD)), \
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[ccp_reg] "I" (_SFR_MEM_ADDR(CCP)), \
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[ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \
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[wdt_reg] "M" (_SFR_MEM_ADDR(WDT_CTRL)), \
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[disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \
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: "r0" \
232
);
233
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#elif defined(__AVR_AT90CAN32__) \
235
|| defined(__AVR_AT90CAN64__) \
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|| defined(__AVR_AT90CAN128__) \
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|| defined(__AVR_AT90PWM1__) \
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|| defined(__AVR_AT90PWM2__) \
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|| defined(__AVR_AT90PWM216__) \
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|| defined(__AVR_AT90PWM2B__) \
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|| defined(__AVR_AT90PWM3__) \
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|| defined(__AVR_AT90PWM316__) \
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|| defined(__AVR_AT90PWM3B__) \
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|| defined(__AVR_AT90PWM161__) \
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|| defined(__AVR_AT90PWM81__) \
246
|| defined(__AVR_AT90USB1286__) \
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|| defined(__AVR_AT90USB1287__) \
248
|| defined(__AVR_AT90USB162__) \
249
|| defined(__AVR_AT90USB646__) \
250
|| defined(__AVR_AT90USB647__) \
251
|| defined(__AVR_AT90USB82__) \
252
|| defined(__AVR_ATmega128A__) \
253
|| defined(__AVR_ATmega1280__) \
254
|| defined(__AVR_ATmega1281__) \
255
|| defined(__AVR_ATmega1284__) \
256
|| defined(__AVR_ATmega1284P__) \
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|| defined(__AVR_ATmega128RFA1__) \
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|| defined(__AVR_ATmega128RFR2__) \
259
|| defined(__AVR_ATmega1284RFR2__) \
260
|| defined(__AVR_ATmega164__) \
261
|| defined(__AVR_ATmega164A__) \
262
|| defined(__AVR_ATmega164P__) \
263
|| defined(__AVR_ATmega164PA__) \
264
|| defined(__AVR_ATmega165__) \
265
|| defined(__AVR_ATmega165A__) \
266
|| defined(__AVR_ATmega165P__) \
267
|| defined(__AVR_ATmega165PA__) \
268
|| defined(__AVR_ATmega168__) \
269
|| defined(__AVR_ATmega168A__) \
270
|| defined(__AVR_ATmega168P__) \
271
|| defined(__AVR_ATmega168PA__) \
272
|| defined(__AVR_ATmega169__) \
273
|| defined(__AVR_ATmega169A__) \
274
|| defined(__AVR_ATmega169P__) \
275
|| defined(__AVR_ATmega169PA__) \
276
|| defined(__AVR_ATmega16HVA__) \
277
|| defined(__AVR_ATmega16HVA2__) \
278
|| defined(__AVR_ATmega16HVB__) \
279
|| defined(__AVR_ATmega16HVBrevB__) \
280
|| defined(__AVR_ATmega16M1__) \
281
|| defined(__AVR_ATmega16U2__) \
282
|| defined(__AVR_ATmega16U4__) \
283
|| defined(__AVR_ATmega2560__) \
284
|| defined(__AVR_ATmega2561__) \
285
|| defined(__AVR_ATmega256RFR2__) \
286
|| defined(__AVR_ATmega2564RFR2__) \
287
|| defined(__AVR_ATmega32A__) \
288
|| defined(__AVR_ATmega324__) \
289
|| defined(__AVR_ATmega324A__) \
290
|| defined(__AVR_ATmega324P__) \
291
|| defined(__AVR_ATmega324PA__) \
292
|| defined(__AVR_ATmega325__) \
293
|| defined(__AVR_ATmega325A__) \
294
|| defined(__AVR_ATmega325P__) \
295
|| defined(__AVR_ATmega325PA__) \
296
|| defined(__AVR_ATmega3250__) \
297
|| defined(__AVR_ATmega3250A__) \
298
|| defined(__AVR_ATmega3250P__) \
299
|| defined(__AVR_ATmega3250PA__) \
300
|| defined(__AVR_ATmega328__) \
301
|| defined(__AVR_ATmega328P__) \
302
|| defined(__AVR_ATmega329__) \
303
|| defined(__AVR_ATmega329A__) \
304
|| defined(__AVR_ATmega329P__) \
305
|| defined(__AVR_ATmega329PA__) \
306
|| defined(__AVR_ATmega3290__) \
307
|| defined(__AVR_ATmega3290A__) \
308
|| defined(__AVR_ATmega3290P__) \
309
|| defined(__AVR_ATmega3290PA__) \
310
|| defined(__AVR_ATmega32C1__) \
311
|| defined(__AVR_ATmega32HVB__) \
312
|| defined(__AVR_ATmega32HVBrevB__) \
313
|| defined(__AVR_ATmega32M1__) \
314
|| defined(__AVR_ATmega32U2__) \
315
|| defined(__AVR_ATmega32U4__) \
316
|| defined(__AVR_ATmega32U6__) \
317
|| defined(__AVR_ATmega406__) \
318
|| defined(__AVR_ATmega48__) \
319
|| defined(__AVR_ATmega48A__) \
320
|| defined(__AVR_ATmega48PA__) \
321
|| defined(__AVR_ATmega48P__) \
322
|| defined(__AVR_ATmega64A__) \
323
|| defined(__AVR_ATmega64RFR2__) \
324
|| defined(__AVR_ATmega644RFR2__) \
325
|| defined(__AVR_ATmega640__) \
326
|| defined(__AVR_ATmega644__) \
327
|| defined(__AVR_ATmega644A__) \
328
|| defined(__AVR_ATmega644P__) \
329
|| defined(__AVR_ATmega644PA__) \
330
|| defined(__AVR_ATmega645__) \
331
|| defined(__AVR_ATmega645A__) \
332
|| defined(__AVR_ATmega645P__) \
333
|| defined(__AVR_ATmega6450__) \
334
|| defined(__AVR_ATmega6450A__) \
335
|| defined(__AVR_ATmega6450P__) \
336
|| defined(__AVR_ATmega649__) \
337
|| defined(__AVR_ATmega649A__) \
338
|| defined(__AVR_ATmega6490__) \
339
|| defined(__AVR_ATmega6490A__) \
340
|| defined(__AVR_ATmega6490P__) \
341
|| defined(__AVR_ATmega649P__) \
342
|| defined(__AVR_ATmega64C1__) \
343
|| defined(__AVR_ATmega64HVE__) \
344
|| defined(__AVR_ATmega64HVE2__) \
345
|| defined(__AVR_ATmega64M1__) \
346
|| defined(__AVR_ATmega8A__) \
347
|| defined(__AVR_ATmega88__) \
348
|| defined(__AVR_ATmega88A__) \
349
|| defined(__AVR_ATmega88P__) \
350
|| defined(__AVR_ATmega88PA__) \
351
|| defined(__AVR_ATmega8HVA__) \
352
|| defined(__AVR_ATmega8U2__) \
353
|| defined(__AVR_ATtiny48__) \
354
|| defined(__AVR_ATtiny88__) \
355
|| defined(__AVR_ATtiny87__) \
356
|| defined(__AVR_ATtiny167__) \
357
|| defined(__AVR_AT90SCR100__) \
358
|| defined(__AVR_ATA6285__) \
359
|| defined(__AVR_ATA6286__) \
360
|| defined(__AVR_ATA6289__) \
361
|| defined(__AVR_ATA5272__) \
362
|| defined(__AVR_ATA5505__) \
363
|| defined(__AVR_ATA5790__) \
364
|| defined(__AVR_ATA5790N__) \
365
|| defined(__AVR_ATA5795__) \
366
|| defined(__AVR_ATA5782__) \
367
|| defined(__AVR_ATA5702M322__) \
368
|| defined(__AVR_ATA5831__) \
369
|| defined(__AVR_ATA6612C__) \
370
|| defined(__AVR_ATA6613C__) \
371
|| defined(__AVR_ATA6614Q__) \
372
|| defined(__AVR_ATA6616C__) \
373
|| defined(__AVR_ATA6617C__) \
374
|| defined(__AVR_ATA664251__)
375
376
/* Use STS instruction. */
377
378
#define wdt_enable(value) \
379
__asm__ __volatile__ ( \
380
"in __tmp_reg__,__SREG__" "\n\t" \
381
"cli" "\n\t" \
382
"wdr" "\n\t" \
383
"sts %0,%1" "\n\t" \
384
"out __SREG__,__tmp_reg__" "\n\t" \
385
"sts %0,%2" "\n\t" \
386
:
/* no outputs */
\
387
: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
388
"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
389
"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
390
_BV(WDE) | (value & 0x07)) ) \
391
: "r0" \
392
)
393
394
#define wdt_disable() \
395
__asm__ __volatile__ ( \
396
"in __tmp_reg__, __SREG__" "\n\t" \
397
"cli" "\n\t" \
398
"sts %0, %1" "\n\t" \
399
"sts %0, __zero_reg__" "\n\t" \
400
"out __SREG__,__tmp_reg__" "\n\t" \
401
:
/* no outputs */
\
402
: "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
403
"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
404
: "r0" \
405
)
406
407
408
#elif defined(__AVR_ATtiny441__) \
409
|| defined(__AVR_ATtiny841__)
410
411
/* Use STS instruction. */
412
413
#define wdt_enable(value) \
414
__asm__ __volatile__ ( \
415
"in __tmp_reg__,__SREG__" "\n\t" \
416
"cli" "\n\t" \
417
"wdr" "\n\t" \
418
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
419
"out %[WDTREG],%[WDVALUE]" "\n\t" \
420
"out __SREG__,__tmp_reg__" "\n\t" \
421
:
/* no outputs */
\
422
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
423
[SIGNATURE] "r" ((uint8_t)0xD8), \
424
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
425
[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
426
| _BV(WDE) | (value & 0x07) )) \
427
: "r0" \
428
)
429
430
#define wdt_disable() \
431
do { \
432
uint8_t temp_wd; \
433
__asm__ __volatile__ ( \
434
"in __tmp_reg__,__SREG__" "\n\t" \
435
"cli" "\n\t" \
436
"wdr" "\n\t" \
437
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
438
"in %[TEMP_WD],%[WDTREG]" "\n\t" \
439
"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
440
"out %[WDTREG],%[TEMP_WD]" "\n\t" \
441
"out __SREG__,__tmp_reg__" "\n\t" \
442
:
/*no output */
\
443
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
444
[SIGNATURE] "r" ((uint8_t)0xD8), \
445
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
446
[TEMP_WD] "d" (temp_wd), \
447
[WDVALUE] "I" (1 << WDE) \
448
: "r0" \
449
); \
450
}while(0)
451
452
#elif defined(__AVR_ATtiny1634__) \
453
|| defined(__AVR_ATtiny828__)
454
455
#define wdt_enable(value) \
456
__asm__ __volatile__ ( \
457
"in __tmp_reg__,__SREG__" "\n\t" \
458
"cli" "\n\t" \
459
"wdr" "\n\t" \
460
"sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
461
"sts %[WDTREG],%[WDVALUE]" "\n\t" \
462
"out __SREG__,__tmp_reg__" "\n\t" \
463
:
/* no outputs */
\
464
: [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
465
[SIGNATURE] "r" ((uint8_t)0xD8), \
466
[WDTREG] "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
467
[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
468
| _BV(WDE) | value)) \
469
: "r0" \
470
)
471
472
#define wdt_disable() \
473
do { \
474
uint8_t temp_wd; \
475
__asm__ __volatile__ ( \
476
"in __tmp_reg__,__SREG__" "\n\t" \
477
"cli" "\n\t" \
478
"wdr" "\n\t" \
479
"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
480
"in %[TEMP_WD],%[WDTREG]" "\n\t" \
481
"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
482
"out %[WDTREG],%[TEMP_WD]" "\n\t" \
483
"out __SREG__,__tmp_reg__" "\n\t" \
484
:
/*no output */
\
485
: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
486
[SIGNATURE] "r" ((uint8_t)0xD8), \
487
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
488
[TEMP_WD] "d" (temp_wd), \
489
[WDVALUE] "I" (1 << WDE) \
490
: "r0" \
491
); \
492
}while(0)
493
494
#elif defined(__AVR_ATtiny4__) \
495
|| defined(__AVR_ATtiny5__) \
496
|| defined(__AVR_ATtiny9__) \
497
|| defined(__AVR_ATtiny10__) \
498
|| defined(__AVR_ATtiny20__) \
499
|| defined(__AVR_ATtiny40__)
500
501
#define wdt_enable(value) \
502
__asm__ __volatile__ ( \
503
"in __tmp_reg__,__SREG__" "\n\t" \
504
"cli" "\n\t" \
505
"wdr" "\n\t" \
506
"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
507
"out %[WDTREG],%[WDVALUE]" "\n\t" \
508
"out __SREG__,__tmp_reg__" "\n\t" \
509
:
/* no outputs */
\
510
: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
511
[SIGNATURE] "r" ((uint8_t)0xD8), \
512
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
513
[WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
514
| _BV(WDE) | value)) \
515
: "r16" \
516
)
517
518
#define wdt_disable() \
519
do { \
520
uint8_t temp_wd; \
521
__asm__ __volatile__ ( \
522
"in __tmp_reg__,__SREG__" "\n\t" \
523
"cli" "\n\t" \
524
"wdr" "\n\t" \
525
"out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
526
"in %[TEMP_WD],%[WDTREG]" "\n\t" \
527
"cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
528
"out %[WDTREG],%[TEMP_WD]" "\n\t" \
529
"out __SREG__,__tmp_reg__" "\n\t" \
530
:
/*no output */
\
531
: [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \
532
[SIGNATURE] "r" ((uint8_t)0xD8), \
533
[WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
534
[TEMP_WD] "d" (temp_wd), \
535
[WDVALUE] "I" (1 << WDE) \
536
: "r16" \
537
); \
538
}while(0)
539
540
/**
541
Undefining explicitly so that it produces an error.
542
*/
543
#elif defined(__AVR_AT90C8534__) \
544
|| defined(__AVR_M3000__)
545
#undef wdt_enable
546
#undef wdt_disale
547
548
#else
549
550
/* Use OUT instruction. */
551
552
#define wdt_enable(value) \
553
__asm__ __volatile__ ( \
554
"in __tmp_reg__,__SREG__" "\n\t" \
555
"cli" "\n\t" \
556
"wdr" "\n\t" \
557
"out %0,%1" "\n\t" \
558
"out __SREG__,__tmp_reg__" "\n\t" \
559
"out %0,%2" \
560
:
/* no outputs */
\
561
: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
562
"r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
563
"r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
564
_BV(WDE) | (value & 0x07)) ) \
565
: "r0" \
566
)
567
568
/**
569
\ingroup avr_watchdog
570
Disable the watchdog timer, if possible. This attempts to turn off the
571
Enable bit in the watchdog control register. See the datasheet for
572
details.
573
*/
574
#define wdt_disable() \
575
__asm__ __volatile__ ( \
576
"in __tmp_reg__, __SREG__" "\n\t" \
577
"cli" "\n\t" \
578
"out %0, %1" "\n\t" \
579
"out %0, __zero_reg__" "\n\t" \
580
"out __SREG__,__tmp_reg__" "\n\t" \
581
:
/* no outputs */
\
582
: "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
583
"r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
584
: "r0" \
585
)
586
587
#endif
588
589
590
591
/**
592
\ingroup avr_watchdog
593
Symbolic constants for the watchdog timeout. Since the watchdog
594
timer is based on a free-running RC oscillator, the times are
595
approximate only and apply to a supply voltage of 5 V. At lower
596
supply voltages, the times will increase. For older devices, the
597
times will be as large as three times when operating at Vcc = 3 V,
598
while the newer devices (e. g. ATmega128, ATmega8) only experience
599
a negligible change.
600
601
Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
602
500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.)
603
Symbolic constants are formed by the prefix
604
\c WDTO_, followed by the time.
605
606
Example that would select a watchdog timer expiry of approximately
607
500 ms:
608
\code
609
wdt_enable(WDTO_500MS);
610
\endcode
611
*/
612
#define WDTO_15MS 0
613
614
/** \ingroup avr_watchdog
615
See \c WDT0_15MS */
616
#define WDTO_30MS 1
617
618
/** \ingroup avr_watchdog See
619
\c WDT0_15MS */
620
#define WDTO_60MS 2
621
622
/** \ingroup avr_watchdog
623
See \c WDT0_15MS */
624
#define WDTO_120MS 3
625
626
/** \ingroup avr_watchdog
627
See \c WDT0_15MS */
628
#define WDTO_250MS 4
629
630
/** \ingroup avr_watchdog
631
See \c WDT0_15MS */
632
#define WDTO_500MS 5
633
634
/** \ingroup avr_watchdog
635
See \c WDT0_15MS */
636
#define WDTO_1S 6
637
638
/** \ingroup avr_watchdog
639
See \c WDT0_15MS */
640
#define WDTO_2S 7
641
642
#if defined(__DOXYGEN__) || defined(WDP3)
643
644
/** \ingroup avr_watchdog
645
See \c WDT0_15MS
646
Note: This is only available on the
647
ATtiny2313,
648
ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
649
ATtiny25, ATtiny45, ATtiny85,
650
ATtiny261, ATtiny461, ATtiny861,
651
ATmega48, ATmega88, ATmega168,
652
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
653
ATmega164P, ATmega324P, ATmega644P, ATmega644,
654
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
655
ATmega8HVA, ATmega16HVA, ATmega32HVB,
656
ATmega406, ATmega1284P,
657
ATmega256RFR2, ATmega128RFR2, ATmega64RFR2,
658
ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2,
659
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
660
AT90PWM81, AT90PWM161,
661
AT90USB82, AT90USB162,
662
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
663
ATtiny48, ATtiny88.
664
*/
665
#define WDTO_4S 8
666
667
/** \ingroup avr_watchdog
668
See \c WDT0_15MS
669
Note: This is only available on the
670
ATtiny2313,
671
ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
672
ATtiny25, ATtiny45, ATtiny85,
673
ATtiny261, ATtiny461, ATtiny861,
674
ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168,
675
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
676
ATmega164P, ATmega324P, ATmega644P, ATmega644,
677
ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
678
ATmega8HVA, ATmega16HVA, ATmega32HVB,
679
ATmega406, ATmega1284P,
680
ATmega256RFR2, ATmega128RFR2, ATmega64RFR2,
681
ATmega2564RFR2, ATmega1284RFR2, ATmega644RFR2,
682
AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
683
AT90PWM81, AT90PWM161,
684
AT90USB82, AT90USB162,
685
AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
686
ATtiny48, ATtiny88,
687
ATxmega16a4u, ATxmega32a4u,
688
ATxmega16c4, ATxmega32c4,
689
ATxmega128c3, ATxmega192c3, ATxmega256c3.
690
*/
691
#define WDTO_8S 9
692
693
#endif
/* defined(__DOXYGEN__) || defined(WDP3) */
694
695
696
#endif
/* _AVR_WDT_H_ */
io.h
stdint.h
Automatically generated by Doxygen 1.8.7 on Wed Jun 4 2014.