NGSPICE rework-14 release (released on December 10th, 2001):
This release fixes most of the bugs that appeared in rework-13. Some leaks in the frontend have been closed. GNU Autoconf interface cleaned (better support for getopt). Better error reporting (thanks to Charles Williams "CDHW"). Added mesa tests (macspice3f4). Added support for ekv model (not source code). The Rawfile format changed again removing "Probe" compatibility code.
NGSPICE rework-13 release (released on November 5th, 2000):
This is a major release in terms of fixes and enhancements. A garbage collector support has been added. If the configuration script detects that you have installed GC (Bohem-Weiser conservative garbage collector), it will use it. Some memory leaks have been fixed too. Enhancements to the code comes from Alan's (Gillespie) contribute code, a description of improvements follows (extracted form Alan's mail): * Output File Format Changes - Rawfile format changed to PSPICE Probe format (Usable with Demo version of Microsim's Probe). (NOTE: Do not rely on this, we may revert to the old format in the next release). Text mode .OP results even though "rawfile" written. Internal device nodes are not saved to "rawfile" (reduces file size). Optionally, these internal nodes can be replaced by device currents and saved. * DC Convergence Enhancements - "Source-Stepping" algorithm modified with a "Dynamic" step size. After each successful step, the node voltages are saved, the source-factor is increased by the step-factor, and the step-factor is increased (for the next step). If the step fails, i.e. the circuit does not converge, the source-factor is set to the value from the previous successful step, the previously stored node voltages are restored, the step-factor is reduced, the source factor is increased by this smaller step-factor, and convergence is attempted again. Same thing done for "Gmin-stepping" algorithm. "Gshunt" option added. This sets the "diagGmin" variable used in the gmin-stepping algorithm to a non-zero value for the final solution. (Normally this is set to zero for the final solution). This helps for circuits with floating nodes (and for some others too). The Gmin implementation across the substrate diodes of MOS1, MOS2, MOS3, MOS6 and BSIM3 devices, and across BJT base-emitter and base-collector diodes, was incorrect. Correcting this dramatically improved DC convergence. (I think this also effects BSIM1 and 2 but I haven't fixed them yet! ). The gm, gmb and gds calculations in the MOS3 model were all wrong. The device equations were fixed, leading to much improved convergence. The Vcrit value used for diode voltage limiting was calculated without taking into account the device area (and in some cases without using the temperature corrected saturation current). This could cause floating point overflows, especially in device models designed to be scaled by a small area, e.g. 2u by 2u diodes (area=4e-12). This is now fixed for Diode, BJT, MOS1, MOS2, and MOS3 models. The diode voltage limiting was modified to add negative voltage limiting. Negative diode voltages are now limited to 3*Vdp-10, where Vdp is the voltage from the previous iteration. If Vdp is positive, then the voltage is limited to -10V. This prevents some more floating point overflows. (Actually, I'm still playing with the best values for this). The Spice3 "fix" for the MOS3 gds discontinuity between the linear and saturated regions only works if the VMAX parameter is non-zero. A "tweak" has been added for the VMAX=0 case. * Transient Convergence Enhancements - Temperature correction of various diode capacitances was implemented slightly incorrectly, leading to capacitance discontinuities in simulations at temperatures other than nominal. This affected the Diode and MOS3 models. A mistake in the implementation of the MOS3 source-bulk capacitance model resulted in a charge storage discontinuity. This has been fixed. The level 2 MOSFET model seems to calculate Von and Vth values for the threshold and subthreshold values respectively, but then uses Vbin to calculate the Vdsat voltage used to find the drain current. However, a jump statement uses Von to decide that the device is in the "cutoff" region, which means that when this jump allows the drain current to be calculated, Vdsat can already be well above zero. This leads to a discontinuity of drain current with respect to gate voltage. The code is now modified to use Vbin for the jump decision. It looks like the code should actually use Vth as the threshold voltage, but since PSPICE and HSPICE both follow the original Berkeley code, this was left alone. * New Model Parameters - A PSPICE/HSPICE-like "M" device parameter (i.e. M devices in parallel) was added to the MOS1,2,3 and BSIM3 mosfet models. * Input Read-in and Checking - Numbers beginning with a "+" sign got the input routine confused. Fixed now. Attempts to nodeset (or .IC) non-existent nodes are flagged with a warning. PWL statements on Voltage or Current sources are now checked for "non-increasing" time-points at the start of the simulation. Previously each time-point was checked as it was reached during the simulation, which could be very annoying if you made a mistake which caused the simulation to fail after hours of run-time. A check which was performed at the end of each sub-circuit expansion was moved to the top level. This check makes sure that all sub-circuits have been defined, but in its original position, it meant that if a sub-circuit included ANY .MODEL statements at all, then ALL the models called in that sub-circuit must also be defined within that sub-circuit. Now SPICE behaves as expected, i.e. a subcircuit may define its own models, but may also use models defined at any level above. * Miscellaneous Fixes/Enhancements - MOS devices reported only half of the Meyer capacitances, and did not include overlap capacitances, when reporting to the .OP printout, or when storing device capacitances to the "rawfile". The ideal switch devices had no time-step control to stop their controlling voltages/currents overshooting the switching thresholds. The time-step control has been modified to use the last two time points to estimate if the next one will move the controlling voltage/current past a switching threshold. If this looks likely, then the time-step is reduced. The "rawfile" writing routines have been modified to print the "reference value" to the console during the simulation. This lets the user see exactly how far and how fast the simulation is proceeding. .OP printout tidied up a lot to make the printout clearer. Analysis order changed to fix a "feature" where, if you ask for a .OP and a .TRAN in the same simulation, the node voltages printed out correspond to the .OP, but the device data was from the last timepoint of the .TRAN.
NGSPICE rework-12 release (released on August 26th, 2000):
Arno did a great work this summer! This release consists of his work. The pole-zero analysis has been corrected. The error was introduced in an attempt to eliminate compiler warnings. The source has been reworked and info file have been updated. As you may see, a new dir called "spicelib" has been created, another step toward the separation of the simulator from the frontend.
NGSPICE rework-11 release (released on May 28th, 2000):
The code has been cleaned, the resistance code for ac parameter has been modified to conform to Spice3 parameter parsing. A new step function has been introduced (u2). Updated documentation to reflect changes.
NGSPICE rework-10 release (released on April 5th, 2000):
All devices are compiled as shared libraries (ld.so). There is an initial support for the BSIM4 model. This release is to be considered as baseline for the project. There are still some harmless bugs in the resistor code.
Release notes for older NGSPICE release are not available. For historical purpose only the following release notes, pertaining to the original Spice3 code have been included into this manual. They have been copied from "SPICE 3 Version 3f5 User's Manual":
Spice3f is the six major release of Spice3. This release incorporates new features not available in Spice 3c or 3d, as well as several performance improvements. All of the feature described here are believed to be fully functional. The development of SPICE is ongoing at Berkeley, and therefore not all of the intended capabilities have been implemented in full yet.
Bugs in 3f2 fixed in 3f3:
Ascii (printer) plots in spice3f2 did not print bode plots vs log of the frequency by default, as in spice2. You had to explicitly request the x-axis to be log; either "plot vdb(2) xlog" (best) or "plot vdb(2) vs log10(frequency)" will do. Now, simply "plot vdb(2)" will work. The on-line documentation has been brought up to date by converting this manual into a format readable on-line. Significant problems with AC sensitivities in 3f2 only have been fixed. Multiple analyses and plots in spice2 emulation mode under 3f2 and earlier generated misleading error messages. This no longer happens in 3f3.
New features and bug fixes incorporated in spice3f (the current release of Spice3):
Sensitivity analysis Added a parameter for fitting JFET models (parameter "B
"). Fixed a discontinuity problem in MOS level 3 (related to the "kappa
" parameter). Working "alter" command. Improved "show" and "showmod" commands for operating points summary tables (like Spice2). Working "trace" command. Interactive "set" variable values now the same as ".options
" settings. Improved plotting, including implicitly transforming data for smith plots. Added function "deriv()
" (derivative) to the front-end. Corrected an error affecting the specified initial conditions for some circuits. Miscellaneous bug fixes in the front-end.
New feature and bugs fixes incorporated in Spice3e (the previous release of Spice3):
Lossy Transmission lines. Proper calculation of sheet resistance in the MOS models. A new command ("where") to aid in debugging troublesome circuits. Smith-chart plots working (see the "plot" command). Arbitrary sources in subcircuits handled correctly. Arbitrary source reciprocal calculations and DC biasing fixed. Minor bug-fixes to the Pole-Zero analysis. Miscellaneous bug fixes in the front end.
Some common problems remaining in Spice3f (note that this list is not complete):
Models defined within subcircuits are not always handled correctly. If you have trouble, move the model definition outside of ".subckt
" and ".ends
" lines. Batch run data is not compacted if a "rawspice" data file is generated, resulting in excessively large output files for some difficult inputs. Sufficient detail is sometimes not preserved in transient analysis. Providing a small value for the "TMAX
" parameter (the fourth argument) in the transient run command will solve this problem. Convergence problems can sometimes be worked around by relaxing the transient "TMAX
" parameter. The substrate node of the bipolar transistor (BJT) is modelled incorrectly (this may actually be due to inherent numerical problems with the model). Do not use substrate node; use a semiconductor capacitor to model substrate effects. Charge is not conserved in MOS devices based on the Meyer model. Transient simulation of strictly resistive circuits (typical for first runs or tests) allow a time step the is too large (e.g. a sinusoidal source driving a resistor). There is no integration error to restrict the time step. Use the "TMAX
" parameter or include reactive elements. Deep nesting of subcircuits may exceed internal static buffers. The PZ analysis can not be interrupted; the sensitivity analysis can not be continued (the interactive "resume" command) once interrupted. There are many other small bugs, particularly in the front end.
Berkeley does not provide support anymore for Spice3, if you need some kind of help you can